Hardware Implementation of Droop

Control for Isolated AC Microgrid

By:

Cristina Guzman
Alben Cardenas Kodjo Agbossou

Université du Québec à Trois-Rivières

Québec-Canada
 Outline

Introduction
Droops control principle
ADALINE estimation technique
Hardware implementation of ADALINE and
Droops control
Co-simulation results
Experimental results
Conclusion

2
 Introduction
Smart Grid: Integration of DER privileging Renewable energy
using Voltage Source Inverters (VSI) PCC Synchronization
Alternative and distributed energy Power electronics AC Link
source interfaces

G
WG VSI

PV
VSI
Energy storage system Voltage and
DC frequency
Link
control
H
O

Fuel cell
H2 Power
VSI
Sharing
Electrolyser
3
3
 Introduction

Literature propositions made around the stability

of the isolated microgrids. Interfaces de PCC Distortion
puissance Linecurrents
Techniques based on impedances

Communication control VSI

Local control
VSI
Techniques

Combined Local control

with communication VSI

4
 Droops control principle

Basic representation of VSI power sharing

V1 V2 V2
P cos cos( )
Z Z
X P *
V1 V2 V2 w w m P P*
Q sin sin( )
Z Z V1 V2
S P jQ
V1 V2
P
Z
sin X Q
V1 V2 V V
*
n Q Q*
Q
V1 V2
cos
V2 V1
Z Z

5
 Droops control principle

Basic representation of VSI power sharing

w w w
*
m P P* V V V
*
n Q Q*
m n
Δw w0 ΔV V0

0 P0 Pmax P (W) –Qmax 0 Q0 Qmax Q(var)

6
 ADALINE estimation technique

Fourier decomposition
X pattern vector Weight vector W VPCC (t ) A0 [ An cos(n t ) Bn sin( n t )]
n 1
sin( t ) B1
cos( t ) Estimated signal
A1
X  W  yˆ (k ) W (k )T X (k )
sin( N t ) BN
cos( N t ) AN

Estimation error _
W (k 1) W (k ) e( k ) X ( k ) e(k ) y(k ) yˆ (k ) + Measured
N
Widrow-Hoff learning rule signal

ADALINE :Adaptive Neural Network y(k)

7
Hardware implementation of Droops
and ADALINE control
VLD
Conventional V/f Droops and ADALINE
based voltage control VDC
Vmes

IGBT VSI
Droops Control
Frequency Droop w/P
Imes
wref fdroop VF DDS Vmes
Mn +
- Sine wave
generator S&H
x
I0
Voltage Droop V/Q I1
P
Vref ADALINE V0 P&Q
Nn + Vdroop calculus
Q
V1
-
x
V_LD
V_REF_Droops

Voltage Control
Vmes ki V_REF_mod PWM
kp
s VSI
8
8
Hardware implementation of Droops and
ADALINE control

Simulink functional blocks

diagram of the
conventional Droops
Continuous
powergui
120 *pi In
E1_W_REF
Wref Delay 14 z-1 System
Generator
a
a<b
a z-1 cast
P_estime cast In18f 7 a>b b sel
cast
Out_18f 7 z-1 Convert 3 a
b Relational 2
Convert 5 h1ms Convert 2 sel z-1a - b a dW
d0 z -1 b -3
Relational 1 z (ab )
FILTRE _8MS3 a
-3 -1 AddSub 1 b
z (ab ) z d0 z-1 z
-1
b d1
Mult 2

System generator
Delay Delay 3
0.0038 /2 -1
1 In z Mult d1 Sat 2
Gain 3 E3_M Delay 12
M
Sat1

functional blocks
7.539794921875 0.159149169921875
-7.539794921875
Constant Constant 8
Constant 1

diagram of the In
115 *sqrt(2)
E2_V_REF
Vref
a -1 Delay 13
a z

conventional Droops
a>b a<b
cast
-1 cast z-1
z sel b sel
Q_estime cast In18f 7 b Convert 1
Convert a
Out_18f 7 Relational 4 -1
Convert 4 Relational 3 z a -b
h1ms
d0 z-1 -1 d0 z-1

control
z b
a -1
FILTRE _8MS2 -3 z
Qmes z (ab ) Delay 2 AddSub
b Delay 1 d1 d1
Mult 1
-1 Sat3 Sat4
0.0326 /2 1 In z

N Gain E4_N Delay 11

8.4852294921875 -8.4852294921875

Constant 2 Constant 3

9
9
Hardware implementation of Droops and
ADALINE control
Real scenario /Simulation and experimental
VSI characteristics
Description (units) VSI1 VSI2
Switching frequency (kHz) 12 12
IGBT max. current and voltage (A) (V) 16, 600 16, 600
Filter inductor (mH) 17  12 
Filter capacitor (µF) 3
 1 
Resistive line value (mΩ)
Inductive line value (µH)
21.8
90


38.6
170


Coefficient m value
Coefficient n value 0.0066

3.9035e-4
 0.0047

2.5466e-4

The inverters characteristics are similar but not identical;
the inverters output filters
local synchronization and control of inverters;
different line impedances between VSI output and PCC;
m and n are calculated as a function of the VSI powers.
10
 Experimental set-up system

PC Windows
One VSI system Matlab/Simulink /Xilinx
User Interface

Measurement board USB-JTAG Link

(ADC and isolation circuits)

Xilinx FPGA
XUP V2P Board
xc2vp30-7ff896

Current and voltage LEM Sensors

VSI control
LEM-LV25 LEM-LAH-50P
and
protection signals

Output filter
LOAD
195V DC source
11
Hardware implementation of Droops and
ADALINE control
Two VSI system Test bench

Line emulators

VSI 1 VSI 2

195V DC source
195 V DC source

FPGA
measurement FPGA
control measurement
control
12
 Co-simulation results

5
Two converters evaluation 61
Droop Inv1
Inverter 1 Estimated Inv1

Frequency (Hz)
60.5
Inverter 2 Droop Inv2
Current (A)

Estimated Inv2
0 60

59.5

-5 59
0 0.1 0.2 0.3 0.4 0.5 0.6 0 0.1 0.2 0.3 0.4 0.5 0.6
Time(s) Time(s)

200 Synchronization 170

Inverter 1
100 Inverter 2 imposes of VSI is 165

Voltage (V)
Voltage (V)

0 made automatically 160

-100 155

-200 150
0 0.1 0.2 0.3 0.4 0.5 0.6 0 0.1 0.2 0.3 0.4 0.5 0.6
Time(s) Time(s)

Negligible effects The output voltage

on voltage THD is not affected

Good power
sharing
13
Simulating the same characteristics physiques
 Experimental results

Test 1: one VSI experimental validation

150 200
V droop Active

Puissance (W)/ (VAR)

Vc estimated 150 Reactive
145
Peak Voltage

100
140
50
135
0

130
58 Voltage
58.5 59 59.5 60 60.5 61 61.5 62
-50
58 58.5 59 59.5 60 60.5
Time (s) Load61 variations
61.5 62
estimation is well Time (s)

achieved
Droop
60.2
Estimated frequency

Estimated
60.1
60
59.9
59.8

Frequency inside 59.7

59.6
the permitted 58 58.5 59 59.5 60 60.5 61 61.5 62
Time (s)
limits
14
Verification of the correct operation of the implemented droop/ADALINE control.
 Experimental results

Test 2: Two parallel VSI experimental results

t1 t2 t3 t4 t5

VSI2

Power
VSI1

15
 Experimental results

Test 2: Two parallel VSI experimental results

t1 t2 t3 t4 t5

VSI2

Frequency
VSI1

16
 Experimental results

Test 2: Two parallel VSI experimental results

t1 t2 t3 t4 t5

VSI2

Voltage
VSI1

17
 Experimental results

Implementation cost of control algorithms

for the Xilinx xc2vp30-7ff896 FPGA
Resource Used Available % Usage

Slices 7,122 13,696 52%

4 input LUTs 11,698 27,392 42%
RAMB16s 66 136 48%
MULT18X18s 76 136 55%

FPGA Slices

Used
Available

18
 Conclusion

Real view of the Droops control / VF-ADALINE

network for VSI synchronization and load sharing
in a microgrid.
The FPGA implementation has permitted a real-
time control and power analysis without
communication between VSIs
Good steady and transient response using
ADALINE based control.
Current and future works: advanced local control
strategies going forward future smart microgrids.
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Thank you! Question time!
Anexe
Experimental setup parameters:
AC Power Source: 120VAC/60Hz.
Signals sampling period: T s =10µs.
FPGA clock period: T FPGA =10ns.
Fundamental frequency: f 0 =60Hz
ROM sine table length: 2P=215
Power electronics converter characteristics:
Voltage Source Inverters:
16A, 600V IGBT full bridge (IRAMX16UP60A)
DC source voltage: 195V.