Apollo 9904 PDF

Cell Based Physical Design with
Apollo
Apollo version 1999.4
CIC Avant! Software - Apollo 1

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Class Schedule
Day1 !Getting started with Apollo " Lab1
!Library structure and elements " Lab2
!Data Preparation / Import Design
!Floor planning " Lab3
Day2 !Floor planning (Region & Group)
!Pre-route Nets / Cell Placement " Lab4
!CTS / Routing
!Apollo built in DRC/LVS
!Export Data " Lab5
Day3 !Dracula DRC verification
!Timemill post layout simulation " Lab6
!Overall review
!Quiz

Starting an Apollo Session
unix% Apollo &
Menu banner
Command
Message/Input area History area
Prompt area
Starting an Apollo Session

Menu banner:
You can access the Avant! application commands via menu bar.
Message/Input area:
The system messages, all commands executed and points entered are displayed in this area. Also,
you can type scheme commands in this area. Note that you can list the commands containing a
string by typing functions “string”; for example, you can type functions “cell” to list all
functions having the string cell in them.
Prompt area:
The scheme commands that correspond to the menu commands you select and prompts to help
you to select objects or specify points required for command execution are displayed in this area.
Command History area:
The scheme commands that you have used in this session are displayed in this area.

Working with an Open Cell
Working with an Open Cell

View command short-cut buttons:
Use these buttons to navigate around the design. Hold the cursor over the button to display a tag
that tells you what the button does.
Command history short-cut buttons:
Use these buttons to invoke any of the last three commands executed.
Selecting and editing short-cut buttons:
Use these buttons to access the query and select commands.
Note that the coordinate of the left-bottom corner of the design chip is (0,0).
To customize the short-cut buttons, modify the avntInit.scm in your Avant! directory. Edit the
setSideButton section. Refer to “Place and Route Getting Started User Guide” for the syntax of
setSideButton.

Short-cut Buttons
redraw scroll up fit cell zoom out 4X
scroll left move center to scroll right zoom out 2X
pan to scroll down fit with margin zoom in 2X
previous next view zoom to area additional

view commands

Using Avant! Online Help
!HTML format
!Click on the help button of any application
menu bar or form.
!Type help “command” in the message/input
area.

Specifying Objects by Pattern
!Ordinary character
!.
!*
!\., \*
![cdrx], []cdrx], [-cdrx], [cdrx-]
![^cdrx], [^]cdrx], [^-cdrx], [^cdrx-]
![2-5], [b-d]
!.*string.* string.* .*string
Specifying Objects by Pattern

# An ordinary character matches itself.
# A dot (.) matches any single character.
# An asterisk (*) matches zero or more occurrences of the character or expression immediately
preceding it. For example, n* matches zero or more occurrences of the character n, and .*
matches zero or more occurrences of any character.
# A backslash (\) followed by a special character matches the character. For example, \.
Matches . and \* matches *.
# A set of characters enclosed by square brackets ([]) matches any character inside the brackets.
To include a right square ()) in the set, place it at the beginning of the set.
# A caret (^) followed by a set of characters, all enclosed by square brackets ([]), matches any
character not included in the set. For example, [^469] matches any character except 4, 6, and
9. A caret in any other position is interpreted as an ordinary character. To include a right
square bracket ()) in the set, place it at the beginning of the set, immediately following the
caret.
# A minus sign (-) between two characters indicates a range of consecutive characters and
matches any character in the range. For example, [2-5] matches 2, 3, 4, or 5 and [b-d] matches
b, c, or d. To include a minus sign in a set, place it at the beginning or end of the set.

Apollo Library Structure
Library Subdirectories & Files
NETL EXP CEL FRAM TIM lib
Cells
Net views Expanded Cell views Frame views Timing views

netlist views
Apollo Library Structure

The library directory should contain the following:
# Library subdirectories containing cells of each type in the library.
# A library information file. This is a binary file that contains information compiled from a
technology, a cell library format (CLF) file, and the cell files inside the library directory.
Cell formats:
# Net views represent the logical connectivity of a design at the top level of hierarchy.
# Expanded netlist views represent the logical connectivity of a design at enough levels of
hierarchy to provide information necessary for binding with the physical layout.
# Cell views represent the physical layout of a design.
# Frame views represent the pins, the blockage areas (areas where no routing on a particular
layer can occur), the via regions (areas where vias can be placed during routing), and the pin
solutions (solutions for routing to pins).
# Timing views contains the timing information of a design.

Cell View
Cell type
! Standard Cell
! Macro Cell
! Pad Cell
! Core Filler Cell
! Pad Filler Cell
! Corner Cell
Layer mapping

Frame View(1)
prBoundary unitTile
blockage
pin
Frame View(1)
The unit tile is the basic unit of area for placement of standard cells. It is the width of metal2 pitch and
about the height of the standard cells.
The prBounbary is the bounding box of the unit tiles used by a standard cell. It marks the lines along
which cells are abut; that is, the polygon that encloses the unit tiles in a standard cell. Apollo uses
prBoundary to align wire tracks and power and ground rails during cell placement.

Frame View(2)
unitTile
row
minimum
distance
M2 pitch
standard cell

Frame View(3)
wire
track

Timing View % CLF file
pad
pad pad pad
definePad “pad” “0” definePad “pad” “180”
cpad cpad
cpad cpad

Timing View % CLF file

A CLF file describes the cell behavior, usually the timing characteristics. Since timing is beyond the
scope of this course, we will present only the definePad CLF function here.
The definePAD function defines the orientation of IO cells and corner cells. Apollo uses this
information when placing pads around the chip boundary.
The syntax is
definePad padName padRotation

Apollo Basic Design Flow
Data Preparation Tape Out
Import Design Timemill post layout simulation
Floor planning Dracula DRC/ERC Check

Pre-route Nets
GDSII file
Cell Placement
Export Data
CTS
Routing
Build in DRC/LVS Check
Terms and Definitions

CTS: Clock Tree Synthesis
PG: Power and Ground
P/G/C: Power, Ground, and Clock
P&R: Place and Route
TDF: Top Design Format

Data Preparation
Technology
Technologyfile
file
Design
Design netlist
netlistfile
file
TDF
TDF
file
file
Referenced
Referencedcell
celllibrary
library
Data Preparation
A technology file defines the following characteristics of a cell library:
# Units
# Colors, stipple patterns, and line styles
# Layers
# Capacitances and resistances (for timing-driven layout)
# Devices
# Design rules
In Apollo, you can import a netlist in EDIF or Verilog HDL format. Apollo will translate it into a
netlist cell, which represents the logical connectivity of a design at the top level.
The “Top Design Format” (TDF) file is used to describe the pad placements when designing a chip,
or pin placements when designing a block-level layout. Also, it can define the clock waveform
used in timing driven layout and clock tree synthesis.
A cell library can contain both top-level designs and the cells used in those designs. In some cases,
cells in a library can contain cells from other libraries. Instead of copying cells to multiple libraries,
Apollo references the other libraries, which are called “reference libraries”.

Technology File
Technology File Section Defines …
Technology Units and unit values
PrimaryColor and Color Primary and display colors used by Apollo
Stipple Stipple patterns used by Apollo
LineStyles Line styles used by Apollo
Tile Unit tiles
Layer Specific layer definitions
ContactCode Devices used in designs
FringeCap Capacitance information for interconnect
layers when they are overlapping or
parallel to each other
DesignRule Design rules
PRRule Cell row spacing

Referenced Cell Library
Your Design
Library
cic35_io_v1.0 ram or rom cic35_core_v1.0
Physical layout

Import Design
!Verilog In / EDIF In
Netlist In > Verilog In Milkyway
!Specify Reference Libraries
Library > Add Ref
!Expand Hierarchical Netlist Cells
Netlist In > Expand
!Generate Cell View Apollo
Gate Level Apollo Cell

Netlist
Import Design
To access Milkyway application, select Tools % Data Prep in Apollo session; when you want to go
back to Apollo, select Tools % ApolloII.
In a cell-based design, the cell libraries you use should be referenced.
Apollo P&R system can not deal with the hierarchical netlist, hence, before binding the netlist into
the Apollo cell, the netlist should be expanded to enough levels of hierarchy to provide information
necessary for binding with the physical layout.
Ref [1] [2] [3]

Settings for Verilog-In(1)
! Verilog File Name → your_design.v
! Verilog List File Name → keep this field blank
! Library Name → your_design_library_name
! Tech File Name → technology file name
! HDL to GDSII Map File → keep this field blank
! Bus Naming Style → [%d] ※1
! Verilog Model Directory → keep this field blank
! Model File Extension → keep this field blank
! Net Name for 1’b0 → VSS
! Net Name for 1’b1 → VDD
! Hierarchy Separator → . ※2
※1 input [1:4] sys → sys[1], sys[2], sys[3], sys[4]

chip.io
chip.core.ram
※2 chip.core.ctrl
chip.core.datapath
chip.core.ram.addr[0]

Verilog File Name:
Type the name of the Verilog file you want to translate.
Library Name:
Type the name of the library in which you want to place the cell. If the library does not exist,
Milkyway will create it.
Bus Naming Style:
Type any string you want Milkyway to append to the bus name specified in the Verilog file when
it translates the bus to individual ports, using %d to indicate the port number.
Net Name for 1’b1 & 1’b0:
Type the tie-up & tie-down net names.
Hierarchy Separator:
Type the character you want to use as a separator in hierarchical names. If this character is used
in cell instance or net names, Milkyway will translate the name with a backslash (\) preceding
the hierarchy separator character.

! Bus Name Append → keep this field blank
! Multiple PG Nets → Disable
! Set Case Sensitive → Enable
! No Backslash Insertion to avoid
Hier Name Collisions → Enable ※1
! Remove First Backslash Of Escaped
Identifier in Database → Disable ※2
! Create Bus For Undefined Cells → From Connection ※3
※1
chip→core→a. chip.core.a. Enable
chip.core.a\. Disable
※2
chip→core→\a[3] chip.core.a[3] Enable
chip.core.\a[3] Disable
※3
sub si (.port(net([4:1])…); → input [3:0] port;
sub si (.port(net([1:4])…); → input [0:3] port;

Set Case Sensitive:
Be carefully. This attribute is set permanently.
No Backslash Insertion to avoid Hier Name Collisions:
Select if you do not want Milkyway to insert a backslash when translating cell instance, port and
net names to avoid confusion with the backslash used as hierarchy separators. If you unselect the
default value, Milkyway will insert a backslash before all hierarchy separators.
Remove First Backslash Of Escaped Identifier in Database:
Select to remove the first backslash of all escaped identifiers.

Settings for Expand Netlist
! Library Name → your_design_library_name
! Unexpanded Cell Name → top_cell_name.NETL
! Expanded Cell Name → top_cell_name.EXP
! Precede Hierarchical Names with “/” → Disable
! Expand netlist cell with no instance → Enable
! Stop at FRAM view cells only → Disable
! Print out net has a pin but no connections → Disable
! Global Net Options (Mode) → Add
! Global Net Options (Net Name) → VDD (VSS) ※1
! Global Net Options (Port Pattern) → VDD (VSS)
※1 1. Select Add Mode

2. Type VDD in both “Net Name” and “Port Pattern” field
3. Click Apply
4. Type VDD in both “Net Name” and “Port Pattern” field
5. Click Apply
6. Click Hide
Settings for Expand Netlist

This command expands the netlist recursively until all objects in the netlist are broken down into
component objects that exist in the layout, creating an expanded netlist cell in the library directory.
Using the Global Net Options subform, you can also specify global net connections to nets and
ports in the subcells.
The paragraph on the right side of ※1 describes how to add VDD & VSS as global nets.

Global Net Options
module top(…); top
… m1
m1 M1(in, out); VDD
…
endmodule in INV out
module m1(in, out);
VSS
input in;
output out; inv_out
inv INV(.in(in), .out(inv_out)); VDD
buf BUF(.in(inv_out), .out(out));
endmodule in BUF out
VSS
M1.INV.VDD
VDD
M1.BUF.VDD
M1.inv_out
Global Net Options

During netlist expansion, all tie-high and tie-low nets throughout the netlist hierarchy must be
connected together. Otherwise, after expansion you would have separate nets like M1/INV/VDD
and M1/BUF/VDD. This is not the desired connectivity.

Generate Cell View
!Open Library
Library > Open
!Create P&R Cell
Cell > Create
!Bind Netlist
Design Setup > Bind Netlist
!Connect Ports to P/G Nets
PreRoute > Connect Ports to P/G
Generate Cell View

To generate cell view, open the library just created, create the cell, and then bind the expanded
netlist. After the netlist is bound, connect P/G nets to the cell ports of power supply, tie-high, or
tie-low by PreRoute > Connect Ports to P/G (aprPGConnect) command.
Ref [4] [5] [6] [7]

Connect Ports to P/G
VDD Power
VDD VDD1
Cell1 VDD
Cell2
(1’b1)
GND VSS
VSS Ground

Settings for Connect Ports to P/G
step1 step2 step3 step4
Net Name VDD VSS VDD VSS

Port Pattern VDD.* VSS.* PAD PAD
Cell Master Pattern .* .* pvdb(i)(f) pv0b(i)(f)
Cell Instance Pattern .* .* .* .*
Net Type Power Ground Power Ground
Cell Types Std/Module Std/Module Pad Pad
Cell Cell
Update Tie Up/Down Disable Disable Disable Enable
Mode Add Add Add Add
Settings for Connect Ports to P/G

& After you fill the field as specified in each step, click apply.
& Net Name: Type the name of the net to which you want to connect ports with names that
match Port Pattern. If the net does not exist, this command creates it.
& Port Pattern: Type a pattern to match the names of the ports in the specified cells that you
want to connect to the specified net.
& Cell Master Pattern: Type a pattern to match the cell master(s) for which you want to connect
specified ports to the specified net.
& Cell Instance Pattern: Type a pattern to match the cell instance(s) you want to connect to the
specified net.
& Net Type: Select the net type you want to assign to the specified net.
& Cell Types: Select the type(s) of cells in which you want to make the specified connections.
& Update Tie Up/Down: Select to update the tie-up/tie-down information for the cell. If you
have any tie-up/tie-down connections (either in the netlist or specified by dbSetCellPortTypes
functions), you need to select this option the last time you execute the command.
& Mode: Select whether you want to connect or disconnect the specified ports.

Floorplan
!Load the TDF File
Design Setup > Load TDF
!Setup the Floorplan
Design Setup > Set Up Floorplan
!Place Macros
Modify > Move or PrePlace > Place Blocks
!Create Groups and Regions
Design Setup > Add to Group by Names
Design Setup > Create Region
Floorplan
After the design is imported into Apollo, do the following:
& Create and load the top design format file to set the constraints for pad placement.
& Setup the rectangular floorplan. The rectilinear floorplan is beyond the scope of this training
course.
& If your design contains macros, place them before cell placement. To place macros, you can
use Modify > Move command to move macros to the location you desired. Also, you can
place macros automatically by PrePlace > Place Blocks command.
& You can create groups and regions for better floorplan. Better P&R result will be obtained
with better floorplan.
Ref [8] [9] [10] [11] [12] [13]

Using TDF pad
pad padName padSide [padOrder] C ul T1 T2 C ur
[padOffset] [“reflect”]
pad “Cul” “left” 4

pad “Cur” “top” 3 L3
pad “Clr” “right” 1
pad “Cll” “bottom” 1
pad “L1” “left” 1 L2
pad “L2” “left” 2 400 400
pad “L3” “left” 3 200
pad “T1” “top” 1
pad “T2” “top” 2 L1
200
C ll C lr
Using TDF pad

The pad function sets the following constraints on pad placement:
& Side of the block to place the pad
& Order relative to other pad on the same side
& Offset from the origin to the bottom or left edge of the pad
& Pad rotation (orientation)
The syntax of TDF pad command is
pad padName padSide [padOrder] [padOffset] [“reflect”]
The rules for TDF pad are as follows:
& If padOrder = 0, the placement of the pad relative to the other pads is not important.
& If two pads have consecutive padOrder values, no pad can be placed between them.
& If you specify a padOffset value that contradicts the specified padOrder, the padOrder has
priority.
& Pads with lower order are placed close to the bottom or left edge of the boundary.
You should place the upper-left corner on the left side, place the upper-right corner on the top side,
place the lower-right corner on the right side, and place the lower-left corner on the bottom side.
Ref [14]

Settings for Set Up Floorplan(1)
! Control Param → aspect ratio
! Core Utilization → desired core utilization
! Row/Core Ratio → 1
! Core Aspect Ration(H/W) → 1
…. 2 1
VDD VDD VDD

VSS VSS
row VSS row
….
cell
3
region
Row/Core Ratio = 3/4 = 75%

Core Utilization = 75% * 2/3 = 50%
Core Aspect Ratio(H/W) = 4/3 =1.33
Channel 1
Settings for Setup Up Floorplan(1)

& Perform automatic floorplan setup and place cell rows in the core area using this command.
& Control Param indicates the method by which you want to specify the size of the core area;
you can specify the ratio of the height divided by the width, the exact width and height, the
number of rows, or the boundary created by Create > Boundary.
& The two rows of options in the Floor Planning form under the Control Param options become
active or inactive depending on the Control Param you choose.
& Type a number from 0 to 1.0 in Core Utilization field to indicate the amount of core area used
for cell placement. This number is calculated as a ratio of the total cell area (standard and
macro cells) to the core area. For example, Core Utilization of 0.8 means that 80% of the core
area is used for cell placement and 20% is available for routing.
& Type a number from 0 to 1.0 in Row/Core Ratio field to indicate the amount of channel space
to provide for routing between the cell rows. A value of 1.0 leaves no routing channel space.
The Row/Core Ratio must be equal to or greater than the Core Utilization.
& Type the aspect ratio (height divided by width) for the core area in Core Aspect Ratio (H/W)
field.

! Horizontal Row → Enable
! Double Back → Enable
! Start First Row → Disable
! Flip First Row → Enable
VDD VDD VDD VSS VSS VSS VDD VDD VDD

VSS VSS VSS VDD VDD VDD VSS VSS VSS
VDD VDD VDD VDD VDD VDD VSS VSS VSS
VSS VSS VSS VSS VSS VSS VDD VDD VDD

VSS VSS VDD VDD
VDD VDD
VDD VDD VSS VSS
VSS VSS VDD VDD VSS VSS
VDD VDD VSS VSS VDD VDD
VSS VSS
Double Back Disable Double Back Enable Double Back Enable

Start First Row Flip First Row

& Select Horizontal Row to orient the cell rows horizontally inside the core area. Deselect to
orient the cell rows vertically.
& Select Double Back if you want to contain pairs of cell rows, with one row in each pair
flipped.
& If you select Double Back and want a pair of rows at the bottom of a horizontal core area or
left side of a vertical core area, select Start First Row.
& If you select Double Back and want a flipped row at the bottom of a horizontal core area or
left side of a vertical core area, select Flip First Row.

! Core to Left, Right, Bottom, Top → desired_core_to_pad(pin)_distance
! Disable all other options
Core to Top
Specify the distances

Core to Left Core to Right
core depending on the P/G ring
around core area.
Core to Bottom

& Type the distance between the left side of the core and the right side of the closest pin or pad
in Core to Left field.
& Leave enough space so that Apollo can place cells and route wires. In designs in which the
area between the core and the boundary must accommodate large power and ground buses,
you can increase the default core-to-boundary distances.

Create Group & Group Constraint
module chip(…);
Group M1: TOP\.M1\..*
… Group M2: TOP\.M2\..*
top TOP(…); Group M3: TOP\.M3\..*
endmodule
module top(…); Group Constraint
…
m1 M1(…);
m2 M2(…); w2
m3 M3(…);
endmodule M2 h2
module m1(…);
… w1
endmodule M3
M1 h1
module m2(…);
…
endmodule
module m3(…); w1 < Max Width
… h1 < Max Height
endmodule w2+h2 < Max Half Perimeter
Create Group & Group Constraints

By using groups and regions, you can place standard cells in specific areas of the design.
Use the commands below to create and edit cell groups:

& Design Setup > Add to Group by Names
& Design Setup > Add to Group by Selected Set
& Design Setup > Remove From Group by Names
& Design Setup > Remove From Group by Selected Set
& Design Setup > Delete/Show Group

Region v.s Group Constraint
Region Group
(M1 Group) Constraint
(M1 Group)
This window is fixed. This window can be

moved to any position
inside the core area.
Region v.s Group Constraint

The region is a fixed window while the group constraint is a sliding window as long as it does not
violate the size constraint.
Use the commands below to deal with regions:
& Design Setup > Create Region
& Design Setup > Create Region Blockages
& Design Setup > Query Region Connections
& Design Setup > Add Instances to Region
& Design Setup > Remove Instances from Region

Interaction Between Regions
Region members: I1, I2
Exclusive Non-exclusive
Region Region
I1 I2 I3 I1 I2 I3
Non-exclusive * Non-exclusive Exclusive * Non-exclusive

Exclusive * Exclusive (Region1 * Region2)
Region2 Region2
Region1 I3 Region1
I1 I1 I2 I3
I2
Interaction Between Regions

There are three combinations of region interaction:
& Non-exclusive, overlapping regions. Cells assigned to the regions share the overlapped area.
& Non-exclusive and exclusive regions that overlap. Only the exclusive region uses the
overlapped area.
& Exclusive regions that overlap. Cells assigned to the regions will share the overlapped area.

Pre-Route Nets
!Create P/G Rings
PreRoute > Rectangular Rings
!Create P/G Straps
PreRoute > Straps
!Pre-route Macros & Pads
PreRoute > Macros/Pads
Pre-Route Nets
You can pre-route any net, but you typically pre-route power, ground, and clock nets in 2 steps:
& Trunk routing before standard cell placement
& Standard cell P/G pins routing after standard cell placement
This is because the cells must be placed so that they do not interfere with the trunks, but the
standard cell P/G pins can be routed only after cells are placed.
Pre-route are marked as any one of four types:

& Ring
& Strap
& Macro/Pads pin connect
& Standard cell pin connect
Ref [15] [16] [17]

Settings for Rectangular Rings(1)
! Around → Core
! Net Name(s) → VDD, VSS
! L-Width → wl
R-Width → wr VSS wt
B-Width → wb
T-Width → wt VDD wt
! L-Layer → METAL2 dt wr
R-Layer → METAL2 wl wr
B-Layer → METAL3 dl core
T-Layer → METAL3 dr
wl db
! Offsets → Absolute
Left → dl wb
Right → dr
Bottom → db wb
Top → dt

& You can create rings around the predefined core, macros, instances, an instance group, or a
user-defined rectangle using PreRoute > Rectangular Rings. You can route power and ground
nets on any metal layer in any direction, but you should route a layer in its preferred direction.
Usually, horizontal routing is on metal1 or metal3, and vertical routing is on metal2 or metal4.
& Type the width, and the layer number (name) on which you want the left (L), right (R),
bottom (B), top (TOP) sections of the ring in L-, R-, B-, T- Width and Layer field.
& Type the distance from core to each side of the ring in the Left, Right, Bottom, Top entry fields
if you select Absolute option. Or you can let Apollo to adjust ring position to correct DRC
violations automatically.
& If the ring you specify creates a DRC error, Apollo does note create the segment of the ring
causing the violation.

Extend → RH, BL
Skip Side(s) → Left, Top
Extend Options
LH RH
TL TH macro
BL BH
LL RL

Select extend options for extending rings to the cell boundary or to the first target on the same net.
& LL Extend the left segment of the ring low.
& LH Extend the left segment of the ring high.
& RL Extend the right segment of the ring low.
& RH Extend the right segment of the ring high.
& BL Extend the bottom segment of the ring left.
& BH Extend the bottom segment of the ring right.
& TL Extend the top segment of the ring left.
& TH Extend the top segment of the ring right.

Create Straps
Extend to High
Boundaries
At First Targets and Generate Pins
VSS
VDD At Core Bdry
Step
Group1
Group2
Pitch
Create Straps
& Select horizontal or vertical for strap direction in direction field. Type the horizontal (vertical)
coordinate where you want the vertical (horizontal) strap to start in Start X (Start Y) field.
& Type the names of the nets for which you want to specify a strap in the Net Name(s) field. To
specify two or more nets, separate the names with commas. The number of net names
specified determines the number of straps in a group.
& You can configure the straps by specifying Groups, Step, and Stop. A Group contains straps of
the nets you specify. The Step is the distance from the reference strap of one group to the
reference strap of an adjacent group. The Stop is the stop coordinate.
& Pitch within Group is the distance you want placed between the center lines of two adjacent
straps within the same group.
& The straps can end at the core boundary, the first target, or the coordinate you specify. The
first target is the same net that the strap reaches first.

Settings for Straps
! Direction → Vertical
Start X →x
Start Y →y
! Net Name(s) → VDD, VSS
Width → desired width strap
Layer → METAL2
! Configure by → Group & Step
Groups →1
Step →0 (x, y)
Pitch within Group → 10.8
! Low Ends → At First Targets
! High Ends → At First Targets
! Place Straps 1 Time(s)
Settings for Straps

This slice shows the typical strap style and its settings.

Pre-Route Macros/Pads
! Instance Type(s)
→ Macro, Pad
! Instances
→ All but Specified
! Nets
→ PG macro
! Select Pins Automatically and Route
→ All
! Primary Routing Layer
→ Preferred (High)
VDD VSS
Pre-Route Macros/Pads
Connect power and ground pins in macros or pads to pre-routed rings, straps, and custom wires
using PreRoute > Macro/Pads. The width of the power and ground connection is the same as the
original power and ground pin.
Select the layer on which to route in Primary Routing Layer option:

& Preferred On the preferred layer; M1 and M3 for horizontal, and M2 and M4 for
vertical routes. If the preferred layer is unavailable and Low option is selected, Apollo
routes on a lower available layer. If the High option is selected, Apollo routes on a higher
available layer.
& Pin On the same layer that pins are on.
& Specified Any valid layer you specify in the Horizontal Layer Vertical Layer entry
fields.

Cell Placement
!Set Placement Options
Place > Placement Common Options
!Automatic Placement
Place > Design Placement
!Optimize Placement
&Area Placement
Place > Area Placement
&Search and Refine
Place > Search & Refine
&Recreate the Floorplan
Cell Placement
The placement phase of the design flow places the cells in the core area. You have the option of
weighting cell placement to optimize various factors of a design. Use Place > Placement Common
Options to set these options. After the placement options are set, place the cells and optimize the
result.
Ref [18] [19] [20] [21]

Settings for Placement Options(1)
! Optimization Mode Congestion Driven, Capacitance Driven, Timing
→ Congestion Driven Driven, Power Driven, Rail Driven, Clock Driven
! Padding
→ Master Padding
additional (%) Mesh Tree
→ -1
! Placement Constraint Rail Driven
→ ※1 high power consumption
! Location Constraint low power consumption
→ Default Values VDD
! Map Offset
→V:0H:0 VSS
※1 Select Region if you have regions.

Select Group if you have group constraints.

The optimization modes are listed below:
& Congestion: Select to distribute cell placement for minimum wire length and congestion.
& Capacitance/Length: Select to consider net-based capacitance and length constraints in cell
placement as opposed to wire length. You need to specify the constraints in the TDF file.
& Timing: Select to consider timing requirements in cell placement as opposed to wire length.
& Power: Select to consider total power consumption in cell placement as opposed to wire
length. Power-driven placement reduces dynamic power consumption by minimizing the
length of nets that have high switching frequency.
& Rail: Minimizes the average cell instance power consumption in row areas that fall in
between two PG straps. This can significantly reduce IR-drop along the standard cell PG
rails. The increase in minimum dynamic runtime power voltage increases the noise margin.
& Heat: Minimizes hot spots by reducing the density of cells with high power consumption,
thereby reducing the power density problems that create hot spots.
& Clock: Select to minimize skew of clock nets.

VDD VDD
A2 A2
X X
A1 A1
X Z X Z
X X
VSS VSS
Before padding After padding 1 unit tile

1 of 4 track is unused by pin 2 of 5 track is unused by pin
feedthroughs percentage = 25% feedthroughs percentage = 40%
additional = 15%

Master Padding:
Select to expand all instances of master cells with low porosity in order to increase the number of
available wire tracks through the cells. If you select this option, you also need to type the
additional (%) amount you want to increase or decrease the padding by. For example, if you want
to increase the padding by 5%, type 5. If you want to automate the padding, type -1. When a
master cell is padded, all standard cells of that master are padded by the same amount. For
example, if an inverter master was padded from two routing tracks to three, all inverter standard
cells in the design will be padded to three routing tracks.
User Padding:
Select to add padding defined by you. User defined padding takes precedence over automatic
padding and can relieve highly congested areas more efficiently than the Master Padding option.
If you have groups or regions, don’t forget to select the Region or Group placement constraint.

Settings for Design Placement
! Speed → According to your design, Avant! suggest medium
! Other options → Default values
2-D congestion map

The 2-D congestion map shows
the edges of the overflowing of
GR cells.
1-D congestion map
Settings for Design Placement

Typically, you can place the cells with the default options. The congestion map is generated as well
as the placement result. The congestion map contains very useful information for routing.

Congestion Map
1-D Congestion Map 2-D Congestion Map
4/3
5/4 6/5 7/5
6/5
9/8
14/12
Horizontal demand = 14
GRcell Horizontal supply = 12
1.20 Overflow = 2
0.99
0.81 0.76
0.43 6/5 8/5
∑ demand Vertical demand = 6
∑
Vertical supply = 5
capacity
Congestion Map
In the 2-D congestion map, edges of overflowing gcells are displayed in colors representing the
severity of the overflow. Each gcell has a vertical and horizontal capacity. This is the number of
unblocked tracks available for routing. Each gcell also has a vertical and horizontal demand. This
is the number of nets assigned to the gcell by the global router. The difference between the
capacity and the demand is the overflow.
The 1-D congestion maps are bar graphs along the left and bottom edges of the design. They show
the sum of the gcell demand versus the sum of the gcell capacity along a cut line. A red line marks
value 1.0. 1-D congestion map values greater than 1.0 indicate trouble. Generally, the 1-D
congestion map is not as useful as 2-D congestion map. The 1-D c9ongestion map is useful only
for small designs.

Optimize Placement
! Area placement moves standard cells from congested areas
to less congested areas.
! Search & Refine performs automatic area placement.
Optimize Placement
& After placement, find routing congestion then try to change the placement to decrease the
congestion. If the violations are extreme, go back to the floorplan step. If there are only minor
violations, use area placement and search & refine placement to improvement the placement.
& When you use area placement, the placer will attempt to reduce the congested areas by
moving standard cells away into less congested areas. The area you specify should include
congested and less congested areas, to give Apollo the space needed to move cells.
& Repeated manual area placement requires practice to learn and time to execute. The Search &
Refine placement command automatically performs area placement on a design until
user-specified termination conditions are met. The Search & Refine command never makes
your placement worse because it reverts to your initial placement if it cannot improve the
placement. You can specify areas in which Apollo runs Search & Refine using PrePlace >
Create Search & Refine Constraint.

Clock Tree Synthesis
! Specify Clock Net ! Set Timing Option
Clock > Specify Clock Net Timing Setup > Timing Options
! Define Clock Source and Waveform Delay Model → TLU
Timing Setup > Load TDF
! Optimize Placement
Clock > Auto. (Gated) Clock Tree
FF 2 FF
clk clk 1
FF 2 FF
2 2
FF FF FF FF
Clock Tree Synthesis

The skew-based timing problem is increasingly critical in deep submicron technologies. Apollo
provides the Clock Tree Synthesis (CTS) capability to help the designer to solve the problem by
distributing the clock net via multiple-level clock trees.
Before running CTS, you have to specify some timing information. First, you should specify the
clock net. Second, if you use the cell library provided by CIC, you should set the timing
option-delay model as TLU. Third, you should define the clock source and waveform in TDF file
and load it. After those described above are prepared completely, use Clock > Auto. (Gated) Clock
Tree to create the clock trees.
Ref [22] [23] [24]

Define Clock Source and Waveform
Syntax: tdfSetClkWaveform “waveFormName” period rise fall “objList”
Example: tdfSetClkWaveform “clock" 10 0 5 “ipad.CIN"
clk
ipad CIN to core
source point
clock
0 5 10
Define Clock Source and Waveform

The clock source must be one of the following
& Top-level logical input port
& Output port of a cell instance
& Clock input of a flip-flop or latch (rarely used)
The source point in the example is a hierarchical name. It means the source point is “CIN” pin of
the pad instance “ipad”.
Ref [25]

Precise Definition of Skew
Skew = max(dsource, sync + dphase) − min(dsource, sync + dphase)
FF sync point
FF
FF
The clock must arrive
FF here early in order to
FF
Source reach all FF at the
point same time.
FF Macro FF
Delay FF
d source,sync FF
d phase
Precise Definition of Skew

& Starting from a set of clock sinks of flip-flops or macro cells, the clock tree is synthesized
from the bottom-up. The clock tree is formed such that the skew is minimized. This brings up
an important point: skew to where? The skew is defined as the difference between the earliest
and the latest arrival times at the sync pins in the design.
& Usually, the phase delay for macro blocks is defined in the cell library with the CLF function
definePortPhaseDelay.
& All flip-flop or latch clock input ports are already sync pins with a phase delay of zero by
default. You can add more sync pins by applying dbDefineSyncPin scheme function.

Settings for Auto Clock Tree(1)
! Net Name(s) → your_clock_net_name(s)
! Buffer(s) → buffd1, buffd3, buffd7, buffda
! Name Separator → !
! Soft Configuration Guide → leave blank
! Build strategy → default values
! Execute ECO Placement → Enable
! High Fanout Net Mode → Enable
Buffer Naming Style ClockNetName!CellMasterName!BufferLevel!BufferNumber
Net Naming Style ClockNetName!BufferLevel!BufferNumber
clk!buffda!2!0
clk!2!0
clk!buffda!1!0 clk!buffda!2!1
clk clk!1!0 clk!2!1
clk!buffda!2!2
clk!2!2

& Type the names of the master buffer cells that you want to use in the tree in Buffer(s) field.
Separate the names with commas.
& Type the name of separator used in naming new buffers in Name Separator field. If you use
the default !, the naming style of the buffers is ClockNetName!CellMasterName!BufferLevel!k
where k is a number between zero and the number of buffers. The naming style for the output
net at the buffers is ClockNetName!BufferLevel!k where k is a number between zero and the
number of buffers.
& Select High Fanout Net Mode to automatically place buffer cells in a multiple-level net tree
for boosting the signal after net synthesis. The skew priority will be lower if you enable this
option.

! Target Goals → PhaseDelay: 0.0 max Skew: 0.0
! Operational Mode → Set Explicit Synchronous Points for all macros
SyncPhase: nonInvertRise
! Other options → Default values
FF FF
FF FF
Source Source
point point
FF FF
Macro FF Macro FF
Delay FF Delay FF
FF FF
Set Explicit Synchronous Points Set Explicit Synchronous Points

for all macros for all inputs

& Specify the maximum or exact phase delay you want of the synthesized clock tree in the
Target Goals-PhaseDelay field. A Phase Delay of 0.0 means a value of infinity. If you specify
0.0 with max mode, GCTS assigns the least cost to the smallest phase delay.
& Specify the maximum skew in Target Goals-Skew field. A Skew of 0.0 means a value of
infinity. If you specify 0.0, GCTS assigns the least cost to the smallest skew. On the other
hand, if you specify a very small target skew, such as 0.01, GCTS heavily biases the solution
with the smallest skew.
& In Operation Mode field, select all macros to synchronize the arrival of a clock signal at
macro input ports in a clock tree. The default (selected) sets all the macros as synchronous
points. Or you can select all inputs to synchronize the arrival of a clock signal at all non-clock
input ports in a clock tree.
& The nonInvertRise SyncPhase means the unate state at the input port is the same as the unate
state at the clock source and the clock signal is rising

Add Filler
!Add Core Filler
Filler
VDD
Cell Cell
PostPlace > Add Core Fillers VSS
!Add Pad Filler IO Filler Overlap
PostPlace > Add Pad Fillers PAD PAD
! Master Cell Name(s) ! Filler

→ feedth → iofeedth002,iofeedth046,iofeedth864
! respect placement blockage ! Overlap Filler
→ Enable → iofeedth002,iofeedth046,iofeedth864
between std cells only ! Side
→ Enable → left right bottom top
! No Filler Under Mx
→ M1
Add Filler
& Add core filler for better electrical characteristic.
& It is necessary to add pad filler because the pad cells are not placed close to each other, there’s
a gap between a pair of pad cells. The pad fillers connect the P/G nets of the pad cells. If you
do not add pad fillers, the pad cells will be lack of power.
& The cell name of the core filler in the cell library provided by CIC is feedth.
& The cell names of the pad fillers in the cell library provided by CIC are iofeedth002,
iofeedth046, and iofeedth864.
& You should specify the pad filler that can be overlapped as well as the non-overlapped filler;
if not, there maybe some gap leaving blank between pad cells.
Ref [26] [27]

Routing
!Route Standard Cell P/G Pins
PreRoute > Standard Cells
!Route the Clock Nets
load “CTS.RouteNetGroup.cmd”
!Auto Route
Route > Auto Route
!Verify Routing
!Optimize Routing
Route > Optimize Routing
Routing
After the cells are placed and the clock trees are synthesized, you can start routing. A sample
routing design flow is presented below:
& Route the P/G pins of the standard cells to the pre-routed P/G ring or strap to make sure that
the P/G ports of all standard cells are connected.
& Route the clock net before all other signals are routed.
& Using Route > Auto Route to route all the other signals.
& Verify the result of routing and make sure all signals are routed successfully.
& Optimize routing to reduce the wire length and the number of vias.
Ref [28] [29] [30]

Route Standard Cell P/G Pins
! Connect
→ Horizontal
! Nets
→ PG
! Select Pins Automatically and Route
→ All
! Other Options
→ Default values
Route Standard Cell P/G Pins

Connects power and ground pins in the standard cells to the power and ground rings or straps, and
connects power and ground rails in the standard cells. If the top cell does not have pads, you can
select Extend to boundaries and generate pins option. This option creates a power and ground
extension wire to the cell boundary and generates a power and ground pin if the following
conditions are met:
& The power and ground pin is not already connected to power and ground in the direction
where Apollo would create the extension wire.
& Creating the power and ground extension wire does not cause a DRC violation.
The pin is marked as fixed to prevent it from being moved by placement and routing operations.
In a typical design, you can apply the default settings of options.

Route the Clock Nets
load “CTS.RouteNetGroup.cmd”
clk
clk!1!0
clk!1!1
.
.
clk!2!0
clk!2!1
.
.
clk!3!0
.
.
Route the Clock Nets

The Auto (Gated) Clock Tree Synthesis automatically generates the script file for routing the
synthesized clock nets. The script will set some options and route the clock nets automatically. By
default, the file name is CTS.RouteNetGroup.cmd”. The only one thing you should do is load the
file in the input window. Then the clock nets are routed as illustrated above.
You can select nets that begin with the original clock net name. The selected nets will be
highlighted so you can see the clock routing result easily.

Auto Route-Global Route
Global Route → Track Assignment → Detail Route
GRcell
Core Area
Assigned nets – available wire track = overflow
(demand)
Auto Route-Global Route

Global routing maps general pathways through the design for each un-routed net. The global router
uses a two-dimensional array of global routing (GR) cells to model the demand and capacity of
global routing. Apollo uses the average height of the standard cells to create the height and width
of each GR cell. During global routing, Apollo assigns nets to the GR cells through which they will
pass. For each GR cell, routing capacity is calculated according to the blockages, pins, and routing
tracks inside the cell. Although global routing does not assign the nets to the actual wire tracks, it
notes the number of nets assigned to each GR cell. Apollo calculates the demand for wire tracks in
each GR cell and reports the overflows, which is the amount of wire tracks still needed after
Apollo assigns nets to the available wire tracks in a GR cell. Apollo might reduce overflows by
detouring nets around congested areas and increasing the wire length.
The global router maps pathways for signal and clock nets. If a wire is pre-routed, Apollo checks
to see whether it is connected completely. If the net is connected completely, Apollo treats the net
as a blockage. If the net is connected partially, Apollo connects all parts of the net.
Apollo treats power and ground nets as blockages.
If you run global routing, any previously created global routing is deleted.

Assign Track & Detail Route
! Phase → global, track assign, detail
! Search Repair Loop → 0
! Global Route Speed → medium
! Global Route Turbo Mode → Enable Speed: 1
GRcells
! Routes the design using 5 by 5 switch
boxes. Every net is routed, even if
this causes violations.
! Routes the design again using 9 by 9
switch box. Again, every net is
routed, even if it causes violations.
5x5 switch box
Assign Track & Detail Route

& Because the detail router routes a small area at a time, it cannot make long routes straight.
Before running the detail router, you need to specify which track within each global route cell
is used for each net. Track assignment operates on the entire design at once, so it can make
long routes straight and reduce the number of vias. After track assignment finishes, all nets
are routed but not very carefully. There are many violations, particularly where the routing
connects to pins. The detail router corrects the violations.
& Detail routing uses the general pathways suggested by global routing and track assignment to
place paths and contacts in order to route the nets. The detail router routes switch boxes one at
a time. A switch box is a rectangular area containing an integral number of global routing
cells. Each switch box overlaps with its neighbor by one global routing cell.
& The size of the switch box is determined automatically.

Verify Routing
!Check DRC Violations
DRC violations appears in message/input area.
If Total Violations are not 0
!Search & Repair

Route > Search & Repair
Verify Routing
& After detail routing, the total DRC violations are shown in message/input area. If the number
of total violations are not 0, use Route > Search & Repair to eliminate the violations.
& Search & Repair command concentrates on areas that contain violations. It does this by
building a switch box centered around each violation (or group of violations) and re-routing it.
The size of each switch box is determined automatically.
Ref [31]

Optimize Routing
Using Query > List PR Summary! to query the statistics.
Signal Wiring Statistics: Signal Wiring Statistics:

metal1 Wire Length: 307.05 metal1 Wire Length: 309.40
============================= =============================
Total Wire Length: 96605.00 Total Wire Length: 93884.80
Number of via1 Contacts: 3543 Number of via1 Contacts: 3531
============================= =============================
Total Number of Contacts: 8570 Total Number of Contacts: 7057
Optimize Routing
After all violations have been eliminated, use Route > Optimize Routing to improve routing quality
by reducing wire length and eliminating vias. Optimization will not change the die size of the
design.

Add Text for Timemill(1)
• Key in the following functions in input area:
dbAllowToAddPGIOText #t
dbAddIOText (geGetEditCell) "*" "*" 43 50
• Set window and layer options for adding P/G texts:
Window Options%Visible Pin Instances%pad cell
Window Options%View Level%20
Layer Panel%Set all layers non-visible except
layer 43 (METAL3)
• Create IO P/G texts using Create > Text
Layer % 43 Height % 50

Add Text for Timemill(2)
P/G Pads Added Texts
pvd(0)a extVDD(VSS)
pvd(0)b
pvd(0)a extVDD(VSS)ac
pvd(0)d extVDD(VSS)dc
pvd(0)i
pvd(0)f

Fill Notches and Gaps
!Route Utility > Fill Gap/Notch
Gap Notch
Net1 Net1 Net2
Fill Notches and Gaps

& Apollo can fill gaps and notches in net topologies to eliminate same-net spacing violations.
The Route > Fill Gap/Notch command create FILL view cell (cellName.FILL).
& Notch and gap cells are only valid if their time stamps are later than the design cell time
stamp. You must not even save the design cell after notch and gap filling. To fill notches and
gap, save the design cell first, then perform notch and gap filling and close the design cell
without saving. If you edit the design, notch and gap filling must be re-run.
& To view the gap and notch cells along with the design cell, enter the scheme command
geSetViewCell “cellName.FILL” #t and to disable the display, enter geSetViewCell
“cellName.FILL” #f.
Ref [32]

DRC/LVS Check
!DRC
Verify > DRC
!LVS
Verify > LVS
!Load Error Cell
Verify > Init Errors - Load Error Cell
!Verify > List Error Summary !
!Using commands of Verify > Show Errors
group to check the errors
DRC/LVS Check
The design rule checking (DRC) operation checks for design rule violations in the current design,
including the following:
& Objects with widths less than the minimum width set for the layer.
& Notches smaller than the minimum distance required between objects on the same layer.
& Same-layer objects closer together than the minimum spacing set for the layer.
& Different-layer objects closer together than the minimum spacing set for the two layers.
The DRC operation creates an error cell, from which you can request a summary of errors or
highlight errors of specific types. By default, the cell name is chip_drc.err.
The LVS operation checks for inconsistencies between the schematic and the physical layout of the
current design, including floating ports (pins not connected to a wire segment), floating nets (wire
segments not connected to a pin), shorts (nets connected that should not be), and opens (nets not
connected that should be).
The LVS operation creates an error cell, from which you can request a summary of errors or
highlight errors of specific types. By default, the cell name is chip_lvs.err.
Ref [33] [34]

Export Data
!Output > Stream Out in Milkyway
& Stream File Name → your_desired_name.gds
& Library Name → your_lib_name
& Child Extraction Depth → 20
& Convert → Specified Cell → your_top_cell
& Convert Reference Lib Child Cells → Enable
& Flatten → Devices Device Arrays
& Pin/Net Options > Output Net → Enable
& Other options → Default values
Layer File
Syntax : Avant!ObjType[Avant!NetType] Avant!Layer GDSIILayer GDSIIDataType
Example : A 54 23 0
Converts Avant! layer 54 to GDSII Stream layer 23 and data type 0
Export Data
Use Output > Stream Out command in Milkyway to export your design data to GDSII stream file.
Ref [35]

Post-layout Jobs
Post-layout Verification
GDSII layout
(Dracula DRC)
Post-layout Timing Analysis

Tape Out (Timemill Simulation)
DRC Overview(1)
DRC checks the layout geometries against fabrication rules
width check area check
WIDTH MT1 LT 0.5 OUT M1W1 59 AREA CO RANGE 0.159 0.161 COTMP
NOT CO COTMP COW1B OUTPUT COW1B 59
If the width of this
geometric is less than
design rule, report this
DRC error.
If the area of this geometric is not

outside spacing check in this range, report this DRC
error.
EXT[H] MT1 LT 0.45 OUT M1S1 59
If the spacing between

these two geometries is
less than design rule,
report this DRC error.

DRC Overview(2)
inside spacing check enclosure spacing check
geom1
geom2 geom2
geom1
If the inside spacing from If the enclosure spacing from

geom1 to geom2 is less than geom1 to geom2 is less than
design rule, report this DRC design rule, report this DRC
error. error.
DRC for Cell-based Design(1)

! For TSMC 0.35um 1P4M Technology.
! In pure cell-based design ( no full customer block mixed ),
only following DRC errors are needed to be take care :
L ay er N am e D racu la E rro r N u m b er D esig n R u le

M ETAL1 M 1W 1 M E T A L 1 w id th < 0 .5 u m
M ETAL1 M 1S1 M E T A L 1 to M E T A L 1 sp ac in g < 0 .4 5 u m
M ETAL1 M 1S2S、 M 1S2D M E T A L 1 to w id e M E T A L 1 sp ac in g < 0 .8 u m
V IA 1 V 1W 1A V IA 1 w id th < 0 .5 u m
V IA 1 V 1S1 V IA 1 to V IA 1 sp ac in g < 0 .4 5 u m
V IA 1 V 1E1 M E T A L 1 e n clo se V IA 1 < 0 .2 u m

L ayer N am e D racula E rror N u m b er D esig n R ule

M ETAL2 M 2W 1 M E T A L 2 w idth < 0.6um
M ETAL2 M 2S 1 M E T A L 2 to M E T A L 2 sp acing < 0 .5 um
M ETAL2 M 2E 1 M E T A L 2 enclose V IA 1 < 0.15u m
M ETAL2 M 2S 2 S 、 M 2S 2 D M E T A L 2 to w ide M E T A L 2 spacing < 0.8um
V IA 2 V 2W 1 A V IA 2 w idth < 0.5u m
V IA 2 V 2S 1 V IA 2 to V IA 2 spacin g < 0 .4 5um
V IA 2 V 2E 1 M E T A L 2 enclose V IA 2 < 0.2um
M ETAL3 M 3W 1 M E T A L 3 w idth < 0.6um
M ETAL3 M 3S 1 M E T A L 3 to M E T A L 3 sp acing < 0 .5 um
M ETAL3 M 3E 1 M E T A L 3 enclose V IA 2 < 0.15u m
M ETAL3 M 3S 2 S 、 M 3S 2 D M E T A L 3 to w ide M E T A L 3 spacing < 0.8um
Layer Name Dracula Error Number Design Rule

VIA3 V3W1A VIA3 width < 0.5um
VIA3 V3S1 VIA3 to VIA3 spacing < 0.45um
VIA3 V3E1 METAL3 enclose VIA3 < 0.2um
METAL4 M4W1 METAL4 width < 0.6um
METAL4 M4S1 METAL4 to METAL4 spacing < 0.6um
METAL4 M4E1 METAL4 enclose VIA3 < 0.15um
METAL4 M4S2S、M4S2D METAL4 to wide METAL4 spacing < 0.8um

DRC Error Explanation(1)
Dracula Error Number : M1W1
Dracula Explanation : WIDTH M1 LT 0.5
Metal1 width is less than 0.5um.
Note
Other analogous DRC violation : M2W1, M3W1, M4W1

Dracula Error Number : M1S1
Dracula Explanation : EXT[H] M1 LT 0.45
Metal1 to Metal1 spacing is less than 0.45um.
Note
Other analogous DRC violation : M2S1, M3S1, M4S1

Dracula Error Number : M1S2S, M1S2D
Dracula Explanation : EXT M1SF S1 LT 0.8
width >= 10um..
Metal1 to wide Metal1 (larger than 10um) spacing is less than 0.8um.
Note
Other analogous DRC violation : M2S2S, M2S2D, M3S2S, M3S2D, M4S2S, M4S2D

Dracula Error Number : V1W1
Dracula Explanation : WIDTH VIA1 LT 0.5
VIA1 width is less

than 0.5um.
Note
Other analogous DRC violation : V2W1, V3W1

Dracula Error Number : V1S1
Dracula Explanation : EXT VIA1 LT 0.45
VDD VDD
VIA1 to VIA1 spacing is less than 0.45um.

Note
Other analogous DRC violation : V2S1, V3S1

Dracula Error Number : V1E1
Dracula Explanation : ENC[T] VIA1 M1 LT 0.2
Metal1 enclose
VIA1 spacing is
less than 0.2um.
Note
Other analogous DRC violation : M2E1, V2E1, M3E1, V3E1, M4E1

Dracula DRC Flow
1
DRC Command File
2
PDRACULA Command File Errors
Compile Dracula command file
Run Files
3 4
Text report ( *.sum, *.drc )

Submit the Job
and Graphic Reports
Compile Dracula Command File

Unix% PDRACULA
**************************************************************************
*/N* DRACULA3 ( REV. 4.51.0398 / SUN-4 S5R4 /GENDATE: 19-MAR-98/14 )
*** ( Copyright 1995, Cadence ) ***
*/N* EXEC TIME =09:47:07 DATE = 7-MAY-99 HOSTNAME = unix
**************************************************************************
:/get drac035s3V4Ma.drc
/get drac035s3V4Ma .drc n
:/finish
/finish
** NOTE : PARTIAL DELETIONS OF FILES WILL BE PERFORMED
** CREATING : COMMAND FILE : jxrun.com
** NOTE : ALL TEMPORARY DATA FILES CREATED BY THIS JOB WILL BE DELETED

Submit the Job
** NOTE : THIS JOB HAS 191 STAGES
END OF DRACULA COMPILATIONS
* 0.136 Mbytes allocated to the current process.

* 0.000 Mbytes is still in use.
* THE END OF PROGRAM
Unix% jxrun.com
jxrun.com > drc.log
drc .log
DRC Summary Report

avt.sum
avt.sum file
------------------- ALL ERROR CELLS LISTING -------------------
BPMO64 BNMO64 BPOD64 BNOD64 NWW159
. . . . . .
------------------- OUTPUT CELL SUMMARY --------------------
CELL-NAME LAYER # ---------- W I N D O W -----------
M1S1 48/ 0 423.52 423.52 1494.07 1220.47

M1S2S 48/ 0 435.90 435.90 1481.70 1208.10
M2W1 50/ 0 1136.65 723.75 1145.75 724.25
. . . . . .
********** INPUT COMMANDS LISTING **********

. . . . . .

What Introduce After Place&Route?
Interconnection wire’s parasitic capacitance
M1 to substrate
M2 capacitance
M1 to M1
capacitance
M1
M1 to M2
capacitance
VDD VDD
VSS VSS
What Introduce After Place&Route?

Interconnection wires’ parasitic resistance
M2 M2 parasitic resistance
VIA
M1 VIA parasitic resistance
VDD VDD M1 parasitic resistance
VSS VSS

Pre-layout And Post-layout Design
pre-layout
post-layout
What is Post-layout Simulation?

! After placement & routing
– The interconnect will introduce extra signal delay.
– The extra signal delay may change the circuit’s
behavior. Therefore, the circuit behavior must be
verified again by post-layout simulation.
parasitic resistance & capacitance will introduce extra signal delay

Why Post-layout Simulation?
clock skew
....
critical path delay
clk
critical path delay data
... . . .data
Why Post-layout Simulation?

1.0u 15-30%
25-45%
0.8u
0.5u 35-60%
0.35u 40-75%
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 ns

Gate delay: short net Gate delay: long net
Wire delay: short net Wire delay: long net

Post-layout Timing Analysis Flow
Gate-level
Netlist
Gate-level
Analysis
Tr-level post-layout Layout

timing analysis Delay
Calculation
Extraction
Tr. Netlist
RC Network
RC Network
Tr-level
Gate-level post-layout
Analysis
timing analysis
Transistor-level Post-layout Simulation

layout
netlist/parasitic Dracula LPE/PRE

extraction
SPICE netlist
simulation Post-layout
TimeMill/PowerMill
pattern simulation
simulation
result

Dracula LPE/PRE
VDD
LPE z2
(layout parasitic extraction)
VSS i z1
VDD VDD z2
PRE
(parasitic resistance extraction)
i zn z1
VSS VSS
Introduction to EPIC Tools

! EPIC tools is a set of tools targeting on
transistor level power, timing and reliability
simulation or analysis.
! The EPIC family includes
– Timemill : Timing analysis
– Powrmill : Power analysis
– Pathmill : Static timing analysis
– Railmill : Reliability analysis
– AMPS : Gate sizing for power optimization

What Is Timemill
!Timemill is a transistor- level timing
simulation tool for digital and mixed signal
CMOS and BiCMOS designs.
!Timemill handles voltage simulation and
timing check.
! Simulation is event driven, targeting
between SPICE ( circuit simulator ) and
Verilog ( logic simulator ).
Timemill Post-layout Simulation Flow

1) Stream out your design.
2) Use Dracula LPE to extract the SPICE netlist.
3) Use spice2e to translate SPICE netlist to EPIC
netlist format.
4) Generate aliasfile (I/O label vs. LPE node number).
5) Generate Timemill technology file.
6) Generate input stimulus and configuration file.
7) Perform post-layout simulation.
8) Check simulation result.

Cell Based Design Timemill Flow
prepare
ftp layout to CIC’s account
layout
replace qepiclpe35 : replace cell layout view and netlist extraction.

layout view
generate gentech : generate technology file for EPIC tools

technology file
Edit Files edit stimulus file and configuration commands
TimeMill
qtimemill : perform simulation
PowerMill
check result You can use qstat to check the queue status
Prepare for Post-layout Simulation
! Apply for a CIC account

&http://www.cic.edu.tw ⇒ CIC 帳號線上申請系統
&Fill in your personal data and your request.
! Install “identd” program
&This program is used to identify yourself when you
log into CIC’s account from remote machine.
! Put your layout file to CIC’s account

Replace Layout View
! Command Syntax
Unix% qepiclpe35 gds_file_name
output_netlist_file_name [all|core|io
[all|core|io] |io ]
options : replace all cell | core cell | io cell
! Important Output Files
& epiclpe.log : layout replace log file
& gentech.ctl : gentech control file
& nodename : a text file which stores those nodes
you can observe during post-layout
simulation
& output netlist file
Generate Timemill Technology File

!Command Syntax
Unix% qgentech - c gentech_control_file
- f hspice - t output_techfile_name - q
! Input files
& gentech control file % gentech.ctl
& spice model file % ls35_4_1.l
! Important output files
& output technology file which contains a large amount of
Hspice simulation result.
& log file % gentech.log

Simulation Pattern % vec format
stimulus file
(is=vec)(en=input.dat)(ot=CLOCK,START,IN<7:0>);
input pattern file input.dat

; time clock start in<7:0>
radix 1 1 44
io i i ii
high 3.3
low 0.0
25 0 0 xx
50 1 0 xx
75 0 0 xx
. . . . .
Simulation Pattern % nsvt format

stimulus file
(is=nsvt)(en=input.dat)(ot=CLOCK,START,IN<7:0>);
input pattern file input.dat

; time clock start in<7:0>
radix 1 1 44
io i i ii
period 25
high 3.3
low 0.0
0 0 xx
1 0 xx
0 0 xx
. . . . .

Simulation Pattern from Verilog test bench
Verilog test bench file
integer outf;
initial begin
outf = $fopen("input.dat");
. . . . .
$fclose(outf);
$finish;
end
always @(sys_clock or start or in)

$fdisplay(outf,"%t %b %b %h",$time,sys_clock,start,in);
. . . . .
Timemill Configuration File

Example Timemill_configuration file
bus_notation [ : ]
print_node ADRS[0]
print_node CLK
print_node DATA[0]
. . . . . .
set_vdd vdd
set_gnd gnd
set_gnd extGnd
set_vdd extVdd
nodename file
ADRS[0]
ADRS[1]
. . . . . .
CLK
DATA[0]
. . . . . .

Some Note about nodename File
. . . . . . . . . . . .
TOP.CNTR.XREG_load_en print_node TOP.CNTR.XREG_load_en
TOP.CNTR.YREG_load_en print_node TOP.CNTR.YREG_load_en
TOP.CNTR.addr_mode[1] print_node TOP.CNTR.addr_mode[1]
TOP.CNTR.addr_mode[2] print_node TOP.CNTR.addr_mode[2]
TOP.CNTR.addr_mode[3] replace print_node TOP.CNTR.addr_mode[3]
. . . . . . . . . . . .
TOP
TOP CNTR
REGF
XREG_load_en
CNTR ALU REGF

ALU
Timemill Post-Layout Simulation

!Command Syntax
Unix% qtimemill -n netlist_file stimulus_file - o
simulation_result -c config_file -p tech_file -t
simulation_time
Example : qtimemill -n my_chip.net stimuli -o my_sim.out -
c config_file -p my_chip.tech -t 36000
!Important output files

& simulation result file % xxx.out
& log file % <user_name>T.exxxx

Simulation Corner Condition
Simulate process varation
• FF : fast-fast
• TT : typical-typical
gentech.ctl • SS : slow-slow
%lib
.lib "ls35_4_1.l" TT
. . . . . .
%corner ; specify temperature and supply voltage
temperature 25 ; in units of C, the process temperature
voltage 3.3 ; in units of volts, the supply voltage
. . . . . .
Simulate chip working situation

• working temperature
• supply voltage
View Simulation Result % nWave

!NOVAS nWave
&A waveform viewer which support Timemill
output waveform format.
! Environment setup
unix% set path=($path /usr/debussy/bin)
unix% setenv LM_LICENSE_FILE 5219@license_server_name
! Starting nWave
unix% nWave &

Load Simulation Result % nWave
File ⇒ Open
Select Signals % nWave

Signals ⇒ Get Signals ...

Check Simulation Result % nWave
Powermill % Power Analysis

! The procedure to use Powermill is the same as
Timemill, except the following :
&additional line must be added into configuration file :
report_node_powr <node_name>
example : report_node_powr vdd
&use qpowrmill command instead of qtimemill
example : qpowrmill -n my_chip.net …...

Power Analysis Result
! The power analysis result is stored in
Powermill simulation log (xxx.log) file
. . . . . .
Current information calculated over the intervals:
0.00000e+00 - 1.00010e+03 ns
Node: vdd
Average current : -3.53355e+05 uA
RMS current : 3.53388e+05 uA
Current peak #1 : -4.54061e+05 uA at 6.78400e+02 ns

Current peak #2 : -4.34973e+05 uA at 4.00000e-01 ns
. . . . . .

Apollo Fundamentals Laboratory Exercise
Apollo version 1999.4

Lab 1
Starting the Graphics Interface
1. Log into the Sun workstation with the user name and password printed on the right side of the
keyboard.
2. After CDE is initialized, open a Terminal window.
3. Key in source /cad2/lab/APOLLO/setup_Apollo_lab.csh under command prompt
to delete all previous files, setup necessary environment variables, and copy lab data into your
home directory.
4. Log out from CDE.
5. Log into the workstation and open a Terminal window again.
6. Key in cd ~/lab1 under command prompt to change the directory to lab1.
7. Key in Apollo & under command prompt to invoke Apollo. The result is as shown in Fig. 1.
Fig. 1
8. Select “Library % Open” from menu banner, and fill the fields in Open Library form as shown
below (Use the left mouse button to select commands or objects). And then click OK. The
message window will show “Open library successfully”.
Library Name c4msram32x4s_fr

Library Path
9. Select “Cell % Open” from menu banner, Open Cell form will be shown. This time we click
Browse… button in Open Cell form to select the cell we want to open. The Browse Cell form
now appears.
10. Click c4msram32x4s in the left column of Browse Cell form, and then it will be displayed in

Cell Name field of Open Cell form.
11. Click OK button of Open Cell form, and the cell window appears.
12. Move your cursor on the cell window to see if the current coordinate in the upper-left corner
changes when you move the cursor.
13. Hold the cursor over the view command short-cut button to display a tag that tells you what the
button does.
14. Find “zoom out 2X” button and click it.
15. Find “previous view” button and click it.
16. Find “next view “ button and click it.
17. Find “zoom in 2X” button and click it.
18. Find “zoom to area” button and enter diagonal corners of a rectangle of the widow.
19. Find “fit cell” button and click it.
20. Find “fit with margin” and click it (You can also type the hotkey “f” to fit with margin).
21. Key in load “zo1.lab1” in the message/input area.
22. Click “Select-point” button and then click the text VDD in the window. Is the text VDD
highlighted?
23. Click “Query-object” button. Check what is shown in the message/input area.
24. Click “Deselect-all” button.
25. Click “Ruler” button. Can you use ruler to measure the length of the text VDD?
26. Select “Cell % Create” from menu banner and click the Help button in the Create Cell form. The
online document appears.
27. Close Documentation Browser and cancel Create Cell form.
28. Key in help “geCreateCell” in message/input area. The same online document as above
appears again.
29. Select “Tools % Quit” to quit from Apollo.

Lab2
Library structure and elements
1. Key in cd ~/lab2 under command prompt to change the directory to lab2.
2. Key in Apollo & under command prompt to invoke Apollo.
3. Select “Library % Open” from menu banner, and fill the fields in Open Library form as shown
below.
Library Name lab2

Library Path
4. Select “Cell % Open” from menu banner, and fill the fields in Open Cell form as shown below.
And then click OK. The cell window appears. What view is opened now? Check the upper left
corner of the window to find the answer.
Cell Name ad01d0
5. Using “Query-object” button to find the following answers: 1) What is the layer name and
number of the rectangle with red border? 2) What is the layer name and number of the light blue
polygon? 3) What is the layer name and number of the dark blue rectangle? 4) What is the layer
name and number of the rectangle with yellow dashed border?
6. Select “Cell % Close”, “Close Window” form appears. Click “Discard All” button and click OK
to close the cell window without save.
And then click OK.
Cell Name ad01d0.FRAM
8. Click the “Layer panel” button and “Layer Panel” window appears. The PRBoundary layer is
covered completely by boundary layer. Show PRBoundary layer in the cell window by disabling
the visibility of boundary layer.
9. Use Ruler to measure the width and height of this cell. Write down the cell width and height.
10. Select “Cell % Close”, “Close Window” form appears. Click “Discard All” button and click OK
to close the cell window without save.
And then click OK.
Cell Name unitTile

12. Use Ruler to measure the width and height of this cell. Is the height is the same as that you just
write down in step 9? Is the width you just write down a multiple of unitTile’s width?
13. Click “Window Options” button. Select wire track in Visible Objects group and then click Apply
and Redraw. The METAL1, METAL2, METAL3, METAL4 tracks all appear.
14. Select “Tools % Quit” to quit from Apollo.

Lab 3
Data Preparation / Import Design / Floor planning
From Lab3 to Lab6, you transfer the gate level net list into the verified gds2 layout.
The design hierarchy is shown below:
Hierarchy 1 Hierarchy 2 Hierarchy 3
IO pads
(pc3d01, pc3o05…)
mem (32x4 synchronous sram)
chip
ctrl (control signal generator)
The top module of the design.
lab mul (8x8 pipeline multiplier)
div (16/5 divider)
outstage (output buffers)
The IO pads of the design are listed below:
Type Master Name Number
Input pc3d01 6
Ouput pc3o05 5
Core power/ground
pvdb/pv0b 1/1
IO DC power/ground
IO AC power/ground pcda/pv0a 1/1
Corner p14frell/p14frelr/p14freul/p14freur 1/1/1/1
1. Change the directory to lab3.

Unix% cd ~/lab3
2. Invoke Apollo.
Unix% Apollo &
3. Choose “Tools % Data Prep”.
4. Choose “Netlist In % Verilog In”.
5. Complete the form as shown below and click OK.

Verilog File Name chip.vg
Verilog List File Name
Library Name lab3
Tech File Name cic_avt35a.tf
HDL To GDSII Map File
Bus Naming Style [%d]
Verilog Model Directory
Model File Extension
Net Name for 1’b0 VSS
Net Name for 1’b1 VDD
Hierarchy Separator .
Bus Name Append
Multiple PG Nets Disable
Set Case Sensitive Enable
No Backslash Insersion to avoid Hier Name Collisions Enable
Remove First Backslash Of All Escaped Identifiers Disable
Create Bus For Undefined Cells From Connection
6. A library named lab3 is created. Now the library contains only NET view.
7. Move the cursor to Terminal window, type ls lab3, you should see the subdirectory NETL.
8. Choose “Library % Add Ref”.
9. Complete the form as shown and click Apply.
Library Name lab3

Ref Library Name cic35_core_v1.0
Library Name lab3

Ref Library Name cic35_io_v1.0
11. Complete the form as shown and click OK.
Library Name lab3

Ref Library Name c4msram32x4s_fr
12. Choose “Netlist In % Expand”.

13. Complete the form as shown and click Global Net Options.

Library Name lab3
Unexpanded Cell Name chip.NETL
Expanded Cell Name chip.EXP
Precede hierarchical names with “/” Disable
Expand netlist cell with no instance Enable
Stop at FRAM view cells only Disable
Print out net has a pin but no connections Disable
Mode Add
Net Name VDD
Port Pattern VDD
15. Complete the form as shown and click Apply. Then click Hide.
Mode Add
Net Name VSS
Port Pattern VSS
16. Click OK, the EXP view will be created.

17. Choose “Tools % ApolloII”.
18. Choose “Library % Open”.
Library Name lab3

Library Path
20. Choose “Cell % Create”.

21. Complete the form as shown and click OK. A cell window appears.
Cell Name chip
22. Choose “Design Setup % Bind Netlist”.

Net Name chip.EXP
24. Press “f” on the cell window.

25. Choose “PreRoute % Connect Ports to P/G”.

26. Connect VDD to macro and core cells. Complete the form as shown and click Apply.
Net Name VDD

Port Pattern VDD
Cell Master Pattern .*
Cell Instance Pattern .*
Net Type Power
Net SubType Core
Cell Types Macro
Std / Module Cell
Update Tie Up/Down Disable
Mode Connect
27. 2 dialog boxes appear. Click OK on both boxes.

28. Connect VSS to macro and core cells. Complete the form as shown and click Apply.
Net Name VSS

Port Pattern VSS
Cell Master Pattern .*
Net Type Ground
Net SubType Core
Cell Types Macro
Std / Module Cell
Mode Connect
29. 2 dialog boxes appear. Click OK on both boxes.

30. Connect VDD to core power pad (pvdb). Complete the form as shown and click Apply.
Net Name VDD
Port Pattern PAD
Cell Master Pattern pvdb
Net Type Power
Net SubType Core
Pad
Cell Types Pad
Mode Connect

31. A dialog box appears. Click OK on it.
32. Connect VDD to core ground pad (pv0b). Complete the form as shown and click OK.
Net Name VSS

Port Pattern PAD
Cell Master Pattern pv0b
Net Type Ground
Net SubType Core
Pad
Cell Types Pad
Update Tie Up/Down Enable
Mode Connect
33. A dialog box appears. Click OK on it.

34. The Input/Message area shows the following messages.
35. Choose “Cell % Save”.

36. Choose “Cell % Save As”.
Cell Name chip_conn_pg

overwrite Enable
38. Choose “Design Setup % Load TDF”.

39. Complete the form as shown and click OK. The IO constraints are loaded.
TDF File Name io.tdf
40. Choose “Design Setup % Set Up Floorplan”.

Control Param aspect ratio

Core Utilization 0.9
Row/Core Ratio 1
Core Aspect Ratio(H/W) 1
Horizontal Row Enable
Double Back Enable
Start First Row Disable
Flip First Row Enable
Core To Left 100
Core To Right 100
Core To Bottom 100
Core To Top 100
Keep Macro Place Disable
Keep Std Cell Place Disable
Min Pad Height Enable
Pad Limit Disable
42. Choose “Modify % Move”.

43. Complete the form as shown.
Snap None
44. In message/input area, type load “zo1.11”.

45. Click (0.200, 1522.600) with the left mouse button to select the macro.
46. Click (0.000, 1522.750) with the left mouse button to select the reference point.
47. In message/input area, type load “zo2.11”.
48. Click (472.300, 913.300) with the left mouse button to select the destination point.
49. Press ESC to end the move command.
50. The Ram Macro is moved to the upper-left corner of the core area.
51. Choose “Cell % Save”
52. Choose “Tools % Quit” to quit from Apollo.

Lab4
Group & Region / Pre-route Nets / Cell Placement
Unix% cd ~/lab4
2. Invoke Apollo.
Unix% Apollo &
Library Name lab4

Library Path
5. Choose “Cell % Open”.

Cell Name chip
7. Choose “Design Setup % Add Group by Names”.

8. Complete the form as shown and click Apply. The CTRL group is created.
Group Name CTRL

Pattern LAB\.CTRL\..*
Group Type Placement
All Ungrouped Cells Disable
9. Complete the form as shown and click Apply. The DIV group is created.
Group Name DIV

Pattern LAB\.DIV\..*
10. Complete the form as shown and click Apply. The MUL group is created.
Group Name MUL

Pattern LAB\.MUL\..*

11. Complete the form as shown and click OK. The OUTSTAGE group is created.
Group Name OUTSTAGE

Pattern LAB\.OUTSTAGE\..*
12. The message shown in input/message area is as follows.
13. In input/message window, type load “create_region.cmd” to load the pre-defined region. (If you
want to create regions manually, use “Design Setup % Create Region”.
Cell Name chip_floorplan

overwrite Enable
17. Choose “PreRoute % Rectangular Rings”.

18. Complete the form as shown and click Apply. The core ring appears.

Around Core
Net Name(s) VDD, VSS
Skip Side(s)
L-Width / L-Layer 30 / 18
R-Width / R-Layer 30 / 18
B-Width / B-Layer 30 / 43
T-Width / T-Layer 30 / 43
Offsets Are Absolute
Offsets Left 5
Offsets Right 5
Offsets Bottom 5
Offsets Top 5
Extend
Create Innermost Core Ring Conservatively Disable
19. Complete the form as shown and click OK. The macro ring appears.
Around All Macros, except Specified

Skip Side(s) Left Top
R-Width / R-Layer 10 / 18
B-Width / B-Layer 10 / 43
Offsets Are Absolute
Offsets Left 5
Offsets Right 5
Offsets Bottom 5
Offsets Top 5
Extend RH BL
Create Innermost Core Ring Conservatively Disable
20. Choose “PreRoute % Straps”.

21. Complete the form as shown and click OK. The strap appears.

Direction Vertical
Start Y 700
Start X 740
Width 5
Layer 18
Low Ends At First Targets
High Ends At First Targets
All other options Default values
22. Choose “PreRoute % Macros/Pads”.

23. Use the default values and click OK.
24. Check if the P/G pads are connected.
25. Check if P/G of macros are connected.
Cell Name chip_preroute

overwrite Enable
29. Choose “Place % Placement Common Options”.

30. Enable the Region Placement Constraint and click OK.
31. Choose “Place % Design Placement”.
32. Use the default value and click OK. The standard cells will be placed on the core area.
33. Check input/message area. The following message is shown in the area.
34. Select the DIV group to see if its members are placed in the corresponding region.
Choose “Select % (De)select by Name”.
Name DIV
Pattern match Disable
Type group
Mode select
Select members of objects

36. The members of DIV group are highlighted. Are they all in the corresponding region?
37. De-select the DIV group by complete the form as shown and click OK.
Name DIV
Pattern match Disable
Type group
Mode deselect
Select members of objects

Cell Name chip_place

overwrite Enable

Lab 5
CTS / Routing / Built in DRC & LVS / Export Data
Unix% cd ~/lab5
2. Invoke Apollo.
Unix% Apollo &
Library Name lab5

Library Path
5. Choose “Cell % Open”.

Cell Name chip
7. Choose “Clock % Specify Clock Net”.

Net Name(s) From Window

Net Name(s) i_clk
File Name
Net Type Clock
9. Choose “Timing Setup % Timing Options”.

10. Change Delay Model to TLU and click OK.
11. In input/message area, type load “clk.tdf”.
12. Choose “Clock % Auto. (Gated) Clock Tree”.
Net Name(s) i_clk

Buffer(s) buffd1, buffd3, buffd7, buffda
Name Separator !
Soft Configuration Guide
Build strategy transition delay
Execute ECO Placement Enable
High Fanout Net Mode Enable

Cell Name chip_cts

overwrite Enable
17. Choose “PostPlace % Add Core Fillers” to add core filler.

Master Cell Name(s) feedth

respect placement blockage Enable
between std cells only Enable
Filler Name Identifier (optional)
No Filler Under Mx M1
Connect to Power Net (optional)
Connect to Ground Net (optional)
19. Choose “PostPlace % Add Pad Fillers” to add io filler.

Filler iofeedth002, iofeedth046, iofeedth864

Overlap Filler iofeedth002, iofeedth046, iofeedth864
Filler Name Identifier
Side left right bottom top
21. Choose “PreRoute % Standard Cells”.

22. Use the default settings and click OK.
23. In the input/message window, type load “CTS.RouteNetGroup.cmd”. The synthesized clock tree
is routed and highlighted.
24. Choose “Route % Auto Route”.
25. Use default settings and click OK.
26. The total DRC violations are shown in the input/message window.
Are there any violations? If not, go to step 30.

27. If there are violations in step 26, choose “Route % Search & Repair”.
28. Change Search Repair Loop to 50 and click OK.
29. The total DRC violations are shown in the input/message window.
Are there any violations?
30. Choose “Query % List PR Summary” and find the following section.
31. Write down the Total Wire Length & Total Number of Contacts.
32. Choose “Route % Optimize Routing”.
34. Choose “Query % List PR Summary” and find the following section.
35. Compare the Total Wire Length & Total Number of Contacts to the previous values. Is there any
improvement?

Cell Name chip_route
overwrite Enable
39. In the input/message window, key in dbAllowToAddPGIOText #t.

40. In the input/message window, key in dbAddIOText (geGetEditCell) “*” “*” 43 50.
41. Click Windows Options button, set pad cell as Visible Pin Instances. Also set View Level to 20.
42. Click Layer Panel button and set all layers non-visible except layer 43.
43. Choose “Create % Text” to create extVDD and extVSS texts. Refer to the slices of the training
manual for the positions of the texts.
45. Choose “Route Utility % Fill Gap/Notch”.
47. Choose “Verify % DRC”.
48. Enable “List Error Summary Immediately” and click OK.
49. Check the error summary. Are there any violations?
50. Choose “Verify % LVS”.
51. Enable “List Error Summary Immediately” “Include existing Notch/Gap Fill Cell” and click OK.
52. Check the error summary. Are there any violations?
53. Choose “Tools % Data Prep” & “Output > Stream Out”.
54. Complete the form as shown and click OK. Is the stream file created?
Stream File Name chip.gds

Library Name lab5
Layer File stout.map
Child Extraction Depth 20
Convert Specified Cell
Cell Name chip
Convert Reference Lib Child Cells Enable
Text Conversion Factor 1.000
Text Width 0.000
Flatten Devices & Device Arrays
Fill FILL
Merge Additional Views Disable
Generate Instance Name As Prop Disable
Generate Geometry Property Disable
Strip Backslash from Instance/Net Names Disable
Pin/Net Options % Output Net As Text

Lab 6
Dracula DRC / Timemill Post layout simulation
Unix% cd ~/lab6
2. Unix% cd dracula
3. Unix% PDRACULA
: /get drac035s3V4Ma.drc
: /finish
4. Unix% jxrun.com
5. After DRC job is finished, view the DRC summary file avt.sum.
6. View the OUTPUT CELL SUMMARY section of avt.sum file. Are there any DRC errors in this
design?
7. Unix% cd ~/lab6/timemill
8. View 00Readme.txt for detail.

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Cell Based Physical Design with

CIC Avant! Software - Apollo 1

CIC Avant! Software - Apollo 2

CIC Avant! Software - Apollo 3

Starting an Apollo Session

CIC Avant! Software - Apollo 4

Working with an Open Cell

CIC Avant! Software - Apollo 5

pan to scroll down fit with margin zoom in 2X

previous next view zoom to area additional

CIC Avant! Software - Apollo 6

CIC Avant! Software - Apollo 7

Specifying Objects by Pattern

CIC Avant! Software - Apollo 8

NETL EXP CEL FRAM TIM lib

Net views Expanded Cell views Frame views Timing views

Apollo Library Structure

CIC Avant! Software - Apollo 9

CIC Avant! Software - Apollo 10

CIC Avant! Software - Apollo 11

CIC Avant! Software - Apollo 12

CIC Avant! Software - Apollo 13

definePad “pad” “0” definePad “pad” “180”

Timing View % CLF file

CIC Avant! Software - Apollo 14

Import Design Timemill post layout simulation

Floor planning Dracula DRC/ERC Check

Build in DRC/LVS Check

Terms and Definitions

CIC Avant! Software - Apollo 15

CIC Avant! Software - Apollo 16

CIC Avant! Software - Apollo 17

cic35_io_v1.0 ram or rom cic35_core_v1.0

CIC Avant! Software - Apollo 18

Gate Level Apollo Cell

In a cell-based design, the cell libraries you use should be referenced.

Ref [1] [2] [3]

CIC Avant! Software - Apollo 19

※1 input [1:4] sys → sys[1], sys[2], sys[3], sys[4]

Settings for Verilog-In(1)

CIC Avant! Software - Apollo 20

Settings for Verilog-In(2)

CIC Avant! Software - Apollo 21

※1 1. Select Add Mode

Settings for Expand Netlist

CIC Avant! Software - Apollo 22

Global Net Options

CIC Avant! Software - Apollo 23

Generate Cell View

Ref [4] [5] [6] [7]

CIC Avant! Software - Apollo 24

CIC Avant! Software - Apollo 25

Net Name VDD VSS VDD VSS

Settings for Connect Ports to P/G

CIC Avant! Software - Apollo 26

Ref [8] [9] [10] [11] [12] [13]

CIC Avant! Software - Apollo 27

pad “Cul” “left” 4

Using TDF pad

CIC Avant! Software - Apollo 28

VDD VDD VDD

Row/Core Ratio = 3/4 = 75%

Settings for Setup Up Floorplan(1)