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Lab Manual
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Instructor’s Name
Introduction
This is the Lab Manual for EEE – 241 Digital Logic Design. The labs
constitute 25 % of the total marks for this course.
During the labs you will work in groups (no more than three students per
group). You are required to complete the ‘Pre-Lab’ section of the lab
before coming to the lab. You will be graded for this and the ‘In-Lab’ tasks
during the in-lab viva. You will complete the ‘Post-Lab’ section of each lab
before coming to the next week’s lab.
You are not allowed to wander in the lab or consult other groups when
performing experiments. Similarly the lab reports must contain original
efforts. CIIT has a zero tolerance anti-plagiarism policy.
Apart from these weekly labs you will complete two projects. One mini-
project that will count towards your Lab Sessional II score and a Final
Project which will be graded as Lab Final Exam. The grading policy is
already discussed in the Course Description File.
Acknowledgement
The labs for EEE-241 Digital Logic Design were designed by Dr Faisal
Siddique and Dr. Naseem Alvi. The manuals were prepared by Mr Ali Raza
Shahid, Mr Sikender Gul and Mr. Shahid Mehmood. The first version was
completed in Session Spring 2014, The second version was completed
during the summer break of 2016.Third version is completed in session
Spring 2016-17. Typesetting and formatting of this version was supervised
by Dr. Omar Ahmad and was carried out by Mr. Abdul Rehman, Mr
Suleman & Mr Baqir Hussain.
History of Revision
Version
and Date Team Comments
of Issue
Safety Precautions
Be calm and relaxed, while working in lab.
When working with voltages over 40 V or current over 10 A, there must be at least
Be sure about the locations of fire extinguishers and first aid kit.
No loose wires or metals pieces should be lying on the table or neat the circuit.
Avoid using long wires, that may get in your way while making adjustments or
changing leads.
Be aware of bracelets, rings, and metal watch bands (if you are wearing any of them).
When working with energize circuit use only one hand while keeping rest of your
o Disconnect the power source from the circuit breaker and pull out the plug
Table of Contents
Introduction (To be written by the course instructor)...............................................................2
Acknowledgement (Edit)...............................................................................................................3
History of Revision (Kindly edit according to your course)......................................................3
Safety Precautions.........................................................................................................................4
Lab # 01: Introduction to Basic Logic Gate Ic’s on Digital Logic Trainer and Proteus
Simulation.......................................................................................................................................8
Objective......................................................................................................................................8
Pre-Lab:.......................................................................................................................................8
EXNOR gate..............................................................................................................................11
In-Lab:.......................................................................................................................................13
Post-Lab Tasks:.........................................................................................................................20
Critical Analysis/Conclusion.....................................................................................................23
Lab #02:Boolean Function and Universal Gates Implementation on Kl-31001 Trainer
using Gate Ic’s..............................................................................................................................24
Objectives..................................................................................................................................24
Pre-Lab:.....................................................................................................................................24
In lab:.........................................................................................................................................24
Post-Lab:....................................................................................................................................30
Critical Analysis/Conclusion.....................................................................................................32
LAB # 03: Introduction to Verilog and simulation using XILINX ISE..................................33
Objective....................................................................................................................................33
Pre-Lab:.....................................................................................................................................33
In-Lab Task 2:............................................................................................................................45
Post-Lab Tasks:.........................................................................................................................45
Critical Analysis/Conclusion.....................................................................................................47
LAB #04 Implementation and Designing of Boolean Functions By Standard Forms
Using Ics/Verilog..........................................................................................................................48
OBJECTIVE..............................................................................................................................48
PRE LAB...................................................................................................................................48
PRELAB TASKS:.....................................................................................................................52
IN-LAB TASKS........................................................................................................................52
POST-LAB TASKS..................................................................................................................54
Critical Analysis/Conclusion.....................................................................................................56
Lab 05- Logic Minimization of Complex Functions using Automated Tools........................57
Objective....................................................................................................................................57
Pre- Lab:....................................................................................................................................57
In-Lab:.......................................................................................................................................59
Critical Analysis/Conclusion.....................................................................................................65
LAB # 06 XILINX ISE design flow with FPGA........................................................................66
Objective....................................................................................................................................66
Pre-Lab:.....................................................................................................................................66
In lab Task.................................................................................................................................71
Post-Lab Tasks:.........................................................................................................................72
Critical Analysis/Conclusion.....................................................................................................73
Lab #07: Design and Implementation of n-bit Adder/Subtractor on FPGA.........................74
Objectives..................................................................................................................................74
Pre-Lab:.....................................................................................................................................74
In lab:.........................................................................................................................................75
Post-Lab:....................................................................................................................................78
Critical Analysis/Conclusion.....................................................................................................79
Lab #08: N-Bit Multiplier and Its Implementation On FPGA................................................80
Objective....................................................................................................................................80
Pre-lab:.......................................................................................................................................80
Pre-lab Tasks.............................................................................................................................82
Post-Lab Tasks...........................................................................................................................83
Critical Analysis/Conclusion.....................................................................................................84
Lab #09: Design and Implementation of Binary to BCD and BCD to 7-Segment decoder
on FPGA.......................................................................................................................................85
Objective....................................................................................................................................85
Pre-Lab:.....................................................................................................................................85
Critical Analysis/Conclusion.....................................................................................................94
LAB # 10:Implementation of up/down Counter with Terminal Count and Reset on
FPGA............................................................................................................................................95
Objective....................................................................................................................................95
Pre-Lab:.....................................................................................................................................95
In lab Task.................................................................................................................................97
Post-Lab Tasks:.........................................................................................................................97
Critical Analysis/Conclusion.....................................................................................................99
Lab #11Mealy /Moore Machine implementation of Sequence Detector...............................100
Objective..................................................................................................................................100
Pre-Lab:...................................................................................................................................100
In lab:.......................................................................................................................................101
Post Lab...................................................................................................................................107
Critical Analysis/Conclusion...................................................................................................110
Lab #12 Universal Shift Register On FPGA...........................................................................111
OBJECTIVE............................................................................................................................111
PRE LAB.................................................................................................................................111
PRELAB TASK.......................................................................................................................114
LAB TASK..............................................................................................................................114
POST LAB TASK...................................................................................................................114
Critical Analysis/Conclusion...................................................................................................115
Objective
Part 1
To know about the basic logic gates, their truth tables, input output characteristics and
analyzing their functionality. Introduction to logic gate IC’s, Integrated Circuits pin
configurations and their use.
Part 2
Learn to use Proteus Software for Simulation of Digital Logic Circuits.
Pre-Lab:
Background Theory:
The Digital Logic Circuits can be represented in the form of (1) Boolean Functions, (2)
Truth Tables, and (3) Logic Diagram. Digital Logic Circuits may be practically
implemented by using electronic gates. The following points are important to understand.
Electronic gates are available in the form of Integrated Circuits (IC’s) and they
require a power.
Supply Gate INPUTS are driven by voltages having two nominal values, e.g. 0V and
5, 12V representing logic 0 and logic 1 respectively.
The OUTPUT of a gate provides two nominal values of voltage only, e.g. 0V and 5,
12V representing logic 0 and logic 1 respectively. In general, there is only one output
to a logic gate except in some special cases.
Truth tables are used to help show the function of a logic gate in terms of input values
combination with desired output.
Logic Diagram is used to represent the Digital Logic Circuit in the form of symbols
connected with each other.
Digital Logic Circuits can be simulated on the virtual environment called simulation
software
The basic operations are described below with the aid of Boolean function, logic symbol, and
truth table.
AND gate:
Figure 1. 1
Table 1. 1
The AND gate is an electronic circuit that gives a high output (1) only if all its inputs are
high. A dot (.) is used to show the AND operation i.e. A.B. Bear in mind that this dot is
sometimes omitted i.e. AB
OR Gate:
Figure 1. 2
Table 1. 2
The OR gate is an electronic circuit that gives a high output (1) if one or more of its inputs
are high. A plus (+) is used to show the OR operation
NOT gate
Figure 1. 3
Table 1. 3
The NOT gate is an electronic circuit that produces an inverted version of the input at its
output. It is also known as an inverter.
NAND gate
Figure 1. 4
Table 1. 4
This is a NOT-AND gate which is equal to an AND gate followed by a NOT gate. The
outputs of all NAND gates are high if any of the inputs are low. The symbol is an AND gate
with a small circle on the output. The small circle represents inversion.
NOR gate
Figure 1. 5
Table 1. 5
This is a NOT-OR gate which is equal to an OR gate followed by a NOT gate. The outputs
of all NOR gates are low if any of the inputs are high. The symbol is an OR gate with a small
circle on the output. The small circle represents inversion.
EXOR gate
Figure 1. 6
Table 1. 6
The 'Exclusive-OR' gate is a circuit which will give a high output if either, but not both, of
its two inputs are high. An encircled plus sign ( ) is used to show the EOR operation.
EXNOR gate
Figure 1. 7
Table 1. 7
The 'Exclusive-NOR' gate circuit does the opposite to the EOR gate. It will give a low output
if either, but not both, of its two inputs are high. The symbol is an EXOR gate with a small
circle on the output. The small circle represents inversion.
Digital systems are said to be constructed by using logic gates. These gates are the AND, OR,
NOT, NAND, NOR, EXOR and EXNOR gates. Logic gate IC’s are available in different
packages and technologies. Two main classifications are as below:
Figure 1. 8
Figure 1.8 shows the 4000 series is CMOS (complementary metal oxide semiconductors)
based integrated circuits. Power ratings are 3V to 15 Volts. CMOS circuitry consumes low
power but it is not fast as compared to TTL.
7
Figure 1. 9
The IC’s available in Lab to perform the Tasks are listed below:
In-Lab:
Equipment Required
Procedure
Figure 1. 10
2. Using the power supply available at KL-31001 Digital Logic Lab, connect pin7
(Ground) and pin14 (Vcc) to power up IC.
3. Give number of possible combinations of inputs using the slide switches SW0-SW3
(as shown in table 1.1 & 1.2) and note down the output with help of LED for all gate
ICs. (You can use LD0-LD14 located on KL-31001 Digital Logic Lab)
(Note: Please make sure the Trainer board is off during the setup of circuit)
In lab Task 1:
Verify all gates using their ICs on KL-31001 Digital Logic Lab
INPUTS OUTPUTS
A B AND NAND OR NOR EXOR EXNO
R
0 0
0 1
1 0
1 1
Table 1. 8
INPUTS OUTPUT
S
A OR
0
1
Table 1. 9
Procedure
The proteus software for simulation is installed in Digital Design Lab. Please follow the
details below to figure out usage proteus tools and process of simulation.
Parts Browsing:
Proteus has many models of electronic equipment such as logic gates, many kinds of switches
and basic electronic devices. The equipment can be founded by clicking on and then a new
window will pop-up and wait for the parts information as shown in figure 1.12.
Finding Steps:
All of the electrical circuits require power supplies. The power supplies for logic circuits are
represented in digital system design on Proteus because the schematic may be too
complicated to understand for simulation section. Therefore power supplies will be needed as
input power for a system. Moreover, all of the input generators, such as ac generator, dc and
pulse are contained in this category and it will be shown when is clicked. In addition
“Ground” will not be contained in this group. Because it is not an input signal it is just a
terminal junction. Therefore it will be grouped in terminal category as shown in figure 1.14&
1.15.
Logic State:
In addition there is another input that usually be used in digital circuit designed circuit but it
does not exist in real world as an equipment it is called as “LOGIC STATE”. It can be
found in the picking part section (type logic state and pick it figure 1.16).
Placing Equipment:
Selecting all devices needed to be placed on the circuit window (Grey window) and wiring it.
It can be done by following these steps:
1. Click on and select the first device that will be placed.
2. Place mouse wherever the device is preferred to be place and then click the left button
of the mouse. The device will be placed, if it is needed to be moved, click the right
button of the mouse on the device symbol to select the mouse. Then hold this device
with the left mouse button and move it to any desired place. (figure 1.17)
To wire devices together, click at the source pin of device and then move mouse cursor to
destination pin of the device. In this step the pink line will be appeared and it will be wire of
circuit after clicking the mouse on the destination pin of the circuit (as shown in figure 1.18).
Digi
Figure 1. 18 Wiring devices to make a circuit
After wiring all devices and connect all inputs according to the circuit, the simulation is ready
to be run by clicking on Play button to run and stop button to stop.
3. Logic probe or LED can be used to observe output state.
NOTE: The digital result on Proteus can be seen also in Small Square at pin of the
equipment & state can be shown in four colors. (Red= Logic 1, Blue = Logic 0, Grey=
Unreadable and Yellow= Logic Congestion)
In-Lab Task 2:
Verify all the basic logic gates using the Proteus simulation tool and note down the values in
the table with the corresponding logic symbol and Boolean function. Then show the
simulated logic circuit diagrams to your Lab Instructor.
Post-Lab Tasks:
1. Make a list of logic gate IC’s of TTL family and CMOS family along with the IC’s
names. (Note: at least each family should contain 15 IC’s).
7400 Series 4000 Series
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Critical Analysis/Conclusion
Lab Assessment
Pre Lab /5
Performance /5
Results /5 /25
Viva /5
Critical Analysis /5
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
Objectives
This experiment is designed to simulate and implement any logic function using
universals gates (NAND/NOR).
To build the understanding of how to construct any combinational logic function
using NAND or NOR gates only.
Pre-Lab:
Background theory:
Digital circuits are more frequently constructed with universal gates. NAND and NOR gate
are called universal gates. Any Boolean logic function can be implemented using NAND only
or NOR only gates. NAND and NOR gates are easier to fabricate with electronic components
than basic gates. Because of the prominence of universal gates in the design of digital
circuits, rules and procedures have been developed for conversion from Boolean function
given in terms of AND, OR, and NOT into its equivalent NAND and NOR logic diagram.
Read and understand the universal gates. List the truth tables of AND, OR, NOT, NAND,
NOR and XOR gates. Identify the NAND and NOR ICs and their specification for CMOS
and TTL families.
In lab:
This lab has two parts. In first part, simulation and implementation of any logic expression by
using only NAND is done. In second part, the same procedure is done by using NOR gate
only.
Procedure
Simulate AND, OR and NOT gates in proteus software, by using only NAND gates.
Verify their truth tables.
Insert the IC on the trainer’s breadboard.
Use any one or more of the NAND gates of the IC for this experiment.
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
Any one or more Logic Switches of the trainer (S1 to S9) can be used for input to the
NAND gate.
For output indication, connect the output pin of the circuit to any one of the LEDs of
the trainer (L0 to L15).
Lab Tasks-Part-1
A F=A’
Input Output
A F
0
1
Table 2.1
A (AB)’ F=AB
B
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
Inputs Output
A B F
0 0
0 1
1 0
1 1
Table 2.2
A A’
F=A+B
B
B’
Inputs Output
A B F
0 0
0 1
1 0
1 1
Table 2.3
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
A (A(AB)’)’
F=A’B+AB’
(AB)’
B (B(AB)’)’
Inputs Output
A B F
0 0
0 1
1 0
1 1
Table 2.4
F=AB+A’B’
(AB)’
B (B(AB)’)’
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
Inputs Output
A B F
0 0
0 1
1 0
1 1
Table 2.5
Procedure
Simulate AND, OR and NOT gates in proteus software, by using only NOR gates.
Verify their truth tables.
Insert the IC on the trainer’s breadboard.
Use any one or more of the NOR gates of the IC for this experiment.
Any one or more Logic Switches of the trainer (S1 to S9) can be used for input to the
NOR gate.
For output indication, connect the output pin of the circuit to any one of the LEDs of
the trainer (L0 to L15).
Lab Tasks-Part-2
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
Input Output
A F
0
1
Table 2.6
Inputs Output
A B F
0 0
0 1
1 0
1 1
Table 2.7
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
Inputs Output
A B F
0 0
0 1
1 0
1 1
Table 2.8
Post-Lab:
Design NAND, XOR and XNOR gate Using NOR gate only.
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
Critical Analysis/Conclusion
Lab Assessment
Pre Lab /5
Performance /5
Results /5 /25
Viva /5
Critical Analysis /5
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
Objective
Part 1
In this lab Verilog (Hardware Description Language) is introduced with Xilinx ISE. Verilog
is used to model electronic systems. It is most commonly used in the design and
verification of digital circuits.
Part 2
Xilinx ISE is a verification and simulation tool for VHDL, Verilog, System Verilog, and
mixed- language designs
Pre-Lab:
Background Theory:
Verilog HDL has evolved as a standard hardware description language. Verilog HDL offers
many useful features:
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
This is the highest level of abstraction provided by Verilog HDL. A module can be
implemented in terms of the desired design algorithm without concern for the hardware
implementation details. Designing at this level is very similar to C programming.
At this level, the module is designed by specifying the data flow. The designer is aware of
how data flows between hardware registers and how the data is processed in the design.
The module is implemented in terms of logic gates and interconnections between these
gates. Design at this level is similar to describing a design in terms of a gate-level logic
diagram.
This is the lowest level of abstraction provided by Verilog. A module can be implemented
in terms of switches, storage nodes, and the interconnections between them. Design at this
level requires knowledge of switch-level implementation details.
3.2 Syntax
3.2.1 Comments
Verilog comments are the same as in C++. Use // for a single line comment or /* … */ for
a multiline comment.
3.2.2 Punctuation
White spaces are ignored in Verilog. A semicolon is used to indicate the end of a command
line and commas are typically used to separate elements in a list. Like C++, Verilog is
case sensitive.
3.2.3 Identifiers
An identifier is usually a variable. You can use any letter, digit, the underscore, or
$. Identifiers may not begin with a digit and may not be the same as a Verilog key word. As
in C++ variable names should be chosen to assist in documentation.
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
Signals in Verilog have one of four values. These are 0 (logic 0), 1 (logic 1), ?, X, or x (
don’t care or unknown), and Z or z for high impedance tri-state.
3.2.5 Constants
Examples:
16 //The number 16 base 10
3.2.6 Parameters
A parameter in Verilog can be any Verilog constant. Parameters are used to generalize a
design. For example a 4-bit adder becomes more useful as a design if it is put together as an
n-bit adder where n is a parameter specified by the user before compilation. Parameter
declarations are done immediately after the module declaration.
parameter n = 12;
3.3 Structure
3.3.1 Module
A module in Verilog is used to define a circuit or a sub circuit. The module is the
fundamental circuit building block in Verilog. Modules have the following structure:
(keywords in bold). Note that the module declaration ends with a semicolon but the keyword
endmodule does not.
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
3.3.2 Ports
Ports in Verilog can be of type input, output¸ or inout. The module ports are given in
the port name list and are declared in the beginning of the module. Here is a sample
module with input and output ports.
module MyModule(yOut, aIn);
output yOut;
input aIn;
endmodule
The port names input and output default to type wire. Either can be a vector and the
output variables can be of re-declared to type reg. The output and input variables in a module
are typically names for the output and input pins on the implementation chip.
3.3.3 Signals
A signal is represented by either a net type or a variable type in Verilog. The net type
represents a circuit node and these can be of several types. The two net types most often
used are wire and tri. Type nets do not have to be declared in Verilog since Verilog
assumes that all signals are nets unless they are declared otherwise. Variables are either of
type reg or integer. Integers are always 32-bits where the reg type of variables may be of
any length. Typically we use integers as loop counters and reg variables for all other
variables. The generic form for representing a signal in Verilog is:
The net types are typically used for input signals and for intermediate signals within
combinational logic. Variables are used for sequential circuits or for outputs which are
assigned a value within a sequential always block.
Example:
wire w; //w is a single net of type wire
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
Symbol Comments
~ Ones complement unary operator
& and
| or
Bitwise
^ exclusive or
~& nand
~| nor
~^ exclusive nor
! Not unary operator also called logical negation
&& Logical and
|| Logical or
+ Add
- Subtract
* Multiply
rithmetic
/ Divide
% Mod operator
> Greater than
< Less than
>= Greater than or equals
ional
{,} Concatenation
{m{}} Repetition where m is repetition number
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
Right click on Design Pane and select a New Source or Add Source (If file is already exists)
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
module half_adder(C,S,x,y);
output C,S;
input x,y;
xor a1(S,x,y);
and a2(C,x,y);
endmodule
Then click Ok
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
In-Lab Task 2:
Verify all the basic logic gates using the XILINX ISE simulation tool and verify your
waveform with logic gates truth table. Then show the simulated result to your Lab Instructor.
Task 01: Make Verilog code for NOT, OR, NOR, NAND, XOR, and XNOR.
Task 03: Run simulation for all gates (made in Task 01).
Post-Lab Tasks:
Implement and simulate the given function below:
(Provide Gate Level Diagram and Truth Table also in Lab Report)
F = x + x’y + yz’
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
Critical Analysis/Conclusion
Lab Assessment
Pre Lab /5
Performance /5
Results /5 /25
Viva /5
Critical Analysis /5
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
OBJECTIVE
In this lab we implement Boolean functions by using SOP (sums of product) and POS
(products of sum)
EQUIPMENT REQUIRED
KL-31001 Digital Logic Lab, Bread Board, Logic gate ICs (NAND &NOR).
PRE LAB
BOOLEAN ALGEBRA
Boolean algebra is algebra for the manipulation of objects that can take on only two
values, typically true and false.
0 as false
1 as true.
BOOLEAN FUNCTION
A Boolean function typically has one or more input values and yields a result, based on these
input value, in the range {0, 1}. A Boolean operator can be completely described using a
table that list inputs, all possible values for these inputs, and the resulting values of the
operation.
A Boolean function can be represented in a truth table and it can be transformed from an
algebraic expression into a circuit diagram composed of logic gates. In evaluating Boolean
equations AND operation is performed before OR operation unless OR operation is
enclosed with in brackets
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
BASIC THEOREMS
CANONICAL FORMS
Any Boolean function that is expressed as a sum of minterms or as a product of maxterms is
said to be in its canonical form.
In general, the unique algebraic expression for any Boolean function can be obtained from
its truth table by using an OR operator to combined all minterms for which the function is
equal to 1.
Minterm
A minterm, denoted as mi, where 0 ≤ i < 2n , is a product (AND) of the n variables in
which each variable is complemented if the value assigned to it is 0, and un
complemented if it is 1.
A shorthand notation:
Or
F (x, y, z) = Σ(3, 5, 6, 7)
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
The inverse of the function can be expressed as a sum (OR) of its 0- minterms. A shorthand
notation
F ' = x' y' z' + x' y' z + x' y z' + x y' z' = m0 + m1 + m2 + m4
Or
F ' (x, y, z) = Σ(0, 1, 2, 4)
Table 4.1
Maxterm
A maxterm, denoted as Mi, where 0 ≤ i < 2n , is a sum (OR) of the n variables (literals) in
which each variable is complemented if the value assigned to it is 1, and un
complemented if it is 0.
A shorthand notation:
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
Or
F (x, y, z) = Π(0, 1, 2, 4)
The inverse of the function can be expressed as a product (AND) of its 1-maxterms.
A shorthand notation
Example: (table4.2)
Or
F ' (x, y, z) = Π(3, 5, 6, 7)
Table 4.2
STANDARD FORMS
The term "Sum of Products" or "SoP" is widely used for the canonical form that is a
disjunction (OR) of minterms.
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
The term "Product of Sums" or "PoS" for the canonical form that is a conjunction
(AND) of maxterms.
PRELAB TASKS:
1. Express the Boolean function F = x + y z as a sum of minterms by using truth table.
2. Express F ' = (x + y z)' as a product of maxterms.
3. Given the function as defined in the truth table, express F using sum of
minterms and product of maxterms
Table 4.3
IN-LAB TASKS
CIRCUIT IMPLEMENTATION
1. First make the circuit diagram of desired Task.
2. Use logic gate ICs which are needed for tasks.
3. Insert connection clips according to circuit diagram you made.
4. Connect input to data switches and output to logic indicator.
5. Follow the input sequence and record the output.
TASK#1: Implement the circuit for given “F”. Function’s output is given in the table.
Finds its Boolean Expression in SOP and POS forms.
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
O
F(SOP) F(POS)
(Using NAND (Using
Gates only) NOR
A B C D F
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 1
0 1 0 0 0
0 1 0 1 0
0 1 1 0 0
0 1 1 1 1
1 0 0 0 0
1 0 0 1 0
1 0 1 0 1
1 0 1 1 1
1 1 0 0 1
Boolean Equation:
Circuit Diagram:
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
POST-LAB TASKS
1) Write a Verilog code for the reduced SOP form of the function, F. (Structural
Level).
2) Write a Verilog code for the reduced POS form of the function, F. (Structural
Level)
3) Simulate and verify the outputs by making an appropriate stimulus for both
modules (Task1 and Task2)
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
Critical Analysis/Conclusion
Lab Assessment
Pre Lab /5
Performance /5
Results /5 /25
Viva /5
Critical Analysis /5
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
Objective
Part 1
In this lab students will learn Karnaugh Map minimization and how to use logic minimization
automated tools for excessive number of variables in a function
Part 2
By using XILIUX ISE Simulation of minimized logic function results are verified after
writing Verilog Behavioral description code
Pre- Lab:
Background Theory:
We can simplify the equations and find a Boolean Function of any truth table using K-Map.
We need some basic concepts for K-Map; like Min Term and Max term.
Min Term:
A product of n variables where each of n variables appear exactly ones in complemented or
uncomplemented form is called the min term of n variables, and denoted by m n. (n starts
from 0 to 2n-1)
Max Term:
A sum of n variables where each of n variables appear exactly ones in complemented or
uncomplemented form is called the max term of n variables, and denoted by Mn. (n starts
from 0 to 2n -1)
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
K-Maps:
3-Variables:
4-Variables:
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
In-Lab:
Equipment Required:
KL-31001 Digital Logic Lab
Bread Board
Logic gate ICs
K-map Minimizer automated tool (Figure 5.1)
Procedure:
1. First make the circuit diagram for the desired task or subtask given by Lab
instructor.
2. Using k-map minimizer tool derive the simplified function
a. Set the number of variables.
b. Set the type of solution.
c. Set the values of function ‘f’. (Function values can be generated
randomly)*
d. Click on solve button then solution will come on solution screen.
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
3. Using logic gate ICs (which is/are needed) for the tasks.
4. Insert connection clips according to the circuit diagram you made.
5. Connect inputs to data Switches and output to logic indicator.
6. Follow the input sequence and record the outputs in the table 5.1.
In-Lab Task 1:
Implement the minimized function given below using logic gate IC.
F(A,B,C,D)= ∑( , , , )
(Note: minterm’s will be specified by Lab Instructor)
Number of gates/ICs
used:______________________________________________________
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
Number of gates/ICs
used:________________________________________________________
Digital Logic Design
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
Truth Table:
In-lab Task 2
Write a Verilog code for the 8 variable function.
F(A,B,C,D,E,F,G,H)= ∑( , , , )
Procedure
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
Results
(Verilog Code & Simulation Wave Forms)
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
Critical Analysis/Conclusion
Lab Assessment
Pre Lab /5
Performance /5
Results /5 /25
Viva /5
Critical Analysis /5
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
Objective
Part 1
In this lab we learn about the XILINX software design flow with FPGA. Implement
different examples on FPGA
Part 2
Implementation of Gray code on FPGA Kit Diligent Nexys-2 Board
Pre-Lab:
Background Theory:
In the coding, when numbers, letters or words are represented by a specific group of symbols,
it is said that the number, letter or word is being encoded. The group of symbols is called as a
code. The digital data is represented, stored and transmitted as group of binary bits. This
group is also called as binary code. The binary code is represented by the number as well as
alphanumeric letter.
It is the non-weighted code and it is not arithmetic codes. That means there are no specific
weights assigned to the bit position. It has a very special feature that, only one bit will change
each time the decimal number is incremented as shown in fig. As only one bit changes at a
time, the gray code is called as a unit distance code. The gray code is a cyclic code. Gray
code cannot be used for arithmetic operation.
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
Bit file will be generated after the completion of ‘Generate Programming File’
process
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
After identification succeeded select the bit file and click on ‘Open’ button
Then bypass the second option
Right click on FPGA chip symbol and click on ‘Program’, to program the FPGA
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
After the Program Succeeded message comes, test the output on FPGA by changing
different input value
In lab Task
Design and implement binary to gray code convertor on FPGA.
Provide K-Map solution and Boolean expression
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0
Post-Lab Tasks:
Provide gate-level circuit diagram of Gray code conversion
Critical Analysis/Conclusion
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
Lab Assessment
Pre Lab /5
Performance /5
Results /5 /25
Viva /5
Critical Analysis /5
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
Objectives
Part 1
This experiment is to design gate-level hierarchal description of a 4-bit binary adder /
Subtractor in HDL and implement it on FPGA
Part 2
Introduce the different Verilog keywords (Parameter, always etc) and use them to simulate
the incremental function in Verilog.
Pre-Lab:
Background theory:
Binary Adder is digital circuit that produces the arithmetic sum of two binary numbers. It can
be constructed with full adders connected in cascade, with the output carry from each full
adder connected to the input carry of the next full adder in the chain. The process of addition
proceeds on a bit-by-bit basis, right to left, beginning with the least significant bit. After the
least significant bit, addition at each position adds not only the respective bits of the words,
but also consider a possible carry bit from addition at the previous position. Addition of n-bit
binary numbers requires the use of a n full adder, or a chain of one-half adder and n-1 full
adders. The four-bit adder is an example of a standard component. It can be used in many
applications involving arithmetic operations.
Binary Adder/Subtractor can be combined into one circuit with one common binary adder by
including an exclusive-OR gate with each full adder. A four-bit adder/subtractor circuit of
two binary numbers A(A3A2A1A0) and B(B3B2B1B0) is shown in Figure 7.1. The mode input
M controls the operation. When M = 0, the circuit is an adder. As B 0 = B, C0 = 0 , full
adders receive the value of B, and the circuit performs A + B. when M = 1, the circuit
becomes a subtractor. Now we have B 1 = B’ and C0 = 1. The B inputs are all
complemented and a 1 is added through the input carry (C0 ). The circuit performs the
operation A plus the 2’s complement of B i.e A-B .The exclusive-OR with output V is for
detecting an overflow and C is carry out.
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
B3 A3 B2 A2 B1 A1 B0 A0
C4 C3 C2 C1 C0
C FA FA FA FA
V S3 S2 S1 S0
In lab:
The first part is implementation of hierarchal description of a 4-bit binary adder / Subtractor.
4 bit
Adder/
Subtractor
Figure 7.2
Procedure
Write the HDL Verilog code for 4 bit binary adder in Xilinx software
Create HDL project
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
In this lab task, different keywords are introduced and use to build the example code.
Parameters: A parameter in Verilog can be any Verilog constant. Parameters are used to
generalize a design. For example a 4-bit adder becomes more useful as a design if it is put
together as an n-bit adder where n is a parameter specified by the user before compilation.
Parameter declarations are done immediately after the module declaration.
Here are some typical parameter examples:
parameter n = 12;
Always: An always block can be considered as a complex circuit part. It can be suspended or
activated. When any signal of the sensitivity list changes or an event occurs, the part is
activated and executes the internal procedural statements. The simplified syntax of an always
block with a sensitivity list (also known as event control expression) is
always @(sensitivity-list)
[procedural statement] ;
end
The (sensitivity-list) term is a list of signals and events to which the always block responds
(i.e., is "sensitive to"). For a combinational circuit, all the input signals should be included in
this list. The body is composed of any number of procedural statements. The begin and end
delimiters can be omitted if there is only one procedural statement in the body. The
@(sensitivity-list) term is actually a timing control construct. It is usually the only timing
control construct in a synthesizable always block.
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
Post-Lab:
Write the HDL (Verilog ) behavioral description of n-bit ripple carry adder /Subtractor:
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
Critical Analysis/Conclusion
Lab Assessment
Pre Lab /5
Performance /5
Results /5 /25
Viva /5
Critical Analysis /5
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
Objective
In this lab we will seek how to implement binary multiplier on FPGA.
Pre-lab:
Background Theory:
Binary Multiplier
Binary multiplier is used to multiply two binary numbers. Multiplication of binary numbers is
performed in the same way as multiplication of decimal numbers. It is build using binary
adders. The common multiplication method is “add and shift” algorithm. If the multiplicand
is N-bits and the Multiplier is M-bits then there is N* M partial product. AND gates are used
to generate the Partial Products. Note that in binary multiplication, the processes involve
shifting the multiplicand, and adding the shifted multiplicand or zero. Each bit of the
multiplier determines whether a 0 is added or a shifter version of the multiplicand (0 implies
zero added, 1 implies shifted multiplicand added). Thus, we can infer a basic shift-and-add
algorithm to implement unsigned binary multiplication.
General Expression
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
Example:
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
Pre-lab Tasks
1. Do binary multiplication of A=3 and B= -7.
2. Implement 2-bit by 2-bit multiplier.
In-Lab Task 1:
1. Implement 4-bit by 3-bit binary multiplier using gate IC’s
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
Post-Lab Tasks
1. Write the HDL (Verilog) gate-level description of a four-bit multiplier and implement
on FPGA.
2. Write the HDL (Verilog) behavioral description of parameterized binary multiplier:
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
Critical Analysis/Conclusion
Lab Assessment
Pre Lab /5
Performance /5
Results /5 /25
Viva /5
Critical Analysis /5
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
Objective
In this lab we design binary to BCD and BCD to 7-Segment decoders. And also learn how to
use 7-segment display of Nexys2 FPGA board.
Pre-Lab:
Background Theory:
Consider decimal 861 and its corresponding value in BCD and binary:
1. If any column (100's, 10's, 1's, etc.) is 5 or greater, add 3 to that column.
2. Shift all #'s to the left 1 position.
3. If 10 shifts have been performed, it's done! Evaluate each column for the BCD values.
4. Go to step 1.
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
if (Hundreds >= 5)
Hundreds = Hundreds + 3;
if (Tens >= 5)
Tens = Tens + 3;
if (Ones >= 5)
Ones = Ones + 3;
Hundreds[0] = Tens[3];
Tens[0] = ones[3];
Ones[0] = Binary[i];
7-Segment Display
A seven-segment display (SSD) is a form of electronic display device for displaying decimal
numerals. The seven elements of the display can be lit in different combinations to represent
the decimal numerals. Often the seven segments are arranged in an oblique (slanted)
arrangement, which aids readability. Seven-segment displays may use a light-emitting diode
(LED) a liquid crystal display (LCD), for each segment, or other light-generating or
controlling techniques. There are two types of simple LED package 7-Segment display:
Common Anode
Common Cathode
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
Nexys2 board contains a four-digit common anode seven-segment LED display. Each of the
four digits is composed of seven segments arranged in a “figure 9.1” pattern, with an LED
embedded in each segment. Segment LEDs can be individually illuminated, so any one of
128 patterns can be displayed on a digit by illuminating certain LED segments and leaving
the others dark.
The anodes of the seven LEDs forming each digit are tied together into one “common anode”
circuit node, but the LED cathodes remain separate. The common anode signals are available
as four “digit enable” input signals to the 4-digit display. The cathodes of similar segments on
all four displays are connected into seven circuit nodes labeled CA through CG (so, for
example, the four “D” cathodes from the four digits are grouped together into a single circuit
node called “CD”). These seven cathode signals are available as inputs to the 4-digit display.
This signal connection scheme creates a multiplexed display, where the cathode signals are
common to all digits but they can only illuminate the segments of the digit whose
corresponding anode signal is asserted.
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
Syntax:
case (switching variable)
default: statement(s);
endcase
module mux_4_1( Y, I, S );
output reg Y;
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
input [3:0]I;
input [1:0]S;
always @ ( I or S)
begin
endcase
end
endmodule
In-Lab Task 1:
Write the HDL (Verilog) behavioral description of BCD to 7-Segment decoder and
implement on FPGA.
First make a truth table for BCD to 7-Segment decoder which has 4-inputs and 8-outputs (A
to G and DP) of 7-Segment display (in given below space).
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
Inputs Outputs
A B C a b c d e f g
D
Implement it on FPGA (Only one 7-Segment should be on) and write down the Verilog code
below.
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
In-Lab Task 2:
Write the HDL (Verilog) behavioral description of binary to BCD decoder and implement on
FPGA.
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
Critical Analysis/Conclusion
Lab Assessment
Pre Lab /5
Performance /5
Results /5 /25
Viva /5
Critical Analysis /5
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
Objective
In this lab we implement up/down counter with terminal count and reset on FPGA. We also
learn how to use internal clock of FPGA and implement clock divisor. The counter value
will be displayed on 7-segment displays of Nexys2 board so we implement scanning display
controller to control multiple 7-segment displays because they have common data bus (CA –
DP).
Pre-Lab:
Up/Down Counting:
Terminal count:
Terminal count is an output signal which actives under any desired condition or
counter will reach to a specific value
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
Clock:
Clock divisor circuit is implemented to use the slower version of the clock by using internal
clock of the board. Nexys2 board has an internal clock of 50 MHz.
Example: 40 ns clock:
As f = 50 MHz so T = 20 ns
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
So if we need 40 ns clock then we count the internal clock of 50 MHz twice then
make change once in 40 ns clock. That is count 2 and when 2 occurs terminal count will be
one for a while then the terminal count output of that counter will be clock of 40 ns.
As 4-digit 7-segment displays have common data bus so multiplexer is used to select one
data and segment id at a time of refresh period
In lab Task
1. Write a HDL (Verilog) behavioral description of up/down counter with terminal
count, enable and reset.
2. Write a HDL (Verilog) behavioral description for binary to display module
which multiplexed between segment data and segment digit id.
3. Join all the necessary modules with respective parameters to implement the
task1 counter on FPGA and display counter result on 7-segment display
Post-Lab Tasks:
Provide simulation result of task 3
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
Critical Analysis/Conclusion
Lab Assessment
Pre Lab /5
Performance /5
Results /5 /25
Viva /5
Critical Analysis /5
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
Objective
This experiment is to design behavioral description of Sequence detector using Mealy/Moore
models of Finite State Machine (FSM) and implement designs into Xilinx
Pre-Lab:
Background theory:
The most general model of a sequential circuit has inputs, outputs, and internal states. It is
customary to distinguish between two models of sequential circuits: the Mealy model and the
Moore model. They differ only in the way the output is generated. The two models of a
sequential circuit are commonly referred to as a finite state machine, abbreviated FSM.
In the Mealy model, the output is a function of both the present state and the input as shown
in Figure 11.1. the outputs may change if the inputs change during the clock cycle. the output
of the Mealy machine is the value that is present immediately before the active edge of the
clock.
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
In the Moore model, the output is a function of only the present state. A circuit may have
both types of outputs as shown in Figure 11. 2. The outputs of the sequential circuit are
synchronized with the clock, because they depend only on flip-flop outputs that are
synchronized with the clock.
In lab:
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
Post Lab
Write a Verilog model of the Mealy FSM described by the state diagram in Figure11.
3.Develop a test bench and demonstrate that the machine state transitions and output
correspond to its state diagram.
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
0/1
a b
1/1
1/0 0/0
0/0
1/0
d 1/1
c
0/1
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
Critical Analysis/Conclusion
Lab Assessment
Pre Lab /5
Performance /5
Results /5 /25
Viva /5
Critical Analysis /5
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
OBJECTIVE
In this lab we implement Universal Shift Register on FPGA and perform all operations of
Universal Shift Register.
PRE LAB
REGISTER
A register is a digital circuit with two basic functions:
Data storage
Data movement
SHIFT REGISTER
A shift register is a group of flip-flops set up in a linear fashion with their inputs and outputs
connected together in such a way that the data is shifted from one device to another when the
circuit is active.
Depending on the signal values on the select lines of the multiplexers, the register can retain
its current state, shift right, shift left or be loaded in parallel. Each operation is the result of a
positive edge on the clock line.
In order for the universal shift register to operate in a specific mode, it must first select the
mode. To accomplish mode selection the universal register uses a set of two selector
switches, S1 and S0. As shown in Table 12.1, each permutation of the switches corresponds
to a loading/input mode.
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
Table 12.1
Locked Mode:
In the locked mode (S1S0 = 00) the register is not admitting any data; so that the content of
the register is not affected by whatever is happening at the inputs.
Shift-Right Mode:
In the shift-right mode (S1S0 = 01) serial inputs are admitted from Q3 to Q0. You can
confirm this aspect by setting the value of the shift-right switch according to the sequence
1100100 as you cycle the clock; see Table 12.2. Watch as the signals move from Q3 to Q0. In
the shift-left mode (S1S0 = 10) the register works in a similar fashion, except that the signals
move from Q0 to Q3.
Table 12.2
Parallel-loading mode:
Finally, in the parallel loading mode (S1S0 = 11) data is read from the lines L0, L1, L2, and
L3 simultaneously. Here, setting L3L2L1L0 = 1010 will cause Q3Q2Q1Q0 = 1010 after
cycling the clock as depicted in Table 12.3.
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
Table 12.3
Fig 12.1
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
PRELAB TASK
Write properties of clear, clock, shift-right , shift-left ,parallel –load of Universal Shift
Register.
LAB TASK
1. Implement Universal Shift Register on FPGA.
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
Critical Analysis/Conclusion
Lab Assessment
Pre Lab /5
Performance /5
Results /5 /25
Viva /5
Critical Analysis /5