VLSI STUDY MATERIAL

2013

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MSME TOOL ROOM,BON HOOGHLY INDUTRIAL AREA,KOLKATA -
700108
CONTENTS
INTRODUCTION

 Technology CAD
 History
 Modern Technology CAD
 Integrated circuits
 Classifications
 Manufacture fabrication
 Packaging
 VLSI

BASIC OF DIGITAL ELECTRONICS

 Introduction
 Number System
 Combinational circuits
 Sequential circuits

MOS

 Introduction
 History
 Mos Structure
 Mode of operations of Mos
 Mos Scaling

CMOS

 Introduction
 Development History
 NMOS
 PMOS
 Pull Up/PullDown Network

Programming language

 HDL
 History of HDL
 VHDL
 Syntax of VHDL

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  Verilog HDL
 Syntax Of Verilog HDL

Hardware devices

 PLD
 History
 Types of Pld and Description

VLSI Softwares

 Microwind
 Xilinx
 Altera

Protoboard

 Product Information
 Features and Specification
 Block Diagrams of Device

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 INTRODUCTION TO VLSI
Very large scale integration(vlsi) is the process of creating integrated circuits By combining
thousands of transistor-based circuits into a single chip. VLSI began in the 1970s when complex
semiconductor and communication technologies were being developed.

The first Semiconductor chips held on transistor each. Subsequent advances added more and
more transistors, and a consequence more individual functions or systems were integrated over
time. Themicroprocessors is a VLSI device.

The first “generation” of computers relied on vacuum tubes. Thencame discrete semiconductor
devices, followed by integrated circuits. The first Small-scale integration (SSI) ICS had small
numbers of devices on a single chip – diodes,transistors,resistors and capacitors (no inductors
though),making it possible to fabricateone or more logic gates on a single device.The fourth
generation consisted of Large scale integration(Lsi),i.e. system with at least a thousand logic
gates.the natural successor to LSI was VLSI(many tens of thousands of gates on a single
chip).Current technology has moved far past this mark and today’s microprocessors have many
millions of gates and hundreds of millions of individual transistors.

As of mid-2006,billion-transistors processors are just on the horizon, with the first being Intel’s
Montecito Itanium Server.This is expected to become more commonplace as semiconductor
fabrication moves from the current generation of 90 nanometer(90 nm)Processor to the next
65 nm and 45 nm generations.

At one time, there was an effort to name and calibrate various levels of large-scale integration
above VLSI. Terms like Ultra-large-scale-integration(ULSI) were used.But the huge number of
gates and transistors available on common devices has rendered such fine distinctions moot.
Terms suggesting more thenvlsi levels of integration are no longer in widespread use. EvenVlsi
is now somewhat quaint, given the common assumption that all microprocessors are VLSI or
better.

Technology CAD
Technology CAD (or Technology Computer Aided Design, or TCAD) is a
branchof electronic design automation that models semiconductor fabrication and
semiconductor device operation. The modeling of the fabrication is termed Process TCAD, while
the modeling of the device operation is termed Device TCAD. Included are the modeling of
process steps (such as diffusion and ion implantation), and modeling of the behavior of the

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electrical devices based on fundamental physics, such as the doping profiles of the devices.
TCAD may also include the creation of compact models (such as the well-
known SPICE transistor models), which try to capture the electrical behavior of such devices but
do not generally derive them from the underlying physics. (However, the SPICE simulator itself
is usually considered as part of ECAD rather than TCAD.)

Introduction
Technology files and design rules are essential building blocks of the integrated circuit design process.
Their accuracy and robustness over process technology, its variability and the operating conditions of
the IC—environmental, parasitic interactions and testing, including adverse conditions such as electro-
static discharge—are critical in determining performance, yield and reliability. Development of these
technology and design rule files involves an iterative process that crosses boundaries of technology and
device development, product design and quality assurance. Modeling and simulation play a critical role
in support of many aspects of this evolution process.

The goals of TCAD start from the physical description of integrated circuit devices, considering both the
physical configuration and related device properties, and build the links between the broad range of
physics and electrical behavior models that support circuit design. Physics-based modeling of devices, in
distributed and lumped forms, is an essential part of the IC process development. It seeks to quantify
the underlying understanding of the technology and abstract that knowledge to the device design level,
including extraction of the key parameters that support circuit design and statistical metrology.
Although the emphasis here is on Metal Oxide Semiconductor (MOS) transistors—the workhorse of the
IC industry—it is useful to briefly overview the development history of the modeling tools and
methodology that has set the stage for the present state-of-the-art.

History
The evolution of technology computer-aided design (TCAD)--the synergistic combination of process,
device and circuit simulation and modeling tools—finds its roots in bipolar technology, starting in the

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late 1960s, and the challenges of junction isolated, double-and triple-diffused transistors. These devices
and technology were the basis of the first integrated circuits; nonetheless, many of the scaling issues
and underlying physical effects are integral to IC design, even after four decades of IC development.
With these early generations of IC, process variability and parametric yield were an issue—a theme that
will reemerge as a controlling factor in future IC technology as well.

Process control issues—both for the intrinsic devices and all the associated parasitics—presented
formidable challenges and mandated the development of a range of advanced physical models for
process and device simulation. Starting in the late 1960s and into the 1970s, the modeling approaches
exploited were dominantly one- and two-dimensional simulators. While TCAD in these early generations
showed exciting promise in addressing the physics-oriented challenges of bipolar technology, the
superior scalability and power consumption of MOS technology revolutionized the IC industry. By the
mid-1980s, CMOS became the dominant driver for integrated electronics. Nonetheless, these early
TCAD developments set the stage for their growth and broad deployment as an essential toolset that
has leveraged technology development through the VLSI and ULSI eras which are now the mainstream.

IC development for more than a quarter-century has been dominated by the MOS technology. In the
1970s and 1980s NMOS was favored owing to speed and area advantages, coupled with technology
limitations and concerns related to isolation, parasitic effects and process complexity. During that era of
NMOS-dominated LSI and the emergence of VLSI, the fundamental scaling laws of MOS technology were
codified and broadly applied. It was also during this period that TCAD reached maturity in terms of
realizing robust process modeling (primarily one-dimensional) which then became an integral
technology design tool, used universally across the industry. At the same time device simulation,
dominantly two-dimensional owing to the nature of MOS devices, became the work-horse of
technologists in the design and scaling of devices. The transition from NMOS to CMOS technology
resulted in the necessity of tightly coupled and fully 2D simulators for process and device simulations.
This third generation of TCAD tools became critical to address the full complexity of twin-well CMOS
technology (see Figure 3a), including issues of design rules and parasitic effects such as latchup. An
abbreviated but prospective view of this period, through the mid-1980s, is given in; and from the point
of view of how TCAD tools were used in the design process.

Modern TCAD
Today the requirements for and use of TCAD cross-cut a very broad landscape of design automation
issues, including many fundamental physical limits. At the core are still a host of process and device
modeling challenges that support intrinsic device scaling and parasitic extraction. These applications
include technology and design rule development, extraction of compact models and more generally
design for manufacturability (DFM). The dominance of interconnects for giga-scale integration
(transistor counts in O(billion)) and clocking frequencies in O (10 gigahertz)) have mandated the
development of tools and methodologies that embrace patterning by electro-magnetic simulations—
both for optical patterns and electronic and optical interconnect performance modeling—as well as
circuit-level modeling. This broad range of issues at the device and interconnect levels, including links to
underlying patterning and processing technologies, is summarized in Figure 1 and provides a conceptual
framework for the discussion that now follow

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Figure 1: Hierarchy of technology CAD tools building from the process level to circuits. Left side icons
show typical manufacturing issues; right side icons reflect MOS scaling results based on TCAD (CRC
Electronic Design Automation for IC Handbook, Chapter 25)

Figure 1 depicts a hierarchy of process, device and circuit levels of simulation tools. On each side of the
boxes indicating modeling level are icons that schematically depict representative applications for TCAD.
The left side gives emphasis to Design For Manufacturing (DFM) issues such as: shallow-trench isolation
(STI), extra features required for phase-shift masking (PSM) and challenges for multi-level interconnects
that include processing issues of chemical-mechanical planarization (CMP), and the need to consider
electro-magnetic effects using electromagnetic field solvers. The right side icons show the more
traditional hierarchy of expected TCAD results and applications: complete process simulations of the
intrinsic devices, predictions of drive current scaling and extraction of technology files for the complete
set of devices and parasitics.

Figure 2 again looks at TCAD capabilities but this time more in the context of design flow information
and how this relates to the physical layers and modeling of the electronic design automation (EDA)
world. Here the simulation levels of process and device modeling are considered as integral capabilities
(within TCAD) that together provide the "mapping" from mask-level information to the functional
capabilities needed at the EDA level such as compact models ("technology files") and even higher-level
behavioral models. Also shown is the extraction and electrical rule checking (ERC); this indicates that
many of the details that to date have been embedded in analytical formulations, may in fact also be
linked to the deeper TCAD level in order to support the growing complexity of technology scaling.

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 Integrated Circuit

Integrated circuit showing memory blocks,logic and input/output pads around the periphery

Microchips with a transparent window showing the integrated circuit inside. Note the fine silver wires
which connect the integrated circuit to the legs of the microchip packaging.

A monolithic integrated circuit (also known as IC,microcircuit,microchip silicon chip, computer chip or
chip)is a miniaturized electronic circuit (consisting mainly of semiconductor devices, as well as passive
components)that has been manufactured in the surface of a thin substrate of semiconductor material.

A hybrid integrated circuit is a miniaturized electronic circuit constructed of individual of semiconductor

devices, as well as passive components, bonded to a substrate or circuit board.

Introduction
Integrated circuits were made possible by experimental discoveries which showed that semiconductor
devices could perform the functions of vacuum tubes, and by mid-20th-century technology
advancements in semiconductor device fabrication. The integration of large numbers of tiny transistors

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into a small chip was an enormous improvement over the manual assembly of circuits using discrete
electronic components. The integrated circuit’s mass production capability,reliability, and building-block
approach to circuit design ensured the rapid adoption of standardized ICs in place of designs using
discrete transistors.

There are two main advantages of ICs over discrete circuits: cost and performance.Cost is low because
the chips,with all their components,are printed as a unit by photolithography and not constructed a
transistor at a time.performance is high since the component switch quickly and consume little power,
because the components are samall and close together. As of 2006,chip area range from a few square
mm to around350 mm2 , with up to 1 million transistors per mm2 .

Advances in integrated circuits

The integrated circuit from an intel 8742,an 8-bit microcontroller that includes a CPU running at 12
MHz,128 bytes of RAM,2048 bytes of EPROM, and i/o in the same chip.

Among the most advanced integrated circuits are the microprocessors or "cores", which control
everything from computers and cellular phones to digital microwave ovens. Digital memory chips and
ASICs are examples of other families of integrated circuits that are important to the modern information
society. While the cost of designing and developing a complex integrated circuit is quite high, when
spread across typically millions of production units the individual IC cost is minimized. The performance
of ICs is high because the small size allows short traces which in turn allows low power logic (such as
CMOS) to be used at fast switching speeds.

ICs have consistently migrated to smaller feature sizes over the years, allowing more circuitry to be
packed on each chip. This increased capacity per unit area can be used to decrease cost and/or increase
functionality—see Moore's law which, in its modern interpretation, states that the number of
transistors in an integrated circuit doubles every two years. In general, as the feature size shrinks,
almost everything improves—the cost per unit and the switching power consumption go down, and the
speed goes up. However, ICs with nanometer-scale devices are not without their problems, principal
among which is leakage current (see subthreshold leakage for a discussion of this), although these
problems are not insurmountable and will likely be solved or at least ameliorated by the introduction of
high-k dielectrics. Since these speed and power consumption gains are apparent to the end user, there
is fierce competition among the manufacturers to use finer geometries. This process, and the expected

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progress over the next few years, is well described by the International Technology Roadmap for
Semiconductors (ITRS).

In current research projects, integrated circuits are also developed for sensoric applications in medical
implants or other bio-electronic devices. Particular sealing strategies have to be taken in such biogenic
environments to avoid corrosion or biodegradation of the exposed semiconductor materials.[19] As one
of the few materials well established in CMOS technology, titanium nitride (TiN) turned out as
exceptionally stable and well suited for electrode applications in medical implants.

Popularity of ICs
Only a half century after their development was initiated ,integrated circuits have become ubiquitous.
computers, cellular phones, and other digital appliances are now inextricable parts of the structure of
modern societies. that is modern computing, communications, manufacturing and transport systems,
including the internet, all depend on the existence of integrated circuits. indeed many scholars believe
that the digital revolution brought about by integrated circuits was one of the most significant
occurrences in the history of mankind.

Classification

A CMOS4000 IC in a DIP

Integrated circuits can be classified into analog, digital and mixed signal (both analog and digital on the
same chip).

Digital integrated circuits can contain anything from one to millions of logic gates, flip-flops,
multiplexers, and other circuits in a few square millimeters. The small size of these circuits allows high
speed, low power dissipation, and reduced manufacturing cost compared with board-level integration.
These digital ICs, typically microprocessors, DSPs, and micro controllers, work using binary mathematics
to process "one" and "zero" signals.

Analog ICs, such as sensors, power management circuits, and operational amplifiers, work by processing
continuous signals. They perform functions like amplification, active filtering, demodulation, and mixing.
Analog ICs ease the burden on circuit designers by having expertly designed analog circuits available
instead of designing a difficult analog circuit from scratch.

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ICs can also combine analog and digital circuits on a single chip to create functions such as A/D
converters and D/A converters. Such mixed-signal circuits offer smaller size and lower cost, but must
carefully account for signal interference.

Modern electronic component distributors often further sub-categorize the huge variety of integrated
circuits now available:

 Digital ICs are further sub-categorized as logic ICs, memory chips, interface ICs (level shifters,
serializer/deserializer, etc.), Power Management ICs, and programmable devices.
 Analog ICs are further sub-categorized as linear ICs and RF ICs.
 mixed-signal integrated circuits are further sub-categorized as data acquisition ICs (including
A/D converters, D/A converter, digital potentiometers) and clock/timing ICs.

Manufacturing
Fabrication

The semiconductors of the periodic table of the chemical elements were identified as the most likely
materials for a solid-statevacuum tube. Starting with copper oxide, proceeding to germanium, then
silicon, the materials were systematically studied in the 1940s and 1950s. Today, silicon monocrystals
are the main substrate used for ICs although some III-V compounds of the periodic table such as gallium
arsenide are used for specialized applications like LEDs, lasers, solar cells and the highest-speed
integrated circuits. It took decades to perfect methods of creating crystals without defects in the
crystalline structure of the semiconducting material.

Semiconductor ICs are fabricated in a layer process which includes these key process steps:

 Imaging
 Deposition
 Etching

The main process steps are supplemented by doping and cleaning.

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Mono-crystal siliconwafers (or for special applications, silicon on sapphire or gallium arsenide wafers)
are used as the substrate. Photolithography is used to mark different areas of the substrate to be doped
or to have polysilicon, insulators or metal (typically aluminium) tracks deposited on them.

 Integrated circuits are composed of many overlapping layers, each defined by photolithography,
and normally shown in different colors. Some layers mark where various dopants are diffused
into the substrate (called diffusion layers), some define where additional ions are implanted
(implant layers), some define the conductors (polysilicon or metal layers), and some define the
connections between the conducting layers (via or contact layers). All components are
constructed from a specific combination of these layers.
 In a self-aligned CMOS process, a transistor is formed wherever the gate layer (polysilicon or
metal) crosses a diffusion layer.
 Capacitive structures, in form very much like the parallel conducting plates of a traditional
electrical capacitor, are formed according to the area of the "plates", with insulating material
between the plates. Capacitors of a wide range of sizes are common on ICs.
 Meandering stripes of varying lengths are sometimes used to form on-chip resistors, though
most logic circuits do not need any resistors. The ratio of the length of the resistive structure to
its width, combined with its sheet resistivity, determines the resistance.
 More rarely, inductive structures can be built as tiny on-chip coils, or simulated by gyrators.

Since a CMOS device only draws current on the transition between logicstates, CMOS devices consume
much less current than bipolar devices.

A random access memory is the most regular type of integrated circuit; the highest density devices are
thus memories; but even a microprocessor will have memory on the chip. (See the regular array
structure at the bottom of the first image.) Although the structures are intricate – with widths which
have been shrinking for decades – the layers remain much thinner than the device widths. The layers of
material are fabricated much like a photographic process, although light waves in the visible spectrum
cannot be used to "expose" a layer of material, as they would be too large for the features. Thus
photons of higher frequencies (typically ultraviolet) are used to create the patterns for each layer.
Because each feature is so small, electron microscopes are essential tools for a process engineer who
might be debugging a fabrication process.

Each device is tested before packaging using automated test equipment (ATE), in a process known as
wafer testing, or wafer probing. The wafer is then cut into rectangular blocks, each of which is called a
die. Each good die (plural dice, dies, or die) is then connected into a package using aluminium (or gold)
bond wires which are thermosonic bonded[22] to pads, usually found around the edge of the die. .
Thermosonic bonding was first introduced by A. Coucoulas which provided a reliable means of forming
these vital electrical connections to the outside world. After packaging, the devices go through final
testing on the same or similar ATE used during wafer probing. Industrial CT scanning can also be used.
Test cost can account for over 25% of the cost of fabrication on lower cost products, but can be
negligible on low yielding, larger, and/or higher cost devices.

As of 2005, a fabrication facility (commonly known as a semiconductor fab) costs over US$1 billion to
construct,[23] because much of the operation is automated. Today, the most advanced processes employ
the following techniques:

 The wafers are up to 300 mm in diameter (wider than a common dinner plate).

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  Use of 32 nanometer or smaller chip manufacturing process. Intel, IBM, NEC, and AMD are using
~32 nanometers for their CPU chips. IBM and AMD introduced immersion lithography for their
45 nm processes
 Copper interconnects where copper wiring replaces aluminium for interconnects.
 Low-K dielectric insulators.
 Silicon on insulator (SOI)
 Strained silicon in a process used by IBM known as strained silicon directly on insulator (SSDOI)
 Multigate devices such as tri-gate transistors being manufactured by Intel from 2011 in their
22 nm process.

Packaging

The earliest integrated circuits were packaged in ceramic flat packs, which continued to be used by the
military for their reliability and small size for many years. Commercial circuit packaging quickly moved to
the dual in-line package (DIP), first in ceramic and later in plastic. In the 1980s pin counts of VLSI circuits
exceeded the practical limit for DIP packaging, leading to pin grid array (PGA) and leadless chip carrier
(LCC) packages. Surface mount packaging appeared in the early 1980s and became popular in the late
1980s, using finer lead pitch with leads formed as either gull-wing or J-lead, as exemplified by small-
outline integrated circuit – a carrier which occupies an area about 30–50% less than an equivalent DIP,
with a typical thickness that is 70% less. This package has "gull wing" leads protruding from the two long
sides and a lead spacing of 0.050 inches.

In the late 1990s, plastic quad flat pack (PQFP) and thin small-outline package (TSOP) packages became
the most common for high pin count devices, though PGA packages are still often used for high-end
microprocessors. Intel and AMD are currently transitioning from PGA packages on high-end
microprocessors to land grid array (LGA) packages.

Ball grid array (BGA) packages have existed since the 1970s. Flip-chip Ball Grid Array packages, which
allow for much higher pin count than other package types, were developed in the 1990s. In an FCBGA
package the die is mounted upside-down (flipped) and connects to the package balls via a package
substrate that is similar to a printed-circuit board rather than by wires. FCBGA packages allow an array
of input-output signals (called Area-I/O) to be distributed over the entire die rather than being confined
to the die periphery.

Traces out of the die, through the package, and into the printed circuit board have very different
electrical properties, compared to on-chip signals. They require special design techniques and need
much more electric power than signals confined to the chip itself.

When multiple dies are put in one package, it is called SiP, for System In Package. When multiple dies
are combined on a small substrate, often ceramic, it's called an MCM, or Multi-Chip Module. The
boundary between a big MCM and a small printed circuit board is sometimes fuzzy.

History, Origins, and Generations

The Birth of the IC

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The idea of the integrated circuit was conceived by a radar scientist working for the Royal Radar
Establishment of the British Ministry of Defence, Geoffrey W.A. Dummer (1909–2002). Dummer
presented the idea to the public at the Symposium on Progress in Quality Electronic Components in
Washington, D.C. on 7 May 1952. He gave many symposia publicly to propagate his ideas, and
unsuccessfully attempted to build such a circuit in 1956.

A precursor idea to the IC was to create small ceramic squares (wafers), each one containing a single
miniaturized component. Components could then be integrated and wired into a bidimensional or
tridimensional compact grid. This idea, which looked very promising in 1957, was proposed to the US
Army by Jack Kilby, and led to the short-lived Micromodule Program (similar to 1951's Project
Tinkertoy). However, as the project was gaining momentum, Kilby came up with a new, revolutionary
design the IC.

The first integrated circuits were manufactured independently by two scientists:jackkilby of Texas
Instruments filed a patent for a “solid circuit” madfe of germanium on February 6,1959.kilby received
patents U.S. patent 3434015.Robert Noyce of Fairchild semiconductor was awarded a patent for a more
complex “unitary circuit” made of silicon on April 25,1961.

Noyce credited Kurt lehovec of Sprague electric for the principle of p-n junction isolsation caused by the
action of a biased p-n junction(the diode) as a key concept behind the IC.

SSI,MSI,LSI
The first integrated circuits contained only a few transistors, Called "small-scale integration" (SSI), They
used digital circuits containing transistors numbering in the tens provided a few logic gates.

SSI circuits were crucial to early aerospace projects, and aerospace projects helped inspire development
of the technology. Both the Minuteman missile and Apollo program needed lightweight digital
computers for their inertial guidance systems; the Apollo guidance computer led and motivated the
integrated-circuit technology, while the Minuteman missile forced it into mass-production.

The Minuteman missile program and various other Navy programs accounted for the total $4 million
integrated circuit market in 1962, and by 1968, U.S. Government space and defense spending still
accounted for 37% of the $312 million total production. The demand by the U.S. Government supported
the nascent integrated circuit market until costs fell enough to allow firms to penetrate the industrial
and eventually the consumer markets. The average price per integrated circuit dropped from $50.00 in
1962 to $2.33 in 1968. Integrated circuits began to appear in consumer products by the turn of the
decade, a typical application being FM inter-carrier sound processing in television receivers.

The next step in the development of integrated circuits, taken in the late 1960s, introduced devices
which contained hundreds of transistors on each chip, called "medium-scale integration" (MSI).

They were attractive economically because while they cost little more to produce than SSI devices, they
allowed more complex systems to be produced using smaller circuit boards, less assembly work
(because of fewer separate components), and a number of other advantages.

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Further development, driven by the same economic factors, led to "large-scale integration" (LSI) in the
mid 1970s, with tens of thousands of transistors per chip.

Integrated circuits such as 1K-bit RAMs, calculator chips, and the first microprocessors, that began to be
manufactured in moderate quantities in the early 1970s, had under 4000 transistors. True LSI circuits,
approaching 10,000 transistors, began to be produced around 1974, for computer main memories and
second-generation microprocessors.

VLSI

The final step in the development process, starting in the 1980s and continuing through the present,
was "very large-scale integration" (VLSI). The development started with hundreds of thousands of
transistors in the early 1980s, and continues beyond several billion transistors as of 2009.

Multiple developments were required to achieve this increased density. Manufacturers moved to
smaller design rules and cleaner fabrication facilities, so that they could make chips with more
transistors and maintain adequate yield. The path of process improvements was summarized by the
International Technology Roadmap for Semiconductors (ITRS). Design tools improved enough to make it
practical to finish these designs in a reasonable time. The more energy efficient CMOS replaced NMOS
and PMOS, avoiding a prohibitive increase in power consumption.

In 1986 the first one megabit RAM chips were introduced, which contained more than one million
transistors. Microprocessor chips passed the million transistor mark in 1989 and the billion transistor
mark in 2005. The trend continues largely unabated, with chips introduced in 2007 containing tens of
billions of memory transistors.

ULSI,WSI,SOC

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To reflect further growth of the complexity, the term ULSI that stands for "ultra-large-scale integration"
was proposed for chips of complexity of more than 1 million transistors. However there is no qualitative
leap between VLSI and ULSI, hence normally in technical texts the vlsi term covers ULSI as well, and
ULSI is reserved only for cases when it is necessary to emphasize the chip complexity, e.g.in marketing

Wafer-scale integration (WSI) is a system of building very-large integrated circuits that uses an entire
silicon wafer to produce a single "super-chip". Through a combination of large size and reduced
packaging, WSI could lead to dramatically reduced costs for some systems, notably massively parallel
supercomputers. The name is taken from the term Very-Large-Scale Integration, the current state of the
art when WSI was being developed.

A system-on-a-chip (SoC or SOC) is an integrated circuit in which all the components needed for a
computer or other system are included on a single chip. The design of such a device can be complex and
costly, and building disparate components on a single piece of silicon may compromise the efficiency of
some elements. However, these drawbacks are offset by lower manufacturing and assembly costs and
by a greatly reduced power budget: because signals among the components are kept on-die, much less
power is required.

Other developments
In the 1980s, programmable logic devices were developed. These devices contain circuits whose logical
function and connectivity can be programmed by the user, rather than being fixed by the integrated
circuit manufacturer. This allows a single chip to be programmed to implement different LSI-type
functions such as logic gates, adders and registers. Current devices called field-programmable gate
arrays can now implement tens of thousands of LSI circuits in parallel and operate up to 1.5 GHz
(Achronix holding the speed record).

The techniques perfected by the integrated circuits industry over the last three decades have been used
to create very small mechanical devices driven by electricity using a technology known as
microelectromechanical systems. These devices are used in a variety of commercial and military
applications. Example commercial applications include DLP projectors, inkjet printers, and
accelerometers used to deploy automobile airbags.

In the past, radios could not be fabricated in the same low-cost processes as microprocessors. But since
1998, a large number of radio chips have been developed using CMOS processes. Examples include
Intel's DECT cordless phone, or Atheros's 802.11 card.

Future developments seem to follow the multi-core multi-microprocessor paradigm, already used by the
Intel and AMD dual-core processors. Rapport Inc. and IBM started shipping the KC256 in 2006, a 256-
core microprocessor. Intel, as recently as February–August 2011, unveiled a prototype, "not for
commercial sale" chip that bears 80 cores. Each core is capable of handling its own task independently
of the others. This is in response to the heat-versus-speed limit that is about to be reached using existing
transistor technology (see: thermal design power). This design provides a new challenge to chip
programming. Parallel programming languages such as the open-source X10 programming language are
designed to assist with this task.

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Since the early 2000s, the integration of optical functionality into silicon chips has been actively pursued
in both academic research and in industry resulting in the successful commercialization of silicon based
integrated optical transceivers combining optical devices (modulators, detectors, routing) with CMOS
based electronics.

Ever since ICs were created, some chip designers have used the silicon surface area for surreptitious,
non-functional images or words. These are sometimes referred to as chip Art, or silicon Art, or silicon
Graffiti, or silicon Doodling.

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DIGITAL
ELECTRONICS

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 Introduction

Digital electronics is classified into combinational logic and sequential logic.

Combinational logic output depends on the inputs levels, whereas sequential logic
output depends on stored levels and also the input levels.

The memory elements are devices capable of storing binary info. The binary info
stored in the memory elements at any given time defines the state of the sequential
circuit. The input and the present state of the memory element determines the output.
Memory elements next state is also a function of external inputs and present state. A
sequential circuit is specified by a time sequence of inputs, outputs, and internal
states.

Numbering System
Many number systems are in use in digital technology. The most common are the
decimal, binary, octal, and hexadecimal systems. The decimal system is clearly the
most familiar to us because it is a tool that we use every day. Examining some of its
characteristics will help us to better understand the other systems. In the next few
pages we shall introduce four numerical representation systems that are used in the
digital system. There are other systems, which we will look at briefly.

 Decimal
 Binary
 Octal
 Hexadecimal

Decimal System
The decimal system is composed of 10 numerals or symbols. These 10 symbols are
0, 1, 2, 3, 4, 5, 6, 7, 8, 9. Using these symbols as digits of a number, we can express
any quantity. The decimal system is also called the base-10 system because it has
10 digits.

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 103 102 101 100 10-1 10-2 10-3
=1000 =100 =10 =1 . =0.1 =0.01 =0.001
Least
Most Significant
Decimal point Significant
Digit
Digit

Binary Codes
Binary codes are codes which are represented in binary system with modification
from the original ones. Below we will be seeing the following:

 Weighted Binary Systems

 Non Weighted Codes

Weighted Binary Systems

Weighted binary codes are those which obey the positional weighting principles, each
position of the number represents a specific weight. The binary counting sequence is
an example.

Decimal 8421 2421 5211 Excess-3

0 0000 0000 0000 0011
1 0001 0001 0001 0100
2 0010 0010 0011 0101
3 0011 0011 0101 0110
4 0100 0100 0111 0111
5 0101 1011 1000 1000
6 0110 1100 1010 1001
7 0111 1101 1100 1010
8 1000 1110 1110 1011
9 1001 1111 1111 1100

8421 Code/BCD Code

The BCD (Binary Coded Decimal) is a straight assignment of the binary equivalent. It is
possible to assign weights to the binary bits according to their positions. The weights in
the BCD code are 8,4,2,1.
Example: The bit assignment 1001, can be seen by its weights to represent the decimal
9 because:
1x8+0x4+0x2+1x1 = 9
2421 Code

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 This is a weighted code, its weights are 2, 4, 2 and 1. A decimal number is represented
in 4-bit form and the total four bits weight is 2 + 4 + 2 + 1 = 9. Hence the 2421 code
represents the decimal numbers from 0 to 9.

5211 Code
This is a weighted code, its weights are 5, 2, 1 and 1. A decimal number is represented
in 4-bit form and the total four bits weight is 5 + 2 + 1 + 1 = 9. Hence the 5211 code
represents the decimal numbers from 0 to 9.

Non weighted codes

Non weighted codes are codes that are not positionally weighted. That is each position
within the binary number is not assigned a fixed value.

Excess-3 Code

It is a Nonweighted code used to express decimal numbers. The code derives its name
from the fact that each binary code is the corresponding 8421 code plus 0011(3).

Gray Code

The gray code belongs to a class of codes called minimum change codes, in which only
one bit in the code changes when moving from one code to the next. The gray code is
non weighted code as the position of bit does not contain any weight. The gray code is
a reflective digital code which has the special property that any two subsequent
numbers codes differ by only one bit. This is also called as unit distance code. In digital
gray code has got a special place.

Decimal Number Binary Code Gray Code

0 0000 0000
1 0001 0001
2 0010 0011
3 0011 0010
4 0100 0110
5 0101 0111
6 0110 0101
7 0111 0100
8 1000 1100
9 1001 1101
10 1010 1111
11 1011 1110
12 1100 1010

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 13 1101 1011
14 1110 1001
15 1111 1000

Summary of laws and Theorems

Identity Dual
Operations with 0 and 1
X + 0 = X (identity) X.1 = X
X + 1 = 1 (null element) X.0 = 0
Idempotency theorem
X+X=X X.X = X
Complementarity
X + X' = 1 X.X' = 0
Involution theorem
(X')' = X
Cummutative law
X+Y=Y+X X.Y = Y X
Associative law
(X + Y) + Z = X + (Y + Z) = X + Y + Z (XY)Z = X(YZ) = XYZ
Distributive law
X(Y + Z) = XY + XZ X + (YZ) = (X + Y)(X + Z)
DeMorgan's theorem
(X + Y + Z + ...)' = X'Y'Z'... or { f (
X1,X2,...,Xn,0,1,+,. ) } = { f ( (XYZ...)' = X' + Y' + Z' + ...
X1',X2',...,Xn',1,0,.,+ ) }
Simplification theorems
XY + XY' = X (uniting) (X + Y)(X + Y') = X
X + XY = X (absorption) X(X + Y) = X
(X + Y')Y = XY (adsorption) XY' + Y = X + Y
Consensus theorem
XY + X'Z + YZ = XY + X'Z (X + Y)(X' + Z)(Y + Z) = (X + Y)(X' + Z)
Duality
(X + Y + Z + ...)D = XYZ... or
{f(X1,X2,...,Xn,0,1,+,.)}D = (XYZ ...)D = X + Y + Z + ...
f(X1,X2,...,Xn,1,0,.,+)

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Combinational Circuits
Multiplexer

A multiplexer (MUX) is a digital switch which connects data from one of n sources to the
output. A number of select inputs determine which data source is connected to the
output. Basically a Mux has ‘n’ Selection line,’2n’ dataline or inputline and one single
output line.Block diagram of MUX with data inputs and with select line is shown in
below figure.

Example of 4:1 MUX

Truth Table

S1 S0 Y
0 0 I0
0 1 I1
1 0 I2
1 1 I3

De-multiplexers

They are digital switches which connect data from one input source to one of n outputs.
Basically demux has one input line which always remain very high,’n’ selection line and
2n output line. Block diagram of Dmux has shown below.

Example Of 1:4 Dmux

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TRUTH TABLE

S1 S0
0 0
0 1
1 0
1 1
F0 F1
D 0
0 D
0 0
0 0
F2 F3
0 0
0 0
D 0
0 D

Decoders
A decoder is a multiple-input, multiple-output logic circuit that converts coded inputs into
coded outputs, where the input and output codes are different; e.g. n-to-2n, BCD
decoders.

Enable inputs must be on for the decoder to function, otherwise its outputs assume a
single "disabled" output code word.

Decoding is necessary in applications such as data multiplexing, 7 segment display and

memory address decoding. Figure below shows the pseudo block of a decoder.

Binary n-to-2n Decoders

A binary decoder has n inputs and 2n outputs. Only one output is active at any one time,
corresponding to the input value. Figure below shows a representation of Binary n-to-
2n decoder

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Example of 2 to 4 Binary Decoder

A 2 to 4 decoder consists of 2 inputs and 4 outputs.Truth Table and Symbol are shown bellow.

Truth Table

X Y F0 F1
0 0 1 0
0 1 0 1
1 0 0 0
1 1 0 0
F2 F3
0 0
0 0
1 0
0 1

Encoders
An encoder is a combinational circuit that performs the inverse operation of a decoder.
If a device output code has fewer bits than the input code has, the device is usually
called an encoder. e.g. 2n-to-n, priority encoders. The simplest encoder is a 2n-to-n
binary encoder, where it has only one of 2ninputs = 1 and the output is the n-bit binary
number corresponding to the active input.

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Concept of Sequential Logic

A sequential circuit as seen in the last page, is combinational logic with some feedback
to maintain its current value, like a memory cell. To understand the basics let's consider
the basic feedback logic circuit below, which is a simple NOT gate whose output is
connected to its input. The effect is that output oscillates between HIGH and LOW (i.e. 1
and 0). Oscillation frequency depends on gate delay and wire delay. Assuming a wire
delay of 0 and a gate delay of 10ns, then oscillation frequency would be (on time + off
time = 20ns) 50Mhz.

The basic idea of having the feedback is to store the value or hold the value, but in the
above circuit, output keeps toggling. We can overcome this problem with the circuit
below, which is basically cascading two inverters, so that the feedback is in-phase, thus
avoids toggling. The equivalent circuit is the same as having a buffer with its output
connected to its input.

There are two types of sequential circuits. Their classification depends on the timing of
their signals:

 Synchronous sequential circuits

 Asynchronous sequential circuits

25 | P a g e
Latches and Flip-Flops

Latches and Flip-flops are one and the same with a slight variation,Latches have level
sensitive control signal input and Flip-flops have edge sensitive control signal input.
Flip-flops and latches which use this control signals are called synchronous circuits. So
if they don't use clock inputs, then they are called asynchronous circuits

RS Latch

RS latch have two inputs, S and R. S is called set and R is called reset. The S input is
used to produce HIGH on Q ( i.e. store binary 1 in flip-flop). The R input is used to
produce LOW on Q (i.e. store binary 0 in flip-flop). Q' is Q complementary output, so it
always holds the opposite value of Q. The output of the S-R latch depends on current
as well as previous inputs or state, and its state (value stored) can change as soon as
its inputs change. The circuit and the truth table of RS latch is shown below.

The circuit and Truth table of RS latch using NAND is also shown below.

Truth Table Of Both Nor and NAnd SR latch

S R Q Q+ S R Q Q+
0 0 0 0 1 1 0 0
0 0 1 1 1 1 1 1
0 1 X 0 0 1 X 0
1 0 X 1 1 0 X 1
1 1 X 0 0 0 X 1

26 | P a g e
If you look closely, there is no control signal (i.e. no clock and no enable), so this kind of
latches or flip-flops are called asynchronous logic elements. Since all the sequential
circuits are built around the RS latch, we will concentrate on synchronous circuits and
not on asynchronous circuits.

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METAL OXIDE
SEMICONDUTOR

28 | P a g e
MOS
The metal–oxide–semiconductor field-effect transistor (MOSFET, MOS-FET, or MOS FET) is
a transistor used for amplifying or switching electronic signals. Although the MOSFET is a four-terminal
device with source (S), gate (G), drain (D), and body (B) terminals,[1] the body (or substrate) of the
MOSFET often is connected to the source terminal, making it a three-terminal device like other field-
effect transistors. Because these two terminals are normally connected to each other (short-circuited)
internally, only three terminals appear in electrical diagrams. The MOSFET is by far the most
common transistor in both digital and analog circuits, though the bipolar junction transistor was at one
time much more common.
In enhancement mode MOSFETs, a voltage drop across the oxide induces a conducting channel between
the source and drain contacts via the field effect. The term "enhancement mode" refers to the increase
of conductivity with increase in oxide field that adds carriers to the channel, also referred to as
the inversion layer. The channel can contain electrons (called an nMOSFET or nMOS), or holes (called a
pMOSFET or pMOS), opposite in type to the substrate, so nMOS is made with a p-type substrate, and
pMOS with an n-type substrate (see article on semiconductor devices). In the less common depletion
mode MOSFET, detailed later on, the channel consists of carriers in a surface impurity layer of opposite
type to the substrate, and conductivity is decreased by application of a field that depletes carriers from
this surface layer.[2]
The 'metal' in the name MOSFET is now often a misnomer because the previously metal gate material is
now often a layer of polysilicon (polycrystalline silicon). Aluminium had been the gate material until the
mid 1970s, when polysilicon became dominant, due to its capability to form self-aligned gates. Metallic
gates are regaining popularity, since it is difficult to increase the speed of operation of transistors
without metal gates.
Likewise, the 'oxide' in the name can be a misnomer, as different dielectric materials are used with the
aim of obtaining strong channels with applied smaller voltages.
An insulated-gate field-effect transistor or IGFET is a related term almost synonymous with MOSFET. The
term may be more inclusive, since many "MOSFETs" use a gate that is not metal, and a gate insulator
that is not oxide. Another synonym is MISFET for metal–insulator–semiconductor FET.

HISTORY OF MOSFET
The basic principle of this kind of transistor was first patented by Julius Edgar Lilienfeld in 1925. Twenty
five years later, when Bell Telephone attempted to patent the junction transistor, they found Lilienfeld
already holding a patent which was worded in a way that would include all types of transistors. Bell Labs
was able to work out an agreement with Lilienfeld, who was still alive at that time (it is not known if they
paid him money or not). It was at that time the Bell Labs version was given the name bipolar junction
transistor, or simply junction transistor, and Lilienfeld's design took the name field effect transistor.
In 1959, Dawon Kahng and Martin M. (John) Atalla at Bell Labs invented the metal–oxide–
semiconductor field-effect transistor (MOSFET) as an offshoot to the patented FET design. Operationally
and structurally different from the bipolar junction transistor,[23]the MOSFET was made by putting an
insulating layer on the surface of the semiconductor and then placing a metallic gate electrode on that.
It used crystalline silicon for the semiconductor and a thermally oxidized layer of silicon dioxide for the
insulator. The silicon MOSFET did not generate localized electron traps at the interface between the

29 | P a g e
silicon and its native oxide layer, and thus was inherently free from the trapping and scattering of
carriers that had impeded the performance of earlier field-effect transistors. Following the development
of clean rooms to reduce contamination to levels never before thought necessary, and
of photolithography and theplanar process to allow circuits to be made in very few steps, the Si–
SiO2 system possessed such technical attractions as low cost of production (on a per circuit basis) and
ease of integration. Additionally, the method of coupling two complementary MOSFETS (P-channel and
N-channel) into one high/low switch, known as CMOS, means that digital circuits dissipate very little
power except when actually switched. Largely because of these three factors, the MOSFET has become
the most widely used type of transistor inintegrated circuits.

Metal–oxide–semiconductor structure
The traditional metal–oxide–semiconductor (MOS) structure is obtained by growing a layer of silicon
dioxide (SiO2) on top of a silicon substrate and depositing a layer of metal or polycrystalline silicon (the
latter is commonly used). As the silicon dioxide is a dielectricmaterial, its structure is equivalent to a
planar capacitor, with one of the electrodes replaced by a semiconductor. When a voltage is applied
across a MOS structure, it modifies the distribution of charges in the semiconductor. If we consider a p-
type semiconductor (with the density of acceptors, p the density of holes; p = NA in neutral bulk), a
positive voltage, , from gate to body (see figure) creates a depletion layer by forcing the positively
charged holes away from the gate-insulator/semiconductor interface, leaving exposed a carrier-free
region of immobile, negatively charged acceptor ions (see doping (semiconductor)). If is high
enough, a high concentration of negative charge carriers forms in an inversion layer located in a thin
layer next to the interface between the semiconductor and the insulator. Unlike the MOSFET, where the
inversion layer electrons are supplied rapidly from the source/drain electrodes, in the MOS capacitor
they are produced much more slowly by thermal generation through carrier generation and
recombination centers in the depletion region. Conventionally, the gate voltage at which the volume
density of electrons in the inversion layer is the same as the volume density of holes in the body is called
the threshold voltage. When the voltage between transistor gate and source (VGS) exceeds the threshold
voltage (Vth), it is known as overdrive voltage.
This structure with p-type body is the basis of the n-type MOSFET, which requires the addition of an n-
type source and drain regions.

30 | P a g e
31 | P a g e
32 | P a g e
MOSFET structure and channel formation

Channel formation in nMOS MOSFET: Top panels: An applied gate voltage bends bands, depleting holes from surface (left).
The charge inducing the bending is balanced by a layer of negative acceptor-ion charge (right). Bottom panel: A larger
applied voltage further depletes holes but conduction band lowers enough in energy to populate a conducting channel.

33 | P a g e
by a MOS capacitance between a body electrode and a gate electrode located above the body and
insulated from all other device regions by a gate dielectric layer which in the case of a MOSFET is an
oxide, such as silicon dioxide. If dielectrics other than an oxide such as silicon dioxide (often referred to
as oxide) are employed the device may be referred to as a metal–insulator–semiconductor FET
(MISFET). Compared to the MOS capacitor, the MOSFET includes two additional terminals
(source and drain), each connected to individual highly doped regions that are separated by the body
region. These regions can be either p or n type, but they must both be of the same type, and of opposite
type to the body region. The source and drain (unlike the body) are highly doped as signified by a '+' sign
after the type of doping.
If the MOSFET is an n-channel or nMOS FET, then the source and drain are 'n+' regions and the body is a
'p' region. If the MOSFET is a p-channel or pMOS FET, then the source and drain are 'p+' regions and the
body is a 'n' region. The source is so named because it is the source of the charge carriers (electrons for
n-channel, holes for p-channel) that flow through the channel; similarly, the drain is where the charge
carriers leave the channel.
The occupancy of the energy bands in a semiconductor is set by the position of the Fermi level relative
to the semiconductor energy-band edges. As described above, and shown in the figure, with sufficient
gate voltage, the valence band edge is driven far from the Fermi level, and holes from the body are
driven away from the gate. At larger gate bias still, near the semiconductor surface the conduction band
edge is brought close to the Fermi level, populating the surface with electrons in an inversion layer or n-
channel at the interface between the p region and the oxide. This conducting channel extends between
the source and the drain, and current is conducted through it when a voltage is applied between the
two electrodes. Increasing the voltage on the gate leads to a higher electron density in the inversion
layer and therefore increases the current flow between the source and drain.
For gate voltages below the threshold value, the channel is lightly populated, and only a very
small subthreshold leakage current can flow between the source and the drain.
When a negative gate-source voltage (positive source-gate) is applied, it creates a p-channel at the
surface of the n region, analogous to the n-channel case, but with opposite polarities of charges and
voltages. When a voltage less negative than the threshold value (a negative voltage for p-channel) is
applied between gate and source, the channel disappears and only a very small subthreshold current
can flow between the source and the drain.
The device may comprise a Silicon On Insulator (SOI) device in which a buried oxide (BOX) is formed
below a thin semiconductor layer. If the channel region between the gate dielectric and a BOX region is
very thin, the very thin channel region is referred to as an ultrathin channel (UTC) region with the source
and drain regions formed on either side thereof in and/or above the thin semiconductor layer.
Alternatively, the device may comprise a semiconductor on insulator (SEMOI) device in which
semiconductors other than silicon are employed. Many alternative semiconductor materials may be
employed.
When the source and drain regions are formed above the channel in whole or in part, they are referred
to as raised source/drain (RSD) regions.

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Modes of operation

Ohmic contact to body to ensure no body bias; top left: subthreshold, top right: Ohmic mode, bottom left: Active mode at
onset of pinch-off, bottom right: Active mode well into pinch-off – channel length modulation evident

The operation of a MOSFET can be separated into three different modes, depending on the voltages at
the terminals. In the following discussion, a simplified algebraic model is used. Modern MOSFET
characteristics are more complex than the algebraic model presented here.

 For an enhancement-mode, n-channel MOSFET, the three operational modes are:

Cutoff, subthreshold, or weak-inversion mode

When VGS < Vth:

where is gate-to-source bias and is the threshold voltage of the device.

According to the basic threshold model, the transistor is turned off, and there is no conduction
between drain and source. A more accurate model considers the effect of thermal energy on
the Boltzmann distribution of electron energies which allow some of the more energetic electrons
at the source to enter the channel and flow to the drain. This results in a subthreshold current that
is an exponential function of gate–source voltage. While the current between drain and source
should ideally be zero when the transistor is being used as a turned-off switch, there is a weak-
inversion current, sometimes called subthreshold leakage.
In weak inversion the current varies exponentially with .

35 | P a g e
Triode mode or linear region (also known as the ohmic mode)
When VGS > Vth and VDS < ( VGS – Vth )
The transistor is turned on, and a channel has been created which allows current to flow
between the drain and the source. The MOSFET operates like a resistor, controlled by the gate
voltage relative to both the source and drain voltages.

MOSFET drain current vs. drain-to-source voltage for several values of ; the boundary
between linear (Ohmic) and saturation(active) modes is indicated by the upward curving parabola.

Saturation or active mode

When VGS > Vth and VDS ≥ ( VGS – Vth )
The switch is turned on, and a channel has been created, which allows current to flow between
the drain and source. Since the drain voltage is higher than the gate voltage, the electrons
spread out, and conduction is not through a narrow channel but through a broader, two- or
three-dimensional current distribution extending away from the interface and deeper in the
substrate. The onset of this region is also known as pinch-off to indicate the lack of channel
region near the drain. The drain current is now weakly dependent upon drain voltage and
controlled primarily by the gate–source voltage

Cross section of a MOSFET operating in the saturation (active) region; channel exhibits pinch-off near drain

36 | P a g e
MOSFET Scaling
Over the past decades, the MOSFET has continually been scaled down in size; typical MOSFET channel
lengths were once severalmicrometres, but modern integrated circuits are incorporating MOSFETs with
channel lengths of tens of nanometers. Robert Dennard's work on scaling theory was pivotal in
recognising that this ongoing reduction was possible. Intel began production of a process featuring a
32 nm feature size (with the channel being even shorter) in late 2009. The semiconductor industry
maintains a "roadmap", the ITRS,[27] which sets the pace for MOSFET development. Historically, the
difficulties with decreasing the size of the MOSFET have been associated with the semiconductor device
fabrication process, the need to use very low voltages, and with poorer electrical performance
necessitating circuit redesign and innovation (small MOSFETs exhibit higher leakage currents, and lower
output resistance, discussed below).
Reasons for MOSFET scaling
Smaller MOSFETs are desirable for several reasons. The main reason to make transistors smaller is to
pack more and more devices in a given chip area. This results in a chip with the same functionality in a
smaller area, or chips with more functionality in the same area. Since fabrication costs for
a semiconductor wafer are relatively fixed, the cost per integrated circuits is mainly related to the number
of chips that can be produced per wafer. Hence, smaller ICs allow more chips per wafer, reducing the
price per chip. In fact, over the past 30 years the number of transistors per chip has been doubled every
2–3 years once a new technology node is introduced. For example the number of MOSFETs in a
microprocessor fabricated in a 45 nm technology can well be twice as many as in a 65 nm chip. This
doubling of transistor density was first observed by Gordon Moore in 1965 and is commonly referred to
as Moore's law.

It is also expected that smaller transistors switch faster. For example, one approach to size reduction is a
scaling of the MOSFET that requires all device dimensions to reduce proportionally. The main device
dimensions are the channel length, channel width, and oxide thickness. When they are scaled down by
equal factors, the transistor channel resistance does not change, while gate capacitance is cut by that
factor. Hence, the RC delay of the transistor scales with a similar factor.

While this has been traditionally the case for the older technologies, for the state-of-the-art MOSFETs
reduction of the transistor dimensions does not necessarily translate to higher chip speed because the
delay due to interconnections is more significant.

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Complementary metal oxide
semiconductor

38 | P a g e
Complementary metal–oxide–semiconductor (CMOS)-
in microprocessors, microcontrollers, static RAM, and other digital logic circuits. CMOS technology is
also used for several analog circuits such as image sensors (CMOS sensor), data converters, and highly
integrated transceivers for many types of communication. Frank Wanlass patented CMOS in 1967 (US
patent 3,356,858).
CMOS is also sometimes referred to as complementary-symmetry metal–oxide–semiconductor (or
COS-MOS). The words "complementary-symmetry" refer to the fact that the typical digital design style
with CMOS uses complementary and symmetrical pairs of p-type and n-type metal oxide semiconductor
field effect transistors (MOSFETs) for logic functions.
Two important cmos is a technology for constructing integrated circuits. CMOS technology is used
characteristics of CMOS devices are high noise immunity and low static power. Since one transistor of
the pair is always off, the series combination draws significant power only momentarily during switching
between on and off states. Consequently, CMOS devices do not produce as much waste heat as other
forms of logic, for example transistor-transistor logic (TTL) or NMOS logic, which normally have some
standing current even when not changing state. CMOS also allows a high density of logic functions on a
chip. It was primarily for this reason that CMOS became the most used technology to be implemented
in VLSI chips.
The phrase "metal–oxide–semiconductor" is a reference to the physical structure of certain field-effect
transistors, having a metal gate electrode placed on top of an oxide insulator, which in turn is on top of
a semiconductor material. Aluminium was once used but now the material is polysilicon. Other metal
gates have made a comeback with the advent of high-k dielectric materials in the CMOS process, as
announced by IBM and Intel for the 45 nanometer node and beyond.
"CMOS" refers to both a particular style of digital circuitry design, and the family of processes used to
implement that circuitry on integrated circuits (chips). CMOS circuitry dissipates less power than logic
families with resistive loads. Since this advantage has increased and grown more important, CMOS
processes and variants have come to dominate, thus the vast majority of modern integrated circuit
manufacturing is on CMOS processes. As of 2010, CPUs with the best performance per watt each year
have been CMOS static logic since 1976.
CMOS circuits use a combination of p-channel and n-channel metal–oxide–semiconductor field-effect
transistors (MOSFETs) to implement logic gates. Although CMOS logic can be implemented with discrete
devices for demonstrations, commercial CMOS products are integrated circuits composed of up to
millions of transistors of both types on a rectangular piece of silicon of between 10 and 400mm2.
Introduction to CMOS Logic Circuits

39 | P a g e
 • CMOS stands for Complementary Metal Oxide Semiconductor

– Complementary: there are N-type and P-type transistors. N-type transistors use
electrons as the current carriers. P-type transistors use holes as the current carriers.

• Electrons are free carriers in the conduction band with energy of Ec or just
above the conduction band edge. Free electrons are generated by doping the
silicon with an N-type impurity such as phosphorous or arsenic.

• A hole is a current carrier due to the absence of an electron in a covalent bond

state, i.e. a missing electron which would otherwise be part of a silicon-to-
silicon bond. Holes are free carriers in the valence band with energy of Ev or
just below the valence band edge. Holes are generated by doping the silicon
with a P-type impurity such as boron.

– Metal: the gate of the transistor was made of aluminum metal in the early days, but is
made of polysilicon today (for the past 25 years or more).

– Oxide: silicon dioxide is the material between the gate and the channel

– Semiconductor: the semiconductor material is silicon, a type IV element in the periodic

chart. Each silicon atom bonds to four other silicon atoms in a tetrahedral crystal
structure.

• CMOS circuits are constructed in such a way that all PMOS transistors must have either an input
from the voltage source or from another PMOS transistor. Similarly, all NMOS transistors must

40 | P a g e
 have either an input from ground or from another NMOS transistor. The composition of a PMOS
transistor creates low resistance between its source and drain contacts when a
low gate voltage is applied and high resistance when a high gate voltage is applied. On the other
hand, the composition of an NMOS transistor creates high resistance between source and drain
when a low gate voltage is applied and low resistance when a high gate voltage is applied.
CMOS accomplishes current reduction by complementing every nMOSFET with a pMOSFET and
connecting both gates and both drains together. A high voltage on the gates will cause the
nMOSFET to conduct and the pMOSFET to not conduct while a low voltage on the gates causes
the reverse. This arrangement greatly reduces power consumption and heat generation.
However, during the switching time both MOSFETs conduct briefly as the gate voltage goes from
one state to another. This induces a brief spike in power consumption and becomes a serious
issue at high frequencies.

• The image on the right shows what happens when an input is connected to both a PMOS
transistor (top of diagram) and an NMOS transistor (bottom of diagram). When the voltage of
input A is low, the NMOS transistor's channel is in a high resistance state. This limits the current
that can flow from Q to ground. The PMOS transistor's channel is in a low resistance state and
much more current can flow from the supply to the output. Because the resistance between the
supply voltage and Q is low, the voltage drop between the supply voltage and Q due to a current
drawn from Q is small. The output therefore registers a high voltage.

• On the other hand, when the voltage of input A is high, the PMOS transistor is in an OFF (high
resistance) state so it would limit the current flowing from the positive supply to the output, while
the NMOS transistor is in an ON (low resistance) state, allowing the output to drain to ground.
Because the resistance between Q and ground is low, the voltage drop due to a current drawn
into Q placing Q above ground is small. This low drop results in the output registering a low
voltage.

• In short, the outputs of the PMOS and NMOS transistors are complementary such that when the
input is low, the output is high, and when the input is high, the output is low. Because of this
behavior of input and output, the CMOS circuits' output is the inverse of the input.

• The power supplies for CMOS are called VDD and VSS, or VCC and Ground(GND) depending on
the manufacturer. VDD and VSS are carryovers from conventional MOS circuits and stand for the
drain and source supplies.These do not apply directly to CMOS since both supplies are really
source supplies. VCC and Ground are carryovers from TTL logic and that nomenclature has been
retained with the introduction of the 54C/74C line of CMOS.

41 | P a g e
MOS Transistor Switches

The gate controls the flow of current between the source and the drain. This allows us to treat the MOS
transistors as simple on/off switches.
Logic value system:
1: Between 1.5 and 15 volts
z: High Impedance (a circuit node not connecting to either Power or Ground)
0: Zero volts
Strength of the “1”and “0”signals:
•Strength of a signal is measured by its ability to sink or source current.
•Power (PWR, VDD): Strongest 1.
•Ground (GND, VSS): Strongest 0.
•By convention, current is sourced from Power, and Ground sinks current.
•NMOS switch (N-SWITCH) is closed or ON if the drain and the source are connected .
This occurs when there is a “1”on the gate .
Pass a good 0.
Pass a poor 1.
•PMOS switch (P-SWITCH) is closed or ON when there is a “0”on the gate.
Pass a good 1.
Pass a poor 0.

SERIES AND PARALLEL CONNECTION OF MOS

42 | P a g e
43 | P a g e
PULL-UP NETWORK

A B Y
0 0 1
0 1 1
1 0 1
1 1 Z

PULL-DOWN NETWORK

A B Y
0 0 Z
0 1 Z
1 0 Z
1 1 0

COMBINED CMOS NETWORK

A B Y
0 0 1
0 1 1
1 0 1
1 1 0

44 | P a g e
PULL-UP NETWORK

A B Y
0 0 1
0 1 Z
1 0 Z
1 1 Z
PULL-DOWN NETWORK

A B Y
0 0 Z
0 1 0
1 0 0
1 1 0
COMBINED CMOS NETWORK

A B Y
0 0 1
0 1 0
1 0 0
1 1 0

45 | P a g e
PULL-UP NETWORK

A B Y
0 0 Z
0 1 1
1 0 1
1 1 Z
PULL-DOWN NETWORK

A B Y
0 0 0
0 1 Z
1 0 Z
1 1 0
COMBINED CMOS NETWORK

A B Y
0 0 0
0 1 1
1 0 1
1 1 0

46 | P a g e
A Systematic Method(I) Start from Pull-Up Network

 Each variable in the given Boolean eqn corresponds to a Pmos transistor in PUN and an NMOS
transistor in PDN.
 Draw PUN using PMOS based on the Boolean eqn.
 AND operation draw in Parallel .
 OR operation draw in Series.
 Invert each variable of the Boolean eqn as the gate input for each PMOS in the PUN.
 Draw PDN using NMOS in complementary form.
 Parallel(PUN) to Series(PDN).
 Series(PUN) to Parallel(PDN).
 Label with the same inputs of PUN.
 Label the output.

A Systematic Method(II) Start from Pull-Up Network

 Each variable in the given Boolean eqn corresponds to a Pmos transistor in PUN and an NMOS
transistor in PDN.
 Invert the Boolean eqn.
 With the Right hand Side of the newly inverted equation, Draw PDN using Nmos.
 AND operation draw in series.
 OR operation drawn in parallel.
 Label each variable of the Boolean equation as the gate input of each NMOS in the PDN.
 Draw PUN using PMOS in complementary form.
 Parallel (PUN) to series (PDN).
 Series (PUN) to parallel (PDN).
 Label with the same inputs of PUN.
 Label the output.
Systematic Approaches

 Note that the both methods lead to exactly the same implementation of a CMOS network.
 The reason to invert output equation in (ii) is because
- Output (F) is conducting to “ground”,i.e. 0,when there is a path formed by input NMOS
transistors.
- Inversion will force the desired result from the equation.
 EXAMPLE
-F=A.C+B:When (A=0 and C=1) or B=1,F=1.However,in the PDN(NMOS) of a CMOS
network=0,i.e. an inverse result.
-Revisit how a NAND CMOS network is implemented
 Inverting each PMOS input in (1) follow the same reasoning.

47 | P a g e
Hardware Description
Language

48 | P a g e
 HARDWARE DESCRIPTION LANGUAGE
In electronics, a hardware description language or HDL is a specialized computer
language used to describe the structure, design and operation of electronic
circuits, and most commonly, digital logiccircuits.A hardware description language
enables a precise, formal description of an electronic circuit that allows for the
automated analysis, simulation, and simulated testing of an electronic circuit. It
also allows for the compilation of an HDL program into a lower level specification
of physical electronic components, such as the set of masks used to create
an integrated circuit.
A hardware description language looks much like a programming language such
as C; it is a textual description consisting of expressions, statements and control
structures. One important difference between most programming languages and
HDLs is that HDLs explicitly include the notion of time.HDLs form an integral part
of Electronic design automation systems, especially for complex circuits, such
as microprocessors.
Due to the exploding complexity of digital electronic circuits since the 1970s
circuit designers needed digital logic descriptions to be performed at a high level
without specifics to a particular electronic technology, i.e. CMOS, BJT etc. Hence a
process flow stemming from data flow model with timing information, called the
register-transfer level (RTL) was chosen and implemented via HDL.
HDLs are standard text-based expressions of the spatial and temporal structure
and behaviour of electronic systems. Like concurrent programming languages,
HDL syntax and semantics include explicit notations for expressing concurrency.
However, in contrast to most software programming languages, HDLs also include
an explicit notion of time, which is a primary attribute of hardware. Languages
whose only characteristic is to express circuit connectivity between a hierarchy of
blocks are properly classified as netlist languages used in electric computer-aided
design (CAD). HDL can be used to express designs
in structural, behavioral or register-transfer-level architectures for the same
circuit functionality; in the latter two cases the synthesizer decides the
architecture and logic gate layout.HDLs are used to write executable
specifications for hardware. A program designed to implement the underlying
semantics of the language statements and simulate the progress of time provides
the hardware designer with the ability to model a piece of hardware before it is
created physically. It is this executability that gives HDLs the illusion of
being programming languages, when they are more precisely classified
49 | P a g e
as specification languages or modeling languages. Simulators capable of
supporting discrete-event (digital) and continuous-time (analog) modeling exist,
and HDLs targeted for each are available.
It is certainly possible to represent hardware semantics using traditional
programming languages, which operate on control flow semantics as opposed
to data flow, such as C++, although to function as such, programs must be
augmented with extensive and unwieldy class libraries. Primarily, however,
software programming languages do not include any capability for explicitly
expressing time, and this is why they cannot function as hardware description
languages. Before the recent introduction of SystemVerilog, C++ integration with
a logic simulator was one of the few ways to use OOP in hardware verification.
SystemVerilog is the first major HDL to offer object orientation and garbage
collection.
Using the proper subset of hardware description language, a program called a
synthesizer (or synthesis tool) can infer hardware logic operations from the
language statements and produce an equivalent netlist of generic hardware
primitives to implement the specified behavior. Synthesizers generally ignorethe
expression of any timing constructs in the text. Digital logic synthesizers, for
example, generally use clock edges as the way to time the circuit, ignoring any
timing constructs. The ability to have a synthesizable subset of the language does
not itself make a hardware description language.

History of HDLs
The first hardware description languages appeared in the late 1960s looking like
more traditional languages. The first that had a lasting effect was described in
1971 in C. Gordon Bell and Allen Newell's textComputer Structures. It was this text
where the concept of RTL was introduced in the ISP language to describe the
behavior of the DEC PDP-8.The language became more wide spread with the
introduction of Digital Equipment Corporation (DEC) PDP-16 RT-Level Modules
and a book describing their use. At least two implementations of the basic ISP
language (ISPL and ISPS) followed. ISPS was well suited to describe relations
between the inputs and the outputs of the design and quickly became adopted by
commercial teams at DEC, as well as a number of research teams both in the USA
and in NATO allies. However, the ability to synthesize logic turned out to be
limited, as the simulator output assumed that the design would be reduced to
practice using those same DEC RTM style PDP-16 modules. The RTM's product

50 | P a g e
never really took off commercially and DEC stopped marketing them in the mid-
1980s, as new techniques and in particular VLSI became more popular.
Separate work circa 1979 at University of Kaiserslautern produced a language
called KARL, which included design calculus language features supporting VLSI
chip floorplanning and structured hardware design. The same work was also the
basis of KARL's interactive graphic sister language ABL, implemented in the early
1980s as the ABLED graphic VLSI design editor, by the telecommunication
research center CSELT at Torino, Italy. In the mid 1980s, a VLSI design framework
was implemented around KARL and ABL by an international consortium funded by
the commission of the European Union (chapter in).By the late 1970s, design
using programmable logic device (PLD)'s became popular, although these designs
were primarily limited to design finite state machines. The work at Data
General in 1980 used these same devices to design a then modern system,
the Data General Eclipse MV/8000, and commercial need began to grow for a
language that could map to well to them. By 1983 Data-I/O introduced ABEL, to
fill that need.
As design shifted to VLSI, the first modern HDL, Verilog, was introduced
by Gateway Design Automation in 1985. Cadence Design Systems later acquired
the rights to Verilog-XL, the HDL-simulator that would become the de facto
standard (of Verilog simulators) for the next decade. In 1987, a request from the
U.S. Department of Defense led to the development of VHDL (VHSIC Hardware
Description Language, where VHSIC is Very High Speed Integrated Circuit). VHDL
was based on the Ada programming language, as well as the experiences that had
been learned with the development of ISPS earlier.Initially, Verilog and VHDL
were used to document and simulate circuit designs already captured and
described in another form (such as schematic files). HDL simulation enabled
engineers to work at a higher level of abstraction than simulation at the
schematic level, and thus increased design capacity from hundreds of transistors
to thousands.The introduction of logic synthesis for HDLs pushed HDLs from the
background into the foreground of digital design. Synthesis tools compiled HDL
source files (written in a constrained format called RTL into a manufacturable
gate/transistor-level netlist description. Writing synthesizable RTL files required
practice and discipline on the part of the designer; compared to a traditional
schematic layout, synthesized RTL netlists were almost always larger in area and
slower in performance[citation needed]. A circuit design from a skilled engineer, using
labor-intensive schematic-capture/hand-layout, would almost always outperform
its logically-synthesized equivalent, but the productivity advantage held by
51 | P a g e
synthesis soon displaced digital schematic capture to exactly those areas that
were problematic for RTL synthesis: extremely high-speed, low-power, or
asynchronous circuitry. In short, logic synthesis propelled HDL technology into a
central role for digital design.Within a few years, both VHDL and Verilog emerged
as the dominant HDLs in the electronics industry, while older and less capable
HDLs gradually disappeared from use. However, VHDL and Verilog share many of
the same limitations: neither HDL is suitable for analog/mixed-signal
circuit simulation. Neither possesses language constructs to describe recursively-
generated logic structures. Specialized HDLs (such as Confluence) were
introduced with the explicit goal of fixing specific Verilog/VHDL limitations,
though none were ever intended to replace VHDL/Verilog.
Over the years, much effort has been invested in improving HDLs. The latest
iteration of Verilog, formally known as IEEE 1800-2005 SystemVerilog, introduces
many new features (classes, random variables, and properties/assertions) to
address the growing need for better testbench randomization, design hierarchy,
and reuse. A future revision of VHDL is also in development, and is expected to
match SystemVerilog's improvements.

Design using HDL

As a result of the efficiency gains realized using HDL, a majority of modern digital
circuit design revolves around it. Most designs begin as a set of requirements or a
high-level architectural diagram. Control and decision structures are often
prototyped in flowchart applications, or entered in a state-diagram editor. The
process of writing the HDL description is highly dependent on the nature of the
circuit and the designer's preference for coding style . The HDL is merely the
'capture language,' often beginning with a high-level algorithmic description such
as a C++ mathematical model. Designers often use scripting languages (such
as Perl) to automatically generate repetitive circuit structures in the HDL
language. Special text editors offer features for automatic indentation, syntax-
dependent coloration, and macro-based expansion of entity/architecture/signal
declaration.
The HDL code then undergoes a code review, or auditing. In preparation for
synthesis, the HDL description is subject to an array of automated checkers. The
checkers report deviations from standardized code guidelines, identify potential
ambiguous code constructs before they can cause misinterpretation, and checkfor

52 | P a g e
common logical coding errors, such as dangling ports or shorted outputs. This
process aids in resolving errors before the code is synthesized.
In industry parlance, HDL design generally ends at the synthesis stage. Once the
synthesis tool has mapped the HDL description into a gate netlist, this netlist is
passed off to the back-end stage. Depending on the physical technology
(FPGA, ASIC gate array, ASIC standard cell), HDLs may or may not play a significant
role in the back-end flow. In general, as the design flow progresses toward a
physically realizable form, the design database becomes progressively more laden
with technology-specific information, which cannot be stored in a generic HDL
description. Finally, an integrated circuit is manufactured or programmed for use.

Simulating and debugging HDL code

Essential to HDL design is the ability to simulate HDL programs. Simulation allows
an HDL description of a design (called a model) to pass design verification, an
important milestone that validates the design's intended function (specification)
against the code implementation in the HDL description. It also permits
architectural exploration. The engineer can experiment with design choices by
writing multiple variations of a base design, then comparing their behavior in
simulation. Thus, simulation is critical for successful HDL design.
To simulate an HDL model, an engineer writes a top-level simulation environment
(called a testbench). At minimum, a testbench contains an instantiation of the
model (called the device under test or DUT), pin/signal declarations for the
model's I/O, and a clock waveform. The testbench code is event driven: the
engineer writes HDL statements to implement the (testbench-generated) reset-
signal, to model interface transactions (such as a host–bus read/write), and to
monitor the DUT's output. An HDL simulator — the program that executes the
testbench — maintains the simulator clock, which is the master reference for all
events in the testbench simulation. Events occur only at the instants dictated by
the testbench HDL (such as a reset-toggle coded into the testbench), or in
reaction (by the model) to stimulus and triggering events. Modern HDL simulators
have full-featured graphical user interfaces, complete with a suite of debug tools.
These allow the user to stop and restart the simulation at any time, insert
simulator breakpoints (independent of the HDL code), and monitor or modify any
element in the HDL model hierarchy. Modern simulators can also link the HDL
environment to user-compiled libraries, through a defined PLI/VHPI interface.

53 | P a g e
Linking is system-dependent (Win32/Linux/SPARC), as the HDL simulator and user
libraries are compiled and linked outside the HDL environment.
Design verification is often the most time-consuming portion of the design
process, due to the disconnect between a device's functional specification, the
designer's interpretation of the specification, and the imprecisionof the HDL
language. The majority of the initial test/debug cycle is conducted in the
HDL simulator environment, as the early stage of the design is subject to frequent
and major circuit changes. An HDL description can also be prototyped and tested
in hardware — programmable logic devices are often used for this purpose.
Hardware prototyping is comparatively more expensive than HDL simulation, but
offers a real-world view of the design. Prototyping is the best way to check
interfacing against other hardware devices and hardware prototypes. Even those
running on slow FPGAs offer much shorter simulation times than pure HDL
simulation.

HDL and programming languages

An HDL is analogous to a software programming language, but with major
differences. Many programming languages are inherently procedural (single-
threaded), with limited syntactical and semantic support to handle concurrency.
HDLs, on the other hand, resemble concurrent programming languages in their
ability to model multiple parallel processes (such as flipflops, adders, etc.) that
automatically execute independently of one another. Any change to the process's
input automatically triggers an update in the simulator's process stack. Both
programming languages and HDLs are processed by a compiler (usually called a
synthesizer in the HDL case), but with different goals. For HDLs, 'compiler' refers
to synthesis, a process of transforming the HDL code listing into a physically
realizable gate netlist. The netlist output can take any of many forms: a
"simulation" netlist with gate-delay information, a "handoff" netlist for post-
synthesis place and route, or a generic industry-standard EDIF format (for
subsequent conversion to a JEDEC-format file).
On the other hand, a software compiler converts the source-code listing into
a microprocessor-specific object-code, for execution on the target
microprocessor. As HDLs and programming languages borrow concepts and
features from each other, the boundary between them is becoming less distinct.
However, pure HDLs are unsuitable for general purpose software application
development, just as general-purpose programming languages are undesirable for

54 | P a g e
modeling hardware. Yet as electronic systems grow increasingly complex,
and reconfigurable systems become increasingly mainstream, there is growing
desire in the industry for a single language that can perform some tasks of both
hardware design and software programming. SystemC is an example of such—
embedded system hardware can be modeled as non-detailed architectural blocks
(blackboxes with modeled signal inputs and output drivers). The target
application is written in C or C++ and natively compiled for the host-development
system (as opposed to targeting the embedded CPU, which requires host-
simulation of the embedded CPU). The high level of abstraction of SystemC
models is well suited to early architecture exploration, as architectural
modifications can be easily evaluated with little concern for signal-level
implementation issues. However, the threading model used in SystemC and its
reliance on shared memory mean that it does not handle parallel execution or
lower level models well.
The two most widely-used and well-supported HDL varieties used in industry
are Verilog and VHDL.

Other include

Name Description

ABEL Advanced Boolean Expression Language

Advanced Boolean Expression Language a

AHDL
proprietary language from Altera

AHPL A Hardware Programing language

high-level HDL based on Haskell (not

Bluespec
embedded DSL)[12]

BluespecSystemVerilog (BSV) based on Bluespec, with Verilog HDL like syntax,

55 | P a g e
 Name Description

by Bluespec, Inc.

C-to-Verilog Converter from C to Verilog

Chisel (Constructing Hardware in a

based on Scala (embedded DSL)
Scala Embedded Language)

Confluence a functional HDL; has been discontinued

a C-based HDL by CoWare. Now discontinued in

CoWareC
favor of SystemC

CUPL (Universal Compiler for a proprietary language from Logical Devices,

Programmable Logic[13]} Inc.

ELLA no longer in common use

ESys.net .net framework written in C#

Handel-C a C-like design language

HHDL based on Haskell (embedded DSL).

Hardware Join Java (HJJ) based on Join Java

HML based on SML

56 | P a g e
 Name Description

Hydra based on Haskell

Impulse C another C-like HDL

Original HDL from CMU, no longer in common

ISPS
use

C++ extended with HDL style threading and

ParC (Parallel C++)
communication for task-parallel programming

JHDL based on Java

Lava based on Haskell (embedded DSL).[14][15][16][17]

Lola a simple language used for teaching

M A HDL from Mentor Graphics

MyHDL based on Python (embedded DSL)

PALASM for Programmable Array Logic (PAL) devices

ROCCC (Riverside Optimizing

Compiler for Configurable Free and open-source C to HDL tool
Computing)

57 | P a g e
 Name Description

RHDL based on the Ruby programming language

Ruby (hardware description

language)

a standardized class of C++ libraries for high-

level behavioral and transaction modeling
SystemC
of digital hardware at a high level of
abstraction, i.e. system-level

a superset of Verilog, with enhancements to

SystemVerilog
address system-level design and verification

SystemTCL SDL based on Tcl.

THDL++ (Templated HDL inspired An extension of VHDL with inheritance,

by C++) advanced templates and policy classes

One of the most widely-used and well-

Verilog
supported HDLs

One of the most widely-used and well-

VHDL (VHSIC HDL)
supported HDLs

58 | P a g e
 VHDL
VHDL (VHSIC hardware description language) is a hardware description
language used in electronic design automation to
describe digital and mixed-signalsystems such as field-programmable gate
arrays and integrated circuits. VHDL can also be used as a general
purpose parallel programming language.

History
VHDL was originally developed at the behest of the U.S Department of Defense in
order to document the behavior of the ASICs that supplier companies were
including in equipment. That is to say, VHDL was developed as an alternative to
huge, complex manuals which were subject to implementation-specific
details.The idea of being able to simulate this documentation was so obviously
attractive that logic simulators were developed that could read the VHDL files.
The next step was the development of logic synthesistools that read the VHDL,
and output a definition of the physical implementation of the circuit.Due to the
Department of Defense requiring as much of the syntax as possible to be based
on Ada, in order to avoid re-inventing concepts that had already been thoroughly
tested in the development of Ada, VHDL borrows heavily from the Ada
programming language in both concepts and syntax.The initial version of VHDL,
designed to IEEE standard 1076-1987, included a wide range of data types,
including numerical (integer and real), logical
(bit and boolean), character and time, plus arrays of bitcalled bit_vector and
of character called string.
A problem not solved by this edition, however, was "multi-valued logic", where a
signal's drive strength (none, weak or strong) and unknown values are also
considered. This required IEEE standard 1164, which defined the 9-value logic
types: scalar std_logic and its vector version std_logic_vector.The updated IEEE
1076, in 1993, made the syntax more consistent, allowed more flexibility in
naming, extended the character type to allow ISO-8859-1 printable characters,
added the xnor operator, etc.[specify]Minor changes in the standard (2000 and
2002) added the idea of protected types (similar to the concept of class in C++)
and removed some restrictions from port mapping rules.
In addition to IEEE standard 1164, several child standards were introduced to
extend functionality of the language. IEEE standard 1076.2 added better handling

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of real and complex data types. IEEE standard 1076.3 introduced signed and
unsigned types to facilitate arithmetical operations on vectors. IEEE standard
1076.1 (known as VHDL-AMS) provided analog and mixed-signal circuit design
extensions.Some other standards support wider use of VHDL, notably VITAL
(VHDL Initiative Towards ASIC Libraries) and microwave circuit design extensions.
In June 2006, the VHDL Technical Committee of Accellera (delegated by IEEE to
work on the next update of the standard) approved so called Draft 3.0 of VHDL-
2006. While maintaining full compatibility with older versions, this proposed
standard provides numerous extensions that make writing and managing VHDL
code easier. Key changes include incorporation of child standards (1164, 1076.2,
1076.3) into the main 1076 standard, an extended set of operators, more flexible
syntax of case and generate statements, incorporation of VHPI (interface to C/C++
languages) and a subset of PSL (Property Specification Language). These changes
should improve quality of synthesizable VHDL code, make testbenches more
flexible, and allow wider use of VHDL for system-level descriptions.
In February 2008, Accellera approved VHDL 4.0 also informally known as VHDL
2008, which addressed more than 90 issues discovered during the trial period for
version 3.0 and includes enhanced generic types. In 2008, Accellera released
VHDL 4.0 to the IEEE for balloting for inclusion in IEEE 1076-2008. The VHDL
standard IEEE 1076-2008 was published in January 2009.

Design
VHDL is commonly used to write text models that describe a logic circuit. Such a
model is processed by a synthesis program, only if it is part of the logic design. A
simulation program is used to test the logic design using simulation models to
represent the logic circuits that interface to the design. This collection of
simulation models is commonly called a testbench.
VHDL has constructs to handle the parallelism inherent in hardware designs, but
these constructs (processes) differ in syntax from the parallel constructs in Ada
(tasks). Like Ada, VHDL is strongly typed and is not case sensitive. In order to
directly represent operations which are common in hardware, there are many
features of VHDL which are not found in Ada, such as an extended set of Boolean
operators including nand and nor. VHDL also allows arrays to be indexed in either
ascending or descending direction; both conventions are used in hardware,
whereas in Ada and most programming languages only ascending indexing is
available.
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VHDL has file input and output capabilities, and can be used as a general-purpose
language for text processing, but files are more commonly used by a simulation
testbench for stimulus or verification data. There are some VHDL compilers which
build executable binaries. In this case, it might be possible to use VHDL to write
a testbench to verify the functionality of the design using files on the host
computer to define stimuli, to interact with the user, and to compare results with
those expected. However, most designers leave this job to the simulator.
It is relatively easy for an inexperienced developer to produce code that simulates
successfully but that cannot be synthesized into a real device, or is too large to be
practical. One particular pitfall is the accidental production of transparent
latches rather than D-type flip-flops as storage elements.[1]
One can design hardware in a VHDL IDE (for FPGA implementation such as Xilinx
ISE, Altera Quartus, Synopsys Synplify or Mentor Graphics HDL Designer) to
produce the RTL schematic of the desired circuit. After that, the generated
schematic can be verified using simulation software which shows the waveforms
of inputs and outputs of the circuit after generating the appropriate testbench. To
generate an appropriate testbench for a particular circuit or VHDL code, the
inputs have to be defined correctly. For example, for clock input, a loop process or
an iterative statement is required.[2]
A final point is that when a VHDL model is translated into the "gates and wires"
that are mapped onto a programmable logic device such as a CPLD or FPGA, then
it is the actual hardware being configured, rather than the VHDL code being
"executed" as if on some form of a processor chip.

Advantage

The key advantage of VHDL, when used for systems design, is that it allows the
behavior of the required system to be described (modeled) and verified
(simulated) before synthesis tools translate the design into real hardware (gates
and wires).
Another benefit is that VHDL allows the description of a concurrent system. VHDL
is a dataflow language, unlike procedural computing languages such as BASIC, C,
and assembly code, which all run sequentially, one instruction at a time.
A VHDL project is multipurpose. Being created once, a calculation block can be
used in many other projects. However, many formational and functional block

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parameters can be tuned (capacity parameters, memory size, element base, block
composition and interconnection structure).
A VHDL project is portable. Being created for one element base, a computing
device project can be ported on another element base, for example VLSI with
various technologies.
VHDL coding can be represented mainly in 3 different ways-
 Dataflow model
 Behavioral model
 Structural model

Identifiers
VHDL identifier syntax:

 A sequence of one or more upper case letters,lower case letters,digits, and

the underscore.
 Upper and lower case letter are treated as same.
 The first character must be a letter.
 Two underscores can not be together.

Data objects
There are three kinds of data objects:signals,variable and constants.

 The data object SIGNAL represents logic signals on a wire in the circuit.A
signal does not have memory.
 A VARIABLE object remembers its content and is used for computations in a
behavioral model.
 A CONSTANT object must be initialized wiyh a value when declared and this
value can not be changed.

Example:

SIGNAL x:BIT;

VARIABLE y;INTEGER;
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 CONSTANT one:STD_LOGIC_VECTOR(3 DOWNTO 0):=”0001”

Data type
BIT and BIT_VECTOR

The BIT and BIT_VECTOR types are predefined in vhdl.Objects of these types can
have the values ‘0’ and ‘1’.

The BIT_VECTOR type is simply a vector of type BIT.A vector with all bits having
the same value can be obtained.

Using the OTHERS keyword

Example:

SIGNAL x:BIT;

SIGNAL y:BIT_VECTOR(7 down to 0);

X<=’1’;

X<=”00000010”;

Y<=(Others=>’0’);--same as “00000000”

STD_LOGIC and STD_LOGIC_VECTOR

The STD_LOGIC and STD_LOGIC_VECTOR types provide more values than the BIT
type for modeling a real circuit more accurately.Objects of these types can have
the following values.

‘0 ’- normal 0

‘1’ - normal 1

‘z’ - high impedence

‘-‘ - don’t care

‘L’ – weak 0

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‘H’ – weak 1

‘U’ – uninitialize

‘X’ - unknown

‘W’ – weak unknown

The STD_LOGIC and STD_LOGIC_VECTOR types are not predefined,and so the

following two library statements must be included in order to use these types.

LIBRARY IEEE:
USE IEEE.STD_LOGIC_1164.ALL;

If objects of type STD_LOGIC_VECTOR are to be used as binary numbers in

arithmetic manipulations,then either one of the following two USE statements
must also be included

USE IEEE.STD_LOGIC_SIGNED.ALL;

For signed number arithmetic,or

USE IEEE.STD_LOGIC_UNSIGNED.ALL:

For unsigned number arithmetic.A vector with all bits having the same value can
be obtained using the OTHERS.

Keyword,as shown in the next example.

Example:

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL:

SIGNAL x:STD_LOGIC;

SIGNAL y:STD_LOGIC_VECTOR(7 DOWN TO 0);

X<=’Z’;

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Y<=”0000001Z”;

Y<=(OTHERS=>’0’);--same as ”00000000”

INTEGER

The predefined INTEGER type defines binary number objects for use with
arithmetic operators.Bydefault,an

INTEGER signal uses 32 bits to represent a signed number.Integers using fewer

bits can also be declared with the

RANGE keyword.

Example:

SIGNAL x:INTEGER;

SIGNAL y:INTEGER RANGE 64 to 64;

BOOLEAN

The predefined BOOLEAN type defines objects having the two values TRUE and
FALSE.

Example:

SIGNAL x:BOOLEAN;

Enumeration TYPE

An enumeration allows the user to specify the values that the data object can
have.

Syntax:

TYPE identifier IS(value1,value2,…);

Example:

TYPE state_typeIS(S1,S2,S3);

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SIGNAL state:state_type;

State<=S1;

ARRAY

The ARRAY type groups single data objects of the same type together into a one-
dimenssional or

Multidimensional array.

Syntax:

TYPE identifier IS ARRAY(range) OF type;

Example:

TYPE byte is ARRAY(7 DOWN TO 0)OF BIT;

TYPE memory_type IS ARRAY(1 TO 128)OF byte;

SIGNAL MEMORY:memory_type;

Memory(3)<=”00101101”;

SUBTYPE

A SUBTYPE is a subset of a type,that is ,a type with a rangt constraint.

Syntax:

SUBTYPE identifier IS type RANGE range;

Example:

SUBTYPE integer4 IS INTEGER RANGE 8 TO & SUBTYPE cell IS

STD_LOGIC_VECTOR(3 DOWNTO 0);

TYPE mem Array IS ARRAY( 0 TO 15) OF cell;

Some standard subtype include:

66 | P a g e
  NATURAL an integer in the range 0 to INTEGER’HIGH
 POSITIVE an integer in the range 1 to INTEGER’HIGH

Data operators

The VHDL built-in operators are listed below:-

LOGICAL OPERATOR

Logical operator Operation Example

AND AND n<=A AND B
OR OR n<=A OR B
NOT NOT n<=NOT A
NAND NAND n<=A NAND B
NOR NOR n<=A NOR B
XOR XOR n<=A XOR B
XNOR XNOR n<=A XNOR B

ARITHMATIC OPAERATOES

Arithmatic Operation Operation Example

+ Addition n<=A+B
- Subtraction n<=A-B
* Multiplication(integer or n<=A*B
floating point)
⁄ Division(integer or n<=A/B
floating point)
MOD 4 Modulus(integer) n<=A MOD B
REM Remainder(integer) n<=A REM B
** Exponentiation n<=A ** B
& Concatenation n<=’a’&’b’
ABS Absolute

RELATIONAL OPERATORS

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Relational Operation Example
Operators
= Equal IF(n=10)THEN
/= Not Equal IF(n/=10)THEN
< Lessthan IF(n<10)THEN
<= Less then or equal IF(n<=10)THEN
> Greater than IF(n>10)THEN
>= Greater than or equal IF(n>=10)THEN

SHIFT OPERATORS

Shift Operators operation Example

SLL Shift left logical N<=”1001010” SLL 2
SRL Shift right logical N<=”1001010” SRL 1
SLA Shift left arithmetic N<=”1001010” SLA 2
SRA Shift right arithmetic N<=”1001010” SRA 1
ROL Rotate left N<=”1001010” ROL 2
ROR Rotate right N<=”1001010” ROR 2

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84 | P a g e
VERILOG
HDL

85 | P a g e
 VERILOG HDL
Verilog is a hardware description language (HDL) used to model electronic
systems. The language (sometimes called Verilog HDL) supports the design,
verification, and implementation of analog, digital, and mixed-signal circuits at
various levels of abstraction.
The designers of Verilog wanted a language with syntax similar to the C
programming language so that it would be familiar to engineers and readily
accepted. The language is case-sensitive, has a preprocessor like C, and the major
control flowkeywords, such as "if" and "while", are similar. The formatting
mechanism in the printing routines and language operators and their precedence
are also similar.
The language differs in some fundamental ways. Verilog uses Begin/End instead
of curly braces to define a block of code. The definition of constants in verilog
require a bit width along with their base, consequently these differ. Verilog 95
and 2001 don't have structures, pointers, or recursive subroutines, however
SystemVerilog now includes these capabilities. Finally, the concept of time —so
important to a HDL— won't be found in C.
The language differs from a conventional programming language in that the
execution of statements is not strictly linear. A Verilog design consists of a
hierarchy of modules. Modules are defined with a set of input, output, and
bidirectional ports. Internally, a module contains a list of wires and registers.
Concurrent and sequential statements define the behaviour of the module by
defining the relationships between the ports, wires, and registers. Sequential
statements are placed inside a begin/end block and executed in sequential order
within the block. But all concurrent statements and all begin/end blocks in the
design are executed in parallel. A module can also contain one or more instances
of another module to define sub-behavior.
A subset of statements in the language is synthesizable. If the modules in a design
contain only synthesizable statements, software can be used to transform or

86 | P a g e
synthesize the design into a netlist that describes the basic components and
connections to be implemented in hardware. The netlist may then be
transformed into, for example, a form describing the standard cells of an
integrated circuit (e.g. an ASICor a bitstream for a programmable logic device (e.g.
a FPGA).

History
Beginning
Verilog was invented by Phil Moorby at Automated Integrated Design Systems
(later renamed to Gateway Design Automation) in 1985 as a hardware modeling
language. Gateway Design Automation was later purchased by Cadence Design
Systems in 1990. Cadence now has full proprietary rights to Gateway's Verilog and
the Verilog-XL simulator logic simulators.
Verilog-95
With the increasing success of VHDL at the time, Cadence decided to make the
language available for open standardization. Cadence transferred Verilog into the
public domain under the Open Verilog International (OVI) (now known as
Accellera) organization. Verilog was later submitted to IEEE and became IEEE
Standard 1364-1995, commonly referred to as Verilog-95.

Verilog 2001
Extensions to Verilog-95 were submitted back to IEEE to cover the deficiencies
that users had found in the original Verilog standard. These extensions became
IEEE Standard 1364-2001 known as Verilog 2001
Verilog 2005
Verilog 2005, IEEE Standard 1364-2005, focus mostly on minor corrections, as any
language improvement was done as a separate project, known as SystemVerilog.

87 | P a g e
The latest versions of the language include support for analog and mixed signal
modelling. These are referred to as Verilog-AMS

 Design Styles

Verilog, like any other hardware description language, permits a design in either
Bottom-up or Top-down methodology

Bottom-Up Design

The traditional method of electronic design is bottom-up. Each design is performed

at the gate-level using the standard gates (refer to the Digital Section for more
details). With the increasing complexity of new designs this approach is nearly
impossible to maintain. New systems consist of ASIC or microprocessors with a
complexity of thousands of transistors. These traditional bottom-up designs have to
give way to new structural, hierarchical design methods. Without these new
practices it would be impossible to handle the new complexity.

Top-Down Design

The desired design-style of all designers is the top-down one. A real top-down
design allows early testing, easy change of different technologies, a structured
system design and offers many other advantages. But it is very difficult to follow a
pure top-down design. Due to this fact most designs are a mix of both methods,
implementing some key elements of both design styles.

 Verilog Abstraction Levels

Verilog supports designing at many different levels of abstraction. Three of them

are very important:

 Behavioral level
 Register-Transfer Level
 Gate Level

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Behavioral level

This level describes a system by concurrent algorithms (Behavioral). Each

algorithm itself is sequential, that means it consists of a set of instructions that are
executed one after the other. Functions, Tasks and Always blocks are the main
elements. There is no regard to the structural realization of the design.

Register-Transfer Level

Designs using the Register-Transfer Level specify the characteristics of a circuit by

operations and the transfer of data between the registers. An explicit clock is
used. RTL design contains exact timing bounds: operations are scheduled to occur
at certain times. Modern RTL code definition is "Any code that is synthesizable is
called RTL code"

Gate Level

Within the logic level the characteristics of a system are described by logical links
and their timing properties. All signals are discrete signals. They can only have
definite logical values (`0', `1', `X', `Z`). The usable operations are predefined logic
primitives (AND, OR, NOT etc gates). Using gate level modeling might not be a
good idea for any level of logic design. Gate level code is generated by tools like
synthesis tools and this netlist is used for gate level simulation and for backend.

Let us consider an example:-

1 // D flip-flop Code
2 module d_ff( d, clk, q, q_bar);
3 input d ,clk;

89 | P a g e
 4 output q, q_bar;
5 wire d ,clk;
6 reg q, q_bar;
7
8 always @ (posedgeclk)
9 begin
10 q <= d;
11 q_bar<= !d;
12 end
13
14 endmodule

Modules

We'll need to backtrack a bit to do this. If you look at the arbiter block in the first
picture, we can see that it has got a name ("arbiter") and input/output ports (req_0,
req_1, gnt_0, and gnt_1).

Since Verilog is a HDL (hardware description language - one used for the
conceptual design of integrated circuits), it also needs to have these things. In
Verilog, we call our "black boxes" module. This is a reserved word within the
program used to refer to things with inputs, outputs, and internal logic workings;
they're the rough equivalents of functions with returns in other programming
languages.

Ports:-

Here we have only two types of ports, input and output. In real life, we can have
bi-directional ports as well. Verilog allows us to define bi-directional ports as
"inout."

Bi-Directional Ports Example -

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inoutread_enable; // port named read_enable is bi-directional

Vector Signals Example –

inout [7:0] address; //port "address" is bidirectional.

Note the [7:0] means we're using the little-endian convention - you start with 0 at
the rightmost bit to begin the vector, then move to the left. If we had done [0:7],
we would be using the big-endian convention and moving from left to right.
Endianness is a purely arbitrary way of deciding which way your data will "read,"
but does differ between systems, so using the right endianness consistently is
important. As an analogy, think of some languages (English) that are written left-
to-right (big-endian) versus others (Arabic) written right-to-left (little-endian).
Knowing which way the language flows is crucial to being able to read it, but the
direction of flow itself was arbitrarily set years back.

Data Type:-

What do data types have to do with hardware? Nothing, actually. People just
wanted to write one more language that had data types in it. It's completely
gratuitous; there's no point

But wait... hardware does have two kinds of drivers.

(Drivers? What are those?)

A driver is a data type which can drive a load. Basically, in a physical circuit, a
driver would be anything that electrons can move through/into.

 Driver that can store a value (example: flip-flop).

 Driver that can not store value, but connects two points (example: wire).

The first type of driver is called a reg in Verilog (short for "register"). The second
data type is called a wire (for... well, "wire").

Examples :

wireand_gate_output; // "and_gate_output" is a wire that only outputs

regd_flip_flop_output; // "d_flip_flop_output" is a register; it stores and outputs a

value

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reg [7:0] address_bus; // "address_bus" is a little-endian 8-bit register

Operators

Operators, thankfully, are the same things here as they are in other programming
languages. They take two values and compare (or otherwise operate on) them to
yield a third result - common examples are addition, equals, logical-and... To
make life easier for us, nearly all operators (at least the ones in the list below) are
exactly the same as their counterparts in the C programming language.

OPERATOR TYPE OPERATOR OPERATION PERFORMED

SYMBOL
ARITHMATIC * Multiply

/ Division

+ Add

- Subtract

% Modulus

LOGICAL ! Logical Negation

&& Logical AND

|| Logical OR

RELATIONAL > Greater than

< Less than

>= Greater than or equal

<= Less than or equal

EQUALITY = Equality

!= Inequality

REDUCTION ~ Bitwise negation

~& NAND

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 | OR

~| NOR

^ XOR

^~ XNOR

~^ XNOR

SHIFT >> Right shift

<< Left shift

CONCATENATION {} Concatenation

CONDITIONAL ? Conditional

CONTROL STATEMENTS

Wait, what's this? if, else, repeat, while, for, case - it's Verilog that looks exactly
like C (and probably whatever other language you're used to program in)! Even
though the functionality appears to be the same as in C, Verilog is an HDL, so the
descriptions should translate to hardware. This means you've got to be careful
when using control statements (otherwise your designs might not be
implementable in hardware).

If-else

If-else statements check a condition to decide whether or not to execute a

portion of code. If a condition is satisfied, the code is executed. Else, it runs this
other portion of code.

1 // begin and end act like curly braces in C/C++.

2 if (enable == 1'b1) begin

3 data = 10; // Decimal assigned

4 address = 16'hDEAD; // Hexadecimal

5 wr_enable = 1'b1; // Binary

6 end else begin

7 data = 32'b0;

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 8 wr_enable = 1'b0;

9 address = address +1;

10 end

Case

Case statements are used where we have one variable which needs to be checked
for multiple values. like an address decoder, where the input is an address and it
needs to be checked for all the values that it can take. Instead of using multiple
nested if-else statements, one for each value we're looking for, we use a single case
statement: this is similar to switch statements in languages like C++.

Case statements begin with the reserved word case and end with the reserved word
endcase (Verilog does not use brackets to delimit blocks of code). The cases,
followed with a colon and the statements you wish executed, are listed within these
two delimiters. It's also a good idea to have a default case. Just like with a finite
state machine (FSM), if the Verilog machine enters into a non-covered statement,
the machine hangs. Defaulting the statement with a return to idle keeps us safe

1 case(address)
2 0 : $display ("It is 11:40PM");
3 1 : $display ("I am feeling sleepy");
4 2 : $display ("Let me skip this tutorial");
5 default : $display ("Need to complete");
6 endcase

While

A while statement executes the code within it repeatedly if the condition it is assigned to check returns
true. While loops are not normally used for models in real life, but they are used in test benches. As
with other statement blocks, they are delimited by begin and end.

1 while (free_time) begin

2 $display ("Continue with webpage development");

3 end

As long as free_time variable is set, code within the begin and end will be
executed. i.e print "Continue with web development". Let's looks at a stranger

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example, which uses most of Verilog constructs. Well, you heard it right. Verilog
has fewer reserved words than VHDL, and in this few, we use even lesser for
actual coding. So good of Verilog... so right.
1 module counter (clk,rst,enable,count);
2 input clk, rst, enable;
3 output [3:0] count;
4 reg [3:0] count;
5
6 always @ (posedgeclk or posedgerst)
7 if (rst) begin
8 count <= 0;
9 end else begin : COUNT
10 while (enable) begin
11 count <= count + 1;
12 disable COUNT;
13 end
14 end
15 endmodule

For loop
For loops in Verilog are almost exactly like for loops in C or C++. The only
difference is that the ++ and -- operators are not supported in Verilog.Instead of
writing i++ as you would in C, you need to write out its full operational equivalent,
i = i + 1.
1 for (i = 0; i < 16; i = i +1) begin
2 $display ("Current value of i is %d", i);
3 end

This code will print the numbers from 0 to 15 in order. Be careful when using for
loops for register transfer logic (RTL) and make sure your code is actually sanely
implementable in hardware... and that your loop is not infinite.

Repeat

Repeat is similar to the for loop we just covered. Instead of explicitly specifying a
variable and incrementing it when we declare the for loop, we tell the program how
many times to run through the code, and no variables are incremented (unless we
want them to be, like in this example).
1 repeat (16) begin
2 $display ("Current value of i is %d", i);
3 i = i + 1;
4 end

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The output is exactly the same as in the previous for-loop program example. It is
relatively rare to use a repeat (or for-loop) in actual hardware implementation.

Variable Assignment

In digital there are two types of elements, combinational and sequential. Of course
we know this. But the question is "How do we model this in Verilog ?". Well
Verilog provides two ways to model the combinational logic and only one way to
model sequential logic.

 Combinational elements can be modeled using assign and always

statements.
 Sequential elements can be modeled using only always statement.
 There is a third block, which is used in test benches only: it is called Initial
statement.

Initial Blocks

An initial block, as the name suggests, is executed only once when simulation
starts. This is useful in writing test benches. If we have multiple initial blocks, then
all of them are executed at the beginning of simulation

Example

1 initial begin
2 clk = 0;
3 reset = 0;
4 req_0 = 0;
5 req_1 = 0;
6 end

In the above example, at the beginning of simulation, (i.e. when time = 0),
all the variables inside the begin and end block are driven zero.

Always Blocks

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As the name suggests, an always block executes always, unlike initial blocks
which execute only once (at the beginning of simulation). A second difference is
that an always block should have a sensitive list or a delay associated with it.
The sensitive list is the one which tells the always block when to execute the block of code, as shown
in the figure below. The @ symbol after reserved word ' always', indicates that the block will be
triggered "at" the condition in parenthesis after symbol @.

One important note about always block: it can not drive wire data type, but can
drive reg and integer data types.

1 always @ (a or b or sel)
2 begin
3 y = 0;
4 if (sel == 0) begin
5 y = a;
6 end else begin
7 y = b;
8 end
9 end

The above example is a 2:1 mux, with input a and b; sel is the select input and y is
the mux output. In any combinational logic, output changes whenever input
changes. This theory when applied to always blocks means that the code inside
always blocks needs to be executed whenever the input variables (or output
controlling variables) change. These variables are the ones included in the sensitive
list, namely a, b and sel.

Comments

There are two forms to introduce comments:-

 Single line comments begin with the token // and end with a carriage
return
 Multi line comments begin with the token /* and end with the token */

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Examples of Comments-

1 /* This is a
2 Multi line comment
3 example */
4 module addbit (
5 a,
6 b,
7 ci,
8 sum,
9 co);
10
11 // Input Ports Single line comment
12 input a;
13 input b;
14 input ci;
15 // Output ports
16 output sum;
17 output co;
18 // Data Types
19 wire a;
20 wire b;
21 wire ci;
22 wire sum;
23 wire co;
24endmodule
Case Sensitivity

Verilog HDL is case sensitive

i.)Lower case letters are unique from upper case letters

ii)All Verilog keywords are lower case

Examples of Unique names:-

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1 input // a Verilog Keyword

2 wire // a Verilog Keyword

3 WIRE // a unique name ( not a

keyword)

4 Wire // a unique name (not a keyword

EXAMPLES OF VERILOG CODING

COUNTER:-
1 //-------------------------------------------------
2 // This is my second Verilog Design
3 // Design Name : first_counter
4 // File Name : first_counter.v
5 // Function : This is a 4 bit up-counter with
6 // Synchronous active high reset and
7 // with active high enable signal
8 //-----------------------------------------------
9 module first_counter (
10 clock , // Clock input of the design
11 reset , // active high, synchronous Reset input
12 enable , // Active high enable signal for counter
13 counter_out // 4 bit vector output of the counter
14 ); // End of port list
15 //-------------Input Ports-----------------------
16 input clock ;
17 input reset ;
18 input enable ;
19 //-------------Output Ports----------------------
20 output [3:0] counter_out ;
21 //-------------Input ports Data Type-------------
22 // By rule all the input ports should be wires
23 wire clock ;
24 wire reset ;
25 wire enable ;
26 //-------------Output Ports Data Type------------

99 | P a g e
 27 // Output port can be a storage element (reg) or a
wire
28 reg [3:0] counter_out ;
29
30 //------------Code Starts Here-------------------
31 // Since this counter is a positive edge trigged
one,
32 // We trigger the below block with respect to
positive
33 // edge of the clock.
34 always @ (posedge clock)
35 begin : COUNTER // Block Name
36 // At every rising edge of clock we check if
reset is active
37 // If active, we load the counter output with
4'b0000
38 if (reset == 1'b1) begin
39 counter_out<= #1 4'b0000;
40 end
41 // If enable is active, then we increment the
counter
42 else if (enable == 1'b1) begin
43 counter_out<= #1 counter_out + 1;
44 end
45 end // End of Block COUNTER
46
47 endmodule // End of Module counter

ADD BITS

1 module addbit (

2 a , // first input

3 b , // Second input

4 ci , // Carry input

5 sum , // sum output

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 6 co // carry output

7 );

8 //Input declaration

9 input a;

10 input b;

11 input ci;

12 //Ouput declaration

13 output sum;

14 output co;

15 //Port Data types

16 wire a;

17 wire b;

18 wire ci;

19 wire sum;

20 wire co;

21 //Code starts here

22 assign {co,sum} = a + b + ci;

23

24 endmodule // End of Module addbit

TRANSMISSION GATES:-

1 module transmission_gates();

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 2
3 regdata_enable_low, in;
4 wire data_bus, out1, out2;
5
6 bufif0 U1(data_bus,in, data_enable_low);
7 buf U2(out1,in);
8 not U3(out2,in);
9
10 initial begin
11 $monitor(
12 "@%g in=%b data_enable_low=%b out1=%b out2= b
data_bus=%b",
13 $time, in, data_enable_low, out1, out2,
data_bus);
14 data_enable_low = 0;
15 in = 0;
16 #4 data_enable_low = 1;
17 #8 $finish;
18 end
19
20 always #2 in = ~in;
21
22 endmodule

MULTIPLEXER:-

1 module mux_from_gates ();

2 reg c0,c1,c2,c3,A,B;
3 wire Y;
4 //Invert the sel signals
5 not (a_inv, A);
6 not (b_inv, B);
7 // 3-input AND gate
8 and (y0,c0,a_inv,b_inv);
9 and (y1,c1,a_inv,B);
10 and (y2,c2,A,b_inv);
11 and (y3,c3,A,B);
12 // 4-input OR gate
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 13 or (Y, y0,y1,y2,y3);
14
15 // Testbench Code goes here
16 initial begin
17 $monitor (
18 "c0 = %b c1 = %b c2 = %b c3 = %b A = %b B = %b Y
= %b",
19 c0, c1, c2, c3, A, B, Y);
20 c0 = 0;
21 c1 = 0;
22 c2 = 0;
23 c3 = 0;
24 A = 0;
25 B = 0;
26 #1 A = 1;
27 #2 B = 1;
28 #4 A = 0;
29 #8 $finish;
30 end
31
32 always #1 c0 = ~c0;
33 always #2 c1 = ~c1;
34 always #3 c2 = ~c2;
35 always #4 c3 = ~c3;
36
37 endmodule

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Programmable logic
device

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Programmable logic device
A programmable logic device or PLD is an electronic component used to build reconfigurabledigital
circuits. Unlike a logic gate, which has a fixed function, a PLD has an undefined function at the time of
manufacture. Before the PLD can be used in a circuit it must be programmed, that is, reconfigured.

It is impossible to discuss PLD technology without mentioning some of the companies involved in its
development.However it is not the purpose of this article to list all manufacturer of PLDs.Inclusion or
omission of a particular company from this article is intended as neither a recommendation nor
acriticism.

Using a ROM as a PLD

Before PLDs were invented, read-only memory (ROM) chips were used to create arbitrary combinational
logic functions of a number of inputs. Consider a ROM with m inputs (the address lines) and n outputs
(the data lines). When used as a memory, the ROM contains 2m words of n bits each.

Now imagine that the inputs are driven not by an m-bit address, but by m independent logic signals.
Theoretically, there are 22m possible Boolean functions of these m input signals. By Boolean function in
this context is meant a single function that maps each of the 2m possible combinations of the m Boolean
inputs to a single Boolean output. There are 22m possible distinct ways to map each of 2m inputs to a
Boolean value, which explains why there are 22m such Boolean functions of m inputs.

Now, consider that each of the n output pins acts, independently, as a logic device that is specially
selected to sample just one of the possible 22m such functions. At any given time, only one of the 2m
possible input values can be present on the ROM, but over time, as the input values span their full
possible domain, each output pin will map out its particular function of the 2m possible input values,
from among the 22m possible such functions. Note that the structure of the ROM allows just n of the 22m
possible such Boolean functions to be produced at the output pins. The ROM therefore becomes
equivalent to n separate logic circuits, each of which generates a chosen function of the m inputs.

The advantage of using a ROM in this way is that any conceivable function of all possible combinations
of the m inputs can be made to appear at any of the n outputs, making this the most general-purpose
combinational logic device available for m input pins and n output pins.

Also, PROMs (programmable ROMs), EPROMs (ultraviolet-erasable PROMs) and EEPROMs (electrically
erasable PROMs) are available that can be programmed using a standard PROM programmer without
requiring specialised hardware or software. However, there are several disadvantages:

 they are usually much slower than dedicated logic circuits,

 they cannot necessarily provide safe "covers" for asynchronous logic transitions so the PROM's
outputs may glitch as the inputs switch,
 they consume more power,
 they are often more expensive than programmable logic, especially if high speed is required.

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Since most ROMs do not have input or output registers, they cannot be used stand-alone for sequential
logic. An external TTL register was often used for sequential designs such as state machines. Common
EPROMs, for example the 2716, are still sometimes used in this way by hobby circuit designers, who
often have some lying around. This use is sometimes called a 'poor man's PAL'.

Early programmable logic

In 1969, Motorola offered the XC157, a mask-programmed gate array with 12 gates and 30
uncommitted input/output pins.

In 1970, Texas Instruments developed a mask-programmable IC based on the IBM read-only associative
memory or ROAM. This device, the TMS2000, was programmed by altering the metal layer during the
production of the IC. The TMS2000 had up to 17 inputs and 18 outputs with 8 JK flip flop for memory. TI
coined the term Programmable Logic Array for this device.

In 1971, General Electric Company (GE) was developing a programmable logic device based on the new
PROM technology. This experimental device improved on IBM's ROAM by allowing multilevel logic. Intel
had just introduced the floating-gate UV erasable PROM so the researcher at GE incorporated that
technology. The GE device was the first erasable PLD ever developed, predating the Altera EPLD by over
a decade. GE obtained several early patents on programmable logic devices.

In 1973 National Semiconductor introduced a mask-programmable PLA device (DM7575) with 14 inputs
and 8 outputs with no memory registers. This was more popular than the TI part but cost of making the
metal mask limited its use. The device is significant because it was the basis for the field programmable
logic array produced by Signetics in 1975, the 82S100. (Intersil actually beat Signetics to market but poor
yield doomed their part.)

In 1974 GE entered into an agreement with Monolithic Memories to develop a mask- programmable
logic device incorporating the GE innovations. The device was named the 'Programmable Associative
Logic Array' or PALA. The MMI 5760 was completed in 1976 and could implement multilevel or
sequential circuits of over 100 gates. The device was supported by a GE design environment where
Boolean equations would be converted to mask patterns for configuring the device. The part was never
brought to market.

PAL
Programmable array logic

PAL devices have arrays of transistor cells arranged in a "fixed-OR, programmable-AND" plane used to
implement "sum-of-products" binary logic equations for each of the outputs in terms of the inputs and
either synchronous or asynchronous feedback from the outputs.

MMI introduced a breakthrough device in 1978, the Programmable Array Logic or PAL. The architecture
was simpler than that of Signetics FPLA because it omitted the programmable OR array. This made the
parts faster, smaller and cheaper. They were available in 20 pin 300 mil DIP packages while the FPLAs
came in 28 pin 600 mil packages. The PAL Handbook demystified the design process. The PALASM design

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software (PAL Assembler) converted the engineers' Boolean equations into the fuse pattern required to
program the part. The PAL devices were soon second-sourced by National Semiconductor, Texas
Instruments and AMD.

After MMI succeeded with the 20-pin PAL parts, AMD introduced the 24-pin 22V10 PAL with additional
features. After buying out MMI (1987), AMD spun off a consolidated operation as Vantis, and that
business was acquired by Lattice Semiconductor in 1999.

There are also PLA’s:programmable Logic Array.

Types of PLD:-

1. Simple programmable logic device (SPLD)

2. Complex programmable logic device (CPLD)
3. Field-programmable gate array (FPGA)

Simple Programmable Logic Devices (SPLD)

Simple programmable logic devices (SPLD) are the simplest, smallest and least-expensive forms of
programmable logic devices. SPLDs can be used in boards to replace 7400-series TTL components (AND,
OR, and NOT gates). They typically comprise 4 to 22 fully connected macrocells. These macrocells are
typically comprised of some combinatorial logic (such as AND OR gates) and a flip-flop. In other words, a
small Boolean logic equation can be built within each macrocell. This equation will combine the state of
some number of binary inputs into a binary output and, if necessary, store that output in the flip-flop
until the next clock edge. Of course, the particulars of the available logic gates and flip-flops are specific
to each manufacturer and product family. But the general idea is always the same.

Most SPLDs use either fuses or non-volatile memory cells (EPROM, EEPROM, FLASH, and others) to
define the functionality.These devices are also known as programmable array logic (PAL), generic array
logic (GAL), programmable logic arrays (PLA), or field-programmable logic arrays (FPLA), and
programmable logic devices (PLD).

SPLD chips are available in a variety of integrated circuit(IC)package types and with different numbers
of pins.Basic IC package types include single in line package(SIP),Dual in line package(DIP),discrete
package(DPAK),small outline package(SOP),and quad flat package(QFP).Many packaging variants are
available.For example ,common SOP variants for SPLD chips include shrink small outline package(SSOP)
and thin shrink small outline L-leaded package(TSSOP).Small outline integrated circuit(SOIC)packaging is
also available for SPLD chips.

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Complex programmable logic device

A complex programmable logic device (CPLD) is a programmable logic device with complexity between
that of PALs and FPGAs, and architectural features of both. The building block of a CPLD is the macrocell,
which contains logic implementing disjunctive normal form expressions and more specialized logic
operations.

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Features in common with PALs

Non-volatile configuration memory. Unlike many FPGAs, an external configuration ROM isn't required,
and the CPLD can function immediately on system start-up.

For all but the largest devices, routing constrains most logic blocks to have input and output signals
connected to external pins(little opportunity for internal state storageor deeply layered logic).

Large number of gates available. CPLDs typically have the equivalent of thousands to tens of thousands
of logic gates, allowing implementation of moderately complicated data processing devices. PALs
typically have a few hundred gate equivalents at most, while FPGAs typically range from tens of
thousands to several million. Some provisions for logic more flexible than sum-of-product expressions,
including complicated feedback paths between macro cells, and specialized logic for implementing
various commonly-used functions, such as integerarithmetic.

The most noticeable difference between a large CPLD and a small FPGA is the presence of on-chip non-
volatile memory in the CPLD. This distinction is rapidly becoming less relevant, as several of the latest
FPGA products also offer models with embedded configuration memory.

The characteristic of non-volatility makes the CPLD the device of choice in modern digital designs to
perform 'boot loader' functions before handing over control to other devices not having this capability.
A good example is where a CPLD is used to load configuration data for an FPGA from non-volatile
memory.

CPLDs were an evolutionary step from even smaller devices that preceded them, PLAs (first shipped by
Signetics), and PALs. These in turn were preceded by standard logic products, that offered no
programmability and were "programmed" by wiring several standard logic chips together.

The main distinction between FPGA and CPLD device architectures is that FPGAs are internally based on
look-up tables (LUTs) while CPLDs form the logic functions with sea-of-gates (for example, sum of
products).

Field-programmable gate array

A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by a
customer or a designer after manufacturing—hence "field-programmable". The FPGA configuration is
generally specified using a hardware description language (HDL), similar to that used for an application-
specific integrated circuit (ASIC) (circuit diagrams were previously used to specify the configuration, as
they were for ASICs, but this is increasingly rare). Contemporary FPGAs have large resources of logic
gates and RAM blocks to implement complex digital computations. As FPGA designs employ very fast IOs
and bidirectional data buses it becomes a challenge to verify correct timing of valid data within setup
time and hold time. Floor planning enables resources allocation within FPGA to meet these time
constraints. FPGAs can be used to implement any logical function that an ASIC could perform. The ability
to update the functionality after shipping, partial re-configuration of a portion of the design and the low

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non-recurring engineering costs relative to an ASIC design (notwithstanding the generally higher unit
cost), offer advantages for many applications.

FPGAs contain programmable logic components called "logic blocks", and a hierarchy of reconfigurable
interconnects that allow the blocks to be "wired together"—somewhat like many (changeable) logic
gates that can be inter-wired in (many) different configurations. Logic blocks can be configured to
perform complex combinational functions, or merely simple logic gates like ANDandXOR. In most FPGAs,
the logic blocks also include memory elements, which may be simple flip-flops or more complete blocks
of memory.

Some FPGAs have analog features in addition to digital functions. The most common analog feature is
programmable slew rate and drive strength on each output pin, allowing the engineer to set slow rates
on lightly loaded pins that would otherwise ring unacceptably, and to set stronger, faster rates on
heavily loaded pins on high-speed channels that would otherwise run too slow. Another relatively
common analog feature is differential comparators on input pins designed to be connected to
differential signaling channels. A few "mixed signal FPGAs" have integrated peripheral analog-to-digital
converters (ADCs) and digital-to-analog converters (DACs) with analog signal conditioning blocks
allowing them to operate as a system-on-a-chip. Such devices blur the line between an FPGA, which
carries digital ones and zeros on its internal programmable interconnect fabric, and field-programmable
analog array (FPAA), which carries analog values on its internal programmable interconnect fabric.

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FPGA design and programming

To define the behavior of the FPGA, the user provides a hardware description language (HDL) or a
schematic design. The HDL form is more suited to work with large structures because it's possible to just
specify them numerically rather than having to draw every piece by hand. However, schematic entry can
allow for easier visualisation of a design.

Then, using an electronic design automation tool, a technology-mapped netlist is generated. The netlist
can then be fitted to the actual FPGA architecture using a process called place-and-route, usually
performed by the FPGA company's proprietary place-and-route software. The user will validate the map,
place and route results via timing analysis, simulation, and other verification methodologies. Once the
design and validation process is complete, the binary file generated (also using the FPGA company's
proprietary software) is used to (re)configure the FPGA. This file is transferred to the FPGA/CPLD via a
serial interface (JTAG) or to an external memory device like an EEPROM.

The most common HDLs are VHDL and Verilog, although in an attempt to reduce the complexity of
designing in HDLs, which have been compared to the equivalent of assembly languages, there are moves
to raise the abstraction level through the introduction of alternative languages. National Instrument's

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LabVIEW graphical programming language (sometimes referred to as "G") has an FPGA add-in module
available to target and program FPGA hardware.

To simplify the design of complex systems in FPGAs, there exist libraries of predefined complex
functions and circuits that have been tested and optimized to speed up the design process. These
predefined circuits are commonly called IP cores, and are available from FPGA vendors and third-party IP
suppliers (rarely free, and typically released under proprietary licenses). Other predefined circuits are
available from developer communities such as OpenCores (typically released under free and open
source licenses such as the GPL, BSD or similar license), and other sources.

In a typical design flow, an FPGA application developer will simulate the design at multiple stages
throughout the design process. Initially the RTL description in VHDL or Verilog is simulated by creating
test benches to simulate the system and observe results. Then, after the synthesis engine has mapped
the design to a netlist, the netlist is translated to a gate level description where simulation is repeated to
confirm the synthesis proceeded without errors. Finally the design is laid out in the FPGA at which point
propagation delays can be added and the simulation run again with these values back-annotated onto
the netlist.

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VLSI
SOFTWARES

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MICROWIND SOFTWARE
A user friendly layout and simulation tool for cmos design

 DSCH3
 Nanolambda
 Virtuosofab
 Memsim
 Prothumb
 Protutor

DSCH3

 It is mainly used as a schematic editor.

 User –friendly environment for rapid design of logic circuit.
 Supports hierarchical logic design.
 Built-in extractor which generates a SPICE netlist from the schematic diagram(compatible with
PSPICE and WINSPICE).
 Generates a verilog description of the schematic for direct compiling into layout.
 Immediate access to symbol properties(delay,fanout).
 Submicron,deep-submicron,nanoscale technology support.
 Up to 5000 symbols.

OPTIONS OF DSCH3

File

New | open | save | save as | select Foundry | make Verilog file | schema to new symbol |properties
|monochrome/color | print| leave DSCH3

Edit

Undo|Cut|Paste|Copy|Move|Rotateleft|RotateRight|FlipHorizontal|FlipVertical|Line|Connect|Text

Insert

User Symbol|Another Schema

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View

View All|ViewSame|Zoom In |Zoom

Out|ListOfSymbols|DesignHierarchy|ElectricalNet|TimingDiagrams|SymbolLibrary|Unselect all

Simulate

Check Floating Lines|Find critical path|StartSimulation|Stopsimulation|Simulation Options

Help

About Dsch|Contents

File:-

New(File menu)

Click on File-> New in order to restart the software to restart the Software with an empty screen. The
current design should be saved before asserting this command, as all the graphic information will be
physically removed from the computer memory. No undo is available to disable the new command.

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Open(File Menu)

Click on the above icon. in the list, double-click on the file to load. ”.Sch” is the default extension that
corresponds to the schematic diagrams.

Save/Save as(File Menu)

Click on file-> save to save the schematic diagram with its current name.

The default name is”EXAMPLE.SCH”.

In the case of “Save as” a new window appears into which you have to enter the design name. Use the
key board and type the desired file name,press”Save”.your design is now Registered with the .Sch
appendix.

select Foundry(File Menu)

Click on file->select Foundry The list of available processes appears .The initial design rule file is
“default.tec”.various technologies are available from 1.2 down to 0.1 micro meter .click on the rule file
name and the software reconfigures itself in order to adapt to the new process.

Verilog(File Menu)

The conversion of schematic diagram into a VERILOG description is useful for compiling the schematic
diagram into layout using microwind.Theverilog description is a text with a predefined syntax. Basically
the text includes a description of the module(name,input,output),the internal wires, and the list of
primitives. An example of verilog file generated by DSCH is given below .

//DSCH

//24/06/0318:38:13

//C:\Dsch3.0\Base.sch

Module Base (A,B,INV,NAND,XOR,NOR);

Input A,B;

Output INV,NAND,XOR,NOR;

Not1 not12(B,Inv)

Nand2 nand24(B,A,NAND)

Xor2 xor27(A,B,XOR)

Nor2 nor28(A,B,NOR)

endmodule

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//Simulation parameters

//A clk 1010

//B clk 2020

COMMENTS://

MODULE DECLARATION:”module”,name,and list of i/os.

MODULE CONTENTS: list of inputs, outputs ,of internal wires, and the declaration of primitives, always
with the primitive keyword first, the name second, and the list of parameters. For example:NOT1 is the
primitive for the inverter, ”not 12” is the cell name,”b” is the input and “INV” the output.

MODULE END:”endmodule”.

schema to new symbol(File Menu)

This command is very important to create user –defined symbols in order to build hierarchical designs.
As an example ,the full adder diagrams based on primitives can be translated into a single symbol which
includes the structure, input and outputs, as shown below.

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i/os.The list of i/os is based on active symbols(buttons,clocks,keyboards,etc..).

The position and side in the symbol may be changed in the table.

VERILOG-The structural description based on primitives is described in verilog format and included to
the symbol description.

REFRESH-Update the layout of the user symbol.

SIZING –Act on the icons to change the shape of the user symbol.

SYMBOL PROPORTIES-This properties may be changed by the user.

Properties (File Menu)

The command file->Properties provide some information about the current technology, the percentage
of memory used by the schematic diagram and its detailed contents.

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In the technology part, details on the time unit, voltage supply, typical delay and typical wire delay are
provided, which configure the delay estimation and current estimation during logic simulation.

Print(File Menu)

Click on file -> Print to transfer the graphical contents of the screen to the printer.

Alternatively, you can make a copy of the window into the clipboard in order to import the screen into
your favorite text editor by pressing <Alt>+<print screen>.in the text editor or in the graphic editor,
simply click on “Edit->Paste”.

Automatically, DSCH3 is switched to monochrome mode prior to printing.

Leave Dsch3(File Menu)

Click on file->Leave dsch3 in the main menu. if you have made a design or if you have modified some
data, you will be asked to save it. After confirmation, You return to windows.

EDIT-

Undo(Edit Menu)

The undo command(Edit->Undo) is useful to not take into account the last editing command. it is
possible to undo the commands cut, paste,copy,move,stretch& edit.

Cut(Edit->Cut or CTRL+X)

Click on the cut icon .Move the cursor to the design window and delimit the active area with the mouse,
consequently all the graphics included in this area are erased .click on undo to fix those elements back
into the design.

 One single symbol can be erased by a click inside its layout when the cut command is active.
 One single inter connect can be erased by a click inside its wire when the cut command is
active.

Paste(Edit->Cut or CTRL+v)

Invoke the paste command . All previously copied elements are pasted at the desired location. Deleted
elements can be replaced that way.

Click on undo to cancel the paste command.

Copy(Edit->Copy or CTRL+C)

Click on the copy icon. Move the cursor to the design window and delimit the active area with the
mouse, consequently all the graphics included in this area are copied. The External shape of the copied
elements appears. Fix those copied elements at the desired location by a click on the mouse.

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Click on undo to cancel the copy command.

Move(Edit Menu)

To move one graphical element click on the move icon or “edit->move”. Then using the mouse draw an
area that includes the elements.Then,drag the mouse to the new location and release the mouse.

As a result the elements are moved to the new place.

 One single line can be moved or stretched(depending where you click) by a direct click on the
line.
 One single text can be moved by a direct click on the text location.

Rotate(Edit Menu)

To apply a rotation to one part of the design click on edit->Rotate. Select one of the proposed action.

 Rotate right or 900.

 Rotate left or - 900.

Then delimit the area inside which the elements will be rotated.

Flip(Edit Menu)

To apply a flip to one part of the design Click on Edit->Flip. Then delimit the area inside which the
elements will be changed.

Line(Edit->Line or Right Button of the mouse)

The line icon is the default icon. It creates an interconnection between two points in the schematic
diagram. If the line icon is not selected click on it .Then move the cursor to the display window and fix
the start point of the interconnect with a press of the mouse. Keep pressed and drag the mouse to the
interconnect end. Release the mouse and see how the line is created.

Connect(Edit Menu)

Use the icon to create the electrical contact between crossing interconnects.

Text(Edit Menu)

Text is added for information only. It has no impact on simulation. Text is useful to add comments on
the schematic diagram, add more information or specific I/Os or nodes.

INSERT-

User symbol(insert Menu)

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The command insert->user symbol is used to add a user defined symbol to the existing schematic
diagram. The user symbol is created using the command file->schema to new symbol. The inserted
symbol can be fixed at the desired location.

Insert another Schema(Insert Menu)

The command file->insert another schema is used to add a SCH file to the existing files. Its contents is
fixed at the right lower side of the existing schematic diagram. The current file name remains
unchanged.

VIEW-

VIEW ALL(View Menu)

Click view->view all to fit the screen with all the graphical elements currently on display.

View Same(View Menu)

Draw again the schematic diagram without changing the scale. Used to refresh the screen.

Zoom In, Zoom Out(View Menu)

The above commands perform zoom in and zoom out operations. When zooming in the area
determined by the mouse will be enlarged to fit the display window.When zooming out the area
determined by the mouse will contain the display window.

 If you click once, a zoom is performed at the desired location.

 Press Ctrl+A for<<View All>>, and Ctrl+O for zoom out.

List of symbols(View Menu)

The command gives the completenetlist corresponding to the schematic diagram. The internal structure
of hierarchical symbols also appears. The symbol name, List of pins, Related node numbers and model
number are listed.

Design Hierarchy(View Menu)

The design hierarchy command gives an interesting insight in the hierarchical structure of symbols,
together with the list of input and output symbols.

Electrical Net(View Menu)

Click on the icon Electrical net or on view->Electrical net, then click in the desired interconnect or pin in
the schematic diagram. After an extraction procedure has been carried out, you will see that all the
wires connected to that node. Click<Escape> or View->Unselect All to Unselect the diagram.

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TIMING DIAGRAM(VIEW MENU)

The timing diagram gives the time domain aspect of all input and output nodes. You may zoom on a
specific time window, add the evaluation of the consumed current, and get the exact value of each
input/output at a desired location.

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Symbol Library(View Menu)

The symbol library contains basic logic and electrical symbols,sources,displays and switches. Most
standard logic symbols(invrter,buffer,nand,and,nor,or,xor)and D-latches are part of the basic symbol
menu. The analog components such as resistor,inductor,capacitor,operational amplifiers are reported in
the advanced menu. Notice several input/output symbols as well as a variety of switches for
programmable arrays. Some more symbols may be found in the IEEE directory, accessible through the
command insert user symbol.

Unselect all(View Menu)

Escape Key-Use the command (view->unselect all)to cancel undesired commands or to redraw the
complete schematic diagram.

Simulate

Check Floating lines (Simulate Menu)

The command simulate check floating lines may be found in the simulation menu.The schematic
diagram is scanned in order to detect interconnects with a wrong connection to the symbol or other
interconnects.

Critical path(View Menu and Simulate Menu)

The critical path is the series of logic gates between the output and input with the longest propagation
delay. The command Simulate find critical path shows the graph of the critical path. Invoke the

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command view critical path details to extract the list of symbols and cumulated delays which build the
critical path.

Start/Stop Simulation(Simulate Menu)

The command start simulation launches the electrical net extraction and the logic simulation. The
simulation speed may be controlled by the cursor Fast-Slow. The simulation may be paused, run step
by step and stopped by default, the logic state of all interconnects is made visible. You may also see
each pin state by a tic in front of Show Pin State. The simulation parameters(Simulation Option) are the
simulation step(10ps by default),the gate delay, wire delay, supply voltage and elementary gate current.
This parameters are loaded from.TEC files at initialization or with the command File Select Foundry.

STEP-1 Create new project.

STEP-2 create new project

STEP-3 go to project menu and select new source.

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STEP-4 select VHDL source file,name it half-adder(let) click next And enter Entity
I/o as A,B,SUM & CARRY.

STEP-5 writ VHDL code for half adder.

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STEP-6 Create new source file for implementation constraint file.name it
adder_ucf,and associate with the corresponding design file.

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STEP-7 To assign the pin location of design,open the ucffile,to run the constraint
editor,where we have to lock the editor where we have to lock i/os of design to a
particular rin number.

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STEP-8 once the constraint editor is open,go to ports tab and assign the pins by
reffering the pin assignment chapter.

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STEP-9 save the ucf file come back to project navigator.now selecting the adder design file,run the
synthesis process,thereafterimplementation,and finally run generate programme file option.

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STEP-10After the all the process are successfully over,run the configure device option to open the
impact programmer.after opening impact add Xilinx device design file,forcpld it is *.jed,and for fpga it is
*.bit file.

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STEP-11Go to operation option and select program option.

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STEP-12Keep the erase option enabled and click ok.

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STEP-13After erasing the cpld,the programming would start and will configure the particular device.

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Now check the functionality on the board and verify it by applying different inputs.

Design flow for quartus-ll series of software of altera

Install Quartus-ll (version 3.0 and above) software on your machine,the supported platforms are
windows NT/Xp/2000.

We take the same example for implementing on the altera MAX7000s CPLD.

STEP-l:startQuartus-ll(version 3.0 & above) software.

STEP-2:For new project creation ,go to file option and select new project wizard.in the opened
window,specify project location and design and entity name.foreg. Entity nameadder,and top design
name also adder.click “next”.

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Step-3click “next” button till you reach EDA tools settings window,there keep all option as none,which in
default will select the inbuilt design tools and softwares for the design processing.CLICK “NEXT”

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Step-3select MAX700S device family in the next window.click “next”.

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Step-4in the next window,select the device as EPM&128slc84-15 .Click’next”.

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Step-5: click “finish”.And the new project would be created .Now we need to make and add new design
file in the project.so goto“FILE”menu,andclick”new”,and select VHDL file,in the “device design
files”tab.CLICK”ok”.

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STEP-6: Write the VHDL code for half adder design,and save the file as “adder.vhd”

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STEP-7: Now goto PROCESSING menu-then-START,click START ANALYSIS and SYNTHESIS.

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STEP-8:Read the synthesis reports

STEP-9: for performing simulation,we need to create stimuli file from where we can apply input signals
and watch the o/p waveforms.

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Goto FILE menu,and click NEW file,gotoother filestab,and select “vector waveform file” option.

Step-10:Add the entity signals in the waveform window,and apply different sets of value to check the
functionality.Save the file as the same name of entity,ADDER.vwf

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Step-11: In AlteraQuartus-ll software you can perform FUNctionaland Timingsimulation.For to
assignmentsmenu,and click settings.

Step-12:Now go to simulator setting ,then to mode,and in the right-hand side window,select the
simulation mode to functional.

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Step-13:After clicking OK,come back to main window,andgotoprocessing window,and click
startsimulation,theQuartus-ll will start the simulation the result would appear in couple of
minutes.observe the results,if found bugs,then change VHDL code and start simulation again.

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Step-14:Once the simulation result found correct,then we need to implement the design in the target
device.For this we need to lock our design I/os with the kit I/O pin details.Go to
assignmentmenu,click“assign pin”option.

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Step-15:Looking at the pin assignment chapter ,lock the MAX7000s CPLD I/O with the particular pin
no,for this select the I/Os number of LHS,name the design I/O in the bottom pin name option,and then
click add,the particular signal will be locked to that pin number.

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Step-16:Once the pin assignment is over,come back to main window.Now we need to implement the
design on the particual device.so, goto processing menu,and click start compilation process.which will fit
the design in CPLD and generate the programming file.

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Step-17:Once the compilation process is over,user can check the reports and see the floorplan window.

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Step-18:Now we need to program CPLD,for this goto tools menu,and click programmer,the software will
automatically add the programming file(adder.pof).in the opened window select the
program/configure option .Now we need to select the programming hardware tab n the LHS of
programming window.

Step-19:In the opened window click add hardwaretab,and select the hardware type as Byte blasterMV
or ByteBlasterll and port as LPT1.

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Step-20:Come back to hardware setupwindow,and click the select hardware tab and close the window.

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Step-21:Now click the start-programming button(play symbol) on the top LHS of the programming
window(keep the program/configure option selected).

Step-22:Theprogramme will start programming and in couple of seconds the device would be
configured .check the DONE indication in the bottom console window.

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Step-23:Check the design functionality on the board,by applying signal from switches or other points.

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PROTOBOARD

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Universal VLSI Protoboard

Product information

The Universal-ll VLSI protoboard is a low cost universal platform for testing and verifyingdesign based
on the Xilinx and Altera PLds.

VLSI protoboard exists for teaching the basic concepts of VLSI designing with various digital logic
circuits;along with PLD architectures.Here universal –ll board gives extreme exposure with four PLD
cards to learners who want to learn VLSI designing along with various PLD architectures.

Universal-ll supports multiple vendor devices from Xilinx and Altera ,who are world leader in PLD
manufacturing.it supports Spartan-2 and XC9500 series of devices from Xilinx;andACEX 1k and
MAX7000s series of devices from Altera.

The basic version of Univesal-ll comes with 50000 gate XC2S50-PQ208 FPGA,XC9572 or MAX7128S
CPLD and EP1k50T144 FPGA from Altera along with supporting circuits to ease prototype efforts
(optional PLD modules available).

Features and Specifications

 Multi-vendor device support for Xilinx and Altera PLDs.

 Packages supported PLCc84,TQ144 AND PQ208.
 Voltage support to +1.2v,+2.5v,+3.3v &+5v devices.
 Upto 140 user I/Os.
 ALL FPGA I/O accessible through headers.
 Four Multiplexed 7-Segment displays(with segment map).
 Interface to RS232 with 9-pin D-type connector.
 User selectable configuration modes,using FLASH /PROM/JTAG/Slave serial.
 Byte blaster cable interface for configuration of Altera FPGAs.
 On board 8-MHz clock oscillator(user selectable).
 Configurable 24 switches as i/p or o/p.
 16 digital LED indicated outputs.
 Power on Reset and configuration reset key.
 Support for i2c interface.
 Short circuit protection circuit

Daughter Cards (Available with Universal protoboard)

 Xilinx FPGA Spartan ll XC2S50 PQ208-5c

 Altera Acex FPGA EP1K50 TQ 144-3C
 Xilinx CPLD XC 9572 PLCC84-15C
 AlTERA MAX7000s CPLD EPM7128s PLCC84-15C

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Application and Practicals
 Temperature controller
 Access control system
 Display and Messaging application
 Pc based application
 8051 microcontroller based application
 Design of 8/16/24/32 bit counters.
 8/16/24/32 bit shift register.
 4-bit and 8-bit ALUs.
 Timer Designs IC8254 and IC8253.
 8255 PPI design.
 Adders and subtractors
 All digital logic gates and functions.

Power supply

Required voltages are generated onboard through regulators;other supply voltages are applied from
external power supply.

Here is the list of voltages on board used.

+12v

+5v

-5v

+3.3v

+2.5v

+1.2v

*Note:The above specifications and features of product are subject to change with new versions of
product.

Connectors

Header Name Ident

PLD Header JH1,JH2,JH3,JH4
Power supply JP6

Jumpers

Jumpers are provided on baseboard for selection of

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1.Configuration mode pins.

2.Bypassing the PROM

3.Selecting configurable input or output.

4.Selecting the O/P LEDs.

 J8-J11 Mode Selection headers

 J6,J7 PROM bypass
 S0-S7 SW1
 S8-S15 SW2
 S16-S23 SW3

SYETEM CONNECTION DIAGRAM OF DEVICES

SYSTEM CONNECTION DIAGRAM(XILINX FPGA)

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SYSTEM CONECTION DIAGRAM(ALTERA FPGA)

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System Connection Diagram(CPLDS)

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 PRECAUTIONS

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PIN ASSIGNMENT FOR HARDWARE DEVICES
(ALTERA DEVICES)

ACEX IK FPGA(EP1K50TC144)

MAX 7000S CPLD (EPM7128SLC84)

INPUT SWITCH

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PIN ASSIGNMENT FOR HARDWARE DEVICES
(ALTERA DEVICES)

ACEX IK FPGA(EP1K50TC144)
MAX 7000S CPLD (EPM7128SLC84)

OUTPUT LEDS

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PIN ASSIGNMENT FOR HARDWARE DEVICES
(XILINX DEVICES)
SPARTAN-ll FPGA (XC2S50PQ208)
XC9500 CPLD (XC95xxPC84)
OUTPUT LEDS

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PIN ASSIGNMENT FOR HARDWARE DEVICES
(XILINX DEVICES)
SPARTAN-ll FPGA (XC2S50PQ208)
XC9500 CPLD (XC95xxPC84)
INPUT SWITCH

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Exercise-1

Using Microwind software design the following schematic circuits.

i.4 Bit Binary parallel adder

ii.4 Bit Binary parallel subtractor

iii.1 Bit ALU

iv. up down counter

v.7 segment display unit

vi.Binary to Excess 3 code converter

vii.Grey code to binary Converter

Exercise-2

Using the Microwind software design the following CMOS circuits.

i.Tristste inverter

ii.Tristate buffer

iii.X-or gate

iv.2 Bit comparator

v.2:1 mux

Exercise-3

Write down the following VHDL coding in the dataflow model by using the Xilinx software.

i.8:1 MUX

ii.1:4 DMUX

iii.Full Adder

iv.4 Bit Comparator

v.Excess 3 Code tp Binary Converter

Exercise-4

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Write down the following VHDL coding in the Behavioral Flow model by using the “case”
statement in XILINX Software.

i.4:1 MUX

ii.8:1 MUX

iii.1:4DMUX

iv.1:8 DMUX

Exercise-5

Write down the following vhdl coding for the following in Xilinx software.

i.D Flip Flop

ii.R-S Flip Flop

iii.J-K flip Flop

iv.T Flip Flop

v.4 Bit Counter

Exercise-6

Write down the following VHDL coding for the following in the Structural Model in XILINX
software.

i.4 Bit Binary Parallel Adder

ii.Full Adder(Using 2 no. of Half Adder)

iii.PISO shift register

iv.7 Segment Display

Exercise-7

Design the following Schematic and find out its vwf by using ALTERA Software.

i.6 input NOR Gate

ii.8 input X-or Gate

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iii. 4 Input BAND Gate

iv.2 Input BNOR Gate

v.12 input AND Gate

vi.6 input BOR Gate

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