MULTI-MODE RECONFIGURABLE

SOFTWARE DEFINED RADIO (SDR)

ARCHITECTURE FOR AVIONIC RADIOS
Joe Zambrano
Abdessamad Amrhar,Alireza Avakh Kisomi, Eric Zhang,
Claude Thibeault, René Jr. Landry

ICNS 2017
April 19, 2017
Track 2:
Communications, Navigation, and Surveillance
Session D:
Software Defined Radio (SDR) & Spectrum
Outline

1.Introduction

2.MM-SDAR prototype

3.Performance

4.Conclusion

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Outline

1.Introduction

2.MM-SDAR prototype

3.Performance

4.Conclusion

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1. Introduction
Context of the AVIO-505 Project
• Objectives:
– Integration of navigation, communication and surveillance systems under a
single universal reconfigurable platform
– Demonstrate the capabilities and performance of SDR in aerospace
– Address new regulatory initiatives (NextGen)

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1. Introduction
AVIO-505 Vision(1/2)
Currently:
a) 1 or more Hardware units per avionic function
b) Redundancy of Hardware components
c) Racks are far from antennas  long cables power loss

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1. Introduction
AVIO-505 Vision(2/2)
AVIO-505 Vision

Multi-Standard Antenna

Short Cables
Software
Defined
Reconfigurable Software Defined Radio Avionic
SDAR Radio

Fiber Optic Network

SDAR SDAR SDAR SDAR SDAR

SDAR
SDAR SDAR SDAR

Advantages :

a) Less components and cables

b) Hardware resources reallocation
c) Easier maintenance
d) Lower cost
e) Coping with changes

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1. Introduction
Multi-Mode SDAR Architecture

Ant.1 Func. 1

Func. 2
Ant.2
Antenna
RF front
switch Tranceiver FPGA GPP
end
matrix Func. n
Avionics
interface
Ant.m
Cockpit
interface
Antennas RF conversion Rate Applications
Function RF filtering &
switching & & conversion & execution &
amplification
duplexing ADC/DAC BB DSP interfacing

Mode  Set of running functions

1.9"

8.5"

GPP : General Purpose Processor PicoSDR2x2E

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1. Introduction
MM-SDAR Target Characteristics

Phase I : functional validation

1. Hardware/computational resources sharing

2. resource allocation : static and dynamic

3. Using Commercial Out of The Shelf hardware and software

Phase II : path to certification

4. Real-time OS with robust protection vs. applications
concurrency

5. Robust resources partitioning

6. Using design patterns that eases certification

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1. Introduction
Selected Applications
b

a) TMS (Transponder Mode-S) a

• ATC transponder
c
b) ADS-B (Automatic Dependent Surveillance-Broadcast)
• OUT: Broadcasts aircrafts info. (position, velocity, etc.)

• IN: Displays traffic information

c) DME :Distance Measuring Equipment

• Measures Slant distance from a DME beacon

d) Wide Band Radio (WBR) –not standard–

• For In-Flight Communication d

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1. Introduction
MM-SDAR Prototype
Avionic radios applications 1. DME 1
implemented: 2. DME 2
3. TMS
4. ADS-B IN/OUT
5. WBR
MOPS

Performance
Comparison
A) Minimum Operational
Performance Standards
PicoSDR2x2E

Characteristics
• 2/5 applications running simultaneously
• Capability to swap between them dynamically
• Using Open-Source software and OS

B) Commercial counterparts

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Outline

1.Introduction

2.MM-SDAR prototype

3.Performance

4.Conclusion

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2. MM-SDAR prototype
Features
Hardware dependent Hardware Independent

PicoSDR2x2E
Ethernet GNU Radio
RX1 DME1 DME2
TX1
Radio420X Vetex6 Core I7
RX2 ADS-B WBR
TX2 TMS

Tranceiver FPGA GPP

Radio420X Vertex6 Core I7

Direct conversion transceiver High speed DSP Runtime environment

+ Frequency reconfiguration • Impairment compensation • Avionic functions exec.
+ Selectivity • HW/SW interfacing • Avionic interface
- IQ imbalance • Channelization • Cockpit interface
- DC offset • TMS • Control and monitoring

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2. MM-SDAR prototype
Latency and Jitter

PicoSDR2X2E
No jitters
Hundreds of ns Tens of ms Latency depends
latency latency on Design
A B C
Tranceiver FPGA GPP
time
DAC
GNURadio Jitters
FIFO buffer
block block block

block block block ABC

ADC
Ethernet time

Challenge Solution

1. TMS response time = 3 µs 1. Implement TMS on FPGA

2. DME precession is time sensitive 2. Implement a time aware mechanism

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2. MM-SDAR prototype
FPGA: Reception
FPGA
CIC decimator
Power
CR1 ↓R (Ratio = R)
Measurement
TMS
TMS RX
RX Filter CR# Custom register
CR0
DME
Control ↓20 RX Filter
D-AGC

Impairments
Compensation DME
From ↓20 RX Filter
D-AGC
Transceiver
RX
ADS-B Time Domain To
Impairments
↓10 RX Filter
D-AGC
Multiplexer GPP
Compensation
RX SWITCH
WBR
↓10 RX Filter
D-AGC

Time Stamp
<Tag Handler>

Power
CR2
Measurement
Tag

• Input oversampling • Output down-sampling

• RX impairment compensation • Time aware mechanism
• Power measurement (for A-AGC) • TMS :
• Digital AGC (per channel) • Datalink (from Ethernet)

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2. MM-SDAR prototype
GPP: general purpose processor

Remote
control

CR5
CR1 Avionics Avionics
CR6
Radio Interface Interface
A-AGC CR7
Contoller
CR2

Local GUI Master control

From Time Domain

FPGA DeMultipexer
CTR RX CTR RX CTR RX Avionics CTR RX

Time DME1 DME2 ADS-B WBR

stamp
Tag TX

Extractor
Tag

To Time Domain
FPGA Multipexer

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Outline

1.Introduction

2.MM-SDAR prototype

3.Performance

4.Conclusion

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3. Performance
Test setup

WBR Test
Radio
X-Plane

IFR 6000
WBR test unit

MM-SDAR
Prototype
Universal
Glass Cockpit

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3. Performance
Results (1/2) - General

Reconfiguration
1. Avionic radios were validated with IFR 6000
2. Switching did not alter performance
3. Switching downtime 200 ms (max)

DME accuracy

Error did not exceed 0.21 NM (maximum tolerated is 1.7 NM)

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3. Performance
Sensitivity
Sensitivity
MM-SDAR MOPS Commercial
TMS −62 dBm −73 dBm −74 dBm
DME −87 dBm −83 dBm −90 dBm
ADS-B −73 dBm −72 dBm −74 dBm

Min decision FPGA TX Exact TX

time Deadline time
A

B
Radio420 Radio420
FPGA
A (RX) B C (TX) D C

D Allowed
latency

3 µs
0.7 µs  14 samples

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3. Performance
Results (2/2): Sensitivity
WBR ACM WBR throughput
(DBPSK,DQPSK,D8PSK,D16QAM)

WBR sensitivity : −61 dBm

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Outline

1.Introduction

2.MM-SDAR prototype

3.Performance

4.Conclusion

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Conclusion

1. 5 various avionic radios applications were integrated

using SDR techniques.
a) With resources sharing and dynamic reallocation
b) No performance degradation (except 200 ms downtime)
2. The results validate the prototype for next-phase:
a) Designing and building RF front-end and duplexing units
b) Flight test
3. TMS could be improved by changing the hardware
4. DSP techniques can compensate some hardware
imperfections but introduce latency (+ resources)
5. Implementing application on GPP is viable as long as
response time requirements are low

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Future work

Next step
1. Design and build RF front-end and duplexing
units
2. Flight-test using a commercial aircraft
Other perspectives
1. Increase number of running radios
(simultaneously) by using custom hardware
2. Implement a real-time OS (complying with
standards)
a) With resources partitioning
b) Real-time Ethernet

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Questions?

Contact us:

Abdessamad.Amrhar@lassena.etsmtl.ca
Joe.Zambrano@lassena.etsmtl.ca
Eric.hang@lassena.etsmtl.ca
ReneJr.Landry@etsmtl.ca
Claude.Thibeault@etsmtl.ca

Thank you.
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