RUPESH KUMAR CHAUHAN +91-9891206573

rupeshchauhan5381@gmail.com

Objective:
To achieve a challenging career in VLSI industry and work in a globally competitive environment where I could use my
technical skills and get the opportunity for continuous learning.

PROFILE SUMMARY
 Basic understanding of Physical Design Flow (Floor planning, Partitioning, Power planning, Placement, Routing, CTS)
 Basic Knowledge of Static Timing Analysis , Parasitic Extraction, Layout concepts (IR, EM, Antenna Effect, Latch-up)
 Exposure to different input and output files in Physical Design (SDC file, liberty file .lib, SPEF, SDF, LEF/DEF)
 Schematic and Layout design of Standard cell CMOS inverter in Technology Node 180nm.
 Exposure of Cadence Virtuoso (layout, schematic) and Simulation tool (Assura)
 Hands on practice on UNIX commands like cd, ls, grep, find, pwd, mkdir, du, df, cat, diff, chmod, cp, rm
 Automation done using TCL scripting (File handling, procedure, list, open, close, read, write, comparison of data)

Academic Summary
B.Tech (Electronics & Communication) (AKTU) ABES Engineering College, Ghaziabad 73.86% (2014-2018)
Class 12th- CBSE Lucknow Public School, Lucknow 67.60% (2013)
Class 10th- CBSE Avadh Collegiate, Lucknow 8.4 CGPA (2011)

TRAINING

VLSI Expert Pvt Ltd Foundation of VLSI design (April’18 – Till now)
 Digital Electronics Concepts
 Realization of Different Logic Gates using NAND , NOR , MUX & Transmission gates
 Filp-Flops, Encoder-Decoder, Multiplexer, Counters, Finite State Machine
 Layout Concepts
 Antenna Effect , IR Drop, Electro-migration effects and their avoidance
 Latch-up concepts, Short channel effects ,Body Effects, Channel length Modulation
 Schematic design, Simulation, Layout Design, DRC/LVS concepts
 Static Timing Analysis
 Unate & Unateness of circuits, Timing Arc and System Timing Arc
 Timing Paths, Delay concepts (Gate delay & Interconnect delay)
 Concept of Setup/Hold Time, violations & different methods to fix
 Input and output files (SCD, LIB, SDF, Wireload model, Timing Report)
 Difference between pre-layout and post-layout timing analysis
 Advance concepts like OCV, AOCV, CRPR, Crosstalk & Shielding
 Parasitic Extraction
 Resistance & Capacitance concepts, Metal Layer Stack, Different metals type
 Interconnect corners, Manufacturing defects & variations
 Project
 Design of Standard Cell layout of CMOS inverter
 TCL based automation : Automation for QOR (Quality of Result) of Different SPEF file
 Test case development for open source STA tool using OpenTimer
 Overview of different advance concepts like FinFet, DPT
 Several 1 day seminars on PD Flow, Layout Design, Library Characterization.

Tools & Language

 Schematic Design : Virtuoso Schematic Editor
 Simulation : Spectre (Cadence)
 Layout : Virtuoso Layout Editor
 Physical Verification : Cadence Assura (DRC)
  Scripting Language :TCL
 Operating System :Linux (Ubuntu)
 STA (Timing Analysis Tool) : OpenTimer

Projects:
Project 1: Automation for QOR (Quality of Result) of Different SPEF file
Description: Created a program to extract the RC related information from different SPEF files according to their logic gate
and put the values in another separate SPEF file and compare their R and C delay values and store it.
Tools & Language : TCL and UNIX
Learning: Understanding about TCL scripting

Project 2: Design of Standard Cell layout of CMOS inverter

Description: Layout design of standard cell CMOS inverter circuit using 180nm GPDK on Cadence Virtuoso. Length of PMOS
is 1um and Width is 3um and for NMOS, Length is 1um and Width is 2um.Performed Physical Verification DRC and used
guard ring to prevent latch-up. Fingering concept is used to reduce the effective resistance.
Technology used: 180nm (GPDK)
Tools: Virtuoso Schematic Editor, Virtuoso Layout Editor, Spectre (Simulation), Cadence Assura (Physical Verification DRC)
Learning: Understanding about layout design of CMOS standard cell, used Guard ring to prevent latch-up, reduced effective
Resistance by using Fingering concept.

Project 3: Test case development for open source STA tool

Description: We have created few test cases as per the circuit given. Test case contained Verilog netlist file, Constraint file
(SDC) and SPEF file. We used liberty files for 180 nm technology node. We have done pre layout and post layout timing
analysis to understand timing concepts at different stage.
Team Size: 2
Tools & Language: OpenTimer, TCL, UNIX
Learning: Understanding about STA tool and liberty (.lib) files. Basic knowledge of Verilog netlist, good understanding about
SPEF and SDC.

Project 4: Exposure of Different Input /Output files (SDC, SDF, .lib)

Description: Understanding of what information are present in these files.
 Where these files are used in PD flow
 Advantages / Disadvantages of these files
 Which tools uses these files and their constraints
 How to generate SDC file
Learning: Able to know which types of information are given by these files. Different types of constraints present in SDC file.

Other Projects:
 Application Controlled Floor Cleaning Robot
 Fridge Door Alarm Circuit