34

Advanced CMOS ‘System on a Chip’ Technology Platforms -

Status Today & Outlook Tomorrow
Reinhard Mahnkopf
INFINEON TECHNOLOGIES CORPORATION
St.- Martin- Strasse 76
D- 81541 Munich
Germany

Abstract
During the last few years there has been an
increasing interest of the product community
to integrate more different features and
functions on just one chip with minimum
process complexity and yield impact. This
‘system on a chip’ integration is definitely a
challenge for process technology because all
the parts have to be combined in a modular
way allowing the designers to re-use the
same IP in various products. A technology
platform allows ‘system on a chip integration’
for a broad spectrum of products, but key is
to take advantage of the potential benefits of
SOC with respect to performance, power and
cost. This requires system know how as well
as leading edge technology.
Technology Platform
Today system on a chip integration of Digital,
Mixed SignaVRF, embedded SRAW DRAM /
NVM, BiCMOS and even MEMS has been
demonstrated already [l], [2], [3]. There are a
lot of chances and opportunities, economical-
ly and technically. The availability of eDRAM
& eNVM functionality offers the product
community the unique chance to address
new segments and realize new products by
taking advantage of having these features on
chip with regard to performance and power.
The bases for a SoC technology platform is a
generic digital CMOS process. Additional
process modules are usually added in a
modular manner to provide the required
functionality. In today’s state of the art
technology platforms a lot of different
technology options are already available. For
example, Infineon’s 0.18pm [4], 0.13pm [5] &
0.10pm platforms, called C10, C l l & C12 are
offering the following technology options
which are kind of representative for the
industry - only the technical implementation
often differs from company to company:
digital, mixed signal/RF, embedded SRAM /
DRAM / NVM (see fig.1).
A rough estimation of the additional process
complexity which comes with SOC is
indicated in tab.1 taking mask count as a
measure. The exact numbers might differ
depending on the technology features
included, the specific requirements on these
features and the technical realization, but a
certain range can be given: A complete SOC
integration including all features mentioned
above is achievable with roughly 2x process
complexity. Yield deterioration and test cost
increase not taken into account.
Functionality Mask Adder
Digital (incl. eSRAM) 100 70
Mixed Signal / RF + 15-25 ?
‘
o
eDRAM + 25 - 35 Yo
eNVM +40-50%

compared to pure digital w/ 4 levels of metal

Digital

Tab.1 Process Complexity Adders for ‘System on

a Chip’ options

Fig.2 shows the modularity of the SOC

Fig.1 SoC Platform Concept at lnfineon technology concept used by lnfineon for the

0-7803-6520-8/01/$10.00 Q 2001 IEEE.

 35

last technology nodes in more detail (eNVM

not shown here). The process modules for nFETl nFET1 nFET/

11I11
the different features can be added or left out 1.8’4 1.2V 1.5V 1.OV 1.2’4
without effecting each other. The concept will 5w1210 375/150 600/255
be described in more detail later on. 15/15 so/% 8om onered offered
28.5 28 20

Mixed Signal CMOS Digital eDRAM

Mx)/zM)
;1 ;:,;
5001210 7301335 500/EU
1.5,/,l.5
700/3GQ
2.37

7601320 5601240 820/385 655/295 8901410

2001100 6/6 10/10 50/50 Bole0
15.5 11.5
IhlogW&*Denca ]-[#I
~ p ~ A n a y p o h l P I
m 9

p , ll h y D e v l c e S / D I
ISBideWARessIor] ) [ ~ ] t I S a l r i d e W A h y 1 Tab.3 Device ‘menu’ for the digital processes
~MIMCAPAC~~~~W I#IMetslulapon]
The leakage current specs have to be relaxed
Fig9 Infineon’s modular SOC technology concept to insure the typically required performance
with additional mixed signal & eDRAM process increase of 20% per generation. This will
modules become even more a challenge for the
.igital
. Process upcoming technology nodes with supply
voltages below 1V.

The core of each SOC platform is a generic

digital process. Table 2 shows an overview of 40.0
the digital platform processes of lnfineon with 35.0
the relevant key figures: 230.0
\

Feature I
I
c10 I
I
c11 I
I
c12 -#5,020,o
&I 150
Supply Voltage / V
8 10.0
5.0
0.0
c10 c11 c12

Tab.2 Infineon’s Digital Platform Technologies w/ Technology Generation

key figures
Fig.3 Gate delay vs. technology generation for
different off current specs
The digital processes already offer the choice
between different transistor options to cover
all needs from ultra low power to highest In addition the generic platform processes
offer DG (Dual Gate oxide) devices with a
performance for ASIC & FP applications. An thicker gate dielectric to satisfy the I/O
overview of the transistor key data for requirements. Often this thick GOX is used
Infineon’s platform technologies is given in
for mixed signal transistors as well. The
tab.3 with typical gate delay data for a
scaling of the most important ground rules
ringoszillator with FI = FO = 1. Besides the can be seen in table 4 exhibiting the 2x in
actual device data additional curves for
density per generation. Leading edge
constant off currents of 10pNpm , I n N p n lithography and masks and sophisticated data
and 100nNFm are plotted in fig.3. engineering is needed: technical as well as
economical problems have to be resolved to
36
continue this trend for the next technology
nodes.
Groundrule I c10 I c11
I I
Tab.4 Groundrule scaling over generations
Fig.4 shows top views of the 6T SRAM cells
for C10 and C11 with the isolation and gate
level patterns. A lot of process optimization
and yield learning was needed, but these
cells can now be implemented without
increasing process complexity. In addition
these technologies offer a 6T dense cell
version by aggressively tightening the ground
rules. Again, 2x boost in density per
generation is achieved as shown in Fig.5.
Fig.4 The 6 Transistor - SRAM cells for C10 &
C11 - SEM top views (nearly on scale)
Cl0 c11 c12
TechnologyGeneration
Fig.5 SRAM cell size vs. technology generation
solid line: standard cells; data points: dense cells
For wiring the lnfineon technologies are using
copper -since CIO- for up to 10 levels (for
C12) for maximum backend performance
I
while the last levels can be chosen to be fine
or relaxed pitch. The copper process
promises an up to 40% reduction in wiring
I c12
resistance compared to an aluminum
I
technology of equivalent dimensions.
Integration of a true low k material (starting
with C11) resulted in superior interconnect
performance (30% performance advantage
compared to oxide based BEOL solutions) at
aggressive pitches. Wirebond or flipchip
packaging can be used in these technologies
for off-chip connections.
Fig.6 Cu wiring of a DSP core in Infineon’s C10
Technology ( 0 . 1 8 ~ )
Mixed signal / RF:
Especially for products in the wireless market
the availability of mixed signal & RF features
becomes increasingly important. Usually
mixed signal functionality includes analog
transistors and passive components, like high
precision resistors, high linearity metal-
insulator-metal capacitors (MIMCAP) and
inductors, intrinsic inductors with standard
metallization or high Q value inductors with
thick wire metallization [6].Different materials
are being used for the MIM capacitors as
dielectric like oxides, nitrides or high k
materials already [7].A salicide blocking
mask is used to realize non salicided poly
and diffusion resistors; a whole range of
sheet rhos can be offered by combining
different device implants. The analog
transistors are designed for low output
conductance and low substrate bias
sensitivity with a modified well construction.
The matching behavior of these devices is of

major importance. With reduced supply
voltage SOC integration of mixed signal
becomes more and more an issue, from
technology and circuit design point of view.
Fig.7 Highly linear Metal- Isolator- Metal-
Capacitor (MIMCAP) in Cu Dual Damascene
Metallization
Advanced CMOS becomes more and more
interesting for RF applications, with reduced
gate length the RF capability of the silicon
devices is entering a regime which was up to
now entirely dominated by lllN
semiconductors. The cutoff frequencies of the
transistors start to exceed 100 GHz (fig.8).
These numbers have been achieved by just
optimizing the transistor layout, without any
additional technology measures. Substrate
loss and cross talk are becoming more and
more an issue in this regime.
10.0
t
I
c10 c11 c12
Technology Generation
Figd Maximum cutoff frequency
,,f vs.
technology generation
37
ed DRAM:
For some products it is crucial to have logic
and embedded DRAM functionality on one
chip. Typical areas of application are graphics,
disk drives, digital video and networking.
Different concepts for eDRAM technologies
have been proposed, integration of high
performance devices into commodity DRAM
[8], integration of a DRAM cell into state-of-
the-art CMOS logic [9], with different storage
cells. The technology plalform concept for
SOC integration of eDRAM functionality
within lnfineon relies -as can be seen already
in fig.2- on a trench based cell concept. A
trench based cell is much more favorable for
SOC than a stacked cell concept. The heat
cycle of the storage capacitor has been
completed before isolation and before the
formation of the high performance logic
devices without complex topology in mid of
line. The borderless contact usually used in
commodity DRAM is omitted to avoid the
negative impact of the DRAM gate stack on
the high speed logic channel length control. A
SEM cross section of the cell in 0.18pm
technology is shown in fig.9. A comparison of
the DRAM cell areas achieved with this
concept and the SRAM cell sizes of the same
technology node exhibit a factor of 8 in
between (fig.10).
hW* e
'
&-
&
UnnUlCldMJvnstian
Fig.9 Cross section of the eDRAM' cell in'
Infineon's C10- 0.18pm- SoC platform
38

concepts are known with their respective pros

and cons [lo]. Within lnfineon the stacked
gate flash concept is used for some
technology generations already. HV devices
and the stacked cell itself need to be
integrated which requires a significant
amount of additional processing. The stacked
gate cell concept uses uniform channel
0,lW I
programming. Fig.12 shows a SEM cross
c10 c11 c12 section after the gate stack etch with poly2 I
Technology Generation dielectric / poly1:

Fig.10 eDRAM & SRAM cell sizes vs. technology

generation

Some products can benefit significantly from

having logic and RAMs on the same chip;
performance requirements and / or cost
aspects determine if an eDRAM- or an
eSRAM integration is the preferable concept.
For non-performance critical circuits the cost
tradeoff between process complexity and cell Fig.12 SEM cross section of the stacked cell after
size is dependent on the ratio between logic poly etch (C10 - 0 . 1 8 technology)
~
& memory density (fig.11).
#of Logic Gates
There are other technology features which
can be integrated on chip as well as part of
SoC like BiCMOS [ l l ] or MEMS, but
sometimes a multi chip module (MCM) or
‘sytem in a package’ (SIP) is the more cost
effective solution here.

Amount of Memory
Fig.11 Areas of application eDWM vs. eSWM
Fmbedded NVM;
Embedded non- volatile memory functionality
is needed whenever non- volatile on chip
data or program storage is required. Areas of
application are in consumer, computer
peripherals, automotive & industrial. For NVM
integration several different technologies and
Future Trends
First announcements of silicon manufacturers
are indicating that the ‘system-on-a-chip’
trend described above will continue at least
for the next one or two technology
generations (0.07pm and 0.05pm) even
though a modular and cost effective
integration of all different functions on just
one chip becomes increasingly difficult. But
one innovation which attracted more and
more attention in the last years could
influence this trend: Sol. While SO1 is clearly
advantageous for digital applications, there
are still some uncertainties about the
suitability of this material for mixed signal
applications and RAMs. Some papers have
 39

been published on this topic already
demonstrating feasibility e.g. for mixed
signal/RF [12] and for eDRAM [13],but the
use of SO1 could shift the optimum design
point for SoC significantly.
From todays point of view there seems to be
a close link between the future of planar
CMOS and SoC integration: The SoC
platform concept will continue as long as we
continue scaling planar CMOS successfully.
Acknowledgments
The author would like to thank the LEAD team
(INFINEON, IBM, UMC) in East Fishkill, NY, USA
for their support and Josef Winnerl, lnfineon
Munich for his helpful suggestions.
Chip)‘; 1999 Symposium .on VLSl Technology,
(1999)
-
[lo] G. Tempel: ‘System-on-a-Chip Technology
Embedded Non Volatile Memory‘ ; IEDM Short
Course; December 1997
[ll] M.S. Carroll, et al.: ‘A 0.16um Modular
-
BiCMOS (COM2 BiCMOS) Technology for RF
Communication ICs‘; IEDM Tech. Digest (1999)
[12] S. Maeda, et al.: ‘Impact of 0.18um SO1
CMOS Technology using Hybrid Trench Isolation
with High Resistivity Substrate on Embedded
RF/Analog Applications’; 2000 Symposium on
VLSl Technology, (2000)
[13] R. Hannon, et al.: ‘0.25um Merged Bulk
DRAM and SO1 Logic using Patterned Sol’;2000
Symposium on VLSl Technology, (2000)

References
[l]F. Ootsuka, et al.: ‘A Highly Dense, High-
Performance 130nm node CMOS Technology for
Large Scale System-on-a-Chip Applications’,
IEDMTech. Digest (2000)
[2] A.H. Perera, et al.: ‘A versatile 0.13um CMOS
Platform Technology supporting High
Performance and Low Power Applications‘, IEDM
Tech. Digest (2000)
[3] M. Yoshida, et al.: ‘An Embedded 0.405um2
Stacked DRAM Technology Integrated with high-
performance 0.2um CMOS Logic and 6-level
metalization‘, IEDM Tech. Digest (1999)
[4] R. Mahnkopf, et al.: ‘System on a Chip’
Technology Platform for 0.18p-i Digital, Mixed
Signal & eDRAM Applications, IEDM Tech. Digest
(1 999)
[5] T. Schiml, et al.: ‘A 0.13um CMOS Platform
with Cu/low-k Interconnects for System on a Chip
Applications‘, 2001 Symposium on VLSl
Technology, (2001)
[6] M.R. Frei, et al.: ‘Integration of high4
inductors in a latch-up resistant CMOS
Technology’; IEDM Tech. Digest (1999)
[7] K. Miyashita, et al.: ‘A High Performance 100
nm Generation SOC Technology (CMOS IV) for
High Density Embedded and Mixed Signal LSls’;
2001 Symposium on VLSl Technology, (2001)
[8] H. Wurzer, et al.: ‘A 0.17um Embedded DRAM
Technology with 0.23um2 cell size and advanced
CMOS logic’; 2000 Symposium on VLSl
Technology, (2000)
[9] K. Kokubun, et al.: ‘New Embedded DRAM
Technology using Self-aligned Salicide Block
(SSB) Process for 0.18um SOC (System on a