Acer 5560

A B C D E
SYSTEM DC/DC
Garda-D Block Diagram

TPS51120 40
Project code: 91.4A901.001 INPUTS OUTPUTS
PCB P/N : 55.4A901.XXX
(Discrete) REVISION : 05217-1 5V_S5
DCBATOUT
Mobile CPU
3D3V_S5
-1M-0111
4 CLK GEN. (Hannstar, ACCL) 4
IDT CV125PA
G792
(ICS 954206) 3
Yonah 478 19
PCB STACKUP SYSTEM DC/DC
1.83G/2G/2.16G TPS51124 41
4, 5 TOP INPUTS OUTPUTS
TVO
14
HOST BUS 400/533/667MHz GND
DCBATOUT
1D05V_S0
DDR2 LVDS 14"WSXGA+ 1D8V_S3

S
533/667MHz LCD 13
TPS51100
533 MHz RGB CRT
S 43
Calistoga
11,12 PCI Express x16 ATI CRT VCC 1D8V_S3 DDR_VREF_S0
14
M54P / M52P
DDR2 533/667MHz
Ver.:A3 :71.945PM.A0U / QK58
M56 Ver.: B24
M52 Ver.: A12 45,46,47,48,49
S
GND
APL5332KAC 43
533 MHz 6,7,8,9,10
M54 Ver.: A12
VRAM x4
3D3V_S0 2D5V_S0
11,12 BOTTOM
3 128/256M
50,51 3
DMI I/F 100MHz APL5912-U 43
Line In PCMCIA I/F PCMCIA
1D8V_S3 1D5V_S0
29
Codec TI SLOT
AZALIA PCI 7412 PWR SW Support
29 ALC883 TSP2220A TypeII MAXIM CHARGER
27
28 27 MAX8725 42
MIC In CARDBUS
PCI BUS 1394 INPUTS OUTPUTS
CardReader 1394
26 MS/MS Pro/xD/ CHG_PWR
CONN
INT.MIC 24,25 MMC/SD/SDIO DCBATOUT
18V 4.0A
6 in 1 UP+5V
Line Out
(SPDIF)
ICH7M Mini-PCI
802.11A/B/G 30
26
5V 100mA
Ver. : B0, 71.ICH7M.A0U / QK65
29 OP AMP
G1421B 29
KI.80101.017 LAN CPU DC/DC
ISL6262
10/100 TXFM RJ45 BCM5787MKFBG-A1 38,39
2 23 23 BCM5789KFBG-C1 2
BCM4401-E 22 BCM4401EKFBG-B0 INPUTS OUTPUTS
29 PCIEx1 Mini Card*1
802.11A/B/G 26 DCBATOUT
VCC_CORE_S0
Giga LAN 0~1.3V
INT.SPKR BCM5789/5787M 35 44A
SPI I/F BIOS
SST25LF080A
MODEM LPC BUS
34 ATI M54 DC/DC
RJ11 MDC Card 15,16,17,18 FAN5234 52
21
INPUTS OUTPUTS
SATA
PATA
PCI Express
SIO KBC
Renesas
LPC DCBATOUT VGA_CORE_S0
New card30 USB NS87381 RE144B DEBUG
3 PORT 32 31 CONN.
34 APL5331KAC 43
21
1D8V_S0 1D2V_S0
21
1 PWR SW MINI USB FIR 32 Touch INT. <Variant Name>
1
TPS223130 HDD 20 CDROM
18 Blue-tooth Pad 33 KB 33
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
BLOCK DIAGRAM
Size Document Number Rev
A3
AG1 -1M
Date: Wednesday, January 11, 2006 Sheet 1 of 53
A B C D E
ICH7M Integrated Pull-up 954305D 27Mhz/LCDCLK Spread Calistoga Strapping Signals and
and Pull-down Resistors ICH7-M EDS 17837 1.5V1
and Frequency Selection Table Configuration EDS 17050 0.71
page 7
SS3 SS2 SS1 SS0
Byte9 bit6 bit5 bit4 Spread Amount% page 3 Pin Name Strap Description Configuration
EE_DIN, EE_DOUT, GNT[3:0], GPIO[25], bit 7 CFG[2:0] FSB Frequency Select
GNT[4]#/GPIO48, GNT[5]#/GPO17, PME#, 0 0 0 0 -0.50 Down 001 = FSB533
ICH7 internal 20K pull-ups 011 = FSB667
LAD[3:0]#/FHW[3:0]#, LAN_RXD[2:0] 0 0 0 1 -1.00 Down others = Reserved
4 LDRQ[0], LDRQ[1]/GPIO[41], 0 0 1 0 -1.50 Down CFG[4:3] Reserved 4

PWRBTN#, TP[3] 0 0 1 1 -2.00 Down CFG5 DMI x2 Select 0 = DMI x2
1 = DMI x4 (Default)
0 1 0 0 -0.75 Down CFG6 Reserved
DD[7], DDREQ ICH7 internal 11.5K pull-downs
0 1 0 1 -1.25 Down CFG7 0 = Reserved
CPU Strap 1 =Mobile CPU(Default)
ACZ_BIT_CLK, ACZ_RST#, ACZ_SDIN[2:0], ICH7 internal 20K pull-downs 0 1 1 0 -1.75 Down
Reserved
ACZ_SDOUT, ACZ_SYNC, DPRSLPVR/GPIO16, 0 1 1 1 -2.25 Down CFG8
EE_CS,SPI_ARB, SPI_CLK, SPKR, 1 0 0 0 +-0.25 Center 0 = Reverse Lanes,15->0,14->1 ect..
CFG9 PCI Express Graphics 1= Normal operation(Default):Lane
1 0 0 1 +-0.5 Center Lane Reversal Numbered in order
USB[7:0][P,N] ICH7 internal 15K pull-downs
1 0 1 0 +-0.75 Center
CFG[11:10] Reserved
SATALED# ICH7 internal 15K pull-up 1 0 1 1 +-1.0 Center
XOR/ALL Z test 00 = Reserved
1 1 0 0 +-0.25 Center CFG[13:12] straps 01 = XOR mode enabled
LAN_CLK ICH7 internal 100K pull-down 10 = All Z mode enabled
1 1 0 1 +-0.5 Center 11 = Normal Operation
(Default)
1 1 1 0 +-0.75 Center
CFG[15:14] Reserved Reserved
ICH7M IDE Integrated Series 1 1 1 1 +-1.0 Center
CFG16 FSB Dynamic ODT 0 = Dynamic ODT Disabled
3 Termination Resistors Global R-comp Disable

1 = Dynamic ODT Enabled (Default)
0 = All R-comp Disable 3
CFG17 1 = Normal Operation (Default)
DD[15:0], DIOW#, DIOR#, DREQ,
approximately 33 ohm
PCI Routing page 16
CFG18
(All R-comps)
VCC Select 0 = 1.05V (Default)
DDACK#, IORDY, DA[2:0], DCS1#, 1 = 1.5V
DCS3#, IDEIRQ
IDSEL INT -> PIRQ REQ/GNT CFG19 DMI Lane Reversal 0 = Normal operation (Default):lane
A->G, B->B, Numbered in order
1 =Reverse Lane,4->0,3->1 ect...
7412 22 C->F, D->G 0
ICH7M Functional Strap Definitions A/C -> E CFG20 SDVO/PCIE
0 = Only SDVO or PCIE x1 is
page 16
MiniPCI 21 B/D -> E 1 Concurrent
operational (Default)
1 =SDVO and PCIE x1 are operating
simultaneously via the PEG port
Signal Usage/When Sampled Comment LAN 23 A -> H 2 SDVOCRTL SDVO Present 0 = No SDVO Card present
ACZ_SDOUT XOR Chain Entrance/ Allows entrance to XOR Chain testing when TP3 _DATA (Default)
PCIE Port Config bit1, pulled low.When TP3 not pulled low at rising edge 1= SDVO Card present
Rising Edge of PWROK of PWROK,sets bit1 of RPC.PC(Config Registers:
offset 224h) NOTE: All strap signals are sampled with respect to the leading
edge of the Calistoga GMCH PWORK in signal.
ACZ_SYNC PCIE bit0, Sets bit0 of RPC.PC(Config Registers:Offset 224h)
Rising Edge of PWROK.
EE_CS Reserved This signal should not be pull high. History
EE_DOUT Reserved This signal should not be pull low.
2 GNT2# Reserved This signal should not be pull low. 2
Top-Block Sampled low:Top-Block Swap mode(inverts A16 for
GNT3# Swap Override. all cycles targeting FWH BIOS space).
Rising Edge of PWROK. Note: Software will not be able to clear the
Top-Swap bit until the system is rebooted
without GNT3# being pulled down.
GNT5#/ Boot BIOS Destination Controllable via Boot BIOS Destination bit
GPIO17#, Selection. (Config Registers:Offset 3410h:bit 11:10).
GNT4#/ Rising Edge of PWROK. GNT5# is MSB, 01-SPI, 10-PCI, 11-LPC.
GPIO48
DPRSLPVR Reserved This signal should not be pull high.

GPIO25 Reserved.
Rising Edge of RSMRST#. This signal should not be pull low.
INTVRMEN Integrated VccSus1_05 Enables integrated VccSus1_05 VRM when
VRM Enable/Disable. sampled high
Always sampled.
LINKALERT# Reserved Requires an external pull-up resistor.
REQ[4:1]# XOR Chain Selection. <Variant Name>
Rising Edge of PWROK. TBD, Chapter 8.
1 1
SATALED# Reserved This signal should not be pull low.
Wistron Corporation
SPKR No Reboot. If sampled high, the system is strapped to the 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Rising Edge of PWROK. "No Reboot" mode(ICH7 will disable the TCO Timer Taipei Hsien 221, Taiwan, R.O.C.
system reboot feature). The status is readable
Title
via the NO REBOOT bit.
Reference
TP3 XOR Chain Entrance. This signal should not be pull low unless using Size Document Number Rev
A3
Rising Edge of PWROK. XOR Chain testing. AG1 SD
Date: Tuesday, January 10, 2006 Sheet 2 of 53
A B C D E
3D3V_S0
3D3V_S0 3D3V_S0
2 R158 1 3D3V_CLKPLL_S0 2 R213 1 3D3V_48MPWR_S0 3D3V_CLKGEN_S0 2 R155 1

0R0603-PAD 0R0603-PAD 0R0603-PAD
1
1
4 4
C228 C229 C301 C226 C257 C254 C230 C255 C303 C258 C508
SCD1U16V2ZY-2GP SC1U6D3V2ZY-GP SC1U6D3V2ZY-GP SC4D7U10V5ZY-3GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP
2
2
3D3V_S0
U24
1
RN35 1 4 SRN33J-5-GP-U CLK_MCH_3GPLL 7

R598 2 3 CLK_MCH_3GPLL# 7
10KR2J-3-GP R173 1 2 33R2J-2-GP PCLKCLK0 56 17
31 PCLK_KBC PCI0 LVDS
22 PCLK_LAN R176 1 2 33R2J-2-GP PCLKCLK1 3 18 RN21 1 4 SRN33J-5-GP-U CLK_PCIE_ICH 16
R179 22R2J-2-GP PCLKCLK2 PCI1 LVDS#
25 PCLK_PCM 2 1 4 PCI2 2 3 CLK_PCIE_ICH# 16
2
32 PCLK_SIO R209 1 2 33R2J-2-GP PCLKCLK3 5 19 CLK_MCH_3GPLL_1

SS_SEL R214 22R2J-2-GP PCI3 SRC1 CLK_MCH_3GPLL_1# RN40 SRN33J-5-GP-U
34 PCLK_FWH 2 1 SRC1# 20 2 3 CLK_PCIE_LAN 35
H/L: 100/96MHz 30 PCLK_MINI R210 1 MINI 2 33R2J-2-GP SS_SEL 9 22 CLK_PCIE_ICH_1 1 GIGA 4 CLK_PCIE_LAN# 35
PCIF1/SEL100/96# SRC2
1
16 CLK_ICHPCI R211 1 2 33R2J-2-GP ITP_EN 8 23 CLK_PCIE_ICH_1#

R597 PCIF0/ITP_EN SRC2# CLK_PCIE_LAN_1 RN25 SRN33J-5-GP-U
1 2 24 2 3 CLK_PCIE_SATA 15
10KR2J-3-GP
16 PM_STPPCI# R174 10KR2J-3-GP 55
SRC3
25 CLK_PCIE_LAN_1# 1 SATA 4 CLK_PCIE_SATA# 15
PCI_STOP# SRC3# CLK_PCIE_SATA_1
DY H/L : CPU_ITP/SRC7 SRC4 26
27 CLK_PCIE_SATA_1# RN29 1 4 SRN33J-5-GP-U CLK_PCIE_NEW 30
SRC4#
2
PCLK_FWH & PCLK_PCM 11,18 SMBC_ICH 46 31 CLK_PCIE_NEW_1 2 NEW 3 CLK_PCIE_NEW# 30

3 SCL SRC5 CLK_PCIE_NEW_1# 3
47 30
need equal length 11,18 SMBD_ICH SDA SRC5#
33 CLK_PCIE_MINI1_1 RN27 1 4 SRN33J-5-GP-U CLK_PCIE_MINI1 26
SRC6 CLK_PCIE_MINI1_1#
SRC6# 32 2 MINIC 3 CLK_PCIE_MINI1# 26
14
15
DOT96
36 CLK_PCIE_PEG_1 RN28 1
Dummy when use UMA
4 SRN33J-5-GP-U
DOT96# CPU2_ITP/SRC7 CLK_PCIE_PEG 45
35 CLK_PCIE_PEG_1# 2 VGA 3 CLK_PCIE_PEG# 45
C256 CPU2_ITP#/SRC7#
1 2 GEN_XTAL_IN 50 44 CLK_CPU_BCLK_1 RN17 3 2 SRN33J-5-GP-U CLK_CPU_BCLK 4
GEN_XTAL_OUT_R GEN_XTAL_OUT 49 XTAL_IN CPU0 CLK_CPU_BCLK_1#
1 2 XTAL_OUT CPU0# 43 4 1 CLK_CPU_BCLK# 4
1
SC20P50V2JN-1GP X2 R154 470R2J-2-GP 41

R177 1 CPU1
32 CLK14_SIO 2 22R2J-2-GP CPU1# 40 CLK_MCH_BCLK_1 RN19 3 2 SRN33J-5-GP-U CLK_MCH_BCLK 6
X-14D31818M-31GP16 CLK_ICH14 R181 1 2 22R2J-2-GP GEN_REF 52 CLK_MCH_BCLK_1# 4 1 CLK_MCH_BCLK# 6
C225 82.30005.831 475R2F-L1-GP 2 R157 1GEN_IREF 39 REF
IREF CPU_STOP# 54 PM_STPCPU# 16
2
1 2 53 CPU_SEL2 CPU_SEL2 4,7

FSC/TEST_SEL CPU_SEL1
FSB/TEST_MODE 16 CPU_SEL1 4,7
SC20P50V2JN-1GP 3D3V_S0 10 12 CLK48 22R2J-2-GP 1 R601 2
VTT_PWRGD#/PD USB48/FSA CLK48_ICH 16
22R2J-2-GP 1 R600 2 CLK48_CARDBUS 25
1 R602 2 CPU_SEL0 4,7
1
2 34 3D3V_CLKGEN_S0 2K2R2J-2-GP
VSS_PCI VDD_SRC
6 VSS_PCI VDD_SRC 21
R212 DY
10KR2J-3-GP 51 7
VSS_REF VDD_PCI
45 VSS_CPU VDD_PCI 1
2
38 CLK_EN# 38 VSSA
13 VSS48 VDD_REF 48
29 VSS_SRC VDD_CPU 42
37 3D3V_CLKPLL_S0
VDDA 3D3V_48MPWR_S0
VDD48 11
VDD_SRC 28
2 2
IDTCV125PAG-GP 71.00125.A0W
EMI capacitor
CLK_PCIE_MINI1 1 2 DY
EC20 SC22P50V2JN-4GP
CLK_PCIE_MINI1# 1 2 DY
PCLK_MINI 1 2 DY
RN34
CLK_PCIE_MINI1 1 4
CLK_PCIE_MINI1# 2 MINIC 3
SRN49D9F-GP CLK_ICH14 1 2 DY
RN42 RN18 EC17 SC22P50V2JN-4GP
CLK_PCIE_LAN 2 3 CLK_CPU_BCLK 1 4 CLK_ICHPCI 1 2 DY
CLK_PCIE_LAN# 1 GIGA 4 CLK_CPU_BCLK# 2 3 EC21 SC22P50V2JN-4GP
SRN49D9F-GP SRN49D9F-GP CLK48_ICH 1 2 DY
RN32 RN16 EC34 SC22P50V2JN-4GP
CLK_PCIE_SATA 2 3 CLK_MCH_BCLK 1 4
CLK_PCIE_SATA# 1 SATA 4 CLK_MCH_BCLK# 2 3
SRN49D9F-GP SRN49D9F-GP <Variant Name>
1 1
SEL2 SEL1 SEL0 CPU FSB RN20 RN31
CLK_PCIE_ICH 1 4 CLK_PCIE_PEG 1 4
0
0
0
0
0
1
266M
133M
X
533M
CLK_PCIE_ICH# 2
SRN49D9F-GP
3 CLK_PCIE_PEG# 2 VGA
SRN49D9F-GP
3 Wistron Corporation
0 1 0 200M X RN30 RN36 Taipei Hsien 221, Taiwan, R.O.C.
0 1 1 166M 667M CLK_PCIE_NEW 1 4 CLK_MCH_3GPLL 1 4
1 0 0 333M X CLK_PCIE_NEW# 2 NEW 3 CLK_MCH_3GPLL# 2 3 Title
1 0 1 100M X SRN49D9F-GP SRN49D9F-GP
1 1 0 400M X Clock Generator IDT CVT125PAG
1 1 1 Reserved X Size Document Number Rev
A3
AG1 -1
A B C D E
A B C D E
TP27 TPAD30
U72A 1D05V_S0
H_A#3 J4 H1 H_ADS# 6
6 H_A#[31..3] A[3]# ADS#
4 H_A#4 L4 E2 H_BNR# 6 4
H_A#5 A[4]# BNR#
M3 A[5]# BPRI# G5 H_BPRI# 6
1
H_A#6 K5
H_A#7 A[6]# R613
ADDR GROUP 0
M1 A[7]# DEFER# H5 H_DEFER# 6
H_A#8 N2 F21 56R2J-4-GP
A[8]# DRDY# H_DRDY# 6
H_A#9 J1 E1 H_DBSY# 6
H_A#10 A[9]# DBSY#
N3 A[10]# H_DINV#[3..0] 6
2
H_A#11 P5 F1 Place testpoint on
A[11]# BR0# H_BREQ#0 6 H_DSTBN#[3..0] 6
H_A#12 P2 H_IERR# with a GND
A[12]# H_DSTBP#[3..0] 6
H_A#13 H_IERR# 0.1" away
CONTROL
L1 A[13]# IERR# D20
H_A#14 P4 B3 H_INIT# 15
H_A#15 A[14]# INIT#
P1 A[15]#
H_A#16 R1 H4 H_LOCK# 6 H_D#[63..0] 6
A[16]# LOCK# U72B
6 H_ADSTB#0 L2 ADSTB[0]# H_CPURST# 6
B1 H_RS#[2..0] 6 H_D#0 E22 AA23 H_D#32
6 H_REQ#[4..0] RESET# D[0]# D[32]#
H_REQ#0 K3 F3 H_RS#0 H_D#1 F24 AB24 H_D#33
H_REQ#1 H2 REQ[0]# RS[0]# H_RS#1 H_D#2 D[1]# D[33]# H_D#34
REQ[1]# RS[1]# F4 E26 D[2]# D[34]# V24
H_REQ#2 K2 G3 H_RS#2 H_D#3 H22 V26 H_D#35
H_REQ#3 J3 REQ[2]# RS[2]# H_D#4 D[3]# D[35]# H_D#36
REQ[3]# TRDY# G2 H_TRDY# 6 F23 D[4]# D[36]# W25
H_REQ#4 L5 H_THERMDA H_D#5 H_D#37
DATA GRP 0
G25 U23
DATA GRP 2
REQ[4]# H_D#6 D[5]# D[37]# H_D#38
HIT# G6 H_HIT# 6 E25 D[6]# D[38]# U25
1
H_A#17 Y2 E4 H_HITM# 6 H_D#7 E23 U22 H_D#39
H_A#18 A[17]# HITM# C675 H_D#8 D[7]# D[39]# H_D#40
U5 A[18]# K24 D[8]# D[40]# AB25
H_A#19 R3 AD4 XDP_BPM#0 TP41 TPAD30 SC2200P50V2KX-2GP H_D#9 G24 W22 H_D#41
A[19]# BPM[0]# D[9]# D[41]#
2
H_A#20 XDP_BPM#1 TP44 TPAD30 H_THERMDC H_D#10 H_D#42
ADDR GROUP 1
W6 A[20]# BPM[1]# AD3 J24 D[10]# D[42]# Y23
H_A#21 U4 AD1 XDP_BPM#2 TP46 TPAD30 H_D#11 J23 AA26 H_D#43
H_A#22 A[21]# BPM[2]# XDP_BPM#3 TP40 TPAD30 H_D#12 D[11]# D[43]# H_D#44
Y5 A[22]# BPM[3]# AC4 H26 D[12]# D[44]# Y26
XDP/ITP SIGNALS
H_A#23 U2 AC2 XDP_BPM#4 TP43 TPAD30 H_D#13 F26 Y22 H_D#45
H_A#24 A[23]# PRDY# XDP_BPM#5 TP47 TPAD30 1D05V_S0 H_D#14 D[13]# D[45]# H_D#46
R4 A[24]# PREQ# AC1 K22 D[14]# D[46]# AC26
3 H_A#25 T5 AC5 XDP_TCK TP39 TPAD30 H_D#15 H25 AA24 H_D#47 3
A[25]# TCK D[15]# D[47]#
2
H_A#26 T3 AA6 XDP_TDI TP30 TPAD30 H23 W24 H_DSTBN#2 6
A[26]# TDI 6 H_DSTBN#0 DSTBN[0]# DSTBN[2]#
H_A#27 W3 AB3 XDP_TDO TP33 TPAD30 R595 G22 Y25 H_DSTBP#2 6
A[27]# TDO 6 H_DSTBP#0 DSTBP[0]# DSTBP[2]#
H_A#28 W5 AB5 XDP_TMS TP29 TPAD30 56R2J-4-GP J26 V23 H_DINV#2 6
A[28]# TMS 6 H_DINV#0 DINV[0]# DINV[2]#
H_A#29 Y4 AB6 XDP_TRST# TP42 TPAD30
H_A#30 A[29]# TRST# XDP_DBRESET# TP18 TPAD30
W2 A[30]# DBR# C20
1
H_A#31 Y1 H_D#16 N22 AC22 H_D#48
A[31]# R596 2 H_D#17 D[16]# D[48]# H_D#49
6 H_ADSTB#1 V4 ADSTB[1]# PROCHOT# D21 1 CPU_PROCHOT# 38 K25 D[17]# D[49]# AC23
THERM
A24 0R2J-2-GP H_D#18 P26 AB22 H_D#50

THERMDA H_THERMDA 19 D[18]# D[50]#
15 H_A20M# A6 A25 H_THERMDC 19 DY H_D#19 R23 AA21 H_D#51
A20M# THERMDC H_D#20 D[19]# D[51]# H_D#52
15 H_FERR# A5 FERR# PM_THRMTRIP-A# 7 L25 D[20]# D[52]# AB21
15 H_IGNNE# C4 C7 H_D#21 L22 AC25 H_D#53
IGNNE# THERMTRIP# D[21]# D[53]#
DATA GRP 1
DATA GRP 3
1 R605 2 PM_THRMTRIP-I# 36 H_D#22 L23 D[22]# D[54]# AD20 H_D#54
15 H_STPCLK# D5 0R0402-PAD H_D#23 M23 AE22 H_D#55
STPCLK# H_D#24 D[23]# D[55]# H_D#56
15 H_INTR C6 LINT0 P25 D[24]# D[56]# AF23
H CLK
B4 A22 PM_THRMTRIP# H_D#25 P22 AD24 H_D#57

15 H_NMI LINT1 BCLK[0] CLK_CPU_BCLK 3 D[25]# D[57]#
A3 A21 should connect to H_D#26 P23 AE21 H_D#58
15 H_SMI# SMI# BCLK[1] CLK_CPU_BCLK# 3 D[26]# D[58]#
ICH7 and Calistoga H_D#27 T24 AD21 H_D#59
TPAD30 TP37 without T-ing H_D#28 D[27]# D[59]# H_D#60
AA1 RSVD[01] R24 D[28]# D[60]# AE25
TPAD30 TP31 AA4 T22 TP28 TPAD30 ( No stub) H_D#29 L26 AF25 H_D#61
TPAD30 TP36 RSVD[02] RSVD[12] 1D05V_S0 H_D#30 D[29]# D[61]# H_D#62
AB2 RSVD[03] T25 D[30]# D[62]# AF22
TPAD30 TP35 AA3 H_D#31 N24 AF26 H_D#63
RSVD[04] D[31]# D[63]#
1
TPAD30 TP26 M4 D2 TP20 TPAD30 M24 AD23
RESERVED
RSVD[05] RSVD[13] 6 H_DSTBN#1 DSTBN[1]# DSTBN[3]# H_DSTBN#3 6

TPAD30 TP25 N5 F6 TP24 TPAD30 R628 N25 AE24 H_DSTBP#3 6
RSVD[06] RSVD[14] 1KR2F-3-GP 6 H_DSTBP#1 DSTBP[1]# DSTBP[3]#
TPAD30 TP34 T2 D3 M26 AC20 H_DINV#3 6
RSVD[07] RSVD[15] 6 H_DINV#1 DINV[1]# DINV[3]#
TPAD30 TP32 V3 C1
RSVD[08] RSVD[16] TP45 TPAD30 Layout Note: CPU_GTLREF0 COMP0 R6301 27D4R2F-L1-GP
B2 RSVD[09] RSVD[17] AF1 AD26 GTLREF COMP[0] R26 2
1 2
TPAD30 TP19 C3 D22 TP17 TPAD30 0.5" max length. MISC U26 COMP1 R6291 2 54D9R2F-L1-GP
RSVD[10] RSVD[18] COMP[1]
1
TP16 TPAD30 R614 1KR2J-1-GP COMP2 R2871 27D4R2F-L1-GP
SC1KP16V2KX-GP
2 TPAD30 TP14 RSVD[19] C23
TP15 TPAD30 C321
DYTEST1 COMP[2] U1
COMP3 R2861
2
54D9R2F-L1-GP 2
B25 RSVD[11] RSVD[20] C24 2 1 C26 TEST1 COMP[3] V1 2
R627
2
BGA479-SKT6-GPU1 2KR2F-3-GP 1 2TEST2 D25 E5 H_DPRSLP# 15,38
62.10079.001 R615 51R2F-2-GP TEST2 DPRSTP#
DPSLP# B5 H_DPSLP# 15
2
2nd source: 62.10053.401 DPWR# D24 H_DPWR# 6
3,7 CPU_SEL0 B22 BSEL[0] PWRGOOD D6 H_PWRGD 15,36
3,7 CPU_SEL1 B23 BSEL[1] SLP# D7 H_CPUSLP# 6,15
3,7 CPU_SEL2 C21 BSEL[2] PSI# AE6 PSI# 38
BGA479-SKT6-GPU1
Layout Note:
1D05V_S0 Comp0, 2 connect with Zo=27.4 ohm, make
trace length shorter than 0.5" .
Comp1, 3 connect with Zo=55 ohm, make
trace length shorter than 0.5" .
XDP_TDI R284 1 2 150R2F-1-GP
XDP_TMS R282 1 2 39D2R3F-2-GP

XDP_TDO R283 1
DY
2 54D9R2F-L1-GP
H_CPURST# R606 1
DY
2 54D9R2F-L1-GP
3D3V_S0
XDP_DBRESET# R207 1
DY
1 2 150R2F-1-GP <Variant Name> 1
XDP_TCK R299 1 2 27D4R2F-L1-GP Wistron Corporation

XDP_TRST# R301 1 2 680R3F-GP Taipei Hsien 221, Taiwan, R.O.C.
All place within 2" to CPU Title
CPU (1 of 2)
A3
AG1 SC
A B C D E
A B C D E
VCC_CORE_S0
U72D
VCC_CORE_S0 A4 P6
VSS[001] VSS[082]
4 A8 VSS[002] VSS[083] P21 4
A11 VSS[003] VSS[084] P24
U72C A14 R2
VSS[004] VSS[085]
A7 VCC[001] VCC[068] AB20 A16 VSS[005] VSS[086] R5
A9 VCC[002] VCC[069] AB7 A19 VSS[006] VSS[087] R22
A10 VCC[003] VCC[070] AC7 A23 VSS[007] VSS[088] R25
A12 VCC[004] VCC[071] AC9 A26 VSS[008] VSS[089] T1
A13 VCC[005] VCC[072] AC12 B6 VSS[009] VSS[090] T4
A18 VCC[008] VCC[075] AC17 B13 VSS[012] VSS[093] U3
A20 VCC[009] VCC[076] AC18 B16 VSS[013] VSS[094] U6
B7 VCC[010] VCC[077] AD7 B19 VSS[014] VSS[095] U21
B9 VCC[011] VCC[078] AD9 B21 VSS[015] VSS[096] U24
B10 VCC[012] VCC[079] AD10 B24 VSS[016] VSS[097] V2
B12 VCC[013] VCC[080] AD12 C5 VSS[017] VSS[098] V5
B17 VCC[016] VCC[083] AD17 C14 VSS[020] VSS[101] W1
B18 VCC[017] VCC[084] AD18 C16 VSS[021] VSS[102] W4
B20 VCC[018] VCC[085] AE9 C19 VSS[022] VSS[103] W23
C9 VCC[019] VCC[086] AE10 C2 VSS[023] VSS[104] W26
C10 VCC[020] VCC[087] AE12 C22 VSS[024] VSS[105] Y3
C12 VCC[021] VCC[088] AE13 C25 VSS[025] VSS[106] Y6
C13 VCC[022] VCC[089] AE15 D1 VSS[026] VSS[107] Y21
C15 VCC[023] VCC[090] AE17 D4 VSS[027] VSS[108] Y24
C17 VCC[024] VCC[091] AE18 D8 VSS[028] VSS[109] AA2
C18 VCC[025] VCC[092] AE20 D11 VSS[029] VSS[110] AA5
D9 VCC[026] VCC[093] AF9 D13 VSS[030] VSS[111] AA8
3 D10 AF10 D16 AA11 3
VCC[027] VCC[094] VSS[031] VSS[112]
D17 AF17 Layout Note E3 AA22
VCC[031] VCC[098] VSS[035] VSS[116]
D18 VCC[032] VCC[099] AF18 E6 VSS[036] VSS[117] AA25
E7 AF20 1D05V_S0 E8 AB1
VCC[033] VCC[100] VSS[037] VSS[118]
E9 VCC[034] E11 VSS[038] VSS[119] AB4
E10 V6 CPU_V6 1 R285 2 E14 AB8
VCC[035] VCCP[01] 0R0402-PAD VSS[039] VSS[120]
E12 VCC[036] VCCP[02] G21 E16 VSS[040] VSS[121] AB11
E13 VCC[037] VCCP[03] J6 E19 VSS[041] VSS[122] AB13
E15 VCC[038] VCCP[04] K6 E21 VSS[042] VSS[123] AB16
1
E17 VCC[039] VCCP[05] M6 E24 VSS[043] VSS[124] AB19

E18 J21 C369 F5 AB23
VCC[040] VCCP[06] VSS[044] VSS[125]
E20 VCC[041] VCCP[07] K21 F8 VSS[045] VSS[126] AB26
2
F7 M21 SCD1U10V2KX-4GP F11 AC3

VCC[042] VCCP[08] VSS[046] VSS[127]
F9 VCC[043] VCCP[09] N21 F13 VSS[047] VSS[128] AC6
F10 VCC[044] VCCP[10] N6 F16 VSS[048] VSS[129] AC8
F12 VCC[045] VCCP[11] R21 F19 VSS[049] VSS[130] AC11
F14 VCC[046] VCCP[12] R6 F2 VSS[050] VSS[131] AC14
F15 VCC[047] VCCP[13] T21 F22 VSS[051] VSS[132] AC16
F17 VCC[048] VCCP[14] T6 F25 VSS[052] VSS[133] AC19
F18 V21 1D5V_VCCA_S0 1D5V_S0 G4 AC21
VCC[049] VCCP[15] 1D05V_S0 VSS[053] VSS[134]
F20 VCC[050] VCCP[16] W21 L22 G1 VSS[054] VSS[135] AC24
AA7 VCC[051] G23 VSS[055] VSS[136] AD2
AA9 VCC[052] VCCA B26 1 2 G26 VSS[056] VSS[137] AD5
AA10 HCB1608KF121T30-GP H3 AD8
VCC[053] VSS[057] VSS[138]
1
AA12 C674 68.00230.041 H6 AD11

VCC[054] C673 VSS[058] VSS[139]
AA13 VCC[055] VID[0] AD6 H_VID0 38 H21 VSS[059] VSS[140] AD13
1
2 SCD01U16V2KX-3GP SC4D7U6D3V3KX-GP 2
AA15 VCC[056] VID[1] AF5 H_VID1 38 H24 VSS[060] VSS[141] AD16
2
AA17 AE5 VCC_CORE_S0 C364 C363 C348 C347 C342 C340 C711 C368 J2 AD19
VCC[057] VID[2] H_VID2 38 VSS[061] VSS[142]
AA18 AF4 SCD1U10V2KX-4GP SCD1U10V2KX-4GPSCD1U10V2KX-4GP SC4D7U6D3V3KX-GP J5 AD22
VCC[058] VID[3] H_VID3 38 VSS[062] VSS[143]
2
2
AA20 AE3 H_VID4 38 SCD1U10V2KX-4GPSCD1U10V2KX-4GPSCD1U10V2KX-4GP SC4D7U6D3V3KX-GP J22 AD25
VCC[059] VID[4] VSS[063] VSS[144]
1
AB9 VCC[060] VID[5] AF2 H_VID5 38 J25 VSS[064] VSS[145] AE1

AC10 AE2 H_VID6 38 R300 K1 AE4
VCC[061] VID[6] 100R2F-L1-GP-U VSS[065] VSS[146]
AB10 VCC[062] H_VID[0..6] 38 K4 VSS[066] VSS[147] AE8
AB12 VCC[063] K23 VSS[067] VSS[148] AE11
AB14 VCC[064] VCCSENSE AF7 VCC_SENSE 38 K26 VSS[068] VSS[149] AE14
2
AB15 VCC[065] L3 VSS[069] VSS[150] AE16

AB17 VCC[066] L6 VSS[070] VSS[151] AE19
AB18 VCC[067] VSSSENSE AE7 VSS_SENSE 38 L21 VSS[071] VSS[152] AE23
VCC_CORE_S0 L24 AE26
VSS[072] VSS[153]
1
BGA479-SKT6-GPU1 Layout Note: M2 AF3

R298 VSS[073] VSS[154]
M5 VSS[074] VSS[155] AF6
100R2F-L1-GP-U VCCSENSE and VSSSENSE lines
DY M22 VSS[075] VSS[156] AF8
1
1
should be of equal length. M25 AF11
C716 C700 C365 C341 C676 C680 C682 VSS[076] VSS[157]
N1 VSS[077] VSS[158] AF13
2
SCD1U10V2KX-4GP SC10U10V5ZY-1GPSC10U10V5ZY-1GP
SC10U10V5ZY-1GP N4 AF16
VSS[078] VSS[159]
2
2
Layout Note: SCD1U10V2KX-4GP N23 AF19
Provide a test point (with SCD1U10V2KX-4GP VSS[079] VSS[160]
N26 VSS[080] VSS[161] AF21
no stub) to connect a SCD1U10V2KX-4GP P3 AF24
differential probe VSS[081] VSS[162]
between VCCSENSE and BGA479-SKT6-GPU1
VSSSENSE at the location
where the two 54.9ohm
resistors terminate the
55 ohm transmission line.
1 <Variant Name> 1
VCC_CORE_S0
Wistron Corporation
DY DY DY DY Taipei Hsien 221, Taiwan, R.O.C.
1
1
C715 C346 C344 C343 C701 C713 C702 C714 C703 C677 C370 C683 C712 C366 C678 Title
SC10U10V5ZY-1GP
SC10U10V5ZY-1GPSC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
CPU (2 of 2)
2
2
A3
AG1 SA
A B C D E
A B C D E
H_XRCOMP
1
R643
24D9R2F-L-GP
4 H_D#[63..0] H_A#[31..3] 4
U71A
H_D#0 F1 H9 H_A#3
H_D#_0 H_A#_3
2
H_D#1 J1 C9 H_A#4
H_D#2 H_D#_1 H_A#_4 H_A#5
4 H1 H_D#_2 H_A#_5 E11 4
H_D#3 J6 G11 H_A#6
H_D#4 H_D#_3 H_A#_6 H_A#7
H3 H_D#_4 H_A#_7 F11
H_D#5 K2 G12 H_A#8
1D05V_S0 H_D#6 H_D#_5 H_A#_8 H_A#9
G1 H_D#_6 H_A#_9 F9
H_D#7 G2 H11 H_A#10
H_D#8 H_D#_7 H_A#_10 H_A#11
K9 H_D#_8 H_A#_11 J12
H_D#9 K1 G14 H_A#12
H_D#_9 H_A#_12
2
H_D#10 K7 D9 H_A#13
R647 H_D#11 H_D#_10 H_A#_13 H_A#14
J8 H_D#_11 H_A#_14 J14
54D9R2F-L1-GP H_D#12 H4 H13 H_A#15
H_D#13 H_D#_12 H_A#_15 H_A#16
J3 H_D#_13 H_A#_16 J15
H_D#14 K11 F14 H_A#17
H_D#_14 H_A#_17
1
H_D#15 G4 D12 H_A#18
H_XSCOMP H_D#16 H_D#_15 H_A#_18 H_A#19
T10 H_D#_16 H_A#_19 A11
H_D#17 W11 C11 H_A#20
H_D#18 H_D#_17 H_A#_20 H_A#21
T3 H_D#_18 H_A#_21 A12
H_D#19 U7 A13 H_A#22
1D05V_S0 H_D#20 H_D#_19 H_A#_22 H_A#23
U9 H_D#_20 H_A#_23 E13
H_D#21 U11 G13 H_A#24
H_D#22 H_D#_21 H_A#_24 H_A#25
T11 H_D#_22 H_A#_25 F12
1
H_D#23 W9 B12 H_A#26

R645 H_D#24 H_D#_23 H_A#_26 H_A#27 1D05V_S0
T1 H_D#_24 H_A#_27 B14
221R2F-2-GP H_D#25 T8 C12 H_A#28
H_D#26 H_D#_25 H_A#_28 H_A#29
T4 H_D#_26 H_A#_29 A14
1
H_D#27 W7 C14 H_A#30
H_D#_27 H_A#_30
2
H_XSWING H_D#28 U5 D14 H_A#31 R274

H_D#29 H_D#_28 H_A#_31 100R2F-L1-GP-U
T9 H_D#_29
1
H_D#30 W6 E8 H_ADS# 4
H_D#_30 H_ADS#
2
3 R644 H_D#31 T5 B9 H_ADSTB#0 4

3
H_D#_31 H_ADSTB#_0
2
100R2F-L1-GP-U C743 H_D#32 AB7 C13
H_D#_32 H_ADSTB#_1 H_ADSTB#1 4
SCD1U16V2ZY-2GP H_D#33 AA9 J13 H_VREF
H_D#_33 H_VREF_0
1
H_D#34 W4 C6 H_BNR# 4
H_D#_34 H_BNR#
2
1
HOST
H_D#35 W3 F6 H_BPRI# 4
H_D#_35 H_BPRI#
2
H_D#36 Y3 C7 H_BREQ#0 4 R246
H_D#37 H_D#_36 H_BREQ#0 C362 200R2F-L-GP
Y7 H_D#_37 H_CPURST# B7 H_CPURST# 4
H_D#38 W5 A7 SCD1U16V2ZY-2GP
H_D#_38 H_DBSY# H_DBSY# 4
1
H_D#39 Y10 C3 H_DEFER# 4
H_D#_39 H_DEFER#
2
H_D#40 AB8 J9 H_DPWR# 4
H_D#41 H_D#_40 H_DPWR#
W2 H_D#_41 H_DRDY# H8 H_DRDY# 4
H_YRCOMP H_D#42 AA4 K13
H_D#43 H_D#_42 H_VREF_1
AA7 H_D#_43 H_DINV#[3..0] 4
H_D#44 AA2 J7 H_DINV#0
H_D#_44 H_DINV#_0
1
H_D#45 AA6 W8 H_DINV#1

R639 H_D#46 H_D#_45 H_DINV#_1 H_DINV#2
AA10 H_D#_46 H_DINV#_2 U3
24D9R2F-L-GP H_D#47 Y8 AB10 H_DINV#3
H_D#48 H_D#_47 H_DINV#_3
AA1 H_D#_48 H_DSTBN#[3..0] 4
H_D#49 AB4 K4 H_DSTBN#0
H_D#_49 H_DSTBN#_0
2
H_D#50 AC9 T7 H_DSTBN#1

H_D#51 H_D#_50 H_DSTBN#_1 H_DSTBN#2
AB11 H_D#_51 H_DSTBN#_2 Y5
H_D#52 AC11 AC4 H_DSTBN#3
H_D#53 H_D#_52 H_DSTBN#_3
AB3 H_D#_53 H_DSTBP#[3..0] 4
H_D#54 AC2 K3 H_DSTBP#0
1D05V_S0 H_D#55 H_D#_54 H_DSTBP#_0 H_DSTBP#1
AD1 H_D#_55 H_DSTBP#_1 T6
H_D#56 AD9 AA5 H_DSTBP#2
H_D#57 H_D#_56 H_DSTBP#_2 H_DSTBP#3
AC1 H_D#_57 H_DSTBP#_3 AC5
H_D#58 AD7 H_D#_58
2
H_D#59 AC6
2 R642 H_D#60 H_D#_59 2
AB5 H_D#_60 H_HIT# D3 H_HIT# 4
54D9R2F-L1-GP H_D#61 AD10 D4
H_D#_61 H_HITM# H_HITM# 4
H_D#62 AD4 B3 H_LOCK# 4
H_D#63 H_D#_62 H_LOCK#
AC8 H_D#_63
1
H_YSCOMP H_XRCOMP E1 H_REQ#[4..0] 4

H_XSCOMP H_XRCOMP H_REQ#0
E2 H_XSCOMP H_REQ#_0 D8
H_XSWING E4 G8 H_REQ#1
H_XSWING H_REQ#_1 H_REQ#2
H_REQ#_2 B8
1D05V_S0 H_YRCOMP Y1 F8 H_REQ#3
H_YSCOMP H_YRCOMP H_REQ#_3 H_REQ#4
U1 H_YSCOMP H_REQ#_4 A8
H_YSWING W1 H_RS#[2..0] 4
H_YSWING
1
B4 H_RS#0
R641 H_RS#_0 H_RS#1
3 CLK_MCH_BCLK AG2 H_CLKIN H_RS#_1 E6
221R2F-2-GP AG1 D6 H_RS#2
3 CLK_MCH_BCLK# H_CLKIN# H_RS#_2
H_SLPCPU# E3 1 R646 2 H_CPUSLP# 4,15

2
H_YSWING E7 0R0402-PAD H_TRDY# 4

H_TRDY#
1
CALISTOGA
2
R640
100R2F-L1-GP-U C741
SCD1U16V2ZY-2GP
1
2
1 Place them near to the chip ( < 0.5") <Variant Name> 1
Wistron Corporation
Title
GMCH (1 of 5)
A3
AG1 SA
A B C D E
A B C D E
U71B
RSVD_0 H32
11 M_CLK_DDR0 AY35 SM_CK_0 RSVD_1 T32
AR1 1D5V_PCIE_S0
11 M_CLK_DDR1 SM_CK_1 RSVD_2 R32
11 M_CLK_DDR2 AW7 SM_CK_2 RSVD_3 F3
11 M_CLK_DDR3 AW40 SM_CK_3 RSVD_4 F7
RSVD
RSVD_5 AG11 U71C
11 M_CLK_DDR#0 AW35 SM_CK#_0 RSVD_6 AF11
AT1 R594
11 M_CLK_DDR#1 SM_CK#_1 RSVD_7 H7 D32 L_BKLTCTL EXP_A_COMPI D40 2 1
24D9R2F-L-GP
11 M_CLK_DDR#2 AY7 SM_CK#_2 RSVD_8 J19 J30 L_BKLTEN EXP_A_COMPO D38
11 M_CLK_DDR#3 AY40 SM_CK#_3 RSVD_9 K30 H30 L_CLKCTLA PEG_RXN[15..0] 45
PEG_RXN0
RSVD_10 J29 H29 L_CLKCTLB EXP_A_RXN_0 F34
PEG_RXN1
11,12 M_CKE0 AU20 SM_CKE_0 RSVD_11 A41 G26 L_DDC_CLK EXP_A_RXN_1 G38
AT20 PEG_RXN2
4 11,12 M_CKE1 SM_CKE_1 RSVD_12 A35 G25 L_DDC_DATA EXP_A_RXN_2 H34
PEG_RXN3
4
11,12 M_CKE2 BA29 SM_CKE_2 RSVD_13 A34 B38 L_IBG EXP_A_RXN_3 J38
AY29 PEG_RXN4
11,12 M_CKE3 SM_CKE_3 RSVD_14 D28 C35 L_VBG EXP_A_RXN_4 L34
PEG_RXN5
RSVD_15 D27 F32 L_VDDEN EXP_A_RXN_5 M38
PEG_RXN6
11,12 M_CS0# AW13 SM_CS#_0 C33 L_VREFH EXP_A_RXN_6 N34
11,12 M_CS1# AW12 C32 P38 PEG_RXN7
SM_CS#_1 L_VREFL EXP_A_RXN_7 PEG_RXN8
AY21 K16 R34
MUXING
11,12 M_CS2# SM_CS#_2 CFG_0 CPU_SEL0 3,4 EXP_A_RXN_8
11,12 M_CS3# AW21 K18 CPU_SEL1 3,4 A33 T38 PEG_RXN9
SM_CS#_3 CFG_1 LA_CLK# EXP_A_RXN_9 PEG_RXN10
CFG_2 J18 CPU_SEL2 3,4 A32 LA_CLK EXP_A_RXN_10 V34
M_OCDCOMP0 AL20 F18 CFG3 E27 W38 PEG_RXN11
M_OCDCOMP1 SM_OCDCOMP_0 CFG_3 CFG4 LB_CLK# EXP_A_RXN_11 PEG_RXN12
AF10 SM_OCDCOMP_1 CFG_4 E15 E26 LB_CLK EXP_A_RXN_12 Y34
1
F15 CFG5 AA38 PEG_RXN13

CFG_5 CPU EXP_A_RXN_13
R244 R273 CFG6 SEL2 SEL1 SEL0 PEG_RXN14
LVDS
11,12 M_ODT0 BA13 SM_ODT_0 CFG_6 E18 C37 LA_DATA#_0 EXP_A_RXN_14 AB34
40D2R2F-GP 40D2R2F-GP BA12 D19 CFG7 B35 AC38 PEG_RXN15
11,12 M_ODT1 SM_ODT_1 CFG_7 LA_DATA#_1 EXP_A_RXN_15
CFG8 0 0 0 266M
DY DY 11,12 M_ODT2 AY20 SM_ODT_2 CFG_8 D16
CFG9 0 0 1 133M
A37 LA_DATA#_2 PEG_RXP0
PEG_RXP[15..0] 45
CFG
11,12 M_ODT3 AU21 SM_ODT_3 CFG_9 G16 EXP_A_RXP_0 D34
2
E16 CFG10 0 1 0 200M F38 PEG_RXP1

CFG_10 EXP_A_RXP_1
DDR
GRAPHICS
M_RCOMPN AV9 D15 CFG11 0 1 1 166M G34 PEG_RXP2
DDR_VREF_S3 M_RCOMPP SM_RCOMP# CFG_11 CFG12 1 0 0 333M EXP_A_RXP_2 PEG_RXP3
AT9 SM_RCOMP CFG_12 G15 B37 LA_DATA_0 EXP_A_RXP_3 H38
K15 CFG13 1 0 1 100M B34 J34 PEG_RXP4
CFG_13 CFG14 1 1 0 400M LA_DATA_1 EXP_A_RXP_4 PEG_RXP5
AK1 SM_VREF_0 CFG_14 C15 A36 LA_DATA_2 EXP_A_RXP_5 L38
AK41 H16 CFG15 1 1 1 Reserved M34 PEG_RXP6
SM_VREF_1 CFG_15 CFG16 EXP_A_RXP_6 PEG_RXP7
CFG_16 G18 EXP_A_RXP_7 N38
1
H15 CFG17 G30 P34 PEG_RXP8

CFG_17 CFG18 LB_DATA#_0 EXP_A_RXP_8 PEG_RXP9
3 CLK_MCH_3GPLL# AF33 G_CLKIN# CFG_18 J25 D30 LB_DATA#_1 EXP_A_RXP_9 R38
3 CLK_MCH_3GPLL AG33 K27 CFG19 F29 T34 PEG_RXP10
G_CLKIN CFG_19 LB_DATA#_2 EXP_A_RXP_10
2
C737 C667 A27 J26 CFG20 V38 PEG_RXP11

D_REFCLKIN# CFG_20 EXP_A_RXP_11
CLK
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP A26 DY W34 PEG_RXP12 45 PEG_TXN[15..0]
D_REFCLKIN EXP_A_RXP_12
C40 D_REFSSCLKIN# PM_BMBUSY# G28 PM_BMBUSY# 16R237 EXP_A_RXP_13 Y38 PEG_RXP13
3 D41 D_REFSSCLKIN PM_EXTTS#_0 F25 PM_EXTTS#0 1 2 VGATE_PWRGD 16,38,48 F30 LB_DATA_0 EXP_A_RXP_14 AA34 PEG_RXP14 3
H26 PM_EXTTS#1 0R2J-2-GP PEG_RXP15
PM
PM_EXTTS#_1 D29 LB_DATA_1 EXP_A_RXP_15 AB38
PCI-EXPRESS
16 DMI_TXN[3..0] PM_THRMTRIP# G6 PM_THRMTRIP-A# 4 1 R239 2 PWROK 16,19 F28 LB_DATA_2
DMI_TXN0 AE35 AH33 0R0402-PAD F36 GTXN0 1 2 PEG_TXN0
DMI_TXN1 DMI_RXN_0 PWROK R238 EXP_A_TXN_0
AF39 DMI_RXN_1 RSTIN# AH34 1 2 PLT_RST1# 16,20,26,30,31,32,34,35,45 EXP_A_TXN_1 G40 GTXN1 C298
1 2 SCD1U16V2KX-3GP
PEG_TXN1
DMI_TXN2 AG35 100R2J-2-GP 1D5V_S0 H36 GTXN2 C297
1 2 SCD1U16V2KX-3GP
PEG_TXN2
DMI_TXN3 DMI_RXN_2 EXP_A_TXN_2
AH39 DMI_RXN_3 EXP_A_TXN_3 J40 GTXN3 C294
1 2 SCD1U16V2KX-3GP
PEG_TXN3
MISC H28 TP13 TPAD30 A16 L36 GTXN4 C293
1 2 SCD1U16V2KX-3GP
PEG_TXN4
SDVO_CTRLCLK TP12 TPAD30 TV_DACA_OUT EXP_A_TXN_4
16 DMI_TXP[3..0] SDVO_CTRLDATA H27 C18 TV_DACB_OUT EXP_A_TXN_5 M40 GTXN5 C290
1 2 SCD1U16V2KX-3GP
PEG_TXN5
DMI_TXP0 AC35 K28 MCH_ICH_SYNC# 16 A19 N36 GTXN6 C289
1 2 SCD1U16V2KX-3GP
PEG_TXN6
DMI_TXP1 DMI_RXP_0 LT_RESET# TV_DACC_OUT EXP_A_TXN_6
P40 GTXN7 C287 SCD1U16V2KX-3GP
PEG_TXN7
TV
AE39 DMI_RXP_1 EXP_A_TXN_7 1 2
DMI_TXP2 AF35 J20 R36 GTXN8 C284
1 2 SCD1U16V2KX-3GP
PEG_TXN8
DMI_TXP3 DMI_RXP_2 TV_IREF EXP_A_TXN_8
AG39 DMI_RXP_3 NC0 D1 B16 TV_IRTNA EXP_A_TXN_9 T40 GTXN9 C283
1 2 SCD1U16V2KX-3GP
PEG_TXN9
NC1 C41 B18 TV_IRTNB EXP_A_TXN_10 V36 GTXN10 C280
1 2 SCD1U16V2KX-3GP
PEG_TXN10
16 DMI_RXN[3..0] NC2 C1 B19 TV_IRTNC EXP_A_TXN_11 W40 GTXN11 C279
1 2 SCD1U16V2KX-3GP
PEG_TXN11
DMI_RXN0 AE37 BA41 Y36 GTXN12 C248
1 2 SCD1U16V2KX-3GP
PEG_TXN12
DMI_RXN1 DMI_TXN_0 NC3 EXP_A_TXN_12
AF41 DMI_TXN_1 NC4 BA40 EXP_A_TXN_13 AA40 GTXN13 C277
1 2 SCD1U16V2KX-3GP
PEG_TXN13
DMI_RXN2 AB36 GTXN14 C245 SCD1U16V2KX-3GP
PEG_TXN14
NC
AG37 DMI_TXN_2 NC5 BA39 EXP_A_TXN_14 1 2

DMI_RXN3 3D3V_S0 1D05V_S0 AC40 GTXN15 C275 SCD1U16V2KX-3GP
AH41 DMI_TXN_3 NC6 BA3 EXP_A_TXN_15 1 2 45 PEG_TXN15PEG_TXP[15..0]
BA2 C273 SCD1U16V2KX-3GP
NC7
DMI
16 DMI_RXP[3..0] NC8 BA1 E23 CRT_BLUE EXP_A_TXP_0 D36 GTXP0 1 2 PEG_TXP0

DMI_RXP0 AC37 B41 D23 F40 GTXP1 C300
1 2 SCD1U16V2KX-3GP
PEG_TXP1
DMI_TXP_0 NC9 CRT_BLUE# EXP_A_TXP_1
4
3
DMI_RXP1 AE41 B2 C22 G36 GTXP2 C299
1 2 SCD1U16V2KX-3GP
PEG_TXP2
DMI_RXP2 DMI_TXP_1 NC10 RN97 CRT_GREEN EXP_A_TXP_2
H40 GTXP3 C296 SCD1U16V2KX-3GP
PEG_TXP3
VGA
AF37 DMI_TXP_2 NC11 AY41 B22 CRT_GREEN# EXP_A_TXP_3 1 2
DMI_RXP3 AG41 AY1 SRN10KJ-5-GP A21 J36 GTXP4 C295
1 2 SCD1U16V2KX-3GP
PEG_TXP4
DMI_TXP_3 NC12 CRT_RED EXP_A_TXP_4
NC13 AW41 B21 CRT_RED# EXP_A_TXP_5 L40 GTXP5 C292
1 2 SCD1U16V2KX-3GP
PEG_TXP5
NC14 AW1 EXP_A_TXP_6 M36 GTXP6 C291
1 2 SCD1U16V2KX-3GP
PEG_TXP6
NC15 A40 EXP_A_TXP_7 N40 GTXP7 C288
1 2 SCD1U16V2KX-3GP
PEG_TXP7
1
2
A4 GMCH_DDCCLK C26 P36 GTXP8 C286
1 2 SCD1U16V2KX-3GP
PEG_TXP8
2 NC16 GMCH_DDCDATA CRT_DDC_CLK EXP_A_TXP_8 2
NC17 A39 C25 CRT_DDC_DATA EXP_A_TXP_9 R40 GTXP9 C285
1 2 SCD1U16V2KX-3GP
PEG_TXP9
NC18 A3 G23 CRT_HSYNC EXP_A_TXP_10 T36 GTXP10 C282
1 2 SCD1U16V2KX-3GP
PEG_TXP10
J22 CRT_IREF EXP_A_TXP_11 V40 GTXP11 C281
1 2 SCD1U16V2KX-3GP
PEG_TXP11
3D3V_S0 H23 W36 GTXP12 C249
1 2 SCD1U16V2KX-3GP
PEG_TXP12
CALISTOGA CRT_VSYNC EXP_A_TXP_12
EXP_A_TXP_13 Y40 GTXP13 C278
1 2 SCD1U16V2KX-3GP
PEG_TXP13
1 R2542 CFG18 AA36 GTXP14 C247
1 2 SCD1U16V2KX-3GP
PEG_TXP14
DUMMY-R2 EXP_A_TXP_14
EXP_A_TXP_15 AB40 GTXP15 C276
1 2 SCD1U16V2KX-3GP
PEG_TXP15
1 R2422 CFG19 C274 SCD1U16V2KX-3GP
3D3V_S0 DUMMY-R2 CALISTOGA
1 R2412 CFG20
DUMMY-R2
1 R2492 CFG3
RN43 DUMMY-R2
1 4 PM_EXTTS#0 1 R2552 CFG4 When High 1K Ohm
2 3 PM_EXTTS#1 DUMMY-R2
1 R2472 CFG5
SRN10KJ-5-GP DUMMY-R2
1D8V_S3 R2602 CFG6
1
DUMMY-R2
CFG6:
1
1 R2532 CFG7 0=Moby Dick ,1=Calistoga (default)

R271 DUMMY-R2
80D6R2F-L-GP 1 R2522 CFG8
DUMMY-R2
M_RCOMPN 1 R2592 CFG9
2
DUMMY-R2 When Low choice

1 R2512 CFG10 lower than 3.5K
M_RCOMPP DUMMY-R2
Ohm
1
1 R256 2 DY CFG11
<Variant Name>
1
R272 2K2R2J-2-GP 1
80D6R2F-L-GP 1 R2772 CFG12
DUMMY-R2
1 R2752 CFG13 Wistron Corporation
2
DUMMY-R2 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

1 R2482 CFG14 Taipei Hsien 221, Taiwan, R.O.C.
DUMMY-R2
1 R2582 CFG15
When PM replace to GM Title
DUMMY-R2
1 R2502 CFG16 GMCH (2 of 5)
DUMMY-R2 Size Document Number Rev
R2762 CFG17 A3
1
DUMMY-R2 AG1 -1
A B C D E
A B C D E
4 4
U71E
11 M_B_DQ[63..0]
M_B_DQ0 AK39
M_B_DQ1 SB_DQ0
AJ37 SB_DQ1 SB_BS_0 AT24 M_B_BS#0 11,12
U71D M_B_DQ2 AP39 AV23 M_B_BS#1 11,12
11 M_A_DQ[63..0] SB_DQ2 SB_BS_1
M_A_DQ0 AJ35 AU12 M_A_BS#0 11,12 M_B_DQ3 AR41 AY28 M_B_BS#2 11,12
M_A_DQ1 SA_DQ0 SA_BS_0 M_B_DQ4 SB_DQ3 SB_BS_2
AJ34 SA_DQ1 SA_BS_1 AV14 M_A_BS#1 11,12 AJ38 SB_DQ4 M_B_CAS# 11,12
M_A_DQ2 AM31 BA20 M_A_BS#2 11,12 M_B_DQ5 AK38 AR24 M_B_DM[7..0] 11
M_A_DQ3 SA_DQ2 SA_BS_2 M_B_DQ6 SB_DQ5 SB_CAS# M_B_DM0
AM33 SA_DQ3 M_A_CAS# 11,12 AN41 SB_DQ6 SB_DM_0 AK36
M_A_DQ4 AJ36 AY13 M_A_DM[7..0] 11 M_B_DQ7 AP41 AR38 M_B_DM1
M_A_DQ5 SA_DQ4 SA_CAS# M_A_DM0 M_B_DQ8 SB_DQ7 SB_DM_1 M_B_DM2
AK35 SA_DQ5 SA_DM_0 AJ33 AT40 SB_DQ8 SB_DM_2 AT36
M_A_DQ6 AJ32 AM35 M_A_DM1 M_B_DQ9 AV41 BA31 M_B_DM3
M_A_DQ7 SA_DQ6 SA_DM_1 M_A_DM2 M_B_DQ10 SB_DQ9 SB_DM_3 M_B_DM4
AH31 SA_DQ7 SA_DM_2 AL26 AU38 SB_DQ10 SB_DM_4 AL17
M_A_DQ8 AN35 AN22 M_A_DM3 M_B_DQ11 AV38 AH8 M_B_DM5
M_A_DQ9 SA_DQ8 SA_DM_3 M_A_DM4 M_B_DQ12 SB_DQ11 SB_DM_5 M_B_DM6
AP33 SA_DQ9 SA_DM_4 AM14 AP38 SB_DQ12 SB_DM_6 BA5
M_A_DQ10 AR31 AL9 M_A_DM5 M_B_DQ13 AR40 AN4 M_B_DM7
M_A_DQ11 SA_DQ10 SA_DM_5 M_A_DM6 M_B_DQ14 SB_DQ13 SB_DM_7
AP31 SA_DQ11 SA_DM_6 AR3 AW38 SB_DQ14 M_B_DQS[7..0] 11
M_A_DQ12 AN38 AH4 M_A_DM7 M_B_DQ15 AY38 AM39 M_B_DQS0
SA_DQ12 SA_DM_7 SB_DQ15 SB_DQS_0
B
M_A_DQ13 AM36 M_A_DQS[7..0] 11 M_B_DQ16 BA38 AT39 M_B_DQS1
M_A_DQ14 SA_DQ13 M_A_DQS0 M_B_DQ17 SB_DQ16 SB_DQS_1 M_B_DQS2
AM34 SA_DQ14 SA_DQS_0 AK33 AV36 SB_DQ17 SB_DQS_2 AU35
A
M_A_DQ15 AN33 AT33 M_A_DQS1 M_B_DQ18 AR36 AR29 M_B_DQS3
M_A_DQ16 SA_DQ15 SA_DQS_1 M_A_DQS2 M_B_DQ19 SB_DQ18 SB_DQS_3 M_B_DQS4
AK26 SA_DQ16 SA_DQS_2 AN28 AP36 SB_DQ19 SB_DQS_4 AR16
M_A_DQ17 AL27 AM22 M_A_DQS3 M_B_DQ20 BA36 AR10 M_B_DQS5
MEMORY
3 M_A_DQ18 SA_DQ17 SA_DQS_3 M_A_DQS4 M_B_DQ21 SB_DQ20 SB_DQS_5 M_B_DQS6 3
AM26 SA_DQ18 SA_DQS_4 AN12 AU36 SB_DQ21 SB_DQS_6 AR7
M_A_DQ19 AN24 AN8 M_A_DQS5 M_B_DQ22 AP35 AN5 M_B_DQS7 M_B_DQS#[7..0] 11
SA_DQ19
MEMORY SA_DQS_5 SB_DQ22 SB_DQS_7
M_A_DQ20 AK28 AP3 M_A_DQS6 M_B_DQ23 AP34 AM40 M_B_DQS#0
M_A_DQ21 SA_DQ20 SA_DQS_6 M_A_DQS7 M_B_DQ24 SB_DQ23 SB_DQS#_0 M_B_DQS#1
AL28 SA_DQ21 SA_DQS_7 AG5 M_A_DQS#[7..0] 11 AY33 SB_DQ24 SB_DQS#_1 AU39
M_A_DQ22 AM24 AK32 M_A_DQS#0 M_B_DQ25 BA33 AT35 M_B_DQS#2
M_A_DQ23 SA_DQ22 SA_DQS#_0 M_A_DQS#1 M_B_DQ26 SB_DQ25 SB_DQS#_2 M_B_DQS#3
AP26 SA_DQ23 SA_DQS#_1 AU33 AT31 SB_DQ26 SB_DQS#_3 AP29
M_A_DQ24 AP23 AN27 M_A_DQS#2 M_B_DQ27 AU29 AP16 M_B_DQS#4
AL22 SA_DQ25 SA_DQS#_3 AM21 AU31 SB_DQ28 SB_DQS#_5 AT10
M_A_DQ26 AP21 AM12 M_A_DQS#4 M_B_DQ29 AW31 AT7 M_B_DQS#6
AN20 SA_DQ27 SA_DQS#_5 AL8 AV29 SB_DQ30 SB_DQS#_7 AP5
M_A_DQ28 AL23 AN3 M_A_DQS#6 M_B_DQ31 AW29 M_B_A[13..0] 11,12
M_A_DQ29 SA_DQ28 SA_DQS#_6 M_A_DQS#7 M_B_DQ32 SB_DQ31 M_B_A0
AP24 SA_DQ29 SA_DQS#_7 AH5 AM19 SB_DQ32 SB_MA_0 AY23
M_A_DQ30 AP20 M_B_DQ33 AL19 AW24 M_B_A1
SYSTEM
SA_DQ30 M_A_A[13..0] 11,12 SB_DQ33 SB_MA_1
M_A_DQ31 AT21 AY16 M_A_A0 M_B_DQ34 AP14 AY24 M_B_A2
M_A_DQ32 SA_DQ31 SA_MA_0 M_A_A1 M_B_DQ35 SB_DQ34 SB_MA_2 M_B_A3
AR12 AU14 AN14 AR28
SYSTEM

AR14 SA_DQ33 SA_MA_2 AW16 AN17 SB_DQ36 SB_MA_4 AT27
M_A_DQ34 AP13 BA16 M_A_A3 M_B_DQ37 AM16 AT28 M_B_A5
AP12 SA_DQ35 SA_MA_4 BA17 AP15 SB_DQ38 SB_MA_6 AU27
M_A_DQ36 AT13 AU16 M_A_A5 M_B_DQ39 AL15 AV28 M_B_A7
AT12 SA_DQ37 SA_MA_6 AV17 AJ11 SB_DQ40 SB_MA_8 AV27
M_A_DQ38 AL14 AU17 M_A_A7 M_B_DQ41 AH10 AW27 M_B_A9
AL12 SA_DQ39 SA_MA_8 AW17 AJ9 SB_DQ42 SB_MA_10 AV24
M_A_DQ40 AK9 AT16 M_A_A9 M_B_DQ43 AN10 BA27 M_B_A11
AN7 SA_DQ41 SA_MA_10 AU13 AK13 SB_DQ44 SB_MA_12 AY27
M_A_DQ42 AK8 AT17 M_A_A11 M_B_DQ45 AH11 AR23 M_B_A13
M_A_DQ43 SA_DQ42 SA_MA_11 M_A_A12 M_B_DQ46 SB_DQ45 SB_MA_13
DDR
AK7 SA_DQ43 SA_MA_12 AV20 AK10 SB_DQ46 M_B_RAS# 11,12
M_A_DQ44 AP9 AV12 M_A_A13 M_B_DQ47 AJ8 AU23
M_A_DQ45 SA_DQ44 SA_MA_13 M_B_DQ48 SB_DQ47 SB_RAS# SB_RCVENIN# TP22 TPAD30
DDR
AN9 SA_DQ45 M_A_RAS# 11,12 BA10 SB_DQ48 SB_RCVENIN# AK16

M_A_DQ46 AT5 AW14 M_B_DQ49 AW10 AK18 SB_RCVENOUT# TP21 TPAD30
2 M_A_DQ47 SA_DQ46 SA_RAS# SA_RCVENIN# TP23 TPAD30 M_B_DQ50 SB_DQ49 SB_RCVENOUT# 2
AL5 SA_DQ47 SA_RCVENIN# AK23 BA4 SB_DQ50 SB_WE# AR27 M_B_WE# 11,12
M_A_DQ48 AY2 AK24 SA_RCVENOUT# TP11 TPAD30 M_B_DQ51 AW4
M_A_DQ49 SA_DQ48 SA_RCVENOUT# M_B_DQ52 SB_DQ51
AW2 SA_DQ49 SA_WE# AY14 M_A_WE# 11,12 AY10 SB_DQ52
M_A_DQ50 AP1 M_B_DQ53 AY9 Place Test PAD Near to Chip
M_A_DQ51 SA_DQ50 M_B_DQ54 SB_DQ53
AN2 SA_DQ51 AW5 SB_DQ54 ascould as possible
M_A_DQ52 AV2 Place Test PAD Near to Chip M_B_DQ55 AY5
AT3 SA_DQ53 as could as possible AV4 SB_DQ56
M_A_DQ54 AN1 M_B_DQ57 AR5
AL2 SA_DQ55 AK4 SB_DQ58
M_A_DQ56 AG7 M_B_DQ59 AK3
AF9 SA_DQ57 AT4 SB_DQ60
M_A_DQ58 AG4 M_B_DQ61 AK5
AF6 SA_DQ59 AJ5 SB_DQ62
M_A_DQ60 AG9 M_B_DQ63 AJ3
M_A_DQ61 SA_DQ60 SB_DQ63
AH6 SA_DQ61
M_A_DQ62 AF4 CALISTOGA
M_A_DQ63 SA_DQ62
AF8 SA_DQ63
CALISTOGA
1 <Variant Name> 1
Wistron Corporation
Title
GMCH (3 of 5)
A3
AG1 SA
A B C D E
A B C D E
U71H
H22 1D05V_S0
VCCSYNC
VTT_0 AC14
2D5V_3GBG_S0 2D5V_S0 C30 AB14
VCC_TXLVDS0 VTT_1
B30 VCC_TXLVDS1 VTT_2 W14
1
4 A30 VCC_TXLVDS2 VTT_3 V14 4
2 R593 1 1D5V_S0 1D5V_PCIE_S0 T14 C361 C332 C742
0R0603-PAD VTT_4 SCD1U10V2KX-4GP SC2D2U6D3V3MX-1-GP SC4D7U10V5ZY-3GP
AJ41 VCC3G0 VTT_5 R14
2
1
2 R592 1 AB41 P14
C672 0R0805-PAD VCC3G1 VTT_6
Y41 VCC3G2 VTT_7 N14
1
SCD1U10V2KX-4GP C670 C669 C668 C671
SCD1U10V2KX-4GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
V41 VCC3G3 VTT_8 M14
2
R41 VCC3G4 VTT_9 L14

1D5V_S0 N41 AD13
VCC3G5 VTT_10
2
1D5V_3GPLL_S0 L41 AC13
VCC3G6 VTT_11
1 2 AC33 VCCA_3GPLL VTT_12 AB13
R240 0R0603-PAD 2D5V_3GBG_S0 G41 AA13
VCCA_3GBG VTT_13
1
C316 H41 Y13
C315 VSSA_3GBG VTT_14
VTT_15 W13
SC4D7U6D3V3KX-GP SCD1U10V2KX-4GP 1D05V_S0 F21 V13
VCCA_CRTDAC0 VTT_16
2
E21 VCCA_CRTDAC1 VTT_17 U13
G21 VSSA_CRTDAC VTT_18 T13
VTT_19 R13
B26 VCCA_DPLLA VTT_20 N13
C39 VCCA_DPLLB VTT_21 M13
1D5V_HPLL_S0 AF1 L13
VCCA_HPLL VTT_22
VTT_23 AB12
A38 VCCA_LVDS VTT_24 AA12
B39 VSSA_LVDS VTT_25 Y12
VTT_26 W12
1D5V_S0 1D5V_MPLL_S0 AF2 V12
1D5V_S0 VCCA_MPLL VTT_27
VTT_28 U12
H20 VCCA_TVBG VTT_29 T12
G20 VSSA_TVBG VTT_30 R12
VTT_31 P12
3 N12 3
VTT_32
VTT_33 M12
E19 VCCA_TVDACA0 VTT_34 L12
F19 VCCA_TVDACA1 VTT_35 R11
C20 VCCA_TVDACB0 VTT_36 P11
D20 VCCA_TVDACB1 VTT_37 N11
1D5V_S0
E20
F20
VCCA_TVDACC0
VCCA_TVDACC1 POWER VTT_38
VTT_39
VTT_40
M11
R10
P10
AH1 VCCD_HMPLL0 VTT_41 N10
L11 AH2 VCCD_HMPLL1 VTT_42 M10
VTT_43 P9
1 2 1D5V_HPLL_S0 A28 N9
HCB1608KF121T30-GP VCCD_LVDS0 VTT_44
B28 VCCD_LVDS1 VTT_45 M9
1
68.00230.041 1D5V_S0 C28 R8

C401 C400 VCCD_LVDS2 VTT_46
VTT_47 P8
2 R257 11D5V_TVDAC_S0 D21 VCCD_TVDAC VTT_48 N8
2
1
0R0603-PAD M8
L30 VTT_49
C339 A23 P7
1D5V_MPLL_S0 SCD1U10V2KX-4GP VCC_HV0 VTT_50
1 2 B23 VCC_HV1 VTT_51 N7
2
HCB1608KF121T30-GP 3D3V_S0 B25 M7
VCC_HV2 VTT_52
1
68.00230.041 SC10U10V5ZY-1GP SCD1U10V2KX-4GP R6

C738 C739 VTT_53
2 R619 1 H19 VCCD_QTVDAC VTT_54 P6
SC10U10V5ZY-1GP SCD1U10V2KX-4GP 0R0603-PAD M6
VTT_55
2
AK31 A6 VCCP_GMCH_CAP3
VCCAUX0 VTT_56
1
1
AF31 VCCAUX1 VTT_57 R5
C698 C697 AE31 P5 C710
SC10U10V5ZY-1GPSCD1U10V2KX-4GP VCCAUX2 VTT_58
AC31 VCCAUX3 VTT_59 N5 SCD22U16V3ZY-GP
2
2
AL30 VCCAUX4 VTT_60 M5
2 2
AK30 VCCAUX5 VTT_61 P4
AJ30 VCCAUX6 VTT_62 N4
AH30 VCCAUX7 VTT_63 M4
AG30 VCCAUX8 VTT_64 R3
1D5V_S0 AF30 P3
VCCAUX9 VTT_65
AE30 VCCAUX10 VTT_66 N3
2 R620 11D5V_QTVDAC_S0 AD30 VCCAUX11 VTT_67 M3
1
0R0603-PAD AC30 R2
C338 VCCAUX12 VTT_68
AG29 VCCAUX13 VTT_69 P2
SCD1U10V2KX-4GP AF29 M2
VCCAUX14 VTT_70
2
AE29 D2 VCCP_GMCH_CAP2
VCCAUX15 VTT_71 VCCP_GMCH_CAP1
AD29 VCCAUX16 VTT_72 AB1
1
AC29 VCCAUX17 VTT_73 R1
AG28 P1 C740 C744
VCCAUX18 VTT_74 SCD47U10V3ZY-GP
AF28 VCCAUX19 VTT_75 N1 SCD47U10V3ZY-GP
2
AE28 VCCAUX20 VTT_76 M1
AH22 VCCAUX21
AJ21 VCCAUX22
AH21 VCCAUX23
AJ20 VCCAUX24
AH20 VCCAUX25
AH19 VCCAUX26
1D5V_S0 P19
1D5V_AUX VCCAUX27
P16 VCCAUX28
AH15 VCCAUX29
1 R245 2 P15 VCCAUX30
0R0805-PAD AH14 VCCAUX31
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
AG14 VCCAUX32
1
C336 C314 C330 C334 AF14

1 VCCAUX33 <Variant Name> 1
AE14 VCCAUX34
Y14 VCCAUX35
2
AF13
AE13
VCCAUX36
VCCAUX37
Wistron Corporation
AF12 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
VCCAUX38 Taipei Hsien 221, Taiwan, R.O.C.
AE12 VCCAUX39
AD12 VCCAUX40 Title
CALISTOGA GMCH (4 of 5)
A3
AG1 SA
A B C D E
A B C D E
U71G
1D05V_S0 AA33 U71I
VCC_0 1D05V_S0
W33 VCC_1 AC41 VSS_0 VSS_97 AK34
P33 VCC_2 AA41 VSS_1 VSS_98 AG34
N33 U71F W41 AF34
VCC_3 VSS_2 VSS_99 U71J
L33 VCC_4 VCC_SM_0 AU41 AD27
VCC_NCTF0 T41 VSS_3 VSS_100 AE34
J33 VCC_5 VCC_SM_1 AT41 AC27
VCC_NCTF1 VSS_NCTF0 AE27 P41 VSS_4 VSS_101 AC34 AT23 VSS_180 VSS_273 J11
AA32 VCC_6 VCC_SM_2 AM41 AB27
VCC_NCTF2 VSS_NCTF1 AE26 M41 VSS_5 VSS_102 C34 AN23 VSS_181 VSS_274 D11
Y32 VCC_7 VCC_SM_3 AU40 AA27
VCC_NCTF3 VSS_NCTF2 AE25 J41 VSS_6 VSS_103 AW33 AM23 VSS_182 VSS_275 B11
W32 VCC_8 VCC_SM_4 BA34 Y27
VCC_NCTF4 VSS_NCTF3 AE24 F41 VSS_7 VSS_104 AV33 AH23 VSS_183 VSS_276 AV10
V32 VCC_9 VCC_SM_5 AY34 W27
VCC_NCTF5 VSS_NCTF4 AE23 AV40 VSS_8 VSS_105 AR33 AC23 VSS_184 VSS_277 AP10
P32 VCC_10 VCC_SM_6 AW34 V27
VCC_NCTF6 VSS_NCTF5 AE22 AP40 VSS_9 VSS_106 AE33 W23 VSS_185 VSS_278 AL10
N32 VCC_11 VCC_SM_7 AV34 U27
VCC_NCTF7 VSS_NCTF6 AE21 AN40 VSS_10 VSS_107 AB33 K23 VSS_186 VSS_279 AJ10
M32 VCC_12 VCC_SM_8 AU34 T27
VCC_NCTF8 VSS_NCTF7 AE20 AK40 VSS_11 VSS_108 Y33 J23 VSS_187 VSS_280 AG10
4 L32 VCC_13 VCC_SM_9 AT34 R27
VCC_NCTF9 VSS_NCTF8 AE19 AJ40 VSS_12 VSS_109 V33 F23 VSS_188 VSS_281 AC10 4
J32 VCC_14 VCC_SM_10 AR34 AD26
VCC_NCTF10 VSS_NCTF9 AE18 AH40 VSS_13 VSS_110 T33 C23 VSS_189 VSS_282 W10
AA31 VCC_15 VCC_SM_11 BA30 AC26
VCC_NCTF11 VSS_NCTF10 AC17 AG40 VSS_14 VSS_111 R33 AA22 VSS_190 VSS_283 U10
W31 VCC_16 VCC_SM_12 AY30 AB26
VCC_NCTF12 VSS_NCTF11 Y17 AF40 VSS_15 VSS_112 M33 K22 VSS_191 VSS_284 BA9
V31 VCC_17 VCC_SM_13 AW30 AA26
VCC_NCTF13 VSS_NCTF12 U17 AE40 VSS_16 VSS_113 H33 G22 VSS_192 VSS_285 AW9
T31 VCC_18 VCC_SM_14 AV30 Y26
VCC_NCTF14 B40 VSS_17 VSS_114 G33 F22 VSS_193 VSS_286 AR9
R31 AU30 W26 1D5V_AUX AY39 F33 E22 AH9
VCC_19 VCC_SM_15 VCC_NCTF15 VSS_18 VSS_115 VSS_194 VSS_287
P31 VCC_20 VCC_SM_16 AT30 V26
VCC_NCTF16 AW39 VSS_19 VSS_116 D33 D22 VSS_195 VSS_288 AB9
N31 VCC_21 VCC_SM_17 AR30 U26
VCC_NCTF17 AV39 VSS_20 VSS_117 B33 A22 VSS_196 VSS_289 Y9
M31 VCC_22 VCC_SM_18 AP30 T26
VCC_NCTF18 AR39 VSS_21 VSS_118 AH32 BA21 VSS_197 VSS_290 R9
AA30 VCC_23 VCC_SM_19 AN30 R26
VCC_NCTF19 VCCAUX_NCTF0 AG27 AN39 VSS_22 VSS_119 AG32 AV21 VSS_198 VSS_291 G9
Y30 VCC_24 VCC_SM_20 AM30 AD25
VCC_NCTF20 VCCAUX_NCTF1 AF27 AJ39 VSS_23 VSS_120 AF32 AR21 VSS_199 VSS_292 E9
W30 VCC_25 VCC_SM_21 AM29 AC25
VCC_NCTF21 VCCAUX_NCTF2 AG26 AC39 VSS_24 VSS_121 AE32 AN21 VSS_200 VSS_293 A9
V30 VCC_26 VCC_SM_22 AL29 AB25
VCC_NCTF22 VCCAUX_NCTF3 AF26 AB39 VSS_25 VSS_122 AC32 AL21 VSS_201 VSS_294 AG8
U30 VCC_27 VCC_SM_23 AK29 AA25
VCC_NCTF23 VCCAUX_NCTF4 AG25 AA39 VSS_26 VSS_123 AB32 AB21 VSS_202 VSS_295 AD8
T30 VCC_28 VCC_SM_24 AJ29 Y25
VCC_NCTF24 VCCAUX_NCTF5 AF25 Y39 VSS_27 VSS_124 G32 Y21 VSS_203 VSS_296 AA8
R30 VCC_29 VCC_SM_25 AH29 W25
VCC_NCTF25 VCCAUX_NCTF6 AG24 W39 VSS_28 VSS_125 B32 P21 VSS_204 VSS_297 U8
P30 VCC_30 VCC_SM_26 AJ28 V25
VCC_NCTF26 VCCAUX_NCTF7 AF24 V39 VSS_29 VSS_126 AY31 K21 VSS_205 VSS_298 K8
N30 VCC_31 VCC_SM_27 AH28 U25
VCC_NCTF27 VCCAUX_NCTF8 AG23 T39 VSS_30 VSS_127 AV31 J21 VSS_206 VSS_299 C8
M30 VCC_32 VCC_SM_28 AJ27 T25
VCC_NCTF28 VCCAUX_NCTF9 AF23 R39 VSS_31 VSS_128 AN31 H21 VSS_207 VSS_300 BA7
L30 VCC_33 VCC_SM_29 AH27 R25
VCC_NCTF29 VCCAUX_NCTF10 AG22 P39 VSS_32 VSS_129 AJ31 C21 VSS_208 VSS_301 AV7
AA29
Y29
W29
VCC_34
VCC_35
VCC_36
VCC_SM_30
VCC_SM_31
VCC_SM_32
BA26
AY26
AW26
AD24
VCC_NCTF30
AC24
VCC_NCTF31
AB24
VCC_NCTF32
VCCAUX_NCTF11 AF22
VCCAUX_NCTF12 AG21
VCCAUX_NCTF13 AF21
N39
M39
L39
VSS_33
VSS_34
VSS_35
VSS VSS_130
VSS_131
VSS_132
AG31
AB31
Y31
AW20
AR20
AM20
VSS_209
VSS_210
VSS_211 VSS
VSS_302
VSS_303
VSS_304
AP7
AL7
AJ7
V29 VCC_37 VCC_SM_33 AV26 AA24
VCC_NCTF33 VCCAUX_NCTF14 AG20 J39 VSS_36 VSS_133 AB30 AA20 VSS_212 VSS_305 AH7
U29 VCC_38 VCC_SM_34 AU26 Y24
VCC_NCTF34 VCCAUX_NCTF15 AF20 H39 VSS_37 VSS_134 E30 K20 VSS_213 VSS_306 AF7
R29 VCC_39 VCC_SM_35 AT26 W24
VCC_NCTF35 VCCAUX_NCTF16 AG19 G39 VSS_38 VSS_135 AT29 B20 VSS_214 VSS_307 AC7
P29 VCC_40 VCC_SM_36 AR26 V24
VCC_NCTF36 VCCAUX_NCTF17 AF19 F39 VSS_39 VSS_136 AN29 A20 VSS_215 VSS_308 R7
M29 VCC_41 VCC_SM_37 AJ26 U24
VCC_NCTF37 VCCAUX_NCTF18 R19 D39 VSS_40 VSS_137 AB29 AN19 VSS_216 VSS_309 G7
3 L29 AH26 T24 3
VCC_42 VCC_SM_38 VCC_NCTF38 VCCAUX_NCTF19 AG18 AT38 VSS_41 VSS_138 T29 AC19 VSS_217 VSS_310 D7
AB28 VCC_43 VCC_SM_39 AJ25 R24
VCC_NCTF39 VCCAUX_NCTF20 AF18 AM38 VSS_42 VSS_139 N29 W19 VSS_218 VSS_311 AG6
AA28 VCC_44 VCC_SM_40 AH25 AD23
VCC_NCTF40 VCCAUX_NCTF21 R18 AH38 VSS_43 VSS_140 K29 K19 VSS_219 VSS_312 AD6
Y28 VCC_45 VCC_SM_41 AJ24 V23
VCC_NCTF41 VCCAUX_NCTF22 AG17 AG38 VSS_44 VSS_141 G29 G19 VSS_220 VSS_313 AB6
V28 VCC_46 VCC_SM_42 AH24 U23
VCC_NCTF42 VCCAUX_NCTF23 AF17 AF38 VSS_45 VSS_142 E29 C19 VSS_221 VSS_314 Y6
U28 VCC_47 VCC_SM_43 BA23 T23
VCC_NCTF43 VCCAUX_NCTF24 AE17 AE38 VSS_46 VSS_143 C29 AH18 VSS_222 VSS_315 U6
T28 VCC_48 VCC_SM_44 AJ23 R23
VCC_NCTF44 VCCAUX_NCTF25 AD17 C38 VSS_47 VSS_144 B29 P18 VSS_223 VSS_316 N6
R28 VCC_49 VCC_SM_45 BA22 AD22
VCC_NCTF45 VCCAUX_NCTF26 AB17 AK37 VSS_48 VSS_145 A29 H18 VSS_224 VSS_317 K6
P28 VCC_50 VCC_SM_46 AY22 V22
VCC_NCTF46 VCCAUX_NCTF27 AA17 AH37 VSS_49 VSS_146 BA28 D18 VSS_225 VSS_318 H6
N28 VCC_51 VCC_SM_47 AW22 U22
VCC_NCTF47 VCCAUX_NCTF28 W17 AB37 VSS_50 VSS_147 AW28 A18 VSS_226 VSS_319 B6
M28 VCC_52 VCC_SM_48 AV22 T22
VCC_NCTF48 VCCAUX_NCTF29 V17 AA37 VSS_51 VSS_148 AU28 AY17 VSS_227 VSS_320 AV5
L28 VCC_53 VCC_SM_49 AU22 R22
VCC_NCTF49 VCCAUX_NCTF30 T17 Y37 VSS_52 VSS_149 AP28 AR17 VSS_228 VSS_321 AF5
P27
N27
M27
VCC_54
VCC_55
VCC_56
VCC_SM_50
VCC_SM_51
VCC_SM_52
AT22
AR22
AP22
AD21
VCC_NCTF50
V21
VCC_NCTF51
U21
VCC_NCTF52
VCCAUX_NCTF31 R17
VCCAUX_NCTF32 AG16
VCCAUX_NCTF33 AF16
NCTF W37
V37
T37
VSS_53
VSS_54
VSS_55
VSS_150
VSS_151
VSS_152
AM28
AD28
AC28
AP17
AM17
AK17
VSS_229
VSS_230
VSS_231
VSS_322
VSS_323
VSS_324
AD5
AY4
AR4
L27 VCC_57 VCC_SM_53 AK22 T21
VCC_NCTF53 VCCAUX_NCTF34 AE16 R37 VSS_56 VSS_153 W28 AV16 VSS_232 VSS_325 AP4
P26 VCC_58 VCC_SM_54 AJ22 R21
VCC_NCTF54 VCCAUX_NCTF35 AD16 P37 VSS_57 VSS_154 J28 AN16 VSS_233 VSS_326 AL4
N26 VCC_59 VCC_SM_55 AK21 AD20
VCC_NCTF55 VCCAUX_NCTF36 AC16 N37 VSS_58 VSS_155 E28 AL16 VSS_234 VSS_327 AJ4
L26 VCC_60 VCC_SM_56 AK20 V20
VCC_NCTF56 VCCAUX_NCTF37 AB16 M37 VSS_59 VSS_156 AP27 J16 VSS_235 VSS_328 Y4
N25 VCC_61 VCC_SM_57 BA19 U20
VCC_NCTF57 VCCAUX_NCTF38 AA16 L37 VSS_60 VSS_157 AM27 F16 VSS_236 VSS_329 U4
M25 VCC_62 VCC_SM_58 AY19 T20
VCC_NCTF58 VCCAUX_NCTF39 Y16 J37 VSS_61 VSS_158 AK27 C16 VSS_237 VSS_330 R4
L25 VCC_63 VCC_SM_59 AW19 R20
VCC_NCTF59 VCCAUX_NCTF40 W16 H37 VSS_62 VSS_159 J27 AN15 VSS_238 VSS_331 J4
P24 VCC_64 VCC_SM_60 AV19 AD19
VCC_NCTF60 VCCAUX_NCTF41 V16 G37 VSS_63 VSS_160 G27 AM15 VSS_239 VSS_332 F4
N24 VCC_65 VCC_SM_61 AU19 V19
VCC_NCTF61 VCCAUX_NCTF42 U16 F37 VSS_64 VSS_161 F27 AK15 VSS_240 VSS_333 C4
M24 VCC_66 VCC_SM_62 AT19 U19
VCC_NCTF62 VCCAUX_NCTF43 T16 D37 VSS_65 VSS_162 C27 N15 VSS_241 VSS_334 AY3
AB23 VCC_67 VCC_SM_63 AR19 T19
VCC_NCTF63 VCCAUX_NCTF44 R16 AY36 VSS_66 VSS_163 B27 M15 VSS_242 VSS_335 AW3
2
AA23
Y23
P23
VCC_68
VCC_69
VCC_70
VCC VCC_SM_64
VCC_SM_65
VCC_SM_66
AP19
AK19
AJ19
AD18
VCC_NCTF64
AC18
VCC_NCTF65
AB18
VCC_NCTF66
VCCAUX_NCTF45 AG15
VCCAUX_NCTF46 AF15
VCCAUX_NCTF47 AE15
AW36
AN36
AH36
VSS_67
VSS_68
VSS_69
VSS_164
VSS_165
VSS_166
AN26
M26
K26
L15
B15
A15
VSS_243
VSS_244
VSS_245
VSS_336
VSS_337
VSS_338
AV3
AL3
AH3
2
N23 VCC_71 VCC_SM_67 AJ18 AA18
VCC_NCTF67 VCCAUX_NCTF48 AD15 AG36 VSS_70 VSS_167 F26 BA14 VSS_246 VSS_339 AG3
M23 VCC_72 VCC_SM_68 AJ17 Y18
VCC_NCTF68 VCCAUX_NCTF49 AC15 AF36 VSS_71 VSS_168 D26 AT14 VSS_247 VSS_340 AF3
L23 VCC_73 VCC_SM_69 AH17 W18
VCC_NCTF69 VCCAUX_NCTF50 AB15 AE36 VSS_72 VSS_169 AK25 AK14 VSS_248 VSS_341 AD3
AC22 VCC_74 VCC_SM_70 AJ16 V18
VCC_NCTF70 VCCAUX_NCTF51 AA15 AC36 VSS_73 VSS_170 P25 AD14 VSS_249 VSS_342 AC3
AB22 VCC_75 VCC_SM_71 AH16 U18
VCC_NCTF71 VCCAUX_NCTF52 Y15 C36 VSS_74 VSS_171 K25 AA14 VSS_250 VSS_343 AA3
Y22 VCC_76 VCC_SM_72 BA15 T18
VCC_NCTF72 VCCAUX_NCTF53 W15 B36 VSS_75 VSS_172 H25 U14 VSS_251 VSS_344 G3
W22 VCC_77 VCC_SM_73 AY15 VCCAUX_NCTF54 V15 BA35 VSS_76 VSS_173 E25 K14 VSS_252 VSS_345 AT2
P22 VCC_78 VCC_SM_74 AW15 VCCAUX_NCTF55 U15 AV35 VSS_77 VSS_174 D25 H14 VSS_253 VSS_346 AR2
N22 VCC_79 VCC_SM_75 AV15 VCCAUX_NCTF56 T15 AR35 VSS_78 VSS_175 A25 E14 VSS_254 VSS_347 AP2
M22 VCC_80 VCC_SM_76 AU15 VCCAUX_NCTF57 R15 AH35 VSS_79 VSS_176 BA24 AV13 VSS_255 VSS_348 AK2
L22 VCC_81 VCC_SM_77 AT15 AB35 VSS_80 VSS_177 AU24 AR13 VSS_256 VSS_349 AJ2
AC21 VCC_82 VCC_SM_78 AR15 CALISTOGA AA35 VSS_81 VSS_178 AL24 AN13 VSS_257 VSS_350 AD2
AA21 VCC_83 VCC_SM_79 AJ15 Y35 VSS_82 VSS_179 AW23 AM13 VSS_258 VSS_351 AB2
W21 VCC_84 VCC_SM_80 AJ14 W35 VSS_83 AL13 VSS_259 VSS_352 Y2
N21 VCC_85 VCC_SM_81 AJ13 V35 VSS_84 AG13 VSS_260 VSS_353 U2
M21 VCC_86 VCC_SM_82 AH13 T35 VSS_85 P13 VSS_261 VSS_354 T2
L21 VCC_87 VCC_SM_83 AK12 R35 VSS_86 F13 VSS_262 VSS_355 N2
AC20 VCC_88 VCC_SM_84 AJ12 P35 VSS_87 D13 VSS_263 VSS_356 J2
1
AB20 VCC_89 VCC_SM_85 AH12 N35 VSS_88 B13 VSS_264 VSS_357 H2

Y20 AG12 C320 C337 C317 C319 C333 C335 C318 TC20 M35 AY12 F2
VCC_90 VCC_SM_86 SC10U10V5ZY-1GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP ST220U2VBM-3GP VSS_89 VSS_265 VSS_358
W20 VCC_91 VCC_SM_87 AK11 L35 VSS_90 AC12 VSS_266 VSS_359 C2
2
P20 BA8 SC10U10V5ZY-1GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP J35 K12 AL1

VCC_92 VCC_SM_88 VSS_91 VSS_267 VSS_360
N20 VCC_93 VCC_SM_89 AY8 H35 VSS_92 H12 VSS_268
M20 VCC_94 VCC_SM_90 AW8 Place these Caps close VCC_0 ~ VCC_110 G35 VSS_93 E12 VSS_269
L20 VCC_95 VCC_SM_91 AV8 F35 VSS_94 AD11 VSS_270
AB19 VCC_96 VCC_SM_92 AT8 D35 VSS_95 AA11 VSS_271
AA19 VCC_97 VCC_SM_93 AR8 AN34 VSS_96 Y11 VSS_272
Y19 AP8 1D8V_S3
VCC_98 VCC_SM_94
1 N19 VCC_99 VCC_SM_95 BA6 <Variant Name> CALISTOGA 1
M19 AY6 CALISTOGA
VCC_100 VCC_SM_96
L19 AW6
SC10U10V5ZY-1GP
VCC_101 VCC_SM_97
ST220U2VBM-3GP
N18 VCC_102 VCC_SM_98 AV6

Wistron Corporation
1
1
C708 C360 C331 C359 C399 C695 C709 C686 C313
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
M18 AT6
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
VCC_103 VCC_SM_99
1
TC21 DY C736 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

SCD1U10V2KX-4GP
L18 VCC_104 VCC_SM_100 AR6

P17 AP6 DY Taipei Hsien 221, Taiwan, R.O.C.
VCC_105 VCC_SM_101
2
N17 VCC_106 VCC_SM_102 AN6

2
M17 AL6 Title

VCC_107 VCC_SM_103
N16
M16
VCC_108
VCC_109
VCC_SM_104
VCC_SM_105
AK6
AJ6 GMCH (5 of 5)
L16 AV1 Size Document Number Rev
VCC_110 VCC_SM_106 A3
VCC_SM_107 AJ1
CALISTOGA AG1 SA
A B C D E
A B C D E
8,12 M_A_A[13..0] DM2

DM1 M_A_A0 102 108 M_A_RAS# 8,12
8,12 M_B_A[13..0] A0 /RAS
M_B_A0 102 108 M_B_RAS# 8,12 M_A_A1 101 109 M_A_WE# 8,12
M_B_A1 A0 /RAS M_A_A2 A1 /WE
101 A1 /WE 109 M_B_WE# 8,12 100 A2 /CAS 113 M_A_CAS# 8,12
M_B_A2 100 113 M_B_CAS# 8,12 M_A_A3 99
M_B_A3 A2 /CAS M_A_A4 A3
99 A3 98 A4 /CS0 110 M_CS0# 7,12
M_B_A4 98 110 M_CS2# 7,12 M_A_A5 97 115 M_CS1# 7,12
M_B_A5 A4 /CS0 M_A_A6 A5 /CS1
97 A5 /CS1 115 M_CS3# 7,12 94 A6
M_B_A6 94 M_A_A7 92 79 M_CKE0 7,12
M_B_A7 A6 M_A_A8 A7 CKE0
92 A7 CKE0 79 M_CKE2 7,12 93 A8 CKE1 80 M_CKE1 7,12
M_B_A8 93 80 M_CKE3 7,12 M_A_A9 91
4 A8 CKE1 A9 4
M_B_A9
M_B_A10
91 A9
M_A_A10
M_A_A11
105 A10/AP CK0 30 M_CLK_DDR0 7 Place near DM1
105 A10/AP CK0 30 M_CLK_DDR3 7 90 A11 /CK0 32 M_CLK_DDR#0 7
M_B_A11 90 32 M_CLK_DDR#3 7 M_A_A12 89
M_B_A12 A11 /CK0 M_A_A13 A12
89 A12 116 A13 CK1 164 M_CLK_DDR1 7
M_B_A13 116 164 M_CLK_DDR2 7 86 166 M_CLK_DDR#1 7 M_CLK_DDR0
A13 CK1 A14 /CK1
86 A14 /CK1 166 M_CLK_DDR#2 7 84 A15 M_A_DM[7..0] 8
1
84 M_B_DM[7..0] 8 8,12 M_A_BS#2 85 10 M_A_DM0 DY
A15 M_B_DM0 A16/BA2 DM0 M_A_DM1 C329
8,12 M_B_BS#2 85 A16/BA2 DM0 10 DM1 26
26 M_B_DM1 107 52 M_A_DM2 SC10P50V2JN-4GP
DM1 8,12 M_A_BS#0 BA0 DM2
2
8,12 M_B_BS#0 107 52 M_B_DM2 8,12 M_A_BS#1 106 67 M_A_DM3 M_CLK_DDR#0
BA0 DM2 M_B_DM3 BA1 DM3 M_A_DM4
8,12 M_B_BS#1 106 BA1 DM3 67 DM4 130
130 M_B_DM4 M_A_DQ0 5 147 M_A_DM5 M_CLK_DDR1
M_B_DQ0 DM4 M_B_DM5 M_A_DQ1 DQ0 DM5 M_A_DM6
5 DQ0 DM5 147 8 M_A_DQ[63..0] 7 DQ1 DM6 170
1
M_B_DQ1 7 170 M_B_DM6 M_A_DQ2 17 185 M_A_DM7 DY
8 M_B_DQ[63..0] DQ1 DM6 DQ2 DM7
M_B_DQ2 17 185 M_B_DM7 M_A_DQ3 19 C449
M_B_DQ3 DQ2 DM7 M_A_DQ4 DQ3 SMBD_ICH SC10P50V2JN-4GP
19 DQ3 4 DQ4 SDA 195
2
M_B_DQ4 4 195 SMBD_ICH 3,18 M_A_DQ5 6 197 SMBC_ICH M_CLK_DDR#1
M_B_DQ5 DQ4 SDA 3D3V_S0 M_A_DQ6 DQ5 SCL
6 DQ5 SCL 197 SMBC_ICH 3,18 14 DQ6
M_B_DQ6 14 M_A_DQ7 16 199
DQ6 DQ7 VDDSPD 3D3V_S0
M_B_DQ7 16 199 M_A_DQ8 23
DQ7 VDDSPD DQ8
1
M_B_DQ8 23 M_A_DQ9 25 198
M_B_DQ9 DQ8 M_A_DQ10 DQ9 SA0 BC7
25 DQ9 SA0 198 35 DQ10 SA1 200
M_B_DQ10 35 200 1 R363 2 M_A_DQ11 37 SCD1U16V2ZY-2GP
DQ10 SA1 DQ11
2
M_B_DQ11 37 10KR2J-3-GP M_A_DQ12 20 50
DQ11 DQ12 NC#50
1
M_B_DQ12 20 50 BC6 M_A_DQ13 22 69
M_B_DQ13 DQ12 NC#50 SCD1U16V2ZY-2GP M_A_DQ14 DQ13 NC#69
22 DQ13 NC#69 69 36 DQ14 NC#83 83
M_B_DQ14 36 83 M_A_DQ15 38 120
DQ14 NC#83 DQ15 NC#120
2
M_B_DQ15 38 120 M_A_DQ16 43 163
M_B_DQ16 DQ15 NC#120 M_A_DQ17 DQ16 NC#163/TEST
43 DQ16 NC#163/TEST 163 45 DQ17
M_B_DQ17 45 M_A_DQ18 55
DQ17 DQ18
M_B_DQ18
M_B_DQ19
55 DQ18 Place near DM2 M_A_DQ19
M_A_DQ20
57 DQ19 VDD 81
3 57 DQ19 VDD 81 44 DQ20 VDD 82 3
M_B_DQ20 44 82 M_A_DQ21 46 87
M_B_DQ21 DQ20 VDD M_CLK_DDR3 M_A_DQ22 DQ21 VDD
46 87 56 88
NORMAL TYPE
NORMAL TYPE
M_B_DQ22 DQ21 VDD M_A_DQ23 DQ22 VDD
56 DQ22 VDD 88 58 DQ23 VDD 95
1
M_B_DQ23 58 95 M_A_DQ24 61 96
M_B_DQ24 DQ23 VDD C326 M_A_DQ25 DQ24 VDD
M_B_DQ25
61 DQ24 VDD 96 DY SC10P50V2JN-4GP M_A_DQ26
63 DQ25 VDD 103
63 DQ25 VDD 103 73 DQ26 VDD 104
2
M_B_DQ26 73 104 M_CLK_DDR#3 M_A_DQ27 75 111
75 DQ27 VDD 111 62 DQ28 VDD 112
M_B_DQ28 62 112 M_CLK_DDR2 M_A_DQ29 64 117
64 DQ29 VDD 117 74 DQ30 VDD 118 1D8V_S3
1
M_B_DQ30 74 118 DY M_A_DQ31 76
DQ30 VDD 1D8V_S3 DQ31
M_B_DQ31 76 C448 M_A_DQ32 123 3
M_B_DQ32 DQ31 SC10P50V2JN-4GP M_A_DQ33 DQ32 VSS
123 DQ32 VSS 3 125 DQ33 VSS 8
2
M_B_DQ33 125 8 M_CLK_DDR#2 M_A_DQ34 135 9
M_B_DQ34 DQ33 VSS M_A_DQ35 DQ34 VSS
135 DQ34 VSS 9 137 DQ35 VSS 12
M_B_DQ35 137 12 M_A_DQ36 124 15
124 DQ36 VSS 15 126 DQ37 VSS 18
M_B_DQ37 126 18 M_A_DQ38 134 21
134 DQ38 VSS 21 136 DQ39 VSS 24
M_B_DQ39 136 24 M_A_DQ40 141 27
141 DQ40 VSS 27 143 DQ41 VSS 28
M_B_DQ41 143 28 M_A_DQ42 151 33
151 DQ42 VSS 33 153 DQ43 VSS 34
M_B_DQ43 153 34 M_A_DQ44 140 39
140 DQ44 VSS 39 142 DQ45 VSS 40
M_B_DQ45 142 40 M_A_DQ46 152 41
152 DQ46 VSS 41 154 DQ47 VSS 42
M_B_DQ47 154 42 M_A_DQ48 157 47
157 DQ48 VSS 47 159 DQ49 VSS 48
M_B_DQ49 159 48 M_A_DQ50 173 53
2 173 DQ50 VSS 53 175 DQ51 VSS 54 2
M_B_DQ51 175 54 M_A_DQ52 158 59
158 DQ52 VSS 59 160 DQ53 VSS 60
M_B_DQ53 160 60 M_A_DQ54 174 65
174 DQ54 VSS 65 176 DQ55 VSS 66
M_B_DQ55 176 66 M_A_DQ56 179 71
179 DQ56 VSS 71 181 DQ57 VSS 72
M_B_DQ57 181 72 M_A_DQ58 189 77
189 DQ58 VSS 77 191 DQ59 VSS 78
M_B_DQ59 191 78 M_A_DQ60 180 121
180 DQ60 VSS 121 182 DQ61 VSS 122
M_B_DQ61 182 122 M_A_DQ62 192 127
192 DQ62 VSS 127 194 DQ63 VSS 128
M_B_DQ63 194 128 132
DQ63 VSS M_A_DQS#0 VSS
VSS 132 11 /DQS0 VSS 133
M_B_DQS#0 11 133 M_A_DQS#1 29 138
/DQS0 VSS 8 M_A_DQS#[7..0] /DQS1 VSS
M_B_DQS#1 29 138 M_A_DQS#2 49 139
8 M_B_DQS#[7..0] /DQS1 VSS /DQS2 VSS
M_B_DQS#2 49 139 M_A_DQS#3 68 144
M_B_DQS#3 /DQS2 VSS M_A_DQS#4 /DQS3 VSS
68 /DQS3 VSS 144 129 /DQS4 VSS 145
M_B_DQS#4 129 145 M_A_DQS#5 146 149
M_B_DQS#5 /DQS4 VSS M_A_DQS#6 /DQS5 VSS
146 /DQS5 VSS 149 167 /DQS6 VSS 150
M_B_DQS#6 167 150 M_A_DQS#7 186 155
M_B_DQS#7 /DQS6 VSS /DQS7 VSS
186 /DQS7 VSS 155 VSS 156
156 M_A_DQS0 13 161
M_B_DQS0 VSS M_A_DQS1 DQS0 VSS
13 DQS0 VSS 161 8 M_A_DQS[7..0] 31 DQS1 VSS 162
M_B_DQS1 31 162 M_A_DQS2 51 165
8 M_B_DQS[7..0] DQS1 VSS DQS2 VSS
M_B_DQS2 51 165 M_A_DQS3 70 168
M_B_DQS3 DQS2 VSS M_A_DQS4 DQS3 VSS
70 DQS3 VSS 168 131 DQS4 VSS 171
M_B_DQS4 131 171 M_A_DQS5 148 172
M_B_DQS5 DQS4 VSS M_A_DQS6 DQS5 VSS
148 DQS5 VSS 172 169 DQS6 VSS 177
M_B_DQS6 169 177 M_A_DQS7 188 178
M_B_DQS7 DQS6 VSS DQS7 VSS
188 DQS7 VSS 178 VSS 183
1 183 114 184 1
VSS 7,12 M_ODT0 ODT0 VSS
7,12 M_ODT2 114 ODT0 VSS 184 7,12 M_ODT1 119 ODT1 VSS 187 <Variant Name>
7,12 M_ODT3 119 ODT1 VSS 187 DDR_VREF_S3 VSS 190
190 DDR_VREF_S3 1 193
DDR_VREF_S3 VSS VREF VSS
1 193 2 196
Wistron Corporation
SC2D2U6D3V3MX-1-GP
VREF VSS VSS VSS

1
2 196 C696 BC10

SC2D2U6D3V3MX-1-GP
VSS VSS
1
C328 BC4 DY 202 201 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
SCD1U16V2ZY-2GP GND GND
DY SCD1U16V2ZY-2GP 202 GND GND 201 Taipei Hsien 221, Taiwan, R.O.C.
2
DDR2-200P-4-GP 62.10017.761
2
DDR2-200P-5-GP 62.10017.771 Title

High 9.2mm
High 5.2mm 2nd source:62.10017.A61
DDR2 Socket
2nd source:62.10017.661 Custom
AG1 SB
A B C D E
A B C D E
PARALLEL TERMINATION Decoupling Capacitor

Put decap near power(0.9V) and pull-up resistor
DDR_VREF_S0
Put decap near power(0.9V)
DDR_VREF_S0
8
RN55
1 M_CKE2 7,11
and pull-up resistor
7 2 M_B_BS#2 8,11
4 6 3 M_B_A12 M_A_A[13..0] 8,11 4
5 4 M_B_A9
1
M_B_A[13..0] 8,11
SRN56J-2-GP C435 C419 C413 C387 C386 C411 C384 C412 C438 C385 C391
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
2
1 2
R314 2 56R2J-4-GP
M_ODT1 7,11 DY DY
1 M_ODT3 7,11
1 R312 2 56R2J-4-GP M_A_A9
1 R315 2 56R2J-4-GP M_B_A8
R313 56R2J-4-GP
1
RN62
8 1 M_B_A5 C418 C396 C415 C434 C436 C398 C397 C409 C408 C407 C437
7 2 M_B_A3 SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
2
6 3 M_B_A1 DY DY
5 4 M_B_A10
SRN56J-2-GP
RN60
8 1 M_B_A13
7 2 M_ODT2 7,11
6 3 M_CS2# 7,11
5 4 M_B_RAS# 8,11 1D8V_S3
SRN56J-2-GP Place these Caps near DM1
RN59
8 1 M_B_BS#1 8,11
1
7 2 M_B_A0
3 6 3 M_B_A2 C734 C735 C394 C395 C417 3
5 4 M_B_A4 SC2D2U6D3V3MX-1-GP SC2D2U6D3V3MX-1-GP SC2D2U6D3V3MX-1-GP SC2D2U6D3V3MX-1-GP SC2D2U6D3V3MX-1-GP
2
SRN56J-2-GP
RN54
8 1 M_B_A6
7 2 M_B_A7
1
6 3 M_B_A11
5 4 M_CKE3 7,11 C389 C414 C388 C410
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
2
SRN56J-2-GP DY DY DY
RN61
8 1 M_B_BS#0 8,11
7 2 M_B_WE# 8,11
6 3 M_CS3# 7,11
5 4 M_B_CAS# 8,11
SRN56J-2-GP 1D8V_S3
Place these Caps near DM2
RN63
8 1 M_A_A13
7 2 M_ODT0 7,11
1
6 3 M_CS0# 7,11
5 4 M_A_RAS# 8,11 C733 C392 C390 C759 C761
SC2D2U6D3V3MX-1-GP SC2D2U6D3V3MX-1-GP SC2D2U6D3V3MX-1-GP SC2D2U6D3V3MX-1-GP SC2D2U6D3V3MX-1-GP
2
SRN56J-2-GP
2 2
RN65
8 1 M_A_BS#1 8,11
7 2 M_A_A0
6 3 M_A_A2 1
1
5 4 M_A_A4
C382 C383 C416 C393
SRN56J-2-GP SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
2
2
DY DY DY
RN66
8 1 M_A_BS#0 8,11
7 2 M_A_WE# 8,11
6 3 M_A_CAS# 8,11
5 4 M_CS1# 7,11
SRN56J-2-GP
RN56
8 1 M_CKE0 7,11
7 2 M_A_BS#2 8,11
6 3 M_A_A12
5 4 M_A_A8
SRN56J-2-GP
RN64
8 1 M_A_A6
7 2 M_A_A7
6 3 M_A_A11
1 5 4 M_CKE1 7,11 <Variant Name> 1
SRN56J-2-GP
RN67 Wistron Corporation

8 1 M_A_A5 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
7 2 M_A_A3 Taipei Hsien 221, Taiwan, R.O.C.
6 3 M_A_A1
5 4 M_A_A10 Title
SRN56J-2-GP DDR2 Termination Resistor

A3
AG1 SA
A B C D E
3D3V_S0
LAUNCH1
14 LAUNCH BD CONN CCD Pin LCD/INVERTER/CCD CONN D41
3D3V_S0
12 Pin Symbol LCD1 5V_S0 1 2 5VCCD
11 INT_MICP 29 3D3V_AUX_S5 EC3
10 1 2 1 5V 43 41 1N4148W-7-F-GP 1 2
9 EC52 SCD01U16V2KX-3GP
2
EMAIL_LED# 1 2 USB- 1 R169 2 SCD1U10V2KX-4GP
Launch
SC1KP16V2KX-GP
SC1KP16V2KX-GP
8 2 MH1 1
1
7 EC15 SC100P50V2JN-3GP R72 0R2J-2-GP EC4 EC6 EC5
MAIL# 3 USB+ VCC_CCD 3VCCD
6
5 INTERNET#
MAIL# 31 100KR2J-1-GP 12 1 45
2
3
1 2
INTERNET# 31
2
4 EBUTTON# EBUTTON# 31 4 GND 4 SCD1U10V2KX-4GP EDID_CLK 46 LCDVDD_S0
1
3 PROGRAM# PROGRAM# 31 5 EDID_DAT 46
2 PWRBTN# 1 R120 2 EC_PWRBTN# 31 5 GND 6
470R2J-2-GP 7
1
1 SCD1U10V2KX-4GP 8
SC10U10V5ZY-1GP
SCD1U16V2ZY-2GP
1
1
13 C127 Inverter Pin 9 C19 C12
ATI_TXACLK- 48
1
4
3
2
1
EC16 RC1 SCD1U16V2ZY-2GP 10 ATI_TXACLK+ 48
2
ACES-CON12-GP Pin Symbol 11 DY
SRC100P50V-2-GP
2
20.K0174.012 12 ATI_TXAOUT2- 48
2
1 Vin 13 ATI_TXAOUT2+ 48
14
5
6
7
8
2nd source: 20.K0185.012 2 Vin 15 ATI_TXAOUT1- 48
Q12 16
GND 2 ATI_TXAOUT1+ 48
3 PWM 17 EVEN CHANNEL
LCDVDD_S0 3D3V_S0 18 ATI_TXAOUT0- 48
3 OUT CAP_LED# Layout 40 mil 4 BLON 19 ATI_TXAOUT0+ 48
R2 U2 20
IN R1
31 CAP_LED 1 Layout 40 mil 5 GND 21 ATI_TXBOUT0- 48
84.00124.F1K 1 6 22
CHDTC124EU-1GP OUT IN ATI_TXBOUT0+ 48
2 GND GND 5 6 GND 23
Q13 48 ATI_LCDVDD_ON 3 4 24
GND 2 ON/OFF# IN ATI_TXBOUT1- 48
25 ATI_TXBOUT1+ 48
1
C9 C8 Launch BD 26
3 OUT NUM_LED# AAT4280IGU-3-T1GP C20 27 ATI_TXBOUT2- 48 ODD CHANNEL
R2 SC1U10V3KX-3GP SCD1U50V3KX-GP SC1U10V3KX-3GP Pin Symbol 28 ATI_TXBOUT2+ 48
2
IN R1 74.04280.B9P
31 NUM_LED 1 29
84.00124.F1K 1 3V_S0 30
CHDTC124EU-1GP ATI_TXBCLK- 48
31 ATI_TXBCLK+ 48
Q40 2 PWRBTN# 32
GND 2 33 BRIGHTNESS BRIGHTNESS 31
3 PROGRAM# 34 BLON_OUT 31
3 OUT EMAIL_LED#
SC1KP16V2KX-GP
SC1KP16V2KX-GP
35
2
R2 4 EBUTTON# 36 1 2 EC31 EC32
R1 USB_PN5 16
IN 1 37 R4751 0R2J-2-GP
2 R9
31 EMAIL_LED USB_PP5 16
84.00124.F1K 5 INTERNET# 46 38 R474 0R2J-2-GP DCBATOUT 100KR2J-1-GP
2
CHDTC124EU-1GP 39 SC modify
Q42 6 MAIL# MH2 40
1
GND 2 3D3V_S5
Layout 60 mil
SC1U50V5ZY-1-GP
LED6 7 NC 44 42
1
3 OUT STDBY_LED#1 R709 on Front Panel C554 C553
SCD1U25V3KX-GP
2 K A
R2 100R2J-2-GP LED-Y-47-GP 8 MAIL_LED# IPEX-CON40-2-GP
IN R1 EC53
83.00190.D7A 20.F0763.040
TOP VIEW
31 STDBY_LED 1
2
84.00124.F1K 1 2 9 PWR_B_LED#
CHDTC124EU-1GP SCD1U10V2KX-4GP L29 DY
Q41
LCD
GND 2 3D3V_S0
10 NC 1 2
LED5 11 INT_MICP
3 OUT PWRLED# 1 R708 2 2 1 on Front Panel 4 3
R2 100R2J-2-GP LED-G-62-GP FILTER-79-GP
31 PWRLED
IN 1
R1 83.00190.Q70 EC54
12 INT_MICN
69.10084.071 40 1
84.00124.F1K 1 2
CHDTC124EU-1GP SCD1U10V2KX-4GP
GND 2
Q20
LED4
3D3V_S5
Charger:
OFF : Battery or DC only
LED BD CONN 3D3V_S0 5V_S0
3 OUT CHRGER_LED#1 R445 3D3V_S0
R2
2 K A on Front Panel Orange : Charging
100R2J-2-GP LED-Y-47-GP
SCD1U10V2KX-4GP
R1 Orange Blink : Battery low
1
IN 1 83.00190.D7A
31 CHRGER_LED
1
84.00124.F1K EC33
CHDTC124EU-1GP Power: LEDB1 R236 SATA Dummy when use IDE R235
10KR2J-3-GP
Q24 10 4K7R2J-2-GP
Green : S0
2
GND 2
on Front Panel 8 SATA
2
LED3 Orange : S3 7 D22
2
3 OUT DC_BATFULL# 1 R444 2 2 1 6 2 CDROM_LED# 20 2 R233 1
R2 100R2J-2-GP LED-G-62-GP Orange Blinking : Enter S4 5 MEDIA_LED# 3 0R2J-2-GP SATA_LED# 15
IN R1 83.00190.Q70 NUM_LED# R798 1
31 DC_BATFULL 1 4 2
84.00124.F1K 5V_S0 3 CAP_LED# 1 HDLED# 0R2J-2-GP 2 R234 1
CHDTC124EU-1GP 0R2J-2-GP HDD_LED# 20
2
Q26 PATA
GND 2
on Front Panel BAW56PT-U
83.00056.E11 PATA
1
LED1 LED-B-27-U-GP 9 -1 modify Dummy when use SATA
3 OUT BT_LED# 1 R430 2 2 1
R2 330R2J-3-GP 83.00190.P70 MLX-CON8-7-GP-U
IN R1 20.K0185.008
31 BLUETOOTH_LED 1
84.00124.F1K 3D3V_S0
CHDTC124EU-1GP
1st source: 20.K0228.008 SRC100P50V-2-GP
RC9
CHRGER_LED#
DY
1 R431 2 K
LED2
A
on Front Panel 8 DC_BATFULL#
1
2
8
7
26 WLAN_LED# 100R2J-2-GP LED-Y-47-GP 3D3V_S0 PWRLED#
RN78 3 6
83.00190.D7A STDBY_LED# 4 5
31 BT_BTN# 1 4 RC2
31 WIRELESS_BTN# 2 3 SRC100P50V-2-GP DY <Variant Name>
MEDIA_LED#
1 NUM_LED
1
2
8
7
SRN10KJ-5-GP CAP_LED
1 3 3
4
6
BTBTN1 WLBTN1 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
4 1 1 4 EC29 DY Taipei Hsien 221, Taiwan, R.O.C.
BT_LED#
Front panel 2nd source: 62.40066.001 2 2
1 2
SC100P50V2JN-3GP Title
LED V V V V 3 3 EC30 DY LCD / LAUNCH / LEDs
5 5 Edge Trigger WLAN_LED# 1 2
Button V V SC100P50V2JN-3GP Size Document Number Rev
SW-SLIDE47-GP SW-SLIDE47-GP Custom
BlutTooth Wireless Charger Power2 62.40018.251 62.40018.251 AG1 -1
A B C D E
Layout Note:
Place these resistors
CRT I/F & CONNECTOR
close to the CRT-out
connector
Ferrite bead impedance: 10 ohm@100MHz 5V_S0
L17
46 ATI_RED 1 2 CRT_R 5V_CRT_S0
2
FCB1608CF-GP
3D3V_S0 D2
L18 CH751H-40PT
46 ATI_GREEN 1 2 CRT_G
1
1
4 FCB1608CF-GP 4
R6 C2
SCD01U16V2KX-3GP
L19
4
3
10KR2J-3-GP
46 ATI_BLUE 1 2 CRT_B RN3
2
FCB1608CF-GP SRN10KJ-5-GP
SC3P50V2CN-1-GP
SC3P50V2CN-1-GP
SC3P50V2CN-1-GP
1
1
C541 C543 C545 C542 C544 C546 CRT1
R456 R457 R458 17
150R2F-1-GP
150R2F-1-GP
150R2F-1-GP
SC6D8P50V2DN-GP
SC6D8P50V2DN-GP
SC6D8P50V2DN-GP
2
1
2
DY DY DY 6
CRT_R
31 CRT_IN# 11 1
2
7
DAT_DDC1_5 12 2 CRT_G
8
JVGA_HS CRT_B
Layout Note: 13 3
9
* Must be a ground return path between this ground and the ground on -1 for CRT SIV Fail JVGA_VS 14 4
10 1 R455 2CRT_IN#
the VGA connector. CLK_DDC1_5 15 5 0R2J-2-GP
DY
Pi-filter & 150 Ohm pull-down resistors should be as close as to CRT
2
16
R461
CONN. RGB will hit 75 Ohm first, pi-filter, then CRT CONN.
1
VIDEO-15-42-GP-U 0R2J-2-GP
1
C3 20.20378.015
SC100P50V2JN-3GP C4 C6
1
SC100P50V2JN-3GP SC18P50V2JN-1-GP
2
1
1
3 C7 C5 3
SC100P50V2JN-3GP SC18P50V2JN-1-GP
2
Hsync & Vsync level shift -1 for CRT SIV Fail
5V_S0
DDC_CLK & DATA level shift
1
3D3V_S0
C539
SCD1U16V2ZY-2GP
2
U59A
14
4
3
RN4
46 ATI_HSY 1 R451 2 HSYNC_4 2 3 JVGA_HS SRN2K2J-1-GP
47R2J-2-GP
TSAHCT125PW-GP
U59B
For System CRT
14
1
2
4
1
G
46 ATI_VSY 1 R449 2 VSYNC_4 5 6 JVGA_VS
47R2J-2-GP 2 3 DAT_DDC1_5
TSAHCT125PW-GP
2 Q3 2
D
46 ATI_DDCDAT
7
2N7002-8-GP
1
G
46 ATI_DDCCLK
2 3 CLK_DDC1_5
Q4
D
2N7002-8-GP
2 C705 TVOUT1
TV OUT CONN
1
L26 TV SC33P50V3JN-GP 9
5V_S0 5V_S0
3
1 2 CRMA_1 6
46 ATI_TV_CRMA IND-1D2UH-5-GP 7
1
TV TV TV C706 5 D23 2 D32 2

R621 C704 2
150R2F-1-GP SC150P-GP SC270P50V2JN-2GP LUMA_1 3 CRT_R 3
TV 4
2
TV
1 TV 1 1
2
1 2 C690 8
SC33P50V3JN-GP BAV99PT-GP-U BAV99PT-GP-U
L24 TV MINDIN7-11-U1-GP
1 2 LUMA_1 22.10021.D81
46 ATI_TV_LUMA IND-1D2UH-5-GP D25 D33
2 2
1
R617
TV C689
TV TV C693 CRMA_1 3 CRT_G 3
<Variant Name>
1 TV Reverse type 1
150R2F-1-GP SC150P-GP SC270P50V2JN-2GP
TV
2
1 1
Wistron Corporation
2
1 2 C691 BAV99PT-GP-U BAV99PT-GP-U 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
L25 TV SC33P50V3JN-GP D24 D34
2 2
1 2 COMP_1 Title
46 ATI_TV_COMP IND-1D2UH-5-GP COMP_1 3 CRT_B 3
CRT/TV Connector
1
R616
TV C688
TV TV C692 TV Size Document Number Rev
TV 150R2F-1-GP SC150P-GP SC270P50V2JN-2GP
1 1
A3
AG1 -1
2
BAV99PT-GP-U BAV99PT-GP-U
2
A B C D E
A B C D E
1 2
4 4
C234 SC4D7P50V3DN-1GP 1D05V_S0
1
3
4
R567
X1 56R2J-4-GP
1
X-32D768KHZ-41GP
3D3V_AUX_S5 RTC_AUX_S5 82.30001.731 R164
DY
2
D19 10MR2J-L-GP H_DPSLP#
2 1
1
1
2
C135
CH751H-40PT SC1U10V3ZY-6GP
2
RTC circuitry 1 2
U20A LPC_LAD[0..3] 31
RCT_X1 AB1 AA6 LPC_LAD0
RTC1 1KR2J-1-GP C236 SC4D7P50V3DN-1GP RCT_X2AB2 RTXC1 LAD0 LPC_LAD1
R123 RTCX2 LAD1 AB5
4 D20 AC4 LPC_LAD2
LPC
LAD2
RTC
1 BAT
1 2BAT_D
2 1 1 2 RTC_RST# AA3 Y6 LPC_LAD3
R540 20KR2J-L2-GP RTCRST# LAD3 3D3V_S0 Open R168 for Dothan A step
2 1 2 INTRUDER# Y5 AC3 Shunt for Dothan B step
CH751H-40PT INTRUDER# LDRQ0# LPC_LDRQ0# 32
3 R541 1MR2J-1-GP INTVRMEN W4 AA5 1 R559
2 & all Yonah
INTVRMEN LDRQ1#/GPIO23
2
1
5 10KR2J-3-GP
C133 C178 W1 AB3 LPC_LFRAME# 31
ACES-CON3-GP SC1U10V3ZY-6GP EE_CS LFRAME# 1D05V_S0
SCD1U16V2ZY-2GP Y1 EE_SHCLK
1
2
20.F0714.003 Y2 AE22 K_A20GATE 31
DY W3
EE_DOUT A20GATE
AH28 H_A20M# 4
EE_DIN A20M#
1
2nd source: 20.D0198.103 H_CPUSLP#_2
3 V3 LAN_CLK CPUSLP# AG27 1 R170 2DY H_CPUSLP# 4,6 R565 3
0R2J-2-GP 56R2J-4-GP
U3 AF24 H_DPRSLP#_2 1 R168 2 H_DPRSLP# 4,38
LAN
CPU
LAN_RSTSYNC TP1/DPRSTP#
TP2/DPSLP# AH25 H_DPSLP# 0R0402-PAD
4
2
U5 LAN_RXD0
V4 LAN_RXD1 FERR# AG26 H_FERR# 4
T5 LAN_RXD2
GPIO49/CPUPWRGD AG24 H_PWRGD 4,36
U7 1D05V_S0
AC97_BTCLK 2 R124 1 LAN_TXD0
28 AC97_BTCLK V6 LAN_TXD1
22R2J-2-GP V7 AG22 H_IGNNE# 4 H_PWRGD 1 R563 2
LAN_TXD2 IGNNE# 200R2F-L-GP
INIT3_3V# AG21 FWH_INIT# 34
21 ACZ_BTCLK_MDC 2 R126 1 ACZ_BIT_CLK U1 AF22 H_INIT# 4
22R2J-2-GP ACZ_SYNC_R ACZ_BIT_CLK INIT# DY
AC-97/AZALIA
21,28 ACZ_SYNC 1 2 R6 ACZ_SYNC INTR AF25 H_INTR 4
R547 39R2J-L-GP 1D05V_S0
21,28 ACZ_RST# 1 2 ACZ_RST#_R R5 AG23 H_RCIN# 31 -1 Modify
R545 39R2J-L-GP ACZ_RST# RCIN#
1
28 ACZ_SDATAIN0 T2 ACZ_SDIN0 NMI AH24 H_NMI 4
21 ACZ_SDATAIN1 T3 AF23 H_SMI# 4 R568
ACZ_SDIN1 SMI#
T1 ACZ_SDIN2 56R2J-4-GP
TPAD30 TP5 AH22 H_STPCLK# 4
ACZ_SDATAOUT_R STPCLK#
21,28 ACZ_SDATAOUT 1 2 T4 ACZ_SDOUT
2
R544 39R2J-L-GP AF26 H_THERMTRIP_R
THERMTRIP#
13 SATA_LED# AF18 SATALED#
AF3 AB15 Layout Note: R568 needs to placed
20 SATA_RXN0 SATA0RXN DD0 IDE_PDD0 20
AE3 AE14 within 2" of ICH7, R568 must be placed
20 SATA_RXP0 SATA0RXP DD1 IDE_PDD1 20
AG2 AG13 within 2" of R169 w/o stub.
20 SATA_TXN0 SATA0TXN DD2 IDE_PDD2 20
20 SATA_TXP0 AH2 SATA0TXP DD3 AF13 IDE_PDD3 20
2 2
DD4 AD14 IDE_PDD4 20
AF7 SATA2RXN DD5 AC13 IDE_PDD5 20
AE7 SATA2RXP DD6 AD12 IDE_PDD6 20
AG6 SATA2TXN DD7 AC12 IDE_PDD7 20
AH6 SATA2TXP DD8 AE12 IDE_PDD8 20
DD9 AF12 IDE_PDD9 20
3 CLK_PCIE_SATA# AF1 AB13 IDE_PDD10 20
SATA
SATA_CLKN DD10
3 CLK_PCIE_SATA AE1 SATA_CLKP DD11 AC14 IDE_PDD11 20
RTC_AUX_S5 Change to 24.9 1% ohm AF14
DD12 IDE_PDD12 20
when use SATA HD SATARBIAS AH10 AH13
SATARBIASN DD13 IDE_PDD13 20
1 2 AG10 SATARBIASP DD14 AH14 IDE_PDD14 20
1
R569 24D9R2F-L-GP AC15 IDE_PDD15 20

R543 DD15
300KR2J-GP
P.H. for internal VCCSUS1_05
20 IDE_PDIOR# AF15
AH15
DIOR# IDE DA0 AH17
AE17
IDE_PDA0 20
20 IDE_PDIOW# DIOW# DA1 IDE_PDA1 20
20 IDE_PDDACK# AF16 DDACK# DA2 AF17 IDE_PDA2 20
2
20 INT_IRQ14 AH16 IDEIRQ

INTVRMEN 20 IDE_PDIORDY AG16 AE16 IDE_PDCS1# 20
Place within 500 mils IORDY DCS1#
20 IDE_PDDREQ AE15 DDREQ DCS3# AD16 IDE_PDCS3# 20
of ICH7ball
1
ICH7-M-GP
R549 71.ICH7M.00U
0R2J-2-GP INTVRMEN
2
Enable 1
Disable 0
DY
1 <Variant Name> 1
Placement Note: Wistron Corporation

Diatance between the ICH-7 M and cap on the "P" signal 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
should be identical distance between the ICH-7 M and cap Taipei Hsien 221, Taiwan, R.O.C.
on the "N" signal for same pair.
Title
ICH7-M (1 of 4)
A3
AG1 -1
A B C D E
A B C D E
3D3V_S0
U20C RN24
22,24,25,30 PCI_AD[0..31]
U20B C22 AF19 SATA0_R0 SATA0_R2 1 8
18,26,30,35 SMB_CLK SMBCLK GPIO21/SATA0GP
PCI_AD0 E18 D7 PCI_REQ#0 PCI_REQ#0 25 B22 AH18 SATA0_R1 SATA0_R0 2 7
18,26,30,35 SMB_DATA
SMB
PCI_AD1 AD0 REQ0# SMB_LINK_ALERT# A26 SMBDATA GPIO19/SATA1GP SATA0_R2 SATA0_R3
PCI
SATA
C18 E7 AH19 3 6
GPIO
AD1 GNT0# PCI_GNT#0 25 LINKALERT# GPIO36/SATA2GP
PCI_AD2 A16 C16 PCI_REQ#1 PCI_REQ#1 30 SMLINK0 B25 AE19 SATA0_R3 SATA0_R1 4 5
PCI_AD3 AD2 REQ1# SMLINK1 SMLINK0 GPIO37/SATA3GP SRN10KJ-4-GP
F18 AD3 GNT1# D16 PCI_GNT#1 30 A25 SMLINK1
PCI_AD4 E16 C17 PCI_REQ#2 PCI_REQ#2 22 AC1 CLK_ICH14 3
PCI_AD5 AD4 REQ2# PM_RI# CLK14
Clocks
A18 AD5 GNT2# D17 PCI_GNT#2 22 A28 RI# CLK48 B2 CLK48_ICH 3
PCI_AD6 E17 E13 PCI_REQ#3
PCI_AD7 AD6 REQ3# PCI_GNT#3 TP69 TPAD30
A17 AD7 GNT3# F13 28 ACZ_SPKR A19 SPKR SUSCLK C20 PM_SUS_CLK 18
PCI_AD8 A15 A13 PCI_REQ#4 31,32 PM_SUS_STAT# A27
PCI_AD9 AD8 REQ4#/GPIO22 PCI_GNT#4 TP2 TPAD30 DBRESET# SUS_STAT#
4 C14 AD9 GNT4#/GPIO48 A14 A22 SYS_RST# SLP_S3# B24 PM_SLP_S3# 18,30,31,36,41,43,52 4
PCI_AD10 E14 C8 PCI_REQ#5 D23 PM_SLP_S5# 31,41,43
PCI_AD11 AD10 GPIO1/REQ5# PCI_GNT#5 TP68 TPAD30 SLP_S4#
D14 AD11 GPIO17/GNT5# D8 7 PM_BMBUSY# AB18 GPIO0/BM_BUSY# SLP_S5# F22
PCI_AD12 B12
PCI_AD13 AD12 SMB_ALERT#
C13 AD13 C/BE0# B15 PCI_C/BE#0 22,24,30 B23 GPIO11/SMBALERT# PWROK AA4 PWROK 7,19
PCI_AD14 G15 C12 PCI_C/BE#1 22,24,30
AD14 C/BE1#
Power MGT
PCI_AD15 G13 D12 PCI_C/BE#2 22,24,30 3 PM_STPPCI# AC20 AC22 PM_DPRSLPVR_R 2 R564 1 100R2J-2-GP PM_DPRSLPVR 38
PCI_AD16 AD15 C/BE2# GPIO18/STPPCI# GPIO16/DPRSLPVR
E12 AD16 C/BE3# C15 PCI_C/BE#3 22,24,30 3 PM_STPCPU# AF21 GPIO20/STPCPU# DY1100KR2J-1-GP
2
GPIO
PCI_AD17 C11 C21 PM_BATLOW#_R R566
AD17 TP0/BATLOW#
SYS
PCI_AD18 D11 A7 PCI_IRDY# 22,25,30 A21 D16
PCI_AD19 AD18 IRDY# GPIO26 PWRBTN#_ICH BAS16-1-GP
A11 AD19 PAR E10 PCI_PAR 22,24,30 PWRBTN# C23 1 SB_PWRBTN# 31
PCI_AD20 A10 B18 R511 1 2 47R2J-2-GP PCIRST1# 22,25,27,30 B21
PCI_AD21 AD20 PCIRST# PSW_CLR# E23 GPIO27
F11 AD21 DEVSEL# A12 PCI_DEVSEL# 22,25,30 33 PSW_CLR# GPIO28 3
PCI_AD22 F10 C9 PCI_PERR# 22,25,30 C19 1 R510
2
PCI_AD23 AD22 PERR# LAN_RST# 10KR2J-3-GP
E9 AD23 PLOCK# E11 PCI_LOCK# 22,25,30,31,32 PM_CLKRUN# AG18 GPIO32/CLKRUN# 2
PCI_AD24 D9 B10 PCI_SERR# 22,25,30 Y4 SB_RSMRST# 31
PCI_AD25 AD24 SERR# RSMRST#
B9 AD25 STOP# F15 PCI_STOP# 22,25,30 AC19 GPIO33/AZ_DOCK_EN#
1
PCI_AD26 A8 F14 PCI_TRDY# 22,25,30 U2 E20 ECSWI# 31
PCI_AD27 AD26 TRDY# GPIO34/AZ_DOCK_RST# GPIO9 R546
A6 AD27 FRAME# F16 PCI_FRAME# 22,25,30 GPIO10 A20
PCI_AD28 C7 30,31,35 PCIE_WAKE# PCIE_WAKE# F20 F19 ICH7_GPI12 100KR2J-1-GP
PCI_AD29 AD28 WAKE# GPIO12
B6 AD29 PLTRST# C26 2 R516 1 PLT_RST1# 7,20,26,30,31,32,34,35,45 25,30,31,32 INT_SERIRQ AH21 SERIRQ GPIO13 E19
PCI_AD30 E6 A9 0R0402-PAD
CLK_ICHPCI 3 19 THRM# AF20 R4
AD30 PCICLK THRM# GPIO14
2
PCI_AD31 D6 B19 ICH_PME#_1
1 2 ICH_PME# 22 E22
AD31 PME# R512 0R0402-PAD GPIO15
7,38,48 VGATE_PWRGD AD22 VRMPWRGD GPIO24 R3
INT_PIRQA# A3
Interrupt I/F G8 INT_PIRQE# AC21
GPIO25 D20
AD21
NEWCARD_RST# 30
PIRQA# GPIO2/PIRQE# INT_PIRQE# 30 34 SPI_WP# GPIO6 GPIO35
INT_PIRQB# INT_PIRQF#
25 INT_PIRQB#
INT_PIRQC#
B4
C5
PIRQB# GPIO3/PIRQF# F7
F8 INT_PIRQG#
INT_PIRQF# 25 31 ECSCI# AC18
ECSMI# E21 GPIO7 GPIO GPIO38 AD20
AE20
PIRQC# GPIO4/PIRQG# INT_PIRQG# 25 GPIO8 GPIO39
INT_PIRQD# B5 G7 INT_PIRQH# INT_PIRQH# 22
3 PIRQD# GPIO5/PIRQH# ICH7-M-GP 3
AE5
MISC AE9 U20D
RSVD[1] RSVD[6]
AD5 RSVD[2] RSVD[7] AG8 35 PCIE_RXN1 F26 PERn1 DMI0RXN V26 DMI_RXN0 7
AG4 RSVD[3] RSVD[8] AH8 35 PCIE_RXP1 F25 PERp1 DMI0RXP V25 DMI_RXP0 7
Direct Media Interface

AH4 F21 LAN SCD1U16V2KX-3GP
2 1 C602 E28 U28 Layout Note:
RSVD[4] RSVD[9] 35 PCIE_TXN1 PETn1 DMI0TXN DMI_TXN0 7
AD9 AH20 SCD1U16V2KX-3GP
2 1 C601 E27 U27 PCIE AC coupling caps
RSVD[5] MCH_SYNC# MCH_ICH_SYNC# 7 35 PCIE_TXP1 PETp1 DMI0TXP DMI_TXP0 7
need to be within 250 mils of the driver.
ICH7-M-GP 26 PCIE_RXN2 H26 Y26 DMI_RXN1 7
PERn2 DMI1RXN
26 PCIE_RXP2 H25 PERp2 DMI1RXP Y25 DMI_RXP1 7
MiniC26 PCIE_TXN2 SCD1U16V2KX-3GP
2 1 C574 G28 W28 DMI_TXN1 7
SCD1U16V2KX-3GP PETn2 DMI1TXN
26 PCIE_TXP2 2 1 C575 G27 PETp2 DMI1TXP W27 DMI_TXP1 7
ICH7 Pullups 7 DMI_TXN[3..0]
PCI-Express
30 PCIE_RXN3N K26 PERn3 DMI2RXN AB26 DMI_RXN2 7 7 DMI_TXP[3..0]
NEW 30 PCIE_RXP3N NEW
K25 PERp3 DMI2RXP AB25 DMI_RXP2 7 7 DMI_RXN[3..0]
30 PCIE_TXN3N SCD1U16V2KX-3GP
2 1 C625NEW
J28 AA28 DMI_TXN2 7 7 DMI_RXP[3..0]
SCD1U16V2KX-3GP PETn3 DMI2TXN
RP5 3D3V_S0 RP7 3D3V_S5 30 PCIE_TXP3N 2 1 C626 J27 PETp3 DMI2TXP AA27 DMI_TXP2 7
PCI_FRAME# 1 10 ICH7_GPI12 1 10
PCI_IRDY# 2 9 PCI_SERR# PM_BATLOW#_R 2 9 PCIE_WAKE# M26 AD25 DMI_RXN3 7
PCI_TRDY# PCI_LOCK# DBRESET# PSW_CLR# PERn4 DMI3RXN 1D5V_S0
3 8 3 8 M25 PERp4 DMI3RXP AD24 DMI_RXP3 7
PCI_STOP# 4 7 PCI_PERR# SMB_LINK_ALERT# 4 7 SMB_ALERT# L28 AC28 DMI_TXN3 7
PCI_DEVSEL# PM_RI# PETn4 DMI3TXN Place within 500 mils of ICH
3D3V_S0 5 6 3D3V_S5 5 6 L27 PETp4 DMI3TXP AC27 DMI_TXP3 7
1
SRN8K2J-2-GP SRN10KJ-L3-GP P26 AE28 CLK_PCIE_ICH# 3 R535
PERn5 DMI_CLKN 24D9R2F-L-GP
RP6 3D3V_S0 RP9 3D3V_S5 P25 AE27 CLK_PCIE_ICH 3
MCH_ICH_SYNC# USB_OC#2 PERp5 DMI_CLKP
1 10 1 10 N28 PETn5
PCI_REQ#1 2 9 PCI_REQ#3 USB_OC#1 2 9 USB_OC#5 N27 C25
PETp5 DMI_ZCOMP
2
PCI_REQ#2 3 8 INT_SERIRQ USB_OC#3 3 8 USB_OC#7 D25 DMI_IRCOMP_R
PCI_REQ#5 PCI_REQ#4 USB_OC#0 USB_OC#4 DMI_IRCOMP
4 7 4 7 T25 PERn6
2 PCI_REQ#0 USB_OC#6 2
3D3V_S0 5 6 3D3V_S5 5 6 T24 PERp6 USBP0N F1 USB_PN0 21
R28 PETn6 USBP0P F2 USB_PP0 21
SRN8K2J-2-GP SRN10KJ-L3-GP R27 PETp6 USBP1N G4 USB_PN1 21 USB
RP4 3D3V_S0 G3 USB_PP1 21
INT_PIRQD# USBP1P
1 10 34 SPI_CLK 1 R125 2 SPI_CLK_1 R2 SPI_CLK USBP2N H1 USB_PN2 21 Pair Device
INT_PIRQG# 2 9 INT_PIRQB# 3D3V_S5 47R2J-2-GP SPI_CS# P6 H2 USB_PP2 21
INT_PIRQF# INT_PIRQH# TPAD30 TP4 SPI_ARB SPI_CS# USBP2P
3 8 P1 J4 USB_PN3 30 0 USB1
SPI
INT_PIRQC# INT_PIRQE# SPI_ARB USBP3N
4 7 USBP3P J3 USB_PP3 30
5 6 INT_PIRQA# SPI_MOSI P5 K1 USB_PN4 21 1 BT
3D3V_S0 SPI_MOSI USBP4N
SPI_MISO P2 K2 USB_PP4 21
USB
SPI_MISO USBP4P
SRN8K2J-2-GP
3D3V_S0 USBP5N L4 USB_PN5 13 2 USB2
RN90 USB_OC#0 D3 L5 USB_PP5 13
ECSWI# USB_OC#1 OC0# USBP5P
3 2 C4 OC1# USBP6N M1 USB_PN6 26 3 NEW C
PM_CLKRUN# 1 2 ECSMI# 4 1 21 USB_OC#2 USB_OC#2 D5 M2 USB_PP6 26
R625 8K2R2J-3-GP USB_OC#3 OC2# USBP6P
D4 OC3# USBP7N N4 USB_PN7 21 4 USB3
ACZ_SPKR 2 1 SRN100KJ-6-GP
RN88 21 USB_OC#4 USB_OC#4 E5 N3 USB_PP7 21
R513 1KR2J-1-GP SMLINK0 USB_OC#5 OC4# USBP7P
DY 3 2 C3 OC5#/GPIO29 5 CCD
ECSCI# 1 R560 2 SMLINK1 4 1 USB_OC#6 A2 D2
10KR2J-3-GP USB_OC#7 OC6#/GPIO30 USBRBIAS# USB_RBIAS_PN
B3 OC7#/GPIO31 USBRBIAS D1 1 2
22D6R2F-L1-GP
6 MINIC1
EXT_FWH# 1 R561 2 SRN10KJ-5-GP R80
10KR2J-3-GP ICH7-M-GP 7 BT2
PCI_GNT#5 SC Modify
3D3V_S5
Q43
3
D
1 2 SPI_WP# 1 EXT_FWH# EXT_FWH# 34
3
R562 1KR2J-1-GP G
2
DY S 2N7002-8-GP D40
2
84.27002.L04 R587 BAT54PT-GP

1 <Variant Name> 1
1 R532 2 3D3V_S5
10KR2J-3-GP 4K7R2J-2-GP
SPI
Default:H 34 SPI_CS# 1 2
Wistron Corporation
1
T=22ms R542 10KR2J-3-GP

1 2 PCI_GNT#4 GNT5# GNT4# RSMRST#_TO_KBC 31 RN91 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
R42 1KR2J-1-GP 3 2 Taipei Hsien 221, Taiwan, R.O.C.
34 SPI_MOSI
1
DY LPC H H 34 SPI_MISO 4 1
R588 C659 Title
1 R557 PWROK PCI H L 100KR2J-1-GPSC4D7U10V5ZY-3GP SRN10KJ-5-GP
2
ICH7-M (2 of 4)
2
10KR2J-3-GP
DY
SPI L H Size Document Number Rev
2
A3
Boot from various source AG1 -1M
A B C D E
A B C D E
Layout Note:
Place near pin AA19 1D05V_S0
U20F
1
G10 V5REF[1] Vcc1_05[1] L11
L12 C646 C610 C613 C617 C615 C699
V5REF_S0 Vcc1_05[2] SCD1U10V2KX-4GPSCD1U10V2KX-4GPSCD1U10V2KX-4GPSCD1U10V2KX-4GP SC10U6D3V5MX-3GP
4 AD17 V5REF[2] Vcc1_05[3] L14 4
2
1D5V_S0 L16 SCD1U10V2KX-4GP
V5REF_S5 Vcc1_05[4]
F6 V5REF_Sus Vcc1_05[5] L17
Vcc1_05[6] L18
1 2 1D5V_ICH7 AA22 M11
L20 0R0603-PAD Vcc1_5_B[1] Vcc1_05[7]
AA23 Vcc1_5_B[2] Vcc1_05[8] M18
1
1
AB22 P11
CORE
Vcc1_5_B[3] Vcc1_05[9]
1
C60 C619 C599 C618 C645 C627 C600 AB23 P18
SC10U6D3V5MX-3GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP Vcc1_5_B[4] Vcc1_05[10] C611 C647 C616
AC23 Vcc1_5_B[5] Vcc1_05[11] T11
2
2
SCD1U10V2KX-4GP C61 SCD1U10V2KX-4GP SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
AC24 Vcc1_5_B[6] Vcc1_05[12] T18
2
SC10U10V5ZY-1GP AC25 U11 DY
Vcc1_5_B[7] Vcc1_05[13]
AC26 Vcc1_5_B[8] Vcc1_05[14] U18
AD26 Vcc1_5_B[9] Vcc1_05[15] V11
AD27 Vcc1_5_B[10] Vcc1_05[16] V12
AD28 Vcc1_5_B[11] Vcc1_05[17] V14
*Within a given well, 5VREF needs to be up before the D26 Vcc1_5_B[12] Vcc1_05[18] V16
corresponding 3.3V rail D27 Vcc1_5_B[13] Vcc1_05[19] V17
D28 V18 3D3V_S5
Vcc1_5_B[14] VCC PAUX Vcc1_05[20]
E24 Vcc1_5_B[15]
E25 Vcc1_5_B[16] VccSus3_3/VccLAN3_3[1] V5
E26 Vcc1_5_B[17] VccSus3_3/VccLAN3_3[2] V1
1
3D3V_S0 5V_S0 F23 W2
Vcc1_5_B[18] VccSus3_3/VccLAN3_3[3] 3D3V_S0 C607 C605
F24 Vcc1_5_B[19] VccSus3_3/VccLAN3_3[4] W7
G22 SCD1U10V2KX-4GP SCD1U10V2KX-4GP
Vcc1_5_B[20]
2
2
G23 U6 3D3V_S5
D7 R21 Vcc1_5_B[21] Vcc3_3/VccHDA
H22 Vcc1_5_B[22]
CH751H-40PT 100R2J-2-GP H23 R7
Vcc1_5_B[23] VccSus3_3/VccSusHDA 1D05V_S0
J22 Vcc1_5_B[24]
J23 Vcc1_5_B[25] V_CPU_IO[1] AE23
1
3 V5REF_S0 K22 AE26 3

Vcc1_5_B[26] V_CPU_IO[2] 3D3V_S0
K23 AH26
VCCA3GP
Vcc1_5_B[27] V_CPU_IO[3]
1
1
L22 Vcc1_5_B[28]
C34 L23 AA7 C595 C609 C620
Vcc1_5_B[29] Vcc3_3[3]
1
SCD1U16V2ZY-2GP M22 AB12 SCD1U10V2KX-4GP
SCD1U10V2KX-4GP SC10U6D3V5MX-3GP
Vcc1_5_B[30] Vcc3_3[4]
2
2
M23 AB20 C644 C641
Vcc1_5_B[31] Vcc3_3[5] SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
N22 Vcc1_5_B[32] Vcc3_3[6] AC16
2
N23 Vcc1_5_B[33] Vcc3_3[7] AD13
IDE
Layout Note: 3D3V_S5 5V_S5 P22 AD18
Place near ICH7 Vcc1_5_B[34] Vcc3_3[8]
P23 Vcc1_5_B[35] Vcc3_3[9] AG12
R22 AG15 Layout Note:
Vcc1_5_B[36] Vcc3_3[10]
2
R23 AG19 3D3V_S0 PCI decoupling

D15 R41 Vcc1_5_B[37] Vcc3_3[11]
R24 Vcc1_5_B[38]
CH751H-40PT 100R2J-2-GP R25 A5 3D3V_S0
Vcc1_5_B[39] Vcc3_3[12]
R26 Vcc1_5_B[40] Vcc3_3[13] B13
1
T22 Vcc1_5_B[41] Vcc3_3[14] B16
1
V5REF_S5 T23 B7 C596 C571 C570

Vcc1_5_B[42] Vcc3_3[15] SCD1U10V2KX-4GP C593 SCD1U10V2KX-4GP SCD1U10V2KX-4GP
T26 Vcc1_5_B[43] Vcc3_3[16] C10
2
1
PCI
T27 D15 SCD1U10V2KX-4GP DY
C57 Vcc1_5_B[44] Vcc3_3[17]
T28 Vcc1_5_B[45] Vcc3_3[18] F9
SCD1U16V2ZY-2GP U22 G11
Vcc1_5_B[46] Vcc3_3[19]
2
U23 Vcc1_5_B[47] Vcc3_3[20] G12

3D3V_S0 V22 G16 RTC_AUX_S5 NO_STUFF
Vcc1_5_B[48] Vcc3_3[21]
V23 Vcc1_5_B[49]
W22 W5 Layout Note:
Vcc1_5_B[50] VccRTC
1
1D5V_GPLL_ICH_S0 W23 Place near AB3

1D5V_S0 L21 Vcc1_5_B[51]
1
C597 Y22 P7 V3D3A_VCCPSUS Layout Note:
SCD1U10V2KX-4GP Vcc1_5_B[52] VccSus3_3[1] 3D3V_S5 IDE decoupling
1 2 Y23 Vcc1_5_B[53]
2
IND-1D2UH-5-GP A24 2 R548 1 C136

VccSus3_3[2]
2
1
2 0R0603-PAD SCD1U10V2KX-4GP 2
B27 C24
SC10U10V5ZY-1GP
Vcc3_3[1] VccSus3_3[3]
1
C637 C649 1D5V_S0 3D3V_S0
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
D19
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP SCD01U16V2KX-3GP VccSus3_3[4] C598
AG28 VccDMIPLL VccSus3_3[5] D22
2
3D3V_ICH_S5 3D3V_S5
1
G19 SCD1U10V2KX-4GP
VccSus3_3[6]
DY
C594
C640
C55
C54
AB7 Vcc1_5_A[1]
AC6 Vcc1_5_A[2] VccSus3_3[7] K3 1 R531 2
2
1
1D5V_S0 C612 C606 AC7 K4 0R0603-PAD

Vcc1_5_A[3] VccSus3_3[8]
2
1
1
1D5V_ICH_S0 AD6 K5
Vcc1_5_A[4] VccSus3_3[9] C589
ARX
AE6 Vcc1_5_A[5] VccSus3_3[10] K6

2
1 2 AF5 L1 SCD1U10V2KX-4GP
2
R558 0R0603-PAD AF6 L2 DY
1
USB
AG5 Vcc1_5_A[8] VccSus3_3[13] L3

C636 3D3V_S0 AH5 L6 NO_STUFF
SCD1U10V2KX-4GP Vcc1_5_A[9] VccSus3_3[14]
VccSus3_3[15] L7
2
SCD1U10V2KX-4GP SCD1U10V2KX-4GP AD2 M6 C588 C608

VccSATAPLL VccSus3_3[16] SCD1U10V2KX-4GPSCD1U10V2KX-4GP
DY VccSus3_3[17] M7
1
1D5V_S0 AH11 N7
C643 Vcc3_3[2] VccSus3_3[18]
SCD1U10V2KX-4GP AB10 AB17
Vcc1_5_A[10] Vcc1_5_A[19]
2
1
AB9 Vcc1_5_A[11] Vcc1_5_A[20] AC17
1
NO_STUFF NO_STUFF AC10 C639 C590

C642 C638 Vcc1_5_A[12] SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
AD10 Vcc1_5_A[13] Vcc1_5_A[21] T7
2
SCD1U10V2KX-4GPSCD1U10V2KX-4GP AE10 F17
Vcc1_5_A[14] Vcc1_5_A[22]
2
1D5V_S0
ATX
3D3V_ICH_S5 DY AF10 Vcc1_5_A[15] Vcc1_5_A[23] G17

AF9 Vcc1_5_A[16]
AG9 Vcc1_5_A[17] Vcc1_5_A[24] AB8
AH9 Vcc1_5_A[18] Vcc1_5_A[25] AC8
1D5V_S0 C592
<Variant Name>
1
1D5V_ICH_S0 E3 K7
1 VccSus3_3[19] VccSus1_05[1] 1
1
NO_STUFF SCD1U10V2KX-4GP
C591 C1 VccUSBPLL VccSus1_05[2] C28
Wistron Corporation
2
SCD1U10V2KX-4GP C587 G20

VccSus1_05[3]
2
TPAD28 TP7 1D5V_S0 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
DY AA2 VccSus1_05/VccLAN1_05[1] Taipei Hsien 221, Taiwan, R.O.C.
Y7 VccSus1_05/VccLAN1_05[2]Vcc1_5_A[26] A1
SCD01U16V2KX-3GP H6
Vcc1_5_A[27]
2
H7 Title
USB CORE
Vcc1_5_A[28]
Vcc1_5_A[29]
Vcc1_5_A[30]
J6
J7 ICH7-M (3 of 4)
ICH7-M-GP A3
AG1 -1M
A B C D E
A B C D E
U20E
A4 VSS[1] VSS[98] P28
A23 VSS[2] VSS[99] R1
B1 VSS[3] VSS[100] R11
B8 VSS[4] VSS[101] R12
B11 VSS[5] VSS[102] R13
B14 VSS[6] VSS[103] R14
B17 VSS[7] VSS[104] R15
4 B20 VSS[8] VSS[105] R16 4
B26 VSS[9] VSS[106] R17
B28 VSS[10] VSS[107] R18
C2 VSS[11] VSS[108] T6
C6 VSS[12] VSS[109] T12
C27 VSS[13] VSS[110] T13
D10 VSS[14] VSS[111] T14
D13 VSS[15] VSS[112] T15
D18 VSS[16] VSS[113] T16
D21 VSS[17] VSS[114] T17
D24 VSS[18] VSS[115] U4
E1 VSS[19] VSS[116] U12
E2 VSS[20] VSS[117] U13
E4 VSS[21] VSS[118] U14
E8 VSS[22] VSS[119] U15
E15 U16 32K suspend clock output 3D3V_S5
VSS[23] VSS[120]
F3 VSS[24] VSS[121] U17
F4 U24 U11
VSS[25] VSS[122]
F5 VSS[26] VSS[123] U25
F12 VSS[27] VSS[124] U26 16,30,31,36,41,43,52 PM_SLP_S3# 1 OE VCC 5
F27 VSS[28] VSS[125] V2 16 PM_SUS_CLK 2 A
F28 V13 3 4 32KHZ 1 2 G792_32K 19
VSS[29] VSS[126] GND Y R44 100R2J-2-GP
G1 VSS[30] VSS[127] V15
G2 VSS[31] VSS[128] V24
G5 V27 NC7SZ126P5X-GP
VSS[32] VSS[129]
G6 VSS[33] VSS[130] V28
1
G9 VSS[34] VSS[131] W6 73.7S126.AAH
G14 W24 R43
VSS[35] VSS[132] 240KR3-GP
G18 VSS[36] VSS[133] W25
3 G21 W26 63.24434.15L 3
VSS[37] VSS[134]
G24 VSS[38] VSS[135] Y3
2
G25 VSS[39] VSS[136] Y24
G26 VSS[40] VSS[137] Y27
H3 VSS[41] VSS[138] Y28
H4 VSS[42] VSS[139] AA1
H5 VSS[43] VSS[140] AA24
H24 VSS[44] VSS[141] AA25
H27
H28
VSS[45]
VSS[46]
VSS[142]
VSS[143]
AA26
AB4 SMBUS
J1 VSS[47] VSS[144] AB6
J2 AB11 3D3V_S0
VSS[48] VSS[145] 3D3V_S5 5V_S0
J5 VSS[49] VSS[146] AB14
J24 VSS[50] VSS[147] AB16
J25 VSS[51] VSS[148] AB19
J26 VSS[52] VSS[149] AB21
4
3
K24 VSS[53] VSS[150] AB24
K27 AB27 RN9
VSS[54] VSS[151]
4
3
K28 VSS[55] VSS[152] AB28 SRN4K7J-8-GP
L13 AC2 RN10
VSS[56] VSS[153]
L15 VSS[57] VSS[154] AC5 SRN4K7J-8-GP
L24 VSS[58] VSS[155] AC9
1
2
L25 VSS[59] VSS[156] AC11
L26 VSS[60] VSS[157] AD1
1
2
1
M3 AD3 Q37
G
VSS[61] VSS[158] 2N7002-8-GP
M4 VSS[62] VSS[159] AD4
M5 VSS[63] VSS[160] AD7 16,26,30,35 SMB_CLK 3 2 SMBC_ICH 3,11
1
M12 AD8
G
VSS[64] VSS[161]
M13 AD11
S
2 VSS[65] VSS[162] 2
M14 VSS[66] VSS[163] AD15 16,26,30,35 SMB_DATA 3 2 SMBD_ICH 3,11
M15 VSS[67] VSS[164] AD19
M16 AD23 Q13 & Q14 connect SMLINK and Q36
S
VSS[68] VSS[165] 2N7002-8-GP
M17 VSS[69] VSS[166] AE2 SMBUS in S) for SMBus 2.0
M24 AE4
M27
VSS[70] VSS[167]
AE8
compliance
VSS[71] VSS[168] 84.27002.L04
M28 VSS[72] VSS[169] AE11
N1 VSS[73] VSS[170] AE13
N2 VSS[74] VSS[171] AE18
N5 VSS[75] VSS[172] AE21
N6 VSS[76] VSS[173] AE24
N11 VSS[77] VSS[174] AE25
N12 VSS[78] VSS[175] AF2
N13 VSS[79] VSS[176] AF4
N14 VSS[80] VSS[177] AF8
N15 VSS[81] VSS[178] AF11
N16 VSS[82] VSS[179] AF27
N17 VSS[83] VSS[180] AF28
N18 VSS[84] VSS[181] AG1
N24 VSS[85] VSS[182] AG3
N25 VSS[86] VSS[183] AG7
N26 VSS[87] VSS[184] AG11
P3 VSS[88] VSS[185] AG14
P4 VSS[89] VSS[186] AG17
P12 VSS[90] VSS[187] AG20
P13 VSS[91] VSS[188] AG25
P14 VSS[92] VSS[189] AH1
P15 VSS[93] VSS[190] AH3
1 P16 VSS[94] VSS[191] AH7 <Variant Name> 1
P17 VSS[95] VSS[192] AH12
P24 VSS[96] VSS[193] AH23
P27 VSS[97] VSS[194] AH27
Wistron Corporation
ICH7-M-GP 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Title
ICH7-M (4 of 4)
A3
AG1 SD
A B C D E
5V_S0
1
FAN1_VCC
R156
FAN1_VCC 10KR2J-3-GP
*Layout* 15 mil
2
FAN1
5
1
C120 C173 FAN1_FG1 3
SC4D7U6D3V3KX-GP C119 2
SCD1U16V2ZY-2GP D21 SC2200P50V2KX-2GP
2
1
BAS16-1-GP C227 *Layout* 15 mil 4
1
SC1KP16V2KX-GP
2
ACES-CON3-GP
20.F0714.003
2
3D3V_S0 5V_S0 2nd source: 20.D0198.103
5V_S0 U18
R140 *Layout* 30 mil
1 2 5V_G792_S0 6 1
10R3J-3-GP VCC FAN1
20 DVCC FG1 4
1
CLK 14 G792_32K 18
1
1
C174
SDA 16 SMBD_KBC 31 Change to 0R2-0 when using UMA
1
SC1U10V3ZY-6GP R141 C123 C125 C124 7 18
DXP1 SCL SMBC_KBC 31
2
4K99R2F-L-GP R117 SC4D7U10V5ZY-3GP

SCD1U16V2ZY-2GP 9 19
DXP2 NC#19
2
10KR2J-3-GP SCD1U16V2ZY-2GP 11 DXP3 G792_DXP2
2
3
5 G792_DXP3 Q46
DGND G792_DXP3 46
2
16 THRM# 1 R118 2 ALERT# 15 17 1 PMBS3904-1-GP

ALERT# DGND
1
DY 0R2J-2-GP 13 THERM#
C687
SC470P50V3JN-2GP
Setting T8 as V_DEGREE 3 THERM_SET SGND1 8
2
2 10 G792_DXN2 C176 C126
100 Degree RESET# SGND2
2
1
12 G792_DXN3
SGND3 G792_DXN3 46
R138 SC2200P50V2KX-2GP
49K9R2F-L-GP SC2200P50V2KX-2GP
2
V_DEGREE G792SFUF-GP 74.00792.A79 G68 G69 System Sensor, Put between CPU and NB.
=(((Degree-72)*0.02)+0.34)*VCC
2
3D3V_AUX_S5
System改接第二組,VGA接第三組
GAP-CLOSEGAP-CLOSE
M52/54: T[op]/105, Tj/125 degree.
1
2
R119
100KR2J-1-GP DXP1:108 Degree (CPU) H_THERMDA 4
DXP2:H/W Setting 100(System)
1
Place near chip as close
1
31,36 PURE_HW_SHUTDOWN# DXP3:105 Degree (VGA) as possible C175

SC2200P50V2KX-2GP
2
H_THERMDC 4
For CPU Sensor

7,16 PWROK 1 R139 2 G792_RESET#
4K7R2F-GP
1
R137
10KR2F-2-GP
2
Digital Output Data Bits

TEMP.
Sign MSB LSB EXT
+127.875 0 111 1111 111 Dummy when G792 enhanced T85V_AUX_S5
function
Thermal Get Setting
+126.375 0 111 1110 011
T6 T7
1
+25.5 0 001 1001 100
HW thermal shut down tempature setting 95 degree R280 Sencor 0 CPU DTS 98 100
+1.75 0 000 0001 110 (18D2 Ohm), 85 degree (25.699 Ohm). 10R2J-2-GP
5V_AUX_S5 Sencor 1 G792-1 CPU 98 100
+0.5 0 000 0000 100 Put the back of CPU .
2
Sencor 2 G792-2 System 78 83
+0.125 0 000 0000 001
1
1
Sencor 3 G792-3 VGA 110 115
-0.125 1 111 1111 111 C367 R278
U34 SCD01U16V2KX-3GP 0R0402-PAD
2
-1.125 1 111 1110 111

1 R281 2 CPU_THSET 1 SET VCC 5 <Variant Name>
2
-25.5 1 110 0110 100 25D5R2F-GP 2 GND
PURE_HW_SHUTDOWN# 3 4 CPU_TH_HYST
OUT# HYST
-55.25 1 100 1000 110 1
Wistron Corporation
-65.000 1 011 1111 000 G709T1UF-GP 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
74.00709.A7F R279 Taipei Hsien 221, Taiwan, R.O.C.
0R2J-2-GP
Rset=0.0012T*T-0.9308T+96.147 DY Title
Thermal/Fan Controllor G792

2

Custom
AG1 SC
5V_S0
SATA Connector
1
2
RN69
SRN10KJ-5-GP
PWR TRACE 100mil 5V_S0 HDD1
PATA
CDROM Connector
PATA
4
3
42 +5V_MOTOR KEY 20
41 28 HDD_CSEL 2 R349 1
+5V_LOGIC CSEL PDIAG 470R2J-2-GP
PDIAG# 34
1A 1 HDDDRV#_5
TP55 V33 RESET# HDD_LED#
2A V33 DASP# 39 HDD_LED# 13
5V_S0 TPAD30 3A 31 INT_IRQ14
V33 INTRQ IDE_PDIORDY 3D3V_S0
IORDY 27
7A 25 IDE_PDIOR#
V5 DIOR#
K
8A 23 IDE_PDIOW#
V5 DIOW#
1
1
D27 EC26 C440 C439 9A 21 IDE_PDDREQ
V5 DMARQ IDE_PDDACK#
SSM22LLPT-GP 29 1 R373 2
SC10U10V5ZY-1GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
DMACK# 10KR2J-3-GP CDROM1

13A V12
2
14A 44 52
V12 RESERVED#44 DY
A
TP50 15A 32 49 50
TPAD30 V12 RESERVED#32 3D3V_S0
RESERVED#11A 11A 47 48
15 IDE_PDD8 45 46 HDDDRV#_5
IDE_PDD15 18 SATA 15 IDE_PDD9 43 44 IDE_PDD7 15
IDE_PDD14 DD15
16 DD14 B+ S6 1 2 SATA_RXP0 15 15 IDE_PDD10 41 42 IDE_PDD6 15
IDE_PDD13 14 S5 SC4700P50V2KX-1GP
1 2C481 15 IDE_PDD11 39 40 IDE_PDD5 15
DD13 B- SATA_RXN0 15
4
3
IDE_PDD12 12 SC4700P50V2KX-1GP
SATA C482 15 IDE_PDD12 37 38 IDE_PDD4 15
IDE_PDD11 DD12 RN23
IDE_PDD10
10 DD11 A- S3 SATA 1
SC4700P50V2KX-1GP
2 SATA_TXN0 15 15 IDE_PDD13 35 36 IDE_PDD3 15
8 DD10 A+ S2 1 2C480 SATA_TXP0 15 15 IDE_PDD14 33 34 IDE_PDD2 15 SRN8K2J-3-GP
IDE_PDD9 6 SC4700P50V2KX-1GP C479 15 IDE_PDD15 31 32 IDE_PDD1 15
IDE_PDD8 DD9
IDE_PDD7
4 DD8 SATA 15 IDE_PDDREQ 29 30 IDE_PDD0 15
3 DD7 GND 40 15 IDE_PDIOR# 27 28
1
2
IDE_PDD6 5 30 25 26 IDE_PDIOW# 15
IDE_PDD5 DD6 GND
7 DD5 GND 26 15 IDE_PDDACK# 23 24 IDE_PDIORDY 15
IDE_PDD4 9 24 21 22
IDE_PDD3 DD4 GND PDIAG INT_IRQ14 15
11 DD3 GND 22 19 20 IDE_PDA1 15
IDE_PDD2 13 43 15 IDE_PDA2 17 18 IDE_PDA0 15
IDE_PDD1 DD2 GND
15 DD1 GND 19 15 IDE_PDCS3# 15 16 IDE_PDCS1# 15
IDE_PDD0 17 45 5V_S0 13 14 CDROM_LED# 13 5V_S0
DD0 GND
GND 46 11 12
GND 2 9 10
IDE_PDA0 35 S1 7 8
DA0 GND
1
IDE_PDA1 33 S4 5 6
IDE_PDA2 DA1 GND C131 C130 CSEL
36 DA2 GND S7 3 4 -1 Modify
IDE_PDCS1# 37 4A SC10U10V5ZY-1GP SCD1U16V2ZY-2GP 1 2
CS0# GND
1
IDE_PDCS3# 38 5A 51
CS1# GND R374
GND 6A
SPD-CONN50-4R-19GPU
SATA 0R2J-2-GP
NP1 NP1 GND 10A
NP2 NP2 GND 12A Close to Connector 20.80346.050
1 49
2
CON44+15P+S7-GP 20.F0794.066
CDROM
PATA : 20.F0793.044 2 50
3D3V_S0 5V_S0
3V to 5V level shift for HDD

4
3 RN74
SRN10KJ-5-GP
PATA
1
2
G
1
7,16,26,30,31,32,34,35,45 PLT_RST1# 2 3 HDDDRV#_5

D
S
2N7002-8-GP
Q25 84.27002.L04
PATA
<Variant Name>
Wistron Corporation
Title
SATA/PATA HDD / ODD
A3
AG1 -1
5V_USB5_S5 5V_USB1_S5
USB PORT
100 mil 80 mil
C812
1
TC22 C810 C808 C809
SCD1U10V2KX-4GP
ST220U6D3VDM-LGP TC16
SC1KP16V2KX-GP
SC1KP16V2KX-GP
SCD1U10V2KX-4GP
80.22715.L02 2 ST100U6D3VDM-5
2
80.10715.591
KEMET
AVX
5V_USB5_S5
USB1
7
5
5V_USB5_S5 L28 DY 1
16 USB_PN0 1 2
USB_1- 2
5V_USB1_S5 USB_1+ 3
5V_S5 U78 4 3 4
16 USB_PP0
FILTER-79-GP 6
1 8 69.10084.071 8
GND OC1# USB_OC#2 16
2 IN OUT1 7
3 6 SKT-USB-105-GP-U
EN1/EN1# OUT2 22.10218.J11
31 USB_EN# 4 EN2/EN2# OC2# 5 USB_OC#4 16 1 2
R632 0R2J-2-GP
1 2
1
G546A2P1UF-GP R631 0R2J-2-GP
SCD1U10V2KX-4GP
1
1
R694 74.00546.A7D C811 -1 Modify
SCD1U10V2KX-4GP
100KR2J-1-GP
C829
2
2
5V_USB5_S5 USB2
7
5
L33
BLUETOOTH MODULE CONNECTOR DY 1

16 USB_PN4 1 2
USB_5- 2
USB_5+ 3
3D3V_S0 4 3 4
16 USB_PP4
U80 FILTER-79-GP 6
69.10084.071 8
3D3V_BT_S0 1 5
OUT IN SKT-USB-105-GP-U
2 GND
3 4 1 2 22.10218.J11
NC#3 ON/OFF# BLUETOOTH_EN 31 R651 0R2J-2-GP
1
SCD1U10V2KX-4GP
1 2
AAT4250IGV-T1-GP R652 0R2J-2-GP
C827
2
Place near BT1 74.04250.A3F
L47 DY
1 2
5V_USB1_S5 USB3
7
BT1 4 3 BT2 5
6
FILTER-79-GP 1
69.10084.071 L38 DY
4 1 2 4 1 2 USB_3- 2
USB_PN1 16 USB_PN7 16 16 USB_PN2
3 R4281 0R2J-2-GP
2 3 USB_3+ 3
USB_PP1 16 USB_PP7 16
2 R429 0R2J-2-GP 2 4
16 USB_PP2 4 3 6
1 3D3V_BT_S0 C828 1 2 SCD1U16V2ZY-2GP 1 BT2_POWER TP38 TPAD30 FILTER-79-GP 8
69.10084.071
SKT-USB-105-GP-U
DY 22.10218.J11
5
ACES-CON4-1-GP ACES-CON4-1-GP 1 2
20.D0197.104 20.D0197.104 R685 0R2J-2-GP
1 2
2nd source: 20.F0760.004 2nd source: 20.F0760.004 R684 0R2J-2-GP
MDC 1.5 CONN

3D3V_LAN_S5
MDC1
13 15
1
MH1 14
1 2 C564
SC1U10V3KX-3GP
2
15,28 ACZ_SDATAOUT 3 4
5 6
15,28 ACZ_SYNC 7 8 <Variant Name>
15 ACZ_SDATAIN1 1 R494 2 AC_DIN1A_R 9 10
15,28 ACZ_RST# 39R2J-L-GP 11 12 ACZ_BTCLK_MDC 15
MH2
16
17
SC22P50V2JN-4GP
1
AMP-CONN12A-GP Taipei Hsien 221, Taiwan, R.O.C.

1
C562 EC563 R495

SC22P50V2JN-4GP 20.F0582.012 100KR2J-1-GP Title
2
USB and MDC I/F

2

2nd source: 20.F0604.012 A3
AG1 -1
A B C D E
CLOSE TO PHY PINS
MDI0+_M
3 MDI1+_M
MDI0-_M
4 MDI1-_M
3D3V_LAN_S5
3
4
SRN49D9F-GP
SRN49D9F-GP
SCD1U10V2KX-4GP SCD1U10V2KX-4GP
1 L9 2XTALVDD 4401E 4401E
0R0603-PAD
1
C378
3D3V_LAN_S5 RN50 RN51
2
1
2
1
4401E
2
4 4
U26 C355
1
1 L7 BIASVDD C350 C351
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
2
SPROMCS 1 8 R201 4401E 0R0603-PAD
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
CS VCC
1
SPROMCLK 2 7 10KR2J-3-GP C270 C377
SK DC
2
1
SPROMDOUT 3 6 DY 4401E
SPROMDIN DI ORG R288
4 DO GND 5 4401E
2
4401E 4K7R2J-2-GP 4401E 4401E
2
3D3V_LAN_S5
AT93C46-10SU-1GP 3D3V_LAN_S5
4401E
J14 1D8V_LAN_S5
3D3V_LAN_S5
VAUXPRSNT
1D8V_LAN_S5
AVDDL
1 R649 2
PLLVDD
16,24,25,30 PCI_AD[0..31] 3D3V_S5
H14 XTALVDD
A14 BIASVDD
0R0603-PAD 4401E
1
C349 C728 R290 11K24R2F-GP

2
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
G11
G14
D11
E10
K12
K14
A10
K13
2
F10
F12
F13
L14
J10
J12
U36
G4
G1
G2
C5
B8
E5
E6
E7
E8
E9
K4
K5
K6
K7
K8
B3
A7
E1
E4
K3
P2
P1
A1
F5
L4
L6
J4
J5
4401E
VDDIO_PCI
VDDIO_PCI
VDDIO_PCI
VDDIO_PCI
VDDIO_PCI
VDDIO_PCI
VDDIO_PCI
VDDIO_PCI
VDDIO_PCI
TEST_MODE
REG18OUT
VDDIO
VDDIO
VDDIO
VAUX_PRSNT
VREF
VESD1
VESD2
VESD3
REGSUP18
REGSUP18
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
EPHY_AVDD
EPHY_AVDD
PLLVDD
BIASVDD
XTALVDD
RDAC
4401E
PCI_AD0 M7 A8
PCI_AD1 AD0 DC#A8
N7 AD1 DC#A9 A9
1D8V_LAN_S5 PCI_AD2 P7 A13
PCI_AD3 AD2 DC#A13
P5 AD3 DC#B9 B9
DY 4401E PCI_AD4 N5 C10
AD4 DC#C10
3 1 L14 2 AVDDL PCI_AD5 M5 AD5 DC#C12 C12 3
0R0603-PAD PCI_AD6
Broadcom LAN
SCD1U10V2KX-4GP
P4 D5
SCD47U10V3ZY-GP
AD6 DC#D5
1
Place PLLVDD/AVDDL C471 PCI_AD7 N4 AD7 DC#D8 D8

CKT as close to chip as C424 PCI_AD8 P3 D9
PCI_AD9 AD8 DC#D9
possible N3 AD9 DC#D10 D10
2
PCI_AD10 N2 D13
PCI_AD11 AD10 DC#D13
M1 AD11 DC#D14 D14
1 L15 PLLVDD PCI_AD12
BCM4401E
2 M2 AD12 DC#E13 E13
0R0603-PAD PCI_AD13
SCD1U10V2KX-4GP
M3 E14
SCD47U10V3ZY-GP
AD13 DC#E14
1
PCI_AD14 L1 F4
PCI_AD15 AD14 DC#F4
L2 AD15 DC#F11 F11
C444 C470 PCI_AD16 K1 F14
AD16 DC#F14
2
DY PCI_AD17 E3 G13
PCI_AD18 AD17 DC#G13
D1 AD18 DC#H11 H11
4401E PCI_AD19 D2 J13
PCI_AD20 AD19 DC#J13
D3 AD20 DC#K9 K9
PCI_AD21 C1 K10
PCI_AD22 AD21 DC#K10
B1 AD22 DC#L5 L5
PCI_AD23 B2 L7
PCI_AD24 AD23 DC#L7
D4 AD24 DC#L8 L8
PCI_AD25 A5 L11
PCI_AD26 AD25 DC#L11
B5 AD26 DC#L12 L12
PCI_AD27 B6 L13
PCI_AD28 AD27 DC#L13
PCI_AD29
C6
C7
AD28 IDSEL:AD23 DC#M6 M6
M8
AD29 DC#M8
PCI_AD30
PCI_AD31
C8 AD30 INTA-->:INT_PIRQH# DC#M9 M9
C9 AD31 DC#M10 M10
GNT:PCI_GNT#2 DC#M11 M11
PCI_C/BE#0 M4 M12
2 16,24,30
16,24,30
PCI_C/BE#0
PCI_C/BE#1 L3
CBE_0#
CBE_1#
REQ:PCI_REQ#2 DC#M12
DC#M13 M13
2
16,24,30 PCI_C/BE#2 PCI_C/BE#2 F3 M14 3D3V_LAN_S5

CBE_2# DC#M14
16,24,30 PCI_C/BE#3 C4 CBE_3# DC#N11 N11
DC#N14 N14
16,25,30 PCI_FRAME# F2 FRAME# DC#P11 P11
16,25,30 PCI_IRDY# F1 IRDY# DC#P13 P13
16,25,30 PCI_TRDY# G3 TRDY# DC#P14 P14
16,25,30 PCI_PERR# J2 PERR#
16,25,30 PCI_SERR# A2 SERR# NC#N6 N6
16 PCI_REQ#2 C3 REQ NC#P6 P6
16 PCI_GNT#2 J3 GNT#
16,25,30 PCI_DEVSEL# H3 DEVSEL# RSVD#N8 N8
PCI_AD23 R310 1 100R2F-L1-GP-U
2 LAN_IDSEL A4 N10
IDSEL RSVD#N10
4401E16,24,30 PCI_PAR J1 PAR RSVD#P8 P8
16,25,27,30 PCIRST1# C2 PCI_RST# RSVD#P10 P10
16 INT_PIRQH# H2 INTA#
3 PCLK_LAN A3 PCI_CLK
16,25,30,31,32 PM_CLKRUN# H4 CLKRUN#
16,25,30 PCI_STOP# H1 STOP# EEDATA_PXE E12
PME#_LAN
SPROM_DOUT
A6 PME# EECLK_PXE E11

LINK_LED100
SPROM_CLK
SPROM_DIN
LINK_LED10
SPROM_CS
1D8V_LAN_S5
EXT_POR
COL_LED
ACT_LED
4401E 4401E 4401E 4401E 4401E 4401E 4401E
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
XTALO
TRD0+
TRD1+
TRST#
GPIO0
GPIO1
TRD0-
TRD1-
XTALI
3D3V_LAN_S5 1 2
TDO
TMS
TCK
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
R292 0R2J-2-GP BCM4401EKFBG-GP
TDI
1
4401E 4401E C756 C754 C750 C749 C727 C729 C753 C751
Q14
D7
H12
D6
C11
D12
B13
B14
C13
C14
N13
J11
K11
L10
A11
B11
B10
A12
P12
N12
L9
G12
H13
B4
B7
B12
E2
F6
F7
F8
F9
G5
G6
G7
G8
G9
G10
H5
H6
H7
H8
H9
H10
J6
J7
J8
J9
K2
N1
N9
P9
PME#_LAN GND 2 71.04401.C0U 4401E
2
1 <Variant Name> 1
3 OUT ICH_PME# 16
1
R2
SPROMDOUT
R1
SPROMCLK
IN
4401E R795
SPROMDIN
1 DY 4401E Wistron Corporation

SPROMCS
4401E 1 R297 2
CHDTC124EU-1GP 1KR2J-1-GP 1 R634 2 200R2J-L1-GP 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
84.00124.F1K 10KR2J-3-GP X4 Taipei Hsien 221, Taiwan, R.O.C.
SC27P50V2JN-2-GP
SC27P50V2JN-2-GP
2
1 R635 2DY 3D3V_LAN_S5 1 2

4K7R2J-2-GP LAN_X0 Title
1
LAN_X1 XTAL-25MHZ-70GP C404
23
23
MDI0+_M
MDI0-_M 82.30020.581 4401E Size BCM4401E
23 MDI1+_M LAN_ACT_LED# 23,35 C381 4401E Document Number Rev
2
2
4401E A3
23 MDI1-_M 100M_LED# 23,35
10M_LED# 23,35
AG1 -1
A B C D E
A B C D E
Voltage
4401E 5789 5787
Rail
VDDIO_PCI 3D3V_LAN_S5 3D3V_S0 Don't Care

4 4
VDDC 1D8V_LAN_S5 1D2V_LAN_S5
VDDIO 3D3V_LAN_S5 3D3V_LAN_S5
VESD 3D3V_LAN_S5 3D3V_S0 Don't Care LAN Connector
VDDP Don't Care 2D5V_S5
RJ1 LED COLOR
3D3V_2D5V_S5 3D3V_S5 2D5V_S5 CONN_PWR_2
9
B1
NP1
1D8V_1D2V_S5 1D8V_LAN_S5 1D2V_S5 22,35 LAN_ACT_LED#
RJ45_1
B2
RJ45_1
B2:YELLOW
RJ45_2 RJ45_2
RJ45_3 RJ45_3
RJ45_4 RJ45_4
RJ45_5 RJ45_5
D36 RJ45_6 RJ45_6
MCT4 RJ45_7 RJ45_7
MCT3 1 6 RJ45_8 RJ45_8
22,35 10M_LED#
A1 A1:Amber
MCT2 CONN_PWR_1 A2
MCT1 2 5 LAN_LED# A3 A3:GREEN
3 22,35 100M_LED# 3
RJ11_1
RJ11_2
8
7
6
5
35 1G_LED# 3 4 NP2
RN6 10
SRN75J-1-GP
CH731UPT-GP RJ45-107-GP
22.10245.J01
1
2
3
4
LAN Link: Green(A3), behavior is the
EC2 same for 10/100/1000 bits
LAN_TERMINAL 1 2
2D5V_LAN_S5 3D3V_LAN_S5 SC1KP2KV8KX-LGP
LAN Data: Yellow(B2), when LAN is
transfering data.
2
R478 R471
0R2J-2-GP For Modem Cable from MDC
0R2J-2-GP
GIGA 4401E TRING1
1
XF2 3 1 2 TIP
1 L5 HFB1608VF-102-GP
1 12 RJ45_7 2 1 2 RING
35 MDI3+ RD+ RX+ RJ45_8 L4 HFB1608VF-102-GP
35 MDI3- 2 RD- RX- 11 4
TCT1 3 10 MCT4
RDCT RXCT MCT3
4 9 ACES-CON2-GP-U
C16 C17 TDCT TXCT RJ45_4 20.F0714.002
35 MDI2+ 5 TD+ TX+ 8
1
RJ45_5
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
35 MDI2- 6 TD- TX- 7 2nd source: 20.D0196.102

2 2
2
1.route on bottom as differential pairs. XFORM-208-GP

68.68161.30A GIGA
2.Tx+/Tx- are pairs. Rx+/Rx- are pairs.
3.No vias, No 90 degree bends.
4.pairs must be equal lengths.
5.6mil trace width,12mil separation.
XF1
6.36mil between pairs and any other trace.
7.Must not cross ground moat,except 35 MDI1+
MDI1+ 1 RD+ RX+ 12 RJ45_3
MDI1- 2 11 RJ45_6
RJ-45 moat. 35 MDI1-
3
RD- RX-
10 MCT2
RDCT RXCT MCT1
4 TDCT TXCT 9
MDI0+ 5 8 RJ45_1 LAN_LED#
35 MDI0+ MDI0- TD+ TX+ RJ45_2
35 MDI0- 6 TD- TX- 7
RJ11 signal must leave the other signal C552 C551
1
LAN_ACT_LED#
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
or power plane 100mil.

XFORM-208-GP
2
DOC_TIP,DOC_RING,TIP,RING: 3D3V_LAN_S5 1
R10
2 CONN_PWR_1
470R2J-2-GP
W/S : 10/100 @ Surface layers 1 R473 470R2J-2-GP
2 CONN_PWR_2
3D3V_LAN_S5
10/20 @ Inner layers
22 MDI0+_M 2 R486
4401E 0R2J-2-GP
1
8
7
6
5
1 10/100 LAN Transformer RJ45 PIN 22 MDI0-_M 2 R491
4401E 0R2J-2-GP
1 <Variant Name> 1
22 MDI1+_M 2 R492
4401E 0R2J-2-GP
1 ERC1
22 MDI1-_M 2 R501
4401E 0R2J-2-GP
1 SRC100P50V-2-GP
TD+ --> TX+ RJ45-1 77.61012.02L
Wistron Corporation
1
2
3
4
TD- --> TX- RJ45-2 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
RD+ --> RX+ RJ45-3 Title
RD- --> RX- RJ45-6 LAN Connector

A3
AG1 SD
A B C D E
A B C D E
C766 should close Pin-P15

and Pin-R17.
1394_AGND 3D3V_PLL_S0
4 VCC_ASKT_S0 4
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
3D3V_S0
C776
16,22,30 PCI_C/BE#0
2
2
2
16,22,30 PCI_C/BE#1 1 2
16,22,30 PCI_C/BE#2 C766
16,22,30 PCI_C/BE#3 C442 C423 SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP
1
1
1
U38A
W10
U19
U15
K19
P15
P14
P13
A15
P10
F14
F12
L14
J19
J14
W8
1 OF 2
U5
P2
V7
K2
K1
P1
P8
P6
F9
F6
L6
J6
SD_D[0..3] 26
VCCCB
VCCP
VCCP
VCCCB
VR_PORT
VR_PORT
C/BE3#
C/BE2#
C/BE1#
C/BE0#
VR_EN#
VDDPLL_33
VDDPLL_15
AVDD_33
AVDD_33
AVDD_33
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
CBB_D[0..15] 25,27
CBB_A[0..25] 25,27
16,22,25,30 PCI_AD[0..31]
PCI_AD0 R11 P19
AD0 CAD0/D3 CBB_D3 27
PCI_AD1 P11 N18 CBB_D4 27
PCI_AD2 AD1 CAD1/D4
U11 AD2 CAD2/D11 N17 CBB_D11 27
PCI_AD3 V11 M15 CBB_D5 27
PCI_AD4 AD3 CAD3/D5
W11 AD4 CAD4/D12 N19 CBB_D12 27
PCI_AD5 R10 M18 CBB_D6 27
PCI_AD6 AD5 CAD5/D6
U10 AD6 CAD6/D13 M17 CBB_D13 27
PCI_AD7 V10 L19 CBB_D7 27 * All 1394 signals must be routed on top side only
PCI_AD8 AD7 CAD7/D7 * Differential pairs of each ports should have equal trace length
R9 AD8 CAD8/D15 L18 CBB_D15 27
PCI_AD9 U9 L15 CBB_A10 27 * Stubs must be keep as short as possible
3 PCI_AD10 AD9 CAD9/A10 3
V9 AD10 CAD10/CE2# K18 CBB_CE2# 27
PCI_AD11 W9 K17 CBB_OE# 27
PCI_AD12 AD11 CAD11/OE#
V8 AD12 CAD12/A11 K15 CBB_A11 27
PCI_AD13 U8 AD13 CAD13/IORD# J18 CBB_IORD# 27 Bypass/Decupoling Capacitors
PCI_AD14 R8 J15 CBB_A9 27
AD14 CAD14/A9
PCI_AD15 W7 AD15 CAD15/IOWR# J17 CBB_IOWR# 27 Should be places as close to
PCI_AD16 W4 H19 CBB_A17 27
AD16 CAD16/A17
PCI_AD17 PCI7412 as possible
TI PCI7412
T2 AD17 CAD17/A24 F15 CBB_A24 27
PCI_AD18 T1 E17 CBB_A7 27
PCI_AD19 AD18 CAD18/A7
R3 AD19 CAD19/A25 D19 CBB_A25 27
PCI_AD20 P5 A16 CBB_A6 27
PCI_AD21 AD20 CAD20/A6 3D3V_S0
R2 AD21 CAD21/A5 E14 CBB_A5 27
PCI_AD22
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
R1 AD22 CAD22/A4 B15 CBB_A4 27
PCI_AD23 P3 B14 CBB_A3 27
N3 AD24 CAD24/A2 A14 CBB_A2 27
1
PCI_AD25 C769 C764 C765 C778
SC1KP16V2KX-GP
SC1KP16V2KX-GP
N2 AD25 CAD25/A1 C13 CBB_A1 27
PCI_AD26 N1 B13 CBB_A0 27
M5 AD27 CAD27/D0 C11 CBB_D0 27
2
PCI_AD28 M6 E11 CBB_D8 27
MC_PWR_CTRL_1/SM_R/B#
PCI_AD29 AD28 CAD28/D8
M3 AD29 CAD29/D1 F11 CBB_D1 27
PCI_AD30 M2 A10 CBB_D9 27
PCI_AD31 AD30 CAD30/D9
M1 AD31 CAD31/D10 C10 CBB_D10 27
3D3V_S0
MC_PWR_CTRL_0
SD_CMD/SM_ALE
SD_CLK/SM_RE#
SD_DAT3/SM_D7
SD_DAT2/SM_D6
SD_DAT1/SM_D5
U7 SD_DAT0/SM_D4 H14 CBB_A13 27
SD_WP/SM_CE#
16,22,30 PCI_PAR PAR CPAR/A13
CC/BE3#/REG#
CC/BE0#/CE1#
CC/BE2#/A12
CC/BE1#/A8
1
C770
SC1KP16V2KX-GP
SD_CD#
VSSPLL
AGND
AGND
AGND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
2
2 2
U14
U13
R14
P9
P7
N6
M14
K14
K6
H6
G14
F13
F10
F7
R17
E6
B5
A5
C6
E7
C5
A4
F8
MC_PWR_CTRL1_0 C8
E9
E13
E18
H18
L17
71.07412.B0U PCI7412ZHK-GP
CBB_CE1# 27
CBB_A8 27
CBB_A12 27
26 SD_D3 CBB_REG# 27
26 SD_D2 SD_CD# 26
1394_AGND
26 SD_D1 3D3V_S0
26 SD_D0
26 SD_WP
26 SD_CMD
26 SD_CLK 4
26 SM_R# 3
RN101
SRN10KJ-5-GP 3D3V_S0 3D3V_PLL_S0
CardR
1 R648 2
0R0603-PAD
1
2
1
C768 C762 C767
SC1KP16V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
MC_PWR_CTRL 26
C
2
B Q48
CHT2222APT-GP
CardR
E
1 <Variant Name> 1
Wistron Corporation
Title
TI PCI7412 (1 of 2)
A3
AG1 SB
A B C D E
A B C D E
4 4
TP81 TP49
TPAD28 TP48 TPAD28
TPAD28 TP79
TPAD28
MS_D[1..3] 26
1
1
1
G89
W12
U38B
U12
V12
1 2
E5
PCI7412ZHK-GP
2 OF 2
GAP-CLOSE
NC#E5
PC2
PC1
PC0
1394_AGND
16,22,30 PCI_TRDY# W5 TRDY#

16,22,30 PCI_STOP# V6 STOP#
16,22,30 PCI_SERR# W6 SERR#
TI PCI7412
16 PCI_REQ#0 L3 REQ#
16,22,30 PCI_PERR# R7 PERR#
16,22,30 PCI_IRDY# V5 IRDY#
16,22,24,30 PCI_AD22 1 R654
2 7412_IDSEL N5 F18 1 R337 2
100R2F-L1-GP-U IDSEL CCLK/A16 33R2J-2-GP CBB_A16 27
16 PCI_GNT#0 L2 GNT# CCLKRUN#/WP/IOIS16# A11 CBB_WP 27
3 R6 C15 3
16,22,30 PCI_FRAME# FRAME# CRST#/RESET CBB_RESET 27
16,22,30 PCI_DEVSEL# U6 DEVSEL#
XD_CD#/SM_PHYS_WP# A3 XD_CD# 26
26 MS_D3 B6 MS_DATA3/SD_DAT3/SM_D3 SM_CLE B4 SM_CLE 26
26 MS_D2 A6 MS_DATA2/SD_DAT2/SM_D2 SM_CD# B8 SM_CD# 26
26 MS_D1 C7 MS_DATA1/SD_DAT1/SM_D1
B7 3D3V_S0
26 MSCSDIO MS_SDIO/DATA0/SD_DAT0/SM_D0 R655
26 MS_CLK A7
A8
MS_CLK/SD_CLK/SM_EL_WP# IDSEL:AD22 SUSPEND# J5
H3
1 2
10KR2J-3-GP
26 MS_CD# MS_CD# SPKROUT PCI_SPKR 28
26 MSCBS E8 MS_BS/SD_CMD/SM_WE# INTA-->:INT_PIRQG# SDA G3 1 R343 2
3D3V_PLL_S0
SCL G2
INTB-->:INT_PIRQB# RI_OUT#/PME# L5 47KR2J-2-GP
1 2 1394_TPBIAS1 W17 P17 1 R653 2 4K7R2J-2-GP
C763
26 1394_TPBIAS0
SCD1U16V2ZY-2GP R13
TPBIAS1
TPBIAS0
INTC-->:INT_PIRQF# PHY_TEST_MA
1394 V15 TPB1P INTD-->:INT_PIRQG# RN68
W15 TPB1N MFUNC6 J3 PM_CLKRUN# 16,22,30,31,32
26 1394_TPB0P V13
W13
TPB0P GNT:PCI_GNT#0 MFUNC5 J2
J1 INTD#
3
4
2
1
3D3V_S0
INTA# CARBUS 1 (INT_PIRQG#)
26 1394_TPB0N TPB0N MFUNC4
1394_AGND
V16 TPA1P REQ:PCI_REQ#0 MFUNC3 H1
SRN4K7J-8-GP
INT_SERIRQ 16,30,31,32 INTB# 1394 (INT_PIRQB#)
W16 TPA1N MFUNC2 H2 INTC# INT_PIRQF# 16 INTC# Flash Media (INT_PIRQF#)
26 1394_TPA0P V14 TPA0P MFUNC1 H5 INTB# INT_PIRQB# 16
26 1394_TPA0N W14 G1 INTA# INT_PIRQG# 16 INTD# SD Host (INT_PIRQG#) share
TPA0N MFUNC0
CSTSCHG/BVD1/STSCHG#/RI#
1394_R1 T19 F1
R1 CLK_48 CLK48_CARDBUS 3 MFUNC4: use bit 19-16 Register define.
1 2 1394_R0T18 R0 A_USB_EN# E10
6K34R2F-GP R322 R12 H15
RSVD#C4/VD0/VCCD1#
CPS CBLOCK#/A19 CBB_A19 27

CAUDIO/BVD2/SPKR#
P12
CLOCK/VD1/VCCD0#
1394
CINT#/READY/IREQ#
C441 1394_XO TEST0

R18
LATCH/VD3/VPPD0
XO
DATA/VD2/VPPD1
2 1394_XI MC_PWR_CTRL-1 TP80 TPAD30 2

R19
CREQ#/INPACK#
XI RSVD#G5 G5
RSVD#M19/D14
CSERR#/WAIT#
2
CDEVSEL#/A21
RSVD#H17/A18
SC12P50V2JN-3GP
CFRAME#/A23
RSVD#B10/D2
CCD1#/CD1#
CCD2#/CD2#
CPERR#/A14
CTRDY#/A22
X5 CSTOP#/A20
CGNT#/WE#
CIRDY#/A15
1394
CVS1/VS1#
CVS2/VS2#
X-24D576MHZ-46GP
RSVD#G6
RSVD#D1
RSVD#E1
RSVD#E2
RSVD#E3
RSVD#F2
RSVD#F3
RSVD#F5
82.30023.351
GRST#
PRST#
1
C422
PCLK
SC12P50V2JN-3GP
1394
1394
B10
C4
D1
E1
E2
E3
F2
F3
F5
G6
H17
M19
C9
A9
B9
B12
F19
E19
G17
E12
F17
G19
C14
C12
G18
A12
G15
A13
B16
N15
B11
K5
L1
K3
PCIRST1# 16,22,27,30
PCLK_PCM 3
3D3V_S0
27 CBB_D2 CBB_CD2# 27
CBB_CD1# 27
1 R344 2 CBB_VS2# 27
43KR2J-GP CBB_VS1# 27
27 CBB_A18
27 CBB_D14 CBB_A22 27
27 CB_LATCH CBB_BVD1# 27
27 CB_CLOCK CBB_A20 27
27 CB_DATA CBB_WAIT# 27
27 CBB_BVD2# CBB_INPACK# 27
27 CBB_A21 CBB_A14 27
27 CBB_A23 CBB_A15 27
27 CBB_WE# CBB_RDY 27
1 <Variant Name> 1
Wistron Corporation
Title
TI PCI7412 (2 of 2)
A3
AG1 SA
A B C D E
A B C D E
Mini Card Connector

3D3V_S5 3D3V_S0 1D5V_S0
MINIC2
1394 Connector
6 1.5V MINIC REFCLK+ 13 CLK_PCIE_MINI1 3
REFCLK- 11 CLK_PCIE_MINI1# 3
2 3.3V
PERN0 23 PCIE_RXN2 16
28 +1.5V PERP0 25 PCIE_RXP2 16
48 +1.5V
4
PETN0 31 PCIE_TXN2 16 4
52 33 PCIE_TXP2 16 L12 1394
+3.3V PETP0 CN1
25 1394_TPA0P 1 2
24 +3.3VAUX USB_D- 36 USB_PN6 16 6
38 USB_PP6 16 FILTER-79-GP TPA0+ 4
USB_D+ 69.10084.071 4 TPA0-
25 1394_TPA0N 3 3
DY 25 1394_TPB0P 1 L13 2 TPB0+ 2
3 RESERVED#3 SMB_CLK 30 R8001 20R2J-2-GP
SMB_CLK 16,18,30,35
5 RESERVED#5 SMB_DATA 32 R8011 0R2J-2-GP
2 SMB_DATA 16,18,30,35
FILTER-79-GP TPB0- 1
8 DY 69.10084.071 4 3 5
RESERVED#8 25 1394_TPB0N
10 RESERVED#10 TP62 TPAD30
1394 SKT-1394-4P-12GP
12 RESERVED#12 WAKE# 1
1
UIM 14 RESERVED#14 CLKREQ# 7 1394
1
16 22 PLT_RST1# 7,16,20,30,31,32,34,35,45 R304 62.10027.451
RESERVED#16 PERST# R302 R303 56R2J-4-GP R306
17 RESERVED#17 56R2J-4-GP 56R2J-4-GP 56R2J-4-GP
19 RESERVED#19 1394 1394
30,31 RF_ON/OFF# 20 RESERVED#20 GND 4 1394 1394
2
37 RESERVED#37 GND 9
2
1
39 RESERVED#39 GND 15 25 1394_TPBIAS0

R476 41 18
RESERVED#41 GND
1
10KR2J-3-GP 43 21 C403
SC220P50V3JN-GP
RESERVED#43 GND
1
DY 45 RESERVED#45 GND 26
C402 R305
47 RESERVED#47 GND 27 1394
2
49 29 SC1U10V3ZY-6GP 1394 5K1R2-GP

RESERVED#49 GND
2
51 RESERVED#51 GND 34 1394
2
GND 35 Close to TI7412(Device)
GND 40
TP61 TPAD28 1 LED_WPAN# 42 50
WLAN_LED# LED_WWAN# GND
13 WLAN_LED# 44 LED_WLAN# GND 53
3 1 LED_WWAN# 46 LED_WPAN# GND 54 3
TP60 TPAD28
NP1
NP2
3D3V_CR_S0
SKT-MINI52P-3-GP 62.10043.231
SD_D[0..3] 24
NP1
NP2
MS_D[1..3] 25
3D3V_S0 1D5V_S0 3D3V_S5
1
C790 C788 C791
CARD1
SC1U10V3ZY-6GP SCD1U16V2ZY-2GP
2
C573 SCD1U16V2ZY-2GP R741
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
37
1
C58 C59 C572 1 CardR CardR CardR
2
C56 R146
100KR2J-1-GP
NP1
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP 2
SCD1U16V2ZY-2GP
SD_CD# 24
2
2
R145
100KR2J-1-GP
3
1
4 MS_CLK-R
1 R680 2 MS_CLK 25
1
MS_D3 0R0402-PAD R88
100KR2J-1-GP
5
1
6
MS_D2 MS_CD# 25 MS/MS PRO
22KR2J-GP
7
1
8 MSCSDIO
MSCSDIO 25
9 MS_D1 CardR
2
Place near MINIC2 10 MSCBS 25
11 MS_D2 CardR
12 MS_D3
13 MSCBS CardR
14 CardR SD/SD IO/MMC
15 MS_CLK
2 MSCSDIO 2
16
17 MS_D1
18 SM_CD# SM_CD# 25
3D3V_S0 19 SM_R# 24
20 SD_CLK 24
21 SD_WP 24
22 SM_CLE 25
1
23 SD_CMD 24
R401 WLAN_LED# 24 MSCBS
100KR2J-1-GP 25 DY1 R677 2 XD_CD# 25
DY Q29 26 MSCSDIO 1 R678 0R2J-2-GP
2 MS_CLK-R xD
3
MS_D1 0R2J-2-GP
D 27 CardR
2
1 2N7002-8-GP 28 MS_D2
30 80211_ACTIVE 84.27002.L04 MS_D3
G 29
S 30 SD_D0
2
DY 31 SD_D1
32 SD_D2
SD_D3
Bottom VIEW
33
34
Q30 NP2 35 SD_WP
3
D 36
RF_ON/OFF# 2N7002-8-GP
1
G 84.27002.L04
38
1 36
Reader
S
2
DY TTN-CON36-GP-U
62.10024.661
CardR POWER SWITCH
3D3V_CR_S0 U75 3D3V_S0
1 <Variant Name> 1
D
Q28 1 5
2N7002EPT-GP OUT IN
31 WLAN_TEST_LED G
2
3
GND
NC#3 ON/OFF# 4 MC_PWR_CTRL 24
Wistron Corporation
C787 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
1
SCD1U16V2ZY-2GP Taipei Hsien 221, Taiwan, R.O.C.

S
-1M Modify DY CardR AAT4250IGV-T1-GP
1
Title
2
C789
74.04250.A3F 2
SC1U10V3ZY-6GP MINI CARD / 1394
CardR Size Document Number Rev
A3
AG1 -1M
A B C D E
5 4 3 2 1
PCMCIA Socket
Cardbus I/F
NP1
D D
PCMCIA1
CBB_D[0..15] 24,25
CBB_A[0..25] 24,25
Power switch
69 CBB_IORD# 24
CBB_IOWR# 24
1 CBB_OE# 24
CBB_WE# 25
35 CBB_REG# 24
CBB_D3 2
CBB_CD1# CBB_RDY 25
36 CBB_WP 25
CBB_D4 3 CBB_RESET 25
CBB_D11 37
CBB_D5 CBB_WAIT# 25
4 CBB_INPACK# 25
CBB_D12 38 U55 VCC_ASKT_S0
CBB_D6 5 C510
CBB_D13 39 CBB_CE1# 24 3 9
CBB_D7 25 CB_DATA DATA AVCC
6 CBB_CE2# 24 25 CB_CLOCK 4 CLOCK AVCC 10 1 2
CBB_D14 40 5 SCD1U16V2ZY-2GP
CBB_CE1# CBB_BVD1# 25 25 CB_LATCH LATCH
CBB_D15
7 CBB_BVD2# 25 16,22,25,30 PCIRST1# 12 RESET# PCMCIA
41 CBB_CD1# 25 5V_S0 1 2 21 SHDN# AVPP 8 VPP_ASKT_S0
CBB_A10 8 R384 10KR2J-3-GP
CBB_CD2# 25 3D3V_S0
1
CBB_CE2# 42 PCMCIA
VCC_ASKT_S0 CBB_VS1# 25 PCMCIA
1
CBB_OE# 9 13 15 R404
CBB_VS2# 25 3.3V OC# 100KR2J-1-GP
CBB_VS1# 43 C511
CBB_A11 10 5V_S0 SCD1U16V2ZY-2GP
2
1
CBB_IORD# 44 C512 1 PCMCIA
5V
2
CBB_A9 11 SC4D7U10V5ZY-3GP 2 24
CBB_IOWR# 5V NC#24
45 PCMCIA NC#23 23
2
C CBB_A8 12 TPAD28 22 C
NC#22
1
1
C464 C468 C466 CBB_A17 C494 C493 TP56
SC1KP16V2KX-GP
46 7 12V NC#19 19
SCD1U16V2ZY-2GP CBB_A13 TP57
13 DY 20 18
SC1U10V3ZY-6GP
SCD1U16V2ZY-2GP
SC4D7U10V5ZY-3GP CBB_A18 TPAD28 12V NC#18
PCMCIA 47 PCMCIA NC#17 17
2
2
PCMCIA CBB_A14 14 16
CBB_A19 NC#16
PCMCIA CBB_WE#
48 PC1 11 GND NC#14 14
15 1 4 25 GND NC#6 6
CBB_A20 49
CBB_RDY 16
CBB_A21 50 TPS2220APWPRG-GP
17 2 3
VPP_ASKT_S0 51 74.02220.A7G
18 CARDBUS-SKT43-GP
52
CBB_A16 19 21.H0057.011
CBB_A22 53
1
C467 C465 CBB_A15 20

SCD1U16V2ZY-2GP CBB_A23 54
PCMCIA SC4D7U10V5ZY-3GP CBB_A12 21
2
PCMCIA CBB_A24 55
CBB_A7 22
CBB_A25 56
CBB_A6 23
CBB_VS2# 57
CBB_A16 CBB_A5 24
CBB_RESET 58
CBB_A4 25
CBB_WAIT# 59
CBB_A3 26
B CBB_INPACK# B
60
CBB_A2 27
CBB_REG# 61
Place close to pin 19. CBB_A1 28
1
CBB_BVD2# 62
C469 CBB_A0 29
DUMMY-C2 CBB_BVD1# 63
CBB_D0 30
CBB_D8 64
CBB_D1 31
2
CBB_D9 65
CBB_D2 32
CBB_D10 66
CBB_WP
Clock AC termination CBB_CD2#
33
67
33MHz clock for 32-bit 34
68
Cardbus card I/F 70
CARDBUS68P-15-GP
NP2
62.10024.671
A <Variant Name> A
1
DY C492
SCD01U16V2KX-3GP
Wistron Corporation
2

Title
PCMCIA
A3
AG1 SC
5 4 3 2 1
A B C D E
4 4
3D3V_S0 5VA_S0
25 PCI_SPKR C477 1 2 PCI_SPKR1 1 R371 2 "VAUX" Pull high to enable standby mode
SCD47U10V3ZY-GP 47KR2J-2-GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
1
1
C499
C817
16 ACZ_SPKR C478 1 2 ACZ_SPKR1 1 R370 2 AUDIO_BEEP 1 2AUDIP_PC_BEEP C803 C804 C497
SCD47U10V3ZY-GP 47KR2J-2-GP SCD1U10V2KX-4GP
2
SC1U10V3KX-3GP
1
AUD_AGND AUD_AGND
31 KBC_BEEP C476 1 2 KBC_BEEP1 1 R369 2 R686 C805
SCD47U10V3ZY-GP 47KR2J-2-GP 1KR2J-1-GP SC100P50V3JN-2GP
2
ACZ_RST# 15,21
ACZ_SYNC 15,21
2
AC97_BTCLK AC97_BTCLK 15
2 1
AUD_AGND 10KR2J-3-GP
R695
25
38
12
11
10
33
44
43
34
13
U77
1
9
6 BIT-CLK
PCBEEP
VAUX
SENSE_B
SENSE_A
RESET#
LFE-OUT
CEN-OUT
DVDD1
DVDD2
AVDD1
AVDD2
SYNC
3 3
29 LINEIN_L SC1U10V3ZY-6GP
2 1C819 LINE1_L 23 5 ACZ_SDATAOUT 15,21
SC1U10V3ZY-6GP LINE1-L SDATA-OUT
29 LINEIN_R 2 1C818 LINE1_R 24 LINE1-R SDATA-IN 8 AC97_DATIN
1 R391 2 ACZ_SDATAIN0 15
14 39R2J-L-GP
LINE2-L
15 LINE2-R
SPDIFO 48 SPDIFO 29
29 LINE1-VREFO SPDIFI/EAPD 47 MUTEIN 29
31 LINE2-VREFO
1
R390
ALC 883 SIDESURR-OUT-L 45

SC1U10V3ZY-6GP
1 2 C806 MIC1_L 21 46 4K7R2J-2-GP
29 MIC_IN MIC1-L SIDESURR-OUT-R
SC1U10V3ZY-6GP
1 2 C831 22 MIC1-R
16 MIC2-L
2
17 MIC2-R SURR-OUT-L 39
SURR-OUT-R 41
32 MIC1-VREFO-R
1 R696 2 MIC1V_L 28 MIC1-VREFO-L
2K2R2J-2-GP 30 35 OUT_L 29
MIC2-VREFO FRONT-OUT-L
36
SC4D7U10V5ZY-3GP
FRONT-OUT-R OUT_R 29
PIN37_VREFO
2
-1 Modify C814
CD-GND
DVSS1
DVSS2
JDREF
AVSS1
AVSS2
1
GPIO0
GPIO1
VREF
CD-R
CD-L
ALC883-1-GP 71.00883.A0G
26
42
4
7
27
40
37
2
3
18
20
19
2 2
1
C816 C821
SCD47U50V5ZY
SC10U10V5ZY-1GP
HP_JKIN 29
2
DY
-1M Modify
AUD_AGND AUD_AGND
POWER GENERATE *Layout*

1) When GPIO0 is assered, AMP should be muted.
G54
2) SPDIFO should be turned off when not used. 1 2
5VA_S0
20 mil
Configuation: GAP-CLOSE
(3 External Jacks, 1 internal Mic, 1 stereo output Speaker Amp. AUD_AGND
1
Pin Symbol Location Re-tasking 1 R368
5V_S0 C473 28K7R3F-GP
SC22P50V2JN-4GP
35/36 FRONT AMP,Jack1 AMP output, line input U53
2
1 SHDN# SET 5
2
39/41 SURR X X 5VA_SETPIN 1 R389 2
2 10KR2F-2-GP
1 GND <Variant Name> 1
1
43/44 CEN/LEFT X SURR-VREFO-L/R C475

3 IN OUT 4
45/46 SIDESURR X SIDESURR-L is MIC2-VREFO-R, SIDESURR-R is LINE2-VREFO-R SC1U10V3KX-3GP
Wistron Corporation
2
G923-330T1UF-GP
1
23/24 LINE1 Jack 2 Line input, line output C796 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
74.00923.A3F C474 Taipei Hsien 221, Taiwan, R.O.C.
SC1U10V3KX-3GP SC2D2U6D3V3MX-1-GP
21/22 MIC1 Jack 3 Mic input, line output
2
Title
14/15 LINE2 X X Azalia codec ALC883
16/17 MIC2 Int. Mic Mic input AUD_AGND AUD_AGND Size Document Number Rev
A3
AG1 -1M
A B C D E
A B C D E
AUDIO OP AMPLIFIER
-1 Modify
4
Internal SPKR 4
C529
1 2
SC220P50V2JN-3GP 5V_S0 SPKR1

28 OUT_L
5
5VA_S0
C526
1 2 SOUND_L2 1 R426 2 SOUND_L_OP1 1 R427 2 ERC4 SPKR_R+ 1
5V_S0
1
10KR2J-3-GP 10KR2J-3-GP 1 8
SC2D2U6D3V3MX-1-GP R432 2 7 SPKR_R- 2
4
3
U79 10KR2J-3-GP 3 6 SPKR_L+ 3
DY RN102 4 5 SPKR_L- 4
1
4 3 SPKR_L+ -1 Modify SRN10KJ-5-GP SRC100P50V-2-GP

LLINEIN LOUT+
2
R424 5 10 SPKR_L-
10KR2J-3-GP L_BYPASS LHPIN LOUT- ACES-CON4-1-GP
6 LBYPASS HP_JKIN 28
6
7 14 20.D0197.104
LVDD SE/BTL#
1
2
16 HP_JKIN
HP/LINE#
2
31 AMP_SHUTDOWN 8 SHUTDOWN MUTEIN 11 MUTEIN 28
C
2
2 TJ MUTEOUT 9
R689 Q49 HP_JKIN#
2nd source: 20.F0760.004
17 HP-IN GND/HS 1 B
23 12 100KR2J-1-GP CHT2222APT-GP
VOL GND/HS
SC10U10V5ZY-1GP
GND/HS 13
E
18 RVDD GND/HS 24
1
1
C530 R_BYPASS 19 RBYPASS
1
20 15 SPKR_R-
RHPIN ROUT- SPKR_R+ R701
21 22
GND
RLINEIN ROUT+
2
AUD_AGND 1KR2J-1-GP
SC10U10V5ZY-1GP
Lin-In
1
C504 G1421BF3UF-GP
25
2
1
3
I/P signal level AUD_AGND 3
-1M Modify R693
need +5V level
2
0R2J-2-GP AUD_AGND
DY LIN1
5V_S0 5V_OP_S0 74.01421.B1G
1
2
AUD_AGND AUD_AGND 28 LINEIN_L R419 11KR2J-1-GP2 LINEIN_L_1 2
1 R425 2 6
0R0603-PAD 28 LINEIN_R 1 2 LINEIN_R_1 3
1
AUD_AGND R420 1KR2J-1-GP 4
1
C503 C528 C527 C501 C815 C813 5
SC10U10V5ZY-1GP SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
1 2 SOUND_R2 1 R691 2 SOUND_R_OP1 1 R692 2 R421 R418 NP1
SC100P50V3JN-2GP
SC100P50V3JN-2GP
2
10KR2J-3-GP 10KR2J-3-GP 4K7R2J-2-GP 4K7R2J-2-GP NP2
2
SC2D2U6D3V3MX-1-GP RI Gain(HP) = -(RF/RI) RF
C807
2
AUD_AGND AUD_AGND PHONE-JK234-GP
28 OUT_R AUD_AGND 22.10133.B11
SC220P50V2JN-3GP
-1 Modify
1 R710 2
5VA_S0 0R0402-PAD
2 U82 2
MIC-In 5 IN OUT 1 SPDIF_PWR
Line-Out
GND 2
HP_JKIN 4 3
ON/OFF# NC#3
SCD1U16V2ZY-2GP
1
C824
5VA_S0 DYAAT4250IGV-T1-GP
74.04250.A3F
2
AUD_AGND
C825
1
1 2 LOUT1
DY R394
1KR2J-1-GP SC680P50V2KX-2GP 9 GND
8 VCC
28 SPDIFO 7 VIN
2
MIC1 16
6
2
DY C498 NP2 HP_JKIN# 5

1
NP1 TC15 4
DY R395 SC4D7U10V5ZY-3GP 5 OUT_L 1 2 HP_OUT_L 1 R707 2 HP_OUT_L_1 2
1
2K2R2J-2-GP 4 TC14 ST100U6D3VDM-5 22R2J-2-GP 3

3 OUT_R 1 2 HP_OUT_R 1 R703 2 HP_OUT_R_1 1
R697 22R2J-2-GP
13 INT_MICP 6 ST100U6D3VDM-5
2
MIC_L PHONE-JK236-GP
28 MIC_IN 1 2 2 AVX
1
1
10R3J-3-GP C826 C823 EC71 22.10271.061
SC1KP16V2KX-GP
1
1
EC69 R706 R702 AUD_AGND
SC680P50V2KX-2GP
SC680P50V2KX-2GP
SC1KP16V2KX-GP
-1 Modify
C820 PHONE-JK233-GP 1KR2J-1-GP 1KR2J-1-GP
2
22.10133.B01
SC100P50V3JN-2GP
1 <Variant Name> 1
2
2
AUD_AGND AUD_AGND
AUD_AGND AUD_AGND
AUD_AGND AUD_AGND Wistron Corporation
Title
Audio AMP G1421B / Jack
A3
AG1 -1
A B C D E
A B C D E
3D3V_S0
5V_S0
16,22,24,25 PCI_AD[0..31]
1
C585 C583 C586 C235 C177 C80
SC4D7U10V5ZY-3GP
C79
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
2
2
SC4D7U10V5ZY-3GP NEW1
IDSEL:AD21
2
NP2
INTA-->:INT_PIRQE# MINI1
MINI1 125 DY DY 26
GNT:PCI_GNT1# MINI MH1

16 PCIE_TXP3N
16 PCIE_TXN3N
25
24
4 1 2 23 4
REQ:PCI_REQ1# 16 PCIE_RXP3N 22
3 4 16 PCIE_RXN3N 21
5 6 20
7 8 3 CLK_PCIE_NEW 19
9 10 PIN 3-16 : LAN RESERVE 18
80211_ACTIVE 3 CLK_PCIE_NEW# CPPE#
26 80211_ACTIVE 11 12 17
13 14 TP3 16
26,31 RF_ON/OFF#
15 16 3D3V_NEW_S0 15
1
INT_PIRQE# 17 18 14
5V_S0
R638 19 20 INT_PIRQE# 16 -1 Modify TPS2231_PERST# 13
10KR2J-3-GP 3D3V_S0 3D3V_NEW_LAN_S5
DY 21 22 12
3 PCLK_MINI
23
25
24
26 PCIRST1# 16,22,25,27
16,31,35 PCIE_WAKE# DY 1 2
R687 0R2J-2-GP RN72
1D5V_NEW_S0
11
10
2
SB Modify 27 28 3D3V_S0 16,18,26,35 SMB_DATA 1 4 9

16 PCI_REQ#1 29 30 PCI_GNT#1 16 16,18,26,35 SMB_CLK 2 NEW 3 8
31 32 SRN33J-5-GP-U 7
PCI_AD31 33 34 CONN_TP1 6
PCI_AD29 35 36 TP54 CONN_TP2 5
37 38 PCI_AD30 TP51 CPUTSB# 4
PCI_AD27 39 40 3
PCI_AD25 41 42 PCI_AD28 16 USB_PP3 2
43 44 PCI_AD26 16 USB_PN3
PCI_C/BE#3 45 46 PCI_AD24 R142 1
16,22,24 PCI_C/BE#3
PCI_AD23 47 48 MOD_IDSEL 1 2 PCI_AD21 NP1
49 50
PCI_AD21 51 52 PCI_AD22 100R2J-2-GP SKT1 FCI-CON26-5-GP
PCI_AD19 53 54 PCI_AD20 20.F0789.026
3 PCI_AD17
55 56
PCI_AD18
PCI_PAR 16,22,24 NEW 3
57 58
PCI_C/BE#2 59 60 PCI_AD16
16,22,24 PCI_C/BE#2
16,22,25 PCI_IRDY# 61 62
63 64 PCI_FRAME# 16,22,25 1 2
1 R121 2 MINI_CLKRUN# 65 66 PCI_TRDY# 16,22,25
10KR2J-3-GP 67 68 CARDBUS-SKT73-GPU
16,22,25 PCI_SERR# PCI_STOP# 16,22,25
69 70
DY 71 72 21.H0114.001
16,22,25 PCI_PERR# PCI_DEVSEL# 16,22,25
PCI_C/BE#1 73 74 NEW
16,22,24 PCI_C/BE#1
PCI_AD14 75 76 PCI_AD15
77 78 PCI_AD13
PCI_AD10 81 82
83 84 PCI_AD9
PCI_AD8 85 86 PCI_C/BE#0
PCI_C/BE#0 16,22,24
16,22,25,31,32 PM_CLKRUN# 1 R122 2 PCI_AD7 87 88
0R0402-PAD PCI_AD6
NEWCARD Connector
89 90
93 94 PCI_AD2
5V_S0 97 98 Reserve the symbol
PCI_AD1 99 100
101 102
INT_SERIRQ 16,25,31,32 for bottom side
103 104 connector
105 106
107 108
109 110 RN70
111 112 CPUTSB# 1 4 3D3V_S5
113 114 TPS2231_PERST# CPPE# 2 3
2 2
115 116 31,36 S5_EN 1 2 NEWCARD_RST# 16
117 118 DYSRN100KJ-6-GPR336 DUMMY-R2
119 120
121 122
20
10
8
9
6
123 124 U41 PLT_RST1# 7,16,20,26,31,32,34,35,45
MH2
SHDN#
PERST#
CPUSB#
CPPE#
SYSRST#
126
PCISLT124-2-GP
62.10034.151 16,18,31,36,41,43,52 PM_SLP_S3# 1 STBY# 3.3VIN 2 3D3V_S0

18 RCLKEN 3.3VOUT 3 3D3V_NEW_S0
2nd source: 62.10043.151 19 OC# 1.5VIN 12 1D5V_S0
21 THERMAL_PAD 1.5VOUT 11 1D5V_NEW_S0
AUXIN 17 3D3V_S5
AUXOUT 15 3D3V_NEW_LAN_S5
7 GND
NC#16
NC#14
NC#13
NC#5
NC#4
NEW
TPS2231RGP-GP
16
14
13
5
4
74.02231.073
3D3V_S0 3D3V_NEW_S0 1D5V_NEW_S0 3D3V_NEW_LAN_S5

1 <Variant Name> 1
C462
Wistron Corporation
1
1
C179 C451
C463 C452 C450 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
SCD1U16V2ZY-2GP
SC1U10V3ZY-6GP SCD1U16V2ZY-2GP Taipei Hsien 221, Taiwan, R.O.C.

NEW
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
2
2
SC1U10V3ZY-6GP NEW
NEW NEW NEW NEW Title
MINI-PCI/NEW Card
Place them Near to Chip Place them Near to Connector Size Document Number Rev
A3
AG1 -1
A B C D E
A B C D E
For S/W Debug

Pin No. Pin No.
3D3V_AUX_S5
PLANARID0 33
1 3D3V_AUX_KBC
TP101
MODE1 2 PLANARID1 33 1394/CardReader Detect Pin
PLANARID2 33
1
3 H8_RESET# TP102
TP103
MODE0 4 INTERNET# 13 non CardR R267 H:non 1394/CardReader
5 KBC_AC_IN# TP104
TP75
H8_TXD1 6 10KR2J-3-GP
L:has 1394/CardReader
7 LID_CLOSE# TP106 H8_RXD1 8 KBC_3D3V_AUX
BLUETOOTH_EN 21
2
TP74 NUM_LED 13 NAPA_U_V
9 PM_SLP_S3# TP108 GND 10 CAP_LED 13 -1 Modify
1
4
5V_AUX_S5 KBC_5V_AUX R268 R586 4
STDBY_LED 13
10KR2J-3-GP 10KR2J-3-GP
PWRLED 13
2 R584 1 CardR
CHRGER_LED 13
1
0R0805-PAD
DC_BATFULL 13
2
C724 C723 EMAIL_LED 13
3D3V_AUX_S5 KBC_3D3V_AUX SC4D7U10V5ZY-3GP SCD1U16V2ZY-2GP H8_RESET# RN48
2
MODE0 8 1 KBC_3D3V_AUX
E
KBC_NMI 7 2
1
2 R261 1 H8_STBY# 6 3 Q45 B PURE_HW_SHUTDOWN# 19,36
0R0805-PAD MODE1 C660 CH3906PT-GP
DY 5 4
1
KBC_XTAL SC10U10V5ZY-1GP
C
C357 C732 C324 C312 KBC_EXTAL SRN10KJ-4-GP
SCD01U16V2KX-3GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SC10U10V5ZY-1GP
142
140
141
143
144
100R2J-2-GP 2 R270 1
86
77
76
36
13
50
49
48
47
46
45
44
43
58
57
56
55
54
53
52
51
12
10
1
9
U73 X3
3D3V_S5 2 1
VCCB
PF0/TMIA
PF1/TMIB
PF2/TMOA
PF3/TMOB
PF4/EXTMIX
PF5/EXTMIY
PF6/EXTMOX
PF7/TMOY
PG4/EXSDAA
PG5/EXSCLA
PG6/EXSDAB
PG7/EXSCLB
VCL
PG0
PG1
PG2
PG3
RES#
RESO#
STBY#
MD0
MD1
X1
X2
VCC
VCC
VCC
VCC
XTAL
EXTAL
1
15 LPC_LAD[0..3]
2
C380 XTAL-10MHZ-3GP C358

R802 SC10P50V2JN-4GP 82.30054.041
2
2K2R2J-2-GP SC10P50V2JN-4GP
42 CHG_I_PWM CHG_I_PWM 112 41
CHG_V_PWM P10/PW0 PA0/KIN8#
42 CHG_V_PWM 110 P11/PW1 PA1/KIN9# 40
1
16 RSMRST#_TO_KBC 1 R618 2 3D3V_S5_SENSE 109 P12/PW2 PA2/KIN10#/PS2AC 39 TCLK 33

1 0R0402-PAD 108 38 RN45 5V_S0
16 SB_RSMRST# P13/PW3 PA3/KIN11#/PS2AD TDATA 33
D42 16 SB_PWRBTN# SB_PWRBTN# 107 37 1 8
BAT54PT-GP 3 SB_RSMRST#_KBC P14/PW4 PA4/KIN12#/PS2BC
13 WIRELESS_BTN# 106 P15/PW5 PA5/KIN13#/PS2BD 35 2 7
1
3
2 3D3V_AUX_S5 13
30,36
BT_BTN#
S5_EN S5_EN
105
104
P16/PW6
P17/PW7
PA6/KIN14#/PS2CC
PA7/KIN15#/PS2CD
34
33
3
4
6
5 EC25
SCD1U16V2ZY-2GP
DY 3
2
AD_OFF 103 120 CRT_IN# 14 SRN10KJ-4-GP
44 AD_OFF P20 PB0/WUE0#/LSMI
2
102 119 ECSCI#_KBC

R472 P21 PB1/WUE1#/LSCI
101 P22 PB2/WUE2# 118
100KR2J-1-GP 100 117 EC_PWRBTN# EC_PWRBTN# 13
P23 PB3/WUE3#
DY 42 CHG_4D35V# 99
98
P24
P25
PB4/WUE4#
PB5/WUE5#
116
115
PM_SLP_S5# 16,41,43
1
1 R3 2 KBC_BB_EN# 97 P26 PB6/WUE6# 114 BATA_IN# 42,44

0R2J-2-GP USB_EN# 96 113 PCIE_WAKE# PCIE_WAKE# 16,30,35
21 USB_EN# P27 PB7/WUE7#
RN71
1
GF_LPC_LAD0 1 8 LPC_LAD0 LPC_LAD0 121 94 KCOL1 C694 050510:For
32,34 GF_LPC_LAD0 P30/LAD0 PC0
GF_LPC_LAD2 LPC_LAD2 LPC_LAD1 KCOL2
RE144B
32,34 GF_LPC_LAD2
GF_LPC_LAD1
2 FIR 7
LPC_LAD1 LPC_LAD2
122 P31/LAD1 PC1 93
KCOL3 SC100P50V2JN-3GP Battery switch
32,34 GF_LPC_LAD1 3 6 123 P32/LAD2 PC2 92
2
32,34 GF_LPC_LAD3
GF_LPC_LAD3 4 5 LPC_LAD3 LPC_LAD3 124 P33/LAD3 PC3 91 KCOL4 fail issue
SRN0J-4-GP LPC_LFRAME# 125 90 KCOL5
PLT_RST1# P34/LFRAME# PC4 KCOL6
7,16,20,26,30,32,34,35,45 PLT_RST1# 126 P35/LRESET# PC5 89 1 ECSCI# 16
127 88 KCOL7 D37
3 PCLK_KBC P36/LCLK PC6 KCOL8 ECSCI#_KBC
16,25,30,32 INT_SERIRQ 128 P37/SERIRQ PC7 87 3 BAT54PT-GP
1
29 AMP_SHUTDOWN 136 66 KCOL9 2

R626 KBC_BEEP P40/TMCI0 PD0 KCOL10
100R2J-2-GP DY 28 KBC_BEEP
KBC_SDA
137
138
P41/TMO0
P42/TMRI0/SDA1
PD1
PD2
65
64 KCOL11 1 ECSWI# 16
PCLK_KBC_RC 26,30 RF_ON/OFF# RF_ON/OFF# 2 63 KCOL12 D38
P43/TMCI1 PD3
1 2
13 BRIGHTNESS BRIGHTNESS 3 62 KCOL13 ECSWI#_KBC 3 BAT54PT-GP

BLON_OUT P44/TMO1 PD4 KCOL14
13 BLON_OUT 4 P45/TMRI1 PD5 61
C707 BLON_IN KCOL15
DY 48 BLON_IN 5 P46 PD6 60 2
1
SC10P50V2JN-4GP KBC_BB_EN# 6 59 KCOL16

P47 PD7
2
R637
2M2R3-GP DY KROW1 78 P60/FTCI/KIN0#/TMIX PE0 32
2 KROW2 2
79 P61/FTOA/KIN1# PE1 31
KROW3 80 30
P62/FTIA/KIN2#/TMIY PE2
2
KROW4 81 29
P63/FTIB/KIN3# PE3
P86/IRQ5#/SCK1/SCL1
KROW5 82 28 KBC_MATRIX0 KBC_3D3V_AUX
P64/FTIC/KIN4# PE4 KBC_MATRIX0 33
KROW6 83
P52/EXSCK1/SCL0
27 KBC_MATRIX1 KBC_MATRIX1 33 RN47
P65/FTID/KIN5# PE5
1 R799 2 KROW7 84 26 BATA_SCL 1 4
P85/IRQ4#/RXD1
P84/IRQ3#/TXD1
15 LPC_LFRAME# GF_LPC_LFRAME# 32,34 P66/FTOB/KIN6#/IRQ6# PE6
0R2J-2-GP KROW8 85 25 NAPA_U_V BATA_SDA 2 3
P82/CLKRUN#
P67/TMOX/KIN7#/IRQ7# PE7
P51/EXRXD1
3D3V_S0
P83/LPCPD#
P50/EXTXD1
FIR
P90/IRQ2#
P91/IRQ1#
P92/IRQ0#
RN98 SRN10KJ-5-GP
P80/PME#
P96/EXCL
P97/SDA0
P81/GA20
Place near KBC 1 8 INTERNET#

2 7 KCOL[1..16] 33
(Near H11,Top side).
VSS
VSS
VSS
VSS
VSS
VSS
KBC_3D3V_AUX
NMI
P70
P71
P72
P73
P74
P75
P76
P77
P93
P94
P95
3 6 KROW[1..8] 33
4 5
71.00144.B0G RE144B-GP KBC_AC_IN# 1 R585 2
68
69
70
71
72
73
74
75
16
15
14
129
130
131
132
133
134
135
24
23
22
21
20
19
18
17
11
7
42
67
95
111
139
SRN10KJ-4-GP 10KR2J-3-GP
RN46
KBC_MATRIX0 1 4
5V_S0 3D3V_S0 KBC_MATRIX1 2 3
13 MAIL# MAIL# SRN10KJ-5-GP

KBC_3D3V_AUX EBUTTON# 3D3V_S0
13 EBUTTON#
13 PROGRAM# PROGRAM# KBC_NMI
BATA_SDA 44
K_A20GATE 1 R599 2
4
3
3
4
BLUETOOTH_LED 13 10KR2J-3-GP
RN96 RN94 44 BATA_SCL WLAN_TEST_LED 26
SRN10KJ-5-GP SRN10KJ-5-GP ECSWI#_KBC H_RCIN# 15 -1 Modify
1 15 K_A20GATE PM_SLP_S3# 16,18,30,36,41,43,52 <Variant Name> 1
LID_CLOSE# LID_CLOSE# 33
16,22,25,30,32 PM_CLKRUN#
16,32 PM_SUS_STAT#
1
2
2
1
1
H8_TXD1 D39
1
Wistron Corporation
G
Q39 H8_RXD1
KBC_SCL 3 2 2N7002-8-GP SMBC_KBC 19
KBC_SCL KBC_AC_IN# 3 AC_IN# 42 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
1
2
D
Q44 Title
KBC_SDA 2 2N7002-8-GP
3 SMBD_KBC 19 BAT54PT-GP KBC_RE144B
D
A3
AG1 -1M
A B C D E
5 4 3 2 1
D D
GF_LPC_LAD0
GF_LPC_LAD1
GF_LPC_LAD[0..3] 31,34
GF_LPC_LAD2
GF_LPC_LAD3
LPC_LDRQ0# 15
PLT_RST1# 7,16,20,26,30,31,34,35,45
INT_SERIRQ 16,25,30,31
GF_LPC_LFRAME# 31,34
3D3V_S0
CLK14_SIO 3
1
PCLK_SIO 3
C105 C68 C39
1
C SC1U10V3ZY-6GP SCD1U16V2ZY-2GPSCD1U16V2ZY-2GP C
2
R26 R68
24
35
32
36
38
40
16
27
28
30
43
25
8
U13 DUMMY-R2
FIR FIR FIR
LCLK
LAD0
LAD1
LAD2
LAD3
LDRQ#/XOR_OUT
LRESET#
SERIRQ
LFRAME#
VDD
VDD
VDD
CLKIN
DUMMY-R2 C38
2
PCLK_SIO_RC
2 1
1 42 C69
CTS1# NC#42
44 DCD1# NC#33 33
45 37 DUMMY-C2 CLK14_SIO_RC 2 1
DSR1# NC#37
3 39
SIO PC87381
RI1# NC#39
46 SIN1 NC#41 41
VCORF 10 4 DUMMY-C2
BADRR_STRAP 2 VCORF NC#4
18
IRRX2_IRSL0/GPIO17
DTR1#_BOUT1/BADDR NC#18
1
C833 FIR
RESERVED/GPO24
47 RTS1#/TRIS# NC#26 26
CLKRUN#/GPIO22
SCD1U16V2ZY-2GP 1 48 29
GPIO21/LPCPD#
R128 SOUT1/TEST# NC#29
NC#31 31
2
10KR2J-3-GP
FIR
GPIO00
GPIO01
GPIO02
GPIO03
GPIO04
GPIO20
GPIO23
2
IRRX1
IRTX
VSS
VSS
VSS
PC87381-VBH-GP
71.87381.A0G
11
12
13
14
15
17
21
19
22
20
5
7
6
9
23
34
Connecting a 10 K external pull-down resistor
makes the base address sample low, setting the FIR
Index-Data pair at 2Eh-2Fh.
B B
IRRX1
IRSL0
IRTX
3D3V_S0 PM_CLKRUN# 16,22,25,30,31
R159
1 FIR 2 LPCPD# 1 2 PM_SUS_STAT# 16,31
R25 DUMMY-R2
10KR2J-3-GP
VISHAY FIR/CIR Module Layout Guide:

(1) FIR_3D3V : 30 mils,
(2) C583, C581 close
Place C581 to U32
,C583 near Pin1
3D3V_S0 U56
and Pin6
SCD1U16V2ZY-2GP
1 VCC2/IRED_ANODE
2
SC10U10V5ZY-1GP
SCD1U16V2ZY-2GP
IRED_CATHODE
1
C509 C532 C531 IRTX 3

IRRX1 TXD
A 4 RXD <Variant Name> A
IRSL0 5 SD
2
FIR FIR FIR 6 VCC1

7
8
MODE
GND
Wistron Corporation
G55 FIR-TFDU6102-GP 56.15001.051
1 2 FIR Title
IR_GND
GAP-CLOSE SIO 87381 / FIR
IR_GND Size Document Number Rev
A3
AG1 -1
5 4 3 2 1
Internal KeyBoard Connector
31 KROW[1..8]
31 KCOL[1..16]
KB1
SW1 ON 26
PSW_CLR# NC#26 KROW1
16 PSW_CLR# 1 5 C01 1
2 6 2 KROW2
C02 KROW3
31 KBC_MATRIX0 3 7 C03 3
4 8 4 KCOL1
31 KBC_MATRIX1 R01 KCOL2
R02 5
SW-DIP-4-2-U2-GP 6 KCOL3
R03 KROW4
C04 7
8 KCOL4
R04 KCOL5
R05 9
10 KCOL6
R06 KCOL7
R07 11
12 KCOL8
R08
Keyboard matrix ( from vendor ) R09 13 KCOL9
14 KROW5
C05 KCOL10
R10 15
US Eur Jap Ohter C06 16 KROW6
17 KROW7
C07 KCOL11
R11 18
19 KCOL12
R12
MATRIXID0# 1 0 1 0 C08 20 KROW8
21 KCOL13
R13 KCOL14
R14 22
MATRIXID1# 1 1 0 0 R15 23 KCOL15
24 KCOL16
R16
NC#25 25
NC#27 27
ACES-CON25-GP
20.K0197.025
Low Active
COVER SWITCH PSW_CLR# 1 - 5 ON
2nd source: 20.K0198.025
NC 2 - 6 ON
3D3V_AUX_S5
KBC_MATRIX1 3 - 7 ON
1 25
2
KBC_MATRIX2 4 - 8 ON
R460
100KR2J-1-GP
K/B
CVR1
1
R459
TOUCH PAD
4 2 1 2 LID_CLOSE# 31 5V_S0
1
3 1 100R2F-L1-GP-U
C547
SC1KP16V2KX-GP
PUSH-SW81-GP
2
5V_S0
1
2
62.40014.141
RN100
SRN10KJ-5-GP
1
EC35 EC327
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
TPAD1
4
3
2
14
12
RN44 11
31 TDATA 1 4 TP_DATA 10
31 TCLK 2 3 TP_CLK 9
SRN33J-5-GP-U 8
SCROLL KEY
7
TP_SCROLL_RIGHT 6
TP_SCROLL_UP 5
TP_SCROLL_DOWN 4
TP_LEFT 3
TP_RIGHT 2
TP_SCROLL_UP
1 SCRL1 2 TP_SCROLL_LEFT 1
13
5
ACES-CON12-GP
3 4 20.K0174.012
8
7
6
5
SW-TACT-59-GP-U1 2nd source: 20.K0185.012
ERC2
8
7
6
5
62.40009.431 SRC100P50V-2-GP
ERC3
TP_LEFT TP_SCROLL_LEFT TP_SCROLL_RIGHT TP_RIGHT 3D3V_AUX_S5 SRC100P50V-2-GP DY
1
2
3
4
1 LEFT1 2 1 SCRL2 2 1 SCRL4 2 1 RIGHT1 2 77.61012.02L
1 12
1
2
3
4
5 5 5 5
2
T/P
2
2
3 4
SW-TACT-59-GP-U1
3 4
SW-TACT-59-GP-U1
3 4
SW-TACT-59-GP-U1
3 4
SW-TACT-59-GP-U1
R265
100KR2J-1-GP R264 R263
Planar
DY 100KR2J-1-GP 100KR2J-1-GP ID(2,1,0)
62.40009.431 62.40009.431 62.40009.431 62.40009.431 DY
1
TP_SCROLL_DOWN
SA: 0,0,0 <Variant Name>
1
1 SCRL3 2 31 PLANARID2
PLANARID2 1
31 PLANARID1
PLANARID1
PLANARID0
SB: 0,0,1
5 31 PLANARID0
SC: 0,1,0 Wistron Corporation
2
3 4 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
2nd source: 62.40009.341

SW-TACT-59-GP-U1 R623
100KR2J-1-GP
R624
100KR2J-1-GP
R622
100KR2J-1-GP
SD: 0,1,1 Taipei Hsien 221, Taiwan, R.O.C.
62.40009.431 DY -1: 1,0,0 Title
KEYBOARD/TOUCHPAD
1

A3
AG1 SC
A B C D E
4
GOLDEN FINGER FOR DEBUG BOARD 4
GF_LPC_LAD[0..3] 31,32
5V_S0 5V_S0
U46
A1 A1 B1 B1
PLT_RST1# A2 B2 PLT_RST1#
7,16,20,26,30,31,32,35,45 PLT_RST1# GF_LPC_LFRAME# A2 B2 GF_LPC_LFRAME#
31,32 GF_LPC_LFRAME# A3 A3 B3 B3
A4 A4 B4 B4
PCLK_FWH A5 B5 PCLK_FWH
3 PCLK_FWH A5 B5
A6 A6 B6 B6
FWH_INIT# A7 B7 FWH_INIT#
15 FWH_INIT# A7 B7
A8 A8 B8 B8
GF_LPC_LAD3 A9 B9 GF_LPC_LAD3
A10 A10 B10 B10
A12 A12 B12 B12
EXT_FWH# A13 B13 EXT_FWH#
16 EXT_FWH# A13 B13
A14 A14 B14 B14
3D3V_S0 A15 B15
A15 B15 3D3V_S0
-1 Modify
SPI FLASH ROM FOX-GF30
ZZ.GF030.XXX
3D3V_S0
3
8M Bits 3
Boot Device must have ID[3:0] = 0000
2
Has internal pull-down resistors
R403 SPI
10KR2J-3-GP U54 3D3V_S5 All may be left floated
FPET7 Elec. P3-46
SPI_CS# 1 8
16 SPI_CS# CE# VDD
1
16 SPI_MISO SPI_MISO 2 7 SPI_HOLD# 1 R402 2 3D3V_S5

SPI_WP# SO HOLD# SPI_CLK 10KR2J-3-GP
16 SPI_WP# 3 WP# SCK 6 SPI_CLK 16
4 5 SPI_MOSI SPI_MOSI 16
VSS SI
SST25LF080A-1GP
72.25080.E01
SOIC 200 Socket P/N:

Wieson: 62.10076.001
SPI ROM:
SST25LF080A: 72.25080.E01 TOP VIEW
SST25VF080B : 72.25080.G01
ST M25P80: 72.25P80.001
A15 (B1)
2 2
A14 (B2)
....
....
A2 (B14)
A1 (B15)
(BOTTOM VIEW)
1 <Variant Name> 1
Wistron Corporation
Title
BIOS : SPI
A3
AG1 -1
A B C D E
5 4 3 2 1
3D3V_LAN_S5
CLOSE TO GPHY PINS
2D5V_LAN_S5
3 MDI0+
3 MDI1+
3 MDI2+
3 MDI3+
4 MDI0-
4 MDI1-
4 MDI2-
4 MDI3-
3D3V_LAN_S5 1 L39 2XTALVDD_G 5789 5789 5789
1
0R0603-PAD 5789 5789 5789 5789
1
C842 GIGA R744 R745 R746 C872
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SRN49D9F-GP
SRN49D9F-GP
SRN49D9F-GP
SRN49D9F-GP
1KR2J-1-GP 1KR2J-1-GP 1KR2J-1-GP SCD1U10V2KX-4GP
2
1
1
C841 C840 SCD1U10V2KX-4GP U84
2
8 VCC A0 1
2
LAN_EE_WP 7 2
WP A1
2
1 L40 2 BIASVDD_G LAN_EECLK 6 SCL NC#3 3 RN103 RN104 RN105 RN106
2
1
2
1
2
1
2
1
0R0603-PAD LAN_EEDATA 5 4
1D2V_LAN_S5 SDA GND
1
D C843 GIGA GIGA D
GIGA GIGA AT24C256N-10SU-GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
1
SCD1U10V2KX-4GP C846 C844 C848 C847
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
1
1
C798 C797 C800 C801 C802 C830 C799 C834
2
1 L41 2AVDD_A13
0R0603-PAD
2
1
C845 GIGA 5789 5789 5789 5789
GIGA GIGA GIGA SCD1U10V2KX-4GP
GIGA GIGA GIGA GIGA
2
GIGA 2D5V_LAN_S5
U83A
2
1 L44 2AVDD_F14
SCD1U10V2KX-4GP
1
C852 0R0603-PAD
3D3V_S0 3D3V_LAN_S5
1
3D3V_S5 R747 GIGA C851 GIGA 16 PCIE_TXP1 P10 A14 BIASVDD_G
0R0402-PAD PCIE_RXDP BIASVDD
16 PCIE_TXN1 N10 PCIE_RXDN
2
GIGA
2
2
1 R751 2 VDDP_G SCD1U10V2KX-4GP 16 PCIE_RXP1 SCD1U16V2KX-3GP

2 1C849N6GIGA
PCIE_TXDP
R750 0R0603-PAD 16 PCIE_RXN1 SCD1U16V2KX-3GP
2 1C853 P6 H14 XTALVDD_G
PCIE_TXDN XTALVDD
0R3-0-U-GP Place PLLVDD/AVDDL
G11
D11
K12
P13
1D2V_LAN_S5 1D2V_LAN_S5 CKT as close to chip as CLK_PCIE_LAN
D5
N8
A8
GIGA 3 CLK_PCIE_LAN REFCLK+
5789 U83B possible 3 CLK_PCIE_LAN# CLK_PCIE_LAN# P8 REFCLK-
1
A13 AVDD_A13
VDDP
VDDP
VDDP
VDDIO
VDDID
VDDID
AVDD
3D3V_LAN_S0 1R776
A1 DC 2 VDDC1.2 B8 1 L42 2 AVDDL_G 7,16,20,26,30,31,32,34,45 PLT_RST1# C2 PERST# AVDD F14 AVDD_F14
0R3-0-U-GP 0R0603-PAD
SCD1U10V2KX-4GP
A3 DC E5 A6
SCD47U10V3ZY-GP
VDDC1.2 16,30,31 PCIE_WAKE# WAKE#
1
C854
SCD1U10V2KX-4GP
A4 DC VDDC1.2 E6
1
C838 A5 DC E7 C855
VDDIO_PCI_G VDDC1.2 3D3V_LAN_S5
A7 DC VDDC1.2 E8
2
DY GIGA R752GIGA
BCM5789
A9 DC VDDC1.2 E9
2
C B1 DC VDDC1.2 E10 2 1VAUX_PRESENTJ12 VAUX_PRESENT

C
B2 DC VDDC1.2 F5 1 L45 2GPHY_PLLVDD 1 5787 2 1KR2J-1-GP A2 ATTN_BTN#
GIGA 0R0603-PAD R753 4K7R2J-2-GP
SCD1U10V2KX-4GP
B3 DC F10 B13
SCD47U10V3ZY-GP
MDI0+ 23
BCM5787M
VDDC1.2 3D3V_LAN_S0 1 TRD0P
1
B5 DC VDDC1.2 G4 DY GIGA R754
5789 24K7R2J-2-GP TRD0N B14 MDI0- 23
B6 DC VDDC1.2 J4
B9 DC J5 C856 C850 DY 2R775 1KR2J-1-GP
1 L3 C13 MDI1+ 23
VDDC1.2 VMAINPRESNT TRD1P
2
C1 DC VDDC1.2 J10 2 1LOW_PWR L6 LOW_PWR TRD1N C14 MDI1- 23
C3 DC K4 R762 0R0402-PAD
VDDC1.2
C5 DC VDDC1.2 K5 1 L43 2 PCIE_PLLVDD 3D3V_LAN_S0
TRD2P D13 MDI2+ 23
C6 DC K6 0R0603-PAD D14 MDI2- 23
VDDC1.2 TRD2N
1
C7 DC K7 C857 SC4D7U10V5ZY-3GP H2
VDDC1.2 PWR_IND_LED#
2
C8 DC K8 DY GIGA C858 J2 E13 MDI3+ 23
VDDC1.2 SCD47U10V3ZY-GP R755 ATTN_IND_LED# TRD3P
C9 DC H3 CLKREQ# TRD3N E14 MDI3- 23
2
C10 DC 4K7R2F-GP 5789
D1 DC
D2 DC 1 L46 2 PCIE_SDSVDD 5787
1
D3 DC F12 0R0603-PAD 2 R756 1 CLK_SEL F4 C12 CS# 1 2
AVDDL REFCLK_SE CS#
1
D4 DC F13 AVDDL_G C859 SC4D7U10V5ZY-3GP 4K7R2F-GP E11 R757 4K7R2J-2-GP
AVDDL C860 SSCLK
E1 DC DY GIGA SCD47U10V3ZY-GP
DY SI E12
SO TPAD28 TP78
E3 DC 5787 SO F11 1
2
E4 DC 16,18,26,30 SMB_CLK 1 2LAN_SMB_CLK D10 SMB_CLK
F1 DC GPHY_PLLVDD G14 GPHY_PLLVDD 16,18,26,30 SMB_DATA
0R2J-2-GP
1 R749 2LAN_SMB_DATAD9
SMB_DATA DY
F2 DC 0R2J-2-GP R758 G12 1 R760
210KR2J-3-GP
3D3V_LAN_S5 R759 2 GPIO0 LAN_EE_WP
F3 DC 578711K24R2F-GP A10 RDAC GPIO1 H13
G1 DC G13 1 R761 2
SC4D7U10V5ZY-3GP
PCIE_PLLVDD GPIO2 10KR2J-3-GP
G2 DC PCIE_PLLVDD M8
GIGA ENERGY_DET C4 5789
G3 DC
H1 DC 1 C863
1
C861
SCD1U10V2KX-4GP
H4 DC SPEED1000LED# A12 1G_LED# 23

E
B
H11 DC M6 PCIE_SDSVDD Q53 3D3V_LAN_S5 B11
B
PCIE_SDSVDD SPD100LED# 100M_LED# 22,23
J1 DC B TRAFFICLED# B10 LAN_ACT_LED# 22,23
2
2
J3 DC 5787
MMJT9435T1G-GPU
K14 NC#K14 LINKLED# A11 10M_LED# 22,23
J11 DC L8 NC#L8
C
1D2V_LAN_S5 2D5V_LAN_S5
J14 DC GIGAGIGA L9
SC4D7U10V5ZY-3GP
NC#L9
K3 DC TRST# D12 1 2
K9 DC L13 REGCTL25 C11 R796 4K7R2F-GP
REGCTL25 TMS
1
K10 DC C864 C862 H12 GIGA

SC10U10V5ZY-1GP
C865 TDI
K13 DC TCK D7
L2 DC SCD1U10V2KX-4GP TDO D6
2
L4 DC J13 REGCTL12 GIGA

L5 DC
REGCTL12 GIGA
L10 LAN_EEDATA
3D3V_LAN_S5GIGA
L11 DC M1 UART_MODE EEDATA
L12 DC K1 SERIAL_DI EECLK K11 LAN_EECLK
3D3V_LAN_S5 L14 DC L1 L7 1 2
SERIAL_DO TEST# R763 4K7R2F-GP
M2 DC
M3 DC VSS J6 5787
E
M4 DC VSS J7 GIGA Q54 GPHY_TVCOI D8 1 2

R764 4K7R2F-GP
M9 DC VSS J8 B
M11 DC J9 MMJT9435T1G-GPU LAN_X1_G P12 5789
VSS XTALI
M12 DC K2 1D2V_LAN_S5 GIGA X8
VSS
C
M13 DC M5 2 5787
1 SC27P50V2JN-2-GP 1 2 2 R765 1LAN_X0_G
N12
SC27P50V2JN-2-GP
SC10U10V5ZY-1GP
2D5V_LAN_S5 VSS XTALO

M14 DC VSS M7 2 R7665787
10R2J-2-GP GIGA200R2J-L1-GP
N2 DC VSS M10 2 R7675787
10R2J-2-GP C866 XTAL-25MHZ-70GP
1
1
R768 0R2J-2-GP C868 C869 C867 C870 82.30020.581 GIGA
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
N3 DC N1
SC4D7U10V5ZY-3GP
VSS BCM5787MKFBG-GP
N4 DC VSS N5 2 5787
1
N13 DC VSS N7 2 R7695787
10R2J-2-GP GIGA C871
2
2
N14 DC N9 R770 0R2J-2-GP GIGA
VSS
A P1 DC VSS N11 LAN_N11
2 5787
1 <Variant Name> A
2 R7725787
10R2J-2-GP GIGA GIGA GIGA GIGA
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
P2 DC VSS P5
P3 P7 2 R771 10R2J-2-GP
5787
C835 P4 DC VSS
1
C839 C837 C836 R773 0R2J-2-GP

DC
P14 DC
VSS
VSS
P9
P11 2 5787
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
R774 0R2J-2-GP 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

2

GIGA
B4
B7
B12
E2
F6
F7
F8
F9
G5
G6
G7
G8
G9
G10
H5
H6
H7
H8
H9
H10
BCM5787MKFBG-GP Title
GIGA GIGA GIGA GIGA 71.05787.00U
"GIGA" -- stuff when 5789 or 5787M.
"5789" -- stuff when 5789. BCM5787M / BCM5789
"5787" -- stuff when 5787. A3
AG1 -1
5 4 3 2 1
1D05V_S0
Aux Power
-1M Modify
4.7K / 0.22U ?
1
R719
3D3V_AUX_S5 56R2J-4-GP
2
1
PM_THRMTRIP-I# 4
R525
E
100KR2J-1-GP
1 R720 2 B CHT2222APT-GP
5V_AUX_S5 4,15 H_PWRGD 10KR2J-3-GP Q51
2
DCBATOUT
SC1U6D3V2KX-GP
100mA DY DY
C
1 2 C37 SHUTDOWN_S5 1 R496 2S5_EN_3 C623
SCD1U16V2ZY-2GP 1KR2J-1-GP
2
U4
Q8 B 1
1
1
1 8 CHT2222APT-GP D17
C36 C35 OUTPUT INPUT BAT54PT-GP 3
2 SENSE FEEDBACK 7 PURE_HW_SHUTDOWN# 19,31
E
1
SCD1U16V2ZY-2GP
SC10U10V6ZY-U AUX_SD 3 6 C33
SHUTDOWN VO TAP
2
DY 4 SC1U50V5ZY-1-GP 2
GND
2
ERROR# OUTPUT 5 DY
2
R45 S5_EN_21 R70 2 S5_EN 30,31
0R0402-PAD LP2951CDR2G-GP 74.02951.F31 10KR2J-3-GP
1
*Layout*
1
C71
SCD1U10V2KX-4GP
15 mil
2
T(soft)=1.736ms
TPS51120_EN1_5 TPS51120_EN1_5 40
1
C472
3D3V_AUX_S5 SC4700P50V2KX-1GP
2
3
D
5V_AUX_S5
1
I max = 120 mA SHUTDOWN_S5 1 Q17
1
R24 G 2N7002-8-GP
1
U5 BC2 36K5R3F-2-GP
R1 S
2
SC22P50V3JN-GP R358
2
1 5 1MR2J-1-GP
SHDN# SET
2 GND 1 2
3 IN OUT 4
2
R23
22KR2J-GP R2
1
G913CF-GP
BC1 BC3 Vout = 1.25*(1+ R1/R2) T(soft)=1.736ms
2
SC1U10V3ZY-6GP SC1U10V3ZY-6GP
74.00913.A3F
2
TPS51120_EN2_3D3 TPS51120_EN2_3D3 40
3
D
1
1 Q16
G 2N7002-8-GP C457
S SC4700P50V2KX-1GP
2
Run Power 5V_S0 5V_S5
U51
1 S D 8
S D
DY C323 2
S D
7
1 2 3 6
4 G D 5
DCBATOUT Q18 SCD1U25V3KX-GP
TP0610K-T1-GP AO4422-1-GP
84.04422.B37
1 R360
2 Z_12V 2 3 RUN_PWR_CTLR
S
10KR2J-3-GP
D
K
1
C272
84.00610.C31 R359 D29
1
200KR3J-GP MMGZ5242BPT-GP 3D3V_S0 3D3V_S5

2
1
U52
SCD1U25V3KX-GP
G
2 1 R742 1 S D 8
A
2
R367 330KR2F-L-GP 47KR2J-2-GP 2 S D 7

1
3 S D 6
R366 4 G D 5 <Variant Name>
2
Q19 100KR2J-1-GP
GND 2 AO4422-1-GP
3
Wistron Corporation
D
2
3 OUT 1
R2 Q52 1D8V_S0 1D8V_S3 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
R1 G
IN 1 S 2N7002-8-GP U27 Taipei Hsien 221, Taiwan, R.O.C.
16,18,30,31,41,43,52 PM_SLP_S3#
2
84.27002.L04 1 S D 8
CHDTC124EU-1GP 2 S D 7 Title
84.00124.F1K S D
3
4 G D
6
5 RUN and AUX POWER
IRF7805ZPBF-GP A3
84.07805.A37 AG1 -1M
A B C D E
TPS51124
CPU_CORE 1D8V/1D05V
Intersil ISL6262
Input Power Output Power
5V_S5
VCC
VID Setting Output Signal 1D8V_S0 (7A)
4 H_VID0 1D8V (O) 4
VID0(I / 1.05V) 6262_PWRGOOD
H_VID1 PGOOD(OD / 3.3V) DCBATOUT_TPS51124
VID1(I / 1.05V) VIN
H_VID2 CLK_EN# 1D05V_S0 (7A)
VID2(I / 1.05V) CLK_EN#(O) 1D05V(O)
H_VID3
VID3(I / 1.05V)
H_VID4 Input Signal
VID4(I / 1.05V)
H_VID5 TPS51124_EN1
VID5(I / 1.05V) Output Power EN1
H_VID6
VID6(I / 1.05V) VCC_CORE_S0(Imax=48A) TPS51124_EN2
VCC_CORE_PWR(O) EN2
Input Signal
PSI#
PSI# (I / 3.3V) Output Signal
CPUCORE_ON CPUCORE_ON
PGD_IN (I / 3.3V) PGOOD1
PM_DPRSLPVR
DPRSLPVR (I / 3.3V) CPUCORE_ON
H_DPRSTP# PGOOD2
DPRSTP# (I / 3.3V)
Voltage Sense
3
VCC_SENSE 3
VSEN(I / Vcore)
VSS_SENSE
RTN(I / Vcore) Charger Max8725
Input Signal Output Signal
Input Power
CHGON#/OFF BT+SENSE
DCBATOUT_6262 ICTL BATT
VCC(I)
BT_TH AC_IN
5V_S0 PKPRES ACOK
VCC(I)
3D3V_S0
VCC(I) Input Power Output Power
AD+ BT+
ACIN VOUT (O)
DCBATOUT
VOUT (O)
2 TPS51120 2
5V/3D3V
PGOOD1(OD / 5V) CPUCORE_ON
PGOOD2(OD / 5V) CPUCORE_ON

TPS51120_EN1_5
EN1
Output Power
TPS51120_EN2_3D3
EN2
Adapter
5V_DC_S5 (6A)
5V(O)
AD_OFF AD_IN
3D3V_DC_S5 (5A) (I) (O)
3D3V(O)
Input Power
1 <Variant Name> 1
Input Power Output Power
DCBATOUT_TPS51120
VIN AD_JK AD+
VCC(I) VCC(O) Wistron Corporation
5V_AUX_S5 Taipei Hsien 221, Taiwan, R.O.C.
VCC(I)
Title
Power Block Diagram
A3 SA
AG1
A B C D E
5 4 3 2 1
G81
DCBATOUT_6262 3D3V_S0 1 2
5V_S5 5V_S0
GAP-CLOSE-PWR
1
PGOOD G80
1
R188 1 2
Power good open-drain output.
1
R777 R222 10R3J-3-GP
0R2J-2-GP 10R2J-2-GP R193 Will be pulled up externally by GAP-CLOSE-PWR
1K91R3F-GP
DY a 680. resistor to VCCP or 1.9k. to 3.3V. G79
2
1 2
2
1
C264 GAP-CLOSE-PWR
6262_AGND
1 2 VGATE_PWRGD 7,16,48 G78
SCD01U25V2KX-3GP R200 0R0402-PAD 1 2
DCBATOUT DCBATOUT_6262
2
D D
1
C307 GAP-CLOSE-PWR
G26
22
20
48
1
SC1U10V3KX-3GP 1 2
3V3
VCC
VIN
PGOOD
GAP-CLOSE-PWR
G25
1 2
21 35 6262_UGATE1 39
GND UGATE1
GAP-CLOSE-PWR
49 GND_T BOOT1 36 6262_BOOT1 1 R226 2 G24
1
0R0603-PAD 1 2
C310
6262_AGND SCD22U25V3ZY-GP GAP-CLOSE-PWR
2
G23
34 6262_PHASE1 39 1 2
PHASE1
4 PSI# 1 R199 2 6262_PSI# 2 PSI#
0R0402-PAD 32 6262_LGATE1 39 GAP-CLOSE-PWR
CPUCORE_ON LGATE1
1 R192 2 6262_PGD_IN3
PGD_IN
R609 3K65R3F-GP
0R0402-PAD 33 6262_VSUM 1 2
6262_RBIAS 4 PGND1
6262_AGND 1 2 RBIAS
R191 147KR2F-GP 24 6262_ISEN1 1 2
ISEN1 6262_ISENP1 39
2
4 CPU_PROCHOT# 5 VR_TT#
1
5V_S5 R221 R608 10KR3F-L-GP
R612 1 2 4K02R3F-GP 1 R611 2 6262_NTC 6 DY SCD22U10V3KX-2GP 0R2J-2-GP
C269 C268 NTC
1 R778 2 5V_S0 C306 DY
2
6262_AGND 1 2 NTC-470K-1-GP 6262_AGND 1 2 6262_SOFT7 0R3-0-U-GP1 R797 2 1 2
SOFT 6262_ISENN1 39
1
SCD01U16V2KX-3GP SCD015U25V3KX-GP 0R0603-PAD
470K /0402 size 31 1 2 R223 1R3F-GP
PVCC
C
Place close to phase 1 chocke H_VID0 1
R227
2
0R0402-PAD
6262_VID0 37 VID0 C309 SC4D7U6D3V3KX-GP
C
H_VID1 6262_VID1 6262_UGATE2 39

If NTC=330Kohm, R10=8.66K 1
R228
2
0R0402-PAD
38 VID1 UGATE2 27
H_VID2 1 2 6262_VID2 39 26 6262_BOOT2 1 R225 2
R231 0R0402-PAD VID2 BOOT2 0R0603-PAD
5 H_VID[0..6]
1
H_VID3 1 2 6262_VID3 40
R232 0R0402-PAD VID3 C308
H_VID4 1 2 6262_VID4 41 SCD22U25V3ZY-GP
VID4
2
R229 0R0402-PAD 28 6262_PHASE2 39
H_VID5 6262_VID5 PHASE2 3K65R3F-GP
1 2 42 VID5 R610
R230 0R0402-PAD 30 6262_LGATE2 39
H_VID6 6262_VID6 LGATE2 6262_VSUM 1
1 2 43 VID6 2
R197 0R0402-PAD 29
6262_CORE_ON PGND2
40,41,43,48 CPUCORE_ON 1 2 44 VR_ON
R198 0R0402-PAD 23 6262_ISEN2 1 2
ISEN2 6262_ISENP2 39
1 2 6262_DPRSLP 45
16 PM_DPRSLPVR DPRSLPVR
2
R196 0R0402-PAD R607 10KR3F-L-GP
1
1 2 6262_DPRSTP# 46 C305 R224
4,15 H_DPRSLP# DPRSTP#
R194 0R0402-PAD 0R2J-2-GP
1 2 6262_CLKEN# 47 SCD22U10V3KX-2GP DY
3 CLK_EN# CLK_EN#
2
R195 0R0402-PAD 1 2 6262_ISENN2 39
1
NC 25 6262_AGND 1 2
R161 1K82R3F-GP C233 SC1KP25V3MX-GP R220 1R3F-GP
1 2
OCSET 8 6262_OCSET 1 R163 2 OCP>=88A
1 2 1 2 6262_VDIFF 13
R160 1K4R3F-1-GP C266 SC470P50V2KX-3GP VDIFF 18K7R3F-1-GP
19 6262_VSUM
B VSUM B
R189
1
DY 6262_FB212 R182
1 2 FB2 2K61R3F-GP
SCD22U10V3KX-2GP
1
2KR2-GP
SCD047U50V3KX-GP
1
1
6262_FB 11 FB
1 2
C259 C260 R219
1 2 1 2 C232 11KR2F-L-GP
2
R162 61K9R2F-GP SCD033U16V3KX-GP R185
2
NTC-10K-9-GP
1 2 6262_COMP10 ISL6262CRZ-T-GPU
COMP
1 2 -1
2
C231 SC390P50V3JN-GP R190 3K57R3F-L-GP
VO 18 6262_VO
Switching Frequency=300KHz
6262_VW 9
Place close to phase 1 chocke
DROOP
1 2 VW
1
VSEN
RTN
DFB
1
C267 SC5600P50V3KX-GP R186
1KR2F-3-GP C304
PL 74.06262.073 U25 SCD22U10V2KX-1GP
15
14
16
17
2
2
5 VSS_SENSE 1 R184 2 6262_RTN 6262_DFB

1
0R0402-PAD 6262_AGND
C265
SCD01U50V3KX-4GP 1 R187
6262_DROOP
2
2
5 VCC_SENSE 1 R183 2 6262_VSEN

0R0402-PAD 2K55R3F-GP G75
1
C262 C263
A
PH Load Line 1 2
<Variant Name> A
6262_VO GAP-CLOSE-PWR
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
1 2
2
When test without cpu, 6262_AGND

C261 SC180P50V3JN-LGP
R183 & R184 change to 0 ohms Wistron Corporation
If VCC_SENSE and VSS_SENSE pins have pulled 6262_AGND 6262_AGND 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
resistors to VCC_CORE_S0
==> Remove R183/R184 Title
CPU Vcore Power_1
A3 -1
AG1
5 4 3 2 1
5 4 3 2 1
DCBATOUT_6262
1
C373
C685 C322 EC321
SCD1U25V3ZY-1GP
SC10U35V0ZY-1GP
SC10U35V0ZY-1GP
SC10U35V0ZY-1GP
D D
2
5
6
7
8
D
D
D
D
U30
IRF7807ZPBF-GP
ENG
G
S
S
S
Panasonic ETQP4LR36WFC
4
3
2
1
10*11.5*4mm VCC_CORE_S0 Iomax=44A
0.34uH / 24A
38 6262_UGATE1 L23 DCR=1.1mohm
OCP>=88A
38 6262_PHASE1 1 2
38 6262_LGATE1 L-D36UH-1-GP
1
TC4 TC9 TC6 TC7 C684
SCD1U25V3ZY-1GP
SE330U2VDM-L2GP
SE330U2VDM-L2GP
SE330U2VDM-L2GP
SE330U2VDM-L2GP
2
2
5
6
7
8
5
6
7
8
2
DY
D
D
D
D
D
D
D
D
U28 U29 G76 G77
IRF7805ZPBF-GP IRF7805ZPBF-GP GAP-CLOSE-PWR GAP-CLOSE-PWR
Id=30A
1
Qg=8~11nC, Rdson=14.4~18mohm
C C
G
S
S
S
G
S
S
S
6262_ISENN1 38
4
3
2
1
4
3
2
1
6262_ISENP1 38
KEMET
ENG 330uF / 3V / V size
ESR=9mohm / Iripple=3.7A
DCBATOUT_6262
1
C718 C311 C717 C372
SCD1U25V3ZY-1GP
SC10U35V0ZY-1GP
SC10U35V0ZY-1GP
SC10U35V0ZY-1GP
2
2
5
6
7
8
D
D
D
D
U33 DY
IRF7807ZPBF-GP
ENG Panasonic ETQP4LR36WFC

G
S
S
S
10*11.5*4mm
4
3
2
1
B
0.34uH / 24A B
DCR=1.1mohm
38 6262_UGATE2 L27
38 6262_PHASE2 1 2
38 6262_LGATE2 L-D36UH-1-GP
1
TC5 TC8
SE330U2VDM-L2GP
SE330U2VDM-L2GP
2
2
5
6
7
8
5
6
7
8
2
D
D
D
D
D
D
D
D
U32 U35 G82 G83

Id=46A IRF7805ZPBF-GP IRF7805ZPBF-GP GAP-CLOSE-PWR GAP-CLOSE-PWR
Qg=15~21nC, Rdson=6.9~8.6mohm
1
1
G
S
S
S
G
S
S
S
4
3
2
1
4
3
2
1
ENG
38 6262_ISENP2
A 38 6262_ISENN2 <Variant Name> A
Wistron Corporation
Title
CPU Vcore Power_2
A3 SD
AG1
5 4 3 2 1
A B C D E
G48
1 2 DCBATOUT_51120
GAP-CLOSE-PWR DCBATOUT_51120 G33
G49 1 2
1 2
SC10U35V0ZY-1GP
SC10U35V0ZY-1GP
GAP-CLOSE-PWR
GAP-CLOSE-PWR G34
1
G50 C792 1 2
5
6
7
8
1 2 C794 EC470
D
D
D
D
U49 SCD1U25V3ZY-1GP GAP-CLOSE-PWR
2
GAP-CLOSE-PWR AO4422-1-GP G35
G51
51120_V5FILT
Iomax=11A 1 2
4 1 2 4
Qg=9.8nC, GAP-CLOSE-PWR
GAP-CLOSE-PWR Rdson=20~25mohm G36
G
S
S
S
G52 R354 GS 10*10*4 4D7uH 5V_PWR 1 2 5V_S5
4
3
2
1
1 2 5V_PWR 5V Iomax=6A
DCBATOUT 51120_VREG5 1 2 51120_DRVH1
L37 DCR=25mohm, Isat=6A GAP-CLOSE-PWR
GAP-CLOSE-PWR 5D1R3F-GP 51120_LL1 1 2 OCP>12A G37
1
IND-4D7UH-85-GP 1 2
C454
5
6
7
8
SC1U10V3KX-3GP GAP-CLOSE-PWR
D
D
D
D
U50 G38
1
AO4422-1-GP 1 2
51120_AGND DCBATOUT_51120
1
C453 C780 R667
51120_LL2 1 2 51120_VBST2_11 R351 2 51120_VBST2 Iomax=11A SC33P50V2JN-3GP 30KR2F-GP TC13 GAP-CLOSE-PWR
2
0R0603-PAD ST220U6D3VDM-15GP
Qg=9.8nC, DY DY G39
2
SCD1U50V3ZY-GP NEC 220uF ,V size
G
S
S
S
1 2
2
1
Rdson=19.6~24mohm ESR=25mohm
4
3
2
1
C456 C455 51120_VFB1 GAP-CLOSE-PWR
51120_LL1 1 251120_VBST1_11 R357 2 51120_VBST1 SCD1U50V3ZY-GP Iripple=2.2A G53
1
0R0603-PAD 1 2
SCD1U50V3ZY-GP 51120_V5FILT 51120_DRVL1 R668
51120_VREG5 7K5R3F-GP GAP-CLOSE-PWR
SC10U10V5KX-2GP
51120_VREG3 51120_COMP2 1R663

DY
SC10U10V5KX-2GP
2
2
1
1
0R0603-PAD
C784 C783 51120_COMP1 1R666 2
0R0603-PAD 51120_AGND
2
3D3V_S0
19
21
28
13
20
22
7
2
3 U45 3
VREG3
VREG5
VBST1
VBST2
V5FILT
COMP2
COMP1
VIN
1
G40
R338 1 2
100KR2J-1-GP
1 2 51120_EN1 29 15 51120_LL2 GAP-CLOSE-PWR
36 TPS51120_EN1_5 EN1 LL2
36 TPS51120_EN2_3D3 1 R352 0R0402-PAD
2 51120_EN2 12 EN2 LL1 26 51120_LL1 G41
2
R356 0R0402-PAD
TP52 1TPAD28 10 1 2
TP53 EN3
1TPAD28 9 EN5
30 51120_PGOOD1 1 R342 2 DCBATOUT_51120 GAP-CLOSE-PWR
51120_VFB2 PGOOD1 51120_PGOOD2 1 0R0402-PAD CPUCORE_ON 38,41,43,48
1 2 6 11 2 G42
VFB2 PGOOD2
51120_V5FILT 1 R664 20R0402-PAD 51120_VFB1 3 VFB1
R339 0R0402-PAD
3D3V_PWR 1 2 3D3V_S5
R665 0R0402-PAD 51120_DRVL1
SC10U35V0ZY-1GP
DRVL1 25
5V_PWR 51120_DRVL2
SC10U35V0ZY-1GP
1 16 GAP-CLOSE-PWR
VO1 DRVL2
1
3D3V_PWR 8 C795 G43
VO2
5
6
7
8
1
27 51120_DRVH1 C793 1 2
DRVH1
D
D
D
D
51120_VREF2 4 14 51120_DRVH2 U47 EC471
VREF2 DRVH2
2
AO4422-1-GP SCD1U25V3ZY-1GP GAP-CLOSE-PWR
SKIPSEL
2
TONSEL
G44
PGND1
PGND2
1
Iomax=11A 1 2
GND
GND
CS1
CS2
C779
SC1KP25V3MX-GP Qg=9.8nC, 3D3V Iomax=6A GAP-CLOSE-PWR
G
S
S
S
2
TPS51120RHBR-GPU1 74.51120.073 Rdson=20~25mohm ENG OCP>12A

G45
24
17
5
33
23
18
51120_SKIPSEL 32
31
4
3
2
1
3D3V_PWR 1 2
L36
51120_AGND 51120_DRVH2
51120_LL2 1 2 GAP-CLOSE-PWR
IND-3D3UH-43-GP G46
51120_TONSEL 1 2 51120_VREF2 1 2
51120_V5FILT
5
6
7
8
R341 0R0402-PAD
D
D
D
D
2 51120_AGND U48 2
GAP-CLOSE-PWR
1 R355 2 51120_CS1 AO4422-1-GP G47
1
1 2
2
15KR3F-GP C777 R662 TC12

1 2 51120_CS2 R340 Iomax=11A SC33P50V2JN-3GP 30K9R3F-GP ST220U6D3VDM-15GP GAP-CLOSE-PWR
2
R353 20KR3F-GP 0R0402-PAD DY DY
G
S
S
S
Qg=9.8nC, NEC 220uF ,V size
4
3
2
1
2
SC Rdson=19.6~24mohm ESR=25mohm
1
OCP 51120_VFB2
51120_DRVL2 Iripple=2.2A
1
51120_AGND
R661
51120_COMP1 13K3R2F-L1-GP
DY
1
2
GND VREF2 FLOAT V5FILT R675
22KR2J-GP G104
1
DY 51120_AGND 1 2
AUTOSKIP C786
Vout=1V*(R1+R2)/R2
1 2
SKIPSEL AUTOSKIP /FAULTS PWM PWM SC390P50V3JN-GP GAP-CLOSE-PWR

2
OFF DY C785 51120_AGND

SC1KP25V3MX-GP
CURRENT D-Cap
2
COMP N/A N/A

MODE MODE DY
For TPS51120,
51120_AGND
380k/CH1 290k/CH1 220k/CH1 180k/CH1 Vout=5V
TONSEL 590k/CH2 440k/CH2 330k/CH2 280k/CH2 51120_COMP2 1. If you use a 6.8uH inductor, the minimum ESR is 70m ohm.
1 <Variant Name> 1
2. If you use a 4.7uH inductor, the minimum ESR is 48m ohm.
1
5V
VFB1 N/A not use ADJ. R674 3. If you use a 3.3uH inductor, the minimum ESR is 34m ohm.
Fixed Output 22KR2J-GP
Vout=3.3V
Wistron Corporation
1
3.3V DY 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

VFB2 N/A not use ADJ. Fixed Output
C782 1. If you use a 4.7uH inductor, the minimum ESR is 51m ohm. Taipei Hsien 221, Taiwan, R.O.C.
1 2
SC390P50V3JN-GP
2. If you use a 3.3uH inductor, the minimum ESR is 36m ohm.
2
DY Title
EN1,EN2 Switcher OFF not use Swithchr ON Switcher ON C781 3. If you use a 2.5uH inductor, the minimum ESR is 27m ohm. 5V_UP_S5/3D3V_S5/5V_S5
SC1KP25V3MX-GP
2
DY Size Document Number Rev

EN3,EN5 LDO OFF not use LDO ON VREG3 on A3 -1
AG1
51120_AGND Date: Tuesday, January 10, 2006 Sheet 40 of 53
A B C D E
DCBATOUT_51124
DCBATOUT DCBATOUT_51124
1D8V / 7.0A
5
6
7
8
1
D
D
D
D
1
G27
2
U43
AO4422-1-GP
EC444
SCD1U25V3ZY-1GP
C425 C426
OCP>=14A
SC10U35V0ZY-1GP
SC10U35V0ZY-1GP
2
2
GAP-CLOSE-PWR 1D8V_S3 1D8V_PWR
G28
G
S
S
S
1 2
1D8V_PWR
ENG G102
4
3
2
1
GAP-CLOSE-PWR Voutsetting=1.838V 1 2
G29 51124_DRVH1 L35 GAP-CLOSE-PWR
51124_LL1
1D05V_S0/7A 1 2 1 2
1
G98
2
OCP>=14A GAP-CLOSE-PWR IND-3D3UH-55-GP GAP-CLOSE-PWR
5
6
7
8
G30 TC11 1D8V Iomax=7A G99
D
D
D
D
1D05V_PWR 1D05V_S0 U42
SC33P50V3JN-GP
1 2 1 2
OCP>14A
1
GAP-CLOSE-PWR
SE220U2D5VDM-3GP
AO4422-1-GP
1
GAP-CLOSE-PWR DY C873 G96
G90 G31 D28 R779 C443 1 2
39K2R2F-L-GP SCD1U50V3ZY-GP GAP-CLOSE-PWR
SSM24PT-GP
1 2 1 2
2
DY DY G100
G
S
S
S
2
GAP-CLOSE-PWR GAP-CLOSE-PWR 51124_VFB1 1 2
A
4
3
2
1
G85 G32 GAP-CLOSE-PWR
1
1 2 1 2 51124_DRVL1 G97
R780 1 2
GAP-CLOSE-PWR GAP-CLOSE-PWR 27KR2F-L-GP GAP-CLOSE-PWR
G92 G103
1 2 1 2
2
Panasonic 220uF ESR=15mohm GAP-CLOSE-PWR
GAP-CLOSE-PWR G101
G91 Iripple=2.7A 1 2
1 2 3D3V_S0 51124_GND GAP-CLOSE-PWR
GAP-CLOSE-PWR
1
G84 DY
R781
1 2
5V_S5 100KR2J-1-GP
GAP-CLOSE-PWR
G87
2
1 2
1
GAP-CLOSE-PWR 1 2
G88 R782 R783 0R0402-PAD
51124_PGD1
51124_PGD2
3D3R3J-L-GP 1D05V_PWR
SC4D7U10V5ZY-3GP
1 2
1D8V_PWR
C874
1 2 CPUCORE_ON 38,40,43,48
1
GAP-CLOSE-PWR 51124_VFB2 R784 0R0402-PAD

G86 2 51124_VFB1
1 2
2
GAP-CLOSE-PWR 1 C875
24
U44
2
5
1
6
7
SC1U10V3ZY-6GP
2
VFB1
VFB2
VO1
VO2
PGOOD1
PGOOD2
51124_GND
R786 DY
51124_V5FILT 15 4 51124_TONSEL 1 2 51124_V5FILT
V5FILT TONSEL 10KR2J-3-GP
16 V5IN
1
21 51124_DRVH1
51124_EN1_1 DRVH1 51124_DRVH2
16,31,43 PM_SLP_S5# 1 2 23 EN1 DRVH2 10
R785
1 0R0402-PAD
2 51124_EN2_1 8 R788
16,18,30,31,36,43,52 PM_SLP_S3# EN2
R787 0R0402-PAD 18 0R0402-PAD
51124_LL1 PGND1
20 LL1 PGND2 13
2
51124_LL2 11 25
LL2 GND
GND 3
1
DY DY 51124_GND
DRVL1
DRVL2
VBST1
VBST2
TRIP1
TRIP2
C876 C877
SCD01U16V3KX-GP
SCD01U16V3KX-GP
2
DCBATOUT_51124
17
14
22
9
19
12
51124_GND 51124_GND TPS51124RGER-GPU1 51124_GND
51124_TRIP1
51124_TRIP2 51124_DRVL2
5
6
7
8
1D05V Iomax=7A
1
D
D
D
D
U40 C446 C445 EC424

AO4422-1-GP OCP>14A
SCD1U25V3ZY-1GP 20KR3F-GPR789
20KR3F-GP R789 R790 51124_DRVL1
SC10U35V0ZY-1GP
SC10U35V0ZY-1GP
2
20KR3F-GP
2
Voutsetting=1.051V
2
51124_GND 51124_GND
G
S
S
S
G105
4
3
2
1
1D05V_PWR 51124_LL1 1 2C878 51124_VBST1 1 2

51124_DRVH2
L34
ENG SCD1U50V3ZY-GP GAP-CLOSE-PWR
51124_LL2 1 2
IND-3D3UH-55-GP 51124_LL2 1 2 C879 51124_VBST2

5
6
7
8
51124_GND
D
D
D
D
U39 TC10 SCD1U50V3ZY-GP

1
SC33P50V3JN-GP
30K1R3F-GP
AO4422-1-GP
1
C880 R793
SE220U2VDM-8GP
C447
SCD1U50V3ZY-GP
2
DY
G
S
S
S
51124_VFB2 DY
4
3
2
1
<Variant Name>
1
51124_DRVL2
ENG
75KR3F-GP
Vtrip(mV)=Rtrip(Kohm)*10(uA)
R794 Iocp=(Vtrip/Rdson)+((1/(2*L*f))*((Vin-Vout)*Vout)/Vin))
Wistron Corporation
2

Panasonic 220uF ESR=15mohm GND OPEN V5FILT
51124_GND Title
Iripple=2.7A
TPS51124 1D8V_S3/1D05V_S0
Vout=0.75V*(R1+R2)/R2 TONSEL 230k/CH1
283k/CH2
283k/CH1
346k/CH2
346k/CH1
423k/CH2 Size
A3
Document Number Rev
AG1 -1
5 4 3 2 1
MAX8725_PDS
ID = 10A @
AD+ DCBATOUT
U61
VGS = 10V
5 4 U16
AD+_TO_SYS 1 R465
D G
6 3 2 1 S D 8
D S S D BT+
7 2 2 7
1
D 8
D S
1 D01R3720F-2-GP 3 S D 6 D
1
D S
R489 4 G D 5
100KR2F-L1-GP C549 AO4407-1-GP
1
SCD1U50V3KX-GP C567 AO4407-1-GP
1
SC1U50V5ZY-1-GP EC559
2
SCD1U50V3KX-GP EC68
2
MAX8725_ACIN Near MAX1909 DY
SCD1U50V3ZY-GP
2
1 Pin 24
1
C30 R507
2
SC1U10V3ZY-6GP 13KR2F-GP
AC_IN Threshold 2.089V Max. G56
2
Near MAX1909 G57 GAP-CLOSE

2
AC_IN > 2.089V --> AC DETECT GAP-CLOSE

Pin 3
1
DCBATOUT
AD+ C568 AD+_TO_SYS
C569
MAX8725_CSSP
MAX8725_CSSN
1
1
SCD1U50V3KX-GP
SCD1U50V3KX-GP
1
D12
2
CH521S-30-GP-U LDO :5.40V (< 5mA)
C
SET Vout MAX VCELL= 4.1998V/CELL C
VBAT=CELL*VCELL==>VCELL=VBAT/CELL 2
MAX1909_LDO
1
=VREF+(VVCTL-1.8) /9.52 =4.1998V Near MAX1909
4
3
2
1
C49
Pin 2
1
2
C52 SCD1U50V3KX-GP U66 C31 C32
G
S
S
S
C51
2
SCD1U25V3ZY-1GP 1 2 SI4835BDY-T1-GP
MAX1909_LDO
SC10U35V0ZY-1GP
SC10U35V0ZY-1GP
2
1
Near MAX1909 SC1U10V3ZY-6GP
MAX8725_DHIV
MAX8725_REF U10
26
25
Pin 1
D
D
D
D
R37
CSSP
CSSN
5
6
7
8
33R2J-2-GP
1
R19 MAX8725_PDS 27 22
PDS DHIV
1
R482 39KR2F-GP AD+_TO_SYS 24 28
100KR2F-L1-GP MAX8725_DC_IN 1 SRC PDL BT+
DCIN LDO 2
1
L3
When V(ICTL)<0.8V or DCIN<7V C48
2
21 MAX8725_DLOV SC1U10V3ZY-6GP CHG_PWR-2 1 2CHG_PWR-3 1 R477 2

-->Charge Disable MAX8725_VCTL DLOV
2
11 VCTL Near MAX1909 IND-6D8UH-43-GP
2 R17 1 MAX8725_ICTL 10 D01R3720F-2-GP
31 CHG_I_PWM
100KR2J-1-GP MAX8725_MODE 7
ICTL Pin 21
MODE
1
V( MODE ) >=2.8V = 4 Cell 23 MAX8725_DHI

DHI
1
5
6
7
8
R16 C558
SC1U10V3ZY-6GP
V( MODE ) = 1.8V = 3 Cell MAX8725_ACIN
D
D
D
D
U65
240KR2F-L-GP
3 ACIN
1
1
AO4422-1-GP C10 C14 C15 C13 C24
2
2
R20 MAX8725_IINP 8 IINP
2
20KR2F-L-GP MAX8725_DLO G59 G58

DLO 20
DY
2
MAX8725_CLS GAP-CLOSE GAP-CLOSE
SC1U10V3ZY-6GP
SC10U35V0ZY-1GP
CLS
1
B B
SC10U25V0KX-3GP
SC10U25V0KX-3GP
SC10U25V0KX-3GP
SC10U25V0KX-3GP
G
S
S
S
2
1
DY C28 R18
4
3
2
1
1
31 CHG_V_PWM 2 R503
1 10KR2F-2-GP MAX8725_ACOK 6 19
ACOK PGND
2
100KR2J-1-GP -1 Modify
29
SC1U10V3ZY-6GP
PGND
2
1
C557
DY R487 18 8725_CSIP
CSIP
MAX1909_LDO 1 2 CHARGE_ON1# 5 PKPRES
2
100KR2J-1-GP
31,44 BATA_IN# 1 R22 2
1KR2J-1-GP
MAX8725_CCV 13 17 8725_CSIN
MAX8725_CCI CCV CSIN
12 CCI BATT 16
1
MAX8725_CCS 14 15
CCS GND
1
REF
5V_AUX_S5 R15 C881 CHG_PWR-3

1
1KR2J-1-GP SC1KP25V3MX-GP
C27
2
R504
SCD01U50V3KX-4GP
2
4
1
78K7R3F-GP MAX8725ETI-GP-U
C25
V_REF :4.2235V (<500uA)
SCD1U25V3ZY-1GP
SCD1U25V3ZY-1GP
1
1
R500 74.08725.A73 EC50 EC49
SCD01U50V3KX-4GP
G15
100KR2J-1-GP 5V_AUX_S5 1 2
2
C26
2
ISOURCE_MAX = (0.075/R465)*(VCLS/VREF) GAP-CLOSE
MAX8725_REF
2
D SCD1U25V3ZY-1GP
31 CHG_4D35V# 1 Q38 R488 =4.1A
G 2N7002-8-GP 15K4R2F-GP So,Constant Power=19V*4.1A=77.9W
S
2
MAX1909_LDO
2
R468 MAX8725_CLS
A
47KR2J-2-GP Pre-CHG_I = 305mA <Variant Name> A
SC1U10V3ZY-6GP
1
1st BTY C29 BATA_CHG_I = (0.075/R477)*(VICTL/3.6)

R713 R490
=3.0A Wistron Corporation
2
100KR2J-1-GP 20KR2F-L-GP
AC_IN# 31
2
1st BTY BATB_CHG_I = (0.075/R477)*(VICTL/3.6) 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
SA rework 0920 Taipei Hsien 221, Taiwan, R.O.C.
84.27002.L04 =2.46A
2
2
3
D
MAX8725_ACOK 2N7002-8-GP Title
1
Q31
G Current limit setting: CHARGER_MAX8725
S 1st BTY
85W(85W/20V=4.25A)
2

A3
AG1 -1
5 4 3 2 1
A B C D E
4
1D5V_S0 4
Iomax=4.0A
3D3V_S0 5V_S5 1D8V_S3
2D5V
Iomax=1A
1
C238 C271 C237
1
SC1U10V3ZY-6GP SC10U10V5ZY-1GP SC10U10V5ZY-1GP
2
C40 DY
SC10U10V5ZY-1GP
U6
2
8 1 2D5V_PWR 2D5V_S0
NC#8 VIN U22
6
7
6
NC#7 BS 2
3 Vo (cal.)=2.568V G18
R202
Vo(cal.)=1.512V
OCP=6A
VCNTL
GND FB
5 4 1 2 1 2 7 5
GND
NC#5 VOUT 38,40,41,48 CPUCORE_ON POK VIN

0R0402-PAD 9 1D5V_S0
VIN
1
GAP-CLOSE-PWR
APL5332KAC-TRLGP 74.05332.B31 R28 G17 PM_SLP_S3# 8 3
EN VOUT
9
2K21R3F-L-GP 1 2 4
VOUT
1
GAP-CLOSE-PWR C239
2
G16 2 5912_FB R165 TC3
GND
FB
1
1K78R3F-GP ST100U4VBM-L1-GP
SCD01U16V2KX-3GP
1 2
2
1
3 TC1 3
R27 GAP-CLOSE-PWR ST100U4VBM-L1-GP APL5912-KAC-GP
2
1KR2F-3-GP 74.05912.A71
Rh/Rl=(Vout/0.8)-1 SO-8-P Trace Length=3cm
Trace Width=5mils
1
2
R204 Trace Resistance>80mohm

2KR2F-3-GP
2
Vo=0.8*(1+(R1/R2))
1D2V_S0
1D8V_S0
Iomax=2A
2 0D9V G20 2
1
5V_S5 1 2
5V_S5 Iomax=1A 1D8V_S3
C565
SC10U10V5ZY-1GP GAP-CLOSE-PWR
2
0D9V_PWR DDR_VREF_S0 G19
1
C18 1 2
1
1D8V_S0 SCD1U16V2ZY-2GP
1
C429 G95 GAP-CLOSE-PWR
2
SC1U10V3ZY-6GP C432 1 2 Vo(cal.)=1.200V G21
2
1
SC10U10V5ZY-1GP 1 2
2
GAP-CLOSE-PWR R30 1D2V_PWR 1D2V_S0

1KR2F-3-GP U7
G94 GAP-CLOSE-PWR
U74
1 2 G22
1 VIN VOUT 4 1 2
10 VIN VDDQSNS 1 GAP-CLOSE-PWR 2 APL5331_1D2V_VREF 3 VREF
16,31,41 PM_SLP_S5# 9 2 G93 6 8 GAP-CLOSE-PWR
S5 VLDOIN VCNTL NC
1
1
8 GND VTT 3 1 2 NC 7
1
7 4 R29 C76 2 5 TC2
16,18,30,31,36,41,52 PM_SLP_S3# S3 PGND SCD1U16V2ZY-2GP GND NC ST100U4VBM-L1-GP
6 5 GAP-CLOSE-PWR 9
VTTREF VTTSNS GND
2
2K2R2F-GP
GND
DDR_VREF_S3 2
2
APL5331KAC-TRLGP
1
C771 C772 TPS51100DGQR-GP -1 Modify

11
SC10U10V5ZY-1GP 74.05331.B31 Trace Length=1cm (500mils)

1
SCD1U16V2ZY-2GP DY 74.51100.079
Trace Width=8mils
2
C774 C775 SO-8-P

SC10U10V5ZY-1GP SC10U10V5ZY-1GP Trace Resistance>25mohm
Vout=1.8V*R2/(R1+R2)
2
1 2nd source: 74.02997.079 <Variant Name> 1
Wistron Corporation
Title
0D9V/1D2V/1D5V/2D5V
A3 -1
AG1
A B C D E
5 4 3 2 1
ADAPTER IN CIRCUIT
DCIN1 AD+
4
U62
D 1 AD+_JK 1 S D 8 D
S D
MMPZ5250BPT-GP
2 7
1
S D
SCD1U10V2KX-4GP
3 6
SCD47U50V5ZY
SCD1U50V3ZY-GP
1
1
2 EC56 EC51 D3 R469 C550 4 G D 5
EC55 330KR2F-L-GP
SCD1U50V3ZY-GP AO4407-1-GP
2
3
2
5 AD+_G
6
MH1
1
DC-JACK116-GP R470
22.10037.C61 Q32 100KR2F-L1-GP
R2
E
B
2
R1
C
C
31 AD_OFF B Q5 PDTA144EU-1GPU
CHT2222APT-GP
connect to KBC
E
C C
MAIN BATTERY CONNECTOR KBC_3D3V_AUX

1
2
3D3V_AUX_S5
D8 D9 D10
BAV99PT-GP-U BAV99PT-GP-U BAV99PT-GP-U
3
83.00099.K11 DY DY
1
BAT1
R73 8
100KR2F-L1-GP 1
RN8 2
2
1 4 BATA_CLK_1 3
31 BATA_SCL
31 BATA_SDA 2 3BATA_DAT_1 4
31,42 BATA_IN# 5
SRN33J-5-GP-U 6
BT+ 7
9
1
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
1
EC11 EC10 EC9 SYN-CON7-15-GP

SC1KP25V3MX-GP
C560 C561 20.80352.007

B SCD1U50V3ZY-GP DUMMY-C3 B
2
DY DY DY
2
A <Variant Name> A
Wistron Corporation
Title
AD/BATT CONN
A3
AG1 -1
5 4 3 2 1
5 4 3 2 1
U70A
STRAPS PIN DESCRIPTION OF RECOMMENDED SETTING RECOMMENDED
PART 1 OF 7
PEG_TXP0 AJ31 AK27 C72 1 SCD1U16V2KX-3GP
2 PEG_RXP0
PEG_TXN0 PCIE_RX0P PCIE_TX0P C73 SCD1U16V2KX-3GPPEG_RXN0 STRAP_B_PTX_PWRS_ENB TRANSMITTER POWER SAVINGS ENABLE INSTALL
AH31 PCIE_RX0N PCIE_TX0N AJ27 1 2 GPIO0
- FULL TX OUTPUT SWING 10K RESISTOR
PCIE TEST PADS
PEG_TXP1 AH30 PCIE_RX1P P PCIE_TX1P AJ25 C75 1 SCD1U16V2KX-3GP
2 PEG_RXP1 TRANSMITTER DE-EMPHASIS ENABLE
PCIE TEST POINTS MUST BE WITHIN 250 MILS PEG_TXN1 AG30 AH25 C74 1 SCD1U16V2KX-3GP
2 PEG_RXN1 STRAP_B_PTX_DEEMPH_EN GPIO1 DEPENDS ON PCIE CHIPSET BEING USED TBD
PCIE_RX1N C PCIE_TX1N FOR M26X,M5X
OF THE ASIC BALL WITH POSITIVE AND NEGATIVE
I INSTALL WITH ATI RS480,RS400,RX480,
SIGNALS THE SAME DISTANCE PEG_TXP2 AG32 AH28 C117 1 SCD1U16V2KX-3GP
2 PEG_RXP2 RC410,RS482 CHIPSETS
PEG_TXN2 AF32
PCIE_RX2P - PCIE_TX2P
AG28 C118 1 SCD1U16V2KX-3GP
2 PEG_RXN2 FOR M26X ONLY
PCIE_RX2N PCIE_TX2N
D E DO NOT INSTALL WITH INTEL 915PM CHIPSET D
PEG_TXP3 AF31
X AG27 C114 1 SCD1U16V2KX-3GP
2 PEG_RXP3
PEG_TXN3 PCIE_RX3P P PCIE_TX3P C113 1 SCD1U16V2KX-3GPPEG_RXN3
AE31 PCIE_RX3N PCIE_TX3N AF27 2 DO NOT INSTALL
RSVD GPIO(3:2) NO ATI FEATURE ENABLED
R 10K RESISTORS
PEG_TXP4 AE30 PCIE_RX4P
E PCIE_TX4P AF25 C122 1 SCD1U16V2KX-3GP
2 PEG_RXP4 REVERSE LANES NOT REVERSED LANE (M26X)
PEG_TXN4 AD30 AE25 C121 1 SCD1U16V2KX-3GP
2 PEG_RXN4 GPIO4
PCIE_RX4N S PCIE_TX4N DO NOT INSTALL
DEBUG ACCESS NO DEBUG ACCESS (M52P,M54P,M56P) 10K RESISTOR
S
PEG_TXP5 AD32 AE28 C115 1 SCD1U16V2KX-3GP
2 PEG_RXP5 STRAP_FORCE_COMPLIANCE DO NOT FORCE COMPLIANCE STATE QUICKLY (M26X)
PEG_TXN5 PCIE_RX5P PCIE_TX5P C116 1 SCD1U16V2KX-3GPPEG_RXN5 GPIO5 INSTALL
AC32 PCIE_RX5N PCIE_TX5N AD28 2 sets the desired PCIE PLL
I bandwidth for M5x parts. NO ATI FEATURE ENABLED (M52P,M54P,M56P) 10K RESISTORS
PEG_TXP6
N C159 1 SCD1U16V2KX-3GPPEG_RXP6 NORMAL RANGE (M26X)
AC31 AD27 2 COMMON MODE RANGE
PEG_TXN6 AB31
PCIE_RX6P T PCIE_TX6P
AC27 C161 1 SCD1U16V2KX-3GP
2 PEG_RXN6 GPIO6 DO NOT INSTALL
PCIE_RX6N PCIE_TX6N NO ATI FEATURE ENABLED (M52P,M54P,M56P) 10K RESISTORS
E RSVD
TPAD28 TP72 1 PEG_TXP7 AB30 R AC25 C164 1 SCD1U16V2KX-3GP
2 PEG_RXP7 DEBUG ACCESS NO DEBUG ACCESS (M26X)
TPAD28 TP73 PEG_TXN7 PCIE_RX7P PCIE_TX7P C165 1 SCD1U16V2KX-3GPPEG_RXN7 GPIO8 DO NOT INSTALL
1 AA30 PCIE_RX7N F PCIE_TX7N AB25 2
FORCE_COMPLIANCE DON'T FORCE COMPLIANCE STATE(M52P,M54P,M56P) 10K RESISTORS
A
PEG_TXP8 AA32 PCIE_RX8P C PCIE_TX8P AB28 C170 1 SCD1U16V2KX-3GP
2 PEG_RXP8
PEG_TXN8 Y32 AA28 C171 1 SCD1U16V2KX-3GP
2 PEG_RXN8 ROMIDCFG(3:0) GPIO[9,13:11] SERIAL FLASH ROM TYPE (M26X,M52P,M54P,M56P) 1011
PEG_RXP[15..0] PCIE_RX8N E PCIE_TX8N - SERIAL M25P10 ROM
7 PEG_RXP[15..0]
PEG_RXN[15..0] PEG_TXP9 Y31 AA27 C163 1 SCD1U16V2KX-3GP
2 PEG_RXP9 IF NO ROM
7 PEG_RXN[15..0] PCIE_RX9P PCIE_TX9P
PEG_TXN9 W31 Y27 C162 1 SCD1U16V2KX-3GP
2 PEG_RXN9 MEMORY APERTURE SIZE GPIO[13:11] GPIO11(M26X) AND GPIO12,13(M52,M54,M56)
PEG_TXP[15..0] PCIE_RX9N PCIE_TX9N SET MEMORY APERTURE SIZE TBD
C 7 PEG_TXP[15..0] SEE M26X,M54X,M56X DATA BOOK FOR C
PEG_TXN[15..0] PEG_TXP10 W30 Y25 C158 1 SCD1U16V2KX-3GP
2 PEG_RXP10 MEMORY,FRAME BUFFER APERATURE SETTINGS
7 PEG_TXN[15..0] PEG_TXN10 PCIE_RX10P PCIE_TX10P C157 1 SCD1U16V2KX-3GPPEG_RXN10
V30 PCIE_RX10N PCIE_TX10N W25 2
MEM_TYPE MEMID MEMORY TYPE AND SPEED SELECT TBD
PCIE SIGNALS CONNECT TO ROOT COMPLEX PEG_TXP11 V32 W28 C167 1 SCD1U16V2KX-3GP
2 PEG_RXP11 (3:0)
PEG_TXN11 PCIE_RX11P PCIE_TX11P C168 1 SCD1U16V2KX-3GPPEG_RXN11
U32 PCIE_RX11N PCIE_TX11N V28 2
RSVD H2SYNC ATI FEATURE NOT ENABLED (M52P,M54P,M56P) DO NOT INSTALL

REFER TO PCI EXPRESS DESIGN GUIDE PEG_TXP12 U31 V27 C169 1 SCD1U16V2KX-3GP
2 PEG_RXP12 V2SYNC 10K RESISTORS
PEG_TXN12 PCIE_RX12P PCIE_TX12P C166 1 SCD1U16V2KX-3GPPEG_RXN12 NO STRAP FUNCTION GENERICC NO STRAP (M26X)
FOR RECOMMENDED AC COUPLING CAPS T31 PCIE_RX12N PCIE_TX12N U27 2
PLACEMENT ALONG THE TX INTERCONNECT
PEG_TXP13 T30 U25 C160 1 SCD1U16V2KX-3GP
2 PEG_RXP13
PEG_TXN13 PCIE_RX13P PCIE_TX13P C222 1 SCD1U16V2KX-3GPPEG_RXN13 RSVD PCIE_TEST ATI FEATURE NOT ENABLED (M52P,M54P,M56P)
R30 PCIE_RX13N PCIE_TX13N T25 2
NO STRAP FUNCTION NO STRAP (M26X)

PEG_TXP14 R32 T28 C221 1 SCD1U16V2KX-3GP
2 PEG_RXP14
P32 PCIE_RX14N PCIE_TX14N R28 2
PEG_TXP15 P31 R27 C220 1 SCD1U16V2KX-3GP

2 PEG_RXP15 3D3V_S0
N31 PCIE_RX15N PCIE_TX15N P27 2
R64 1 2 10KR2J-3-GP
Clock Calibration 46 GPIO0 R52 1 10KR2J-3-GP
46 GPIO1 2
CLK_PCIE_PEG AL28 DY R53 1 2 10KR2J-3-GP
3 CLK_PCIE_PEG CLK_PCIE_PEG# PCIE_REFCLKP 46 GPIO2 R58 1 10KR2J-3-GP
3 CLK_PCIE_PEG# AK28 PCIE_REFCLKN PCIE_CALRN R538 1 46 GPIO3 DY 2
PCIE_CALRN AE24 2 2KR2F-3-GP 1D2V_S0 46 GPIO4 DY R49 1 2 10KR2J-3-GP
B PCIE_CALRP B
PCIE_CALRP AD24 1 R133 2 46 GPIO5
R51 1 2 10KR2J-3-GP
562R3F-GP DY R56 1 2 10KR2J-3-GP
R111 1 100R2J-2-GP VGA_RST# PCIE_CALI R135 1 46 GPIO6
7,16,20,26,30,31,32,34,35 PLT_RST1# 2 AG24 PERSTB PCIE_CALI AB24 2 1K47R3F-GP 46 GPIO8 DY R66 1 2 10KR2J-3-GP
1
SC100P50V2JN-3GP
2
C420 PCIE_TEST
FOR M26X 46 GPIO11 DY R50 1 2 10KR2J-3-GP
AA24 PCIE_TEST PCIE_CALRN = 100R 46 GPIO12 256M R54 1 2 10KR2J-3-GP
PCIE CALRP = 150R 23 22 21 20 46 GPIO13 DY R65R61

1 2 10KR2J-3-GP
10KR2J-3-GP
R112 46 GPIO9 DY 1 2
PCIE CALI = 10K GPIO[9,13:11]=0000 for 128M
2PERSTB_MASK Tie To VSS MEM_ID0 MEM_ID2
1 AF24 PERSTB_MASK FOR M52P,M54P,M56P 46 MEM_ID3 DY R59 1 2 10KR2J-3-GP
MEM_ID1 MEM_ID3 MEM SIZE VENDOR CHIPs DY R55 1 2 10KR2J-3-GP
PCIE_CALRN = 2K 46 MEM_ID2
10KR2F-2-GP 46 MEM_ID1 128In256 R63 1 2 10KR2J-3-GP
M52P-GP PCIE CALRP = 562R 1 0 1 0 64M 16M*16 Infineon x2 46 MEM_ID0
R60
128Hy256R106 1 2 10KR2J-3-GP
71.0M52P.00U 1 1 1 0 64M 16M*16 Hynix x2 10KR2J-3-GP
PCIE CALI = 1.47K 0 0 Samsung 46 DAC2_HSY DY R104 1 2
1 1 128M 16M*16 x4 46 DAC2_VSY DY R537 1 2 10KR2J-3-GP
0 0 0 256M 32M*16 Samsung x4 10KR2J-3-GP
M54P:71.0M54P.A0U 0 1
1
0 0 128M 16M*16 Infineon x4 46 GENERICC DY R151 1
PCIE_TEST
2
10KR2J-3-GP
DY 1 2
M56P:71.0M56P.B0U 1
1
1
0
0
0
0
0
256M
128M
32M*16
16M*16
Infineon
Hynix
x4
x4
0 0 0 0 256M 32M*16 Hynix x4 When no ROM is attached, GPIO[9] is set to 0.
GPIO[13:12] is used to select the frame buffer aperture size.
GPIO[13:12] = 00: 128M frame buffer, same as ROM strap 00
GPIO[13:12] = 01: 256M frame buffer, same as ROM strap 01
VGA THERMAL SENSOR GPIO[13:12]
GPIO[13:12]
= 10: 64M frame buffer, same as ROM strap 10
= 11: reserved, same as ROM strap 11
A <Variant Name> A
Place near GPU Wistron Corporation

IT IS REQUIRED TO DESIGN IN A THERMAL SENSOR Title

TO FACILITATE THERMAL EVALUATION AND TO PROTECT THE ASIC ATI M5X-P PCIE 1/4
A3
AG1 SD
5 4 3 2 1
5 4 3 2 1
3D3V_S0 U70B PART 2 OF 7

3D3V_S0 AL9
Integrated TXCM
TXCP AM9
2
TMDS
1
R520 AK10
TX0M
1
0R2J-2-GP R518 AG8 AL10

R522 0R3-0-U-GP GPIO_34 TX0P
DUMMY-R2
DY U67
AH7 GPIO_33
1 AG9 GPIO_32 TX1M AL11
AH8 GPIO_31 V TX1P AM11
2
8 1 VGA_GPIO16 AJ8
VGA_XTALIN_1 7 SEL1 CKOUT
2 3D3V_SS_S0 AH9
GPIO_30 I AL12
REFOUT VDD GPIO_29 TX2M
2
6 SEL0 VSS 3 AG10 GPIO_28 D TX2P AM12
1
MB88154_XO5 4 MB88154_XI C576 AF10
XOUT XIN GPIO_27 E
1
DUAL LINK IS
SCD1U10V2KX-4GP
D AH6 GPIO_26 TX3M AK9 D
Expand GPIO
2
R114 AF8 GPIO_25 O TX3P AJ9 ONLY SUPPORTED ON M56P
2
R493 R521 MB88154PNF-JN-GP AF7
0R2J-2-GP 180R2F-1-GP 71.88154.A0A GPIO_24 DO NOT CONNECT TXM,P[3:5]
AE9 GPIO_23 TX4M AK11
& WITH M52P,M54P,M26X
0R2J-2-GP
AE10 GPIO_22 TX4P AJ11

2
VGA_XTALIN AG7 GPIO_21

1
AF9 GPIO_20 TX5M AK12

1
AF13 GPIO_19
M TX5P AJ12
AE13 R524
R113 GPIO_18 U AM8 VGA_TPVDD 1 2
TPVDD 2D5V_S0
DVPCNTL,DVPDATA[23..0] FOR M26X L C582 0R0603-PAD FOR M26X TPVDD
1
147R2F-GP AL8 SC1U6D3V2KX-GP
ARE CONFIGURED FOR CONNECT TO +1.8V OR VSS T TPVSS CONNECT TO +1.8V
2
+3.3V SIGNALING MODE TO DEFINE DVO SIGNAL LEVEL I AJ6 FOR M52P,M54P,M56P
TXVDDR_1
2
ON THIS DESIGN FOR M52P,M54P,M56P AK4 NC_DVOVMODE_0 M TXVDDR_2 AK6 CONNECT TO +2.5V
MB88154_XI AL4 AL6
NOT CONNECTED NC_DVOVMODE_1 E TXVDDR_3
1
AM6 VGA_TXVDDR FOR M26X TXVDDR

TXVDDR_4
1
C579 R519 X7 AF2 D C603 C604 C581

R93 DVPCNTL_0 CONNECT TO +1.8V
1
SC1U6D3V2KX-GP SCD1U10V2KX-4GP R523
SCD1U10V2KX-4GP
XTAL-27MHZ-31-GP AF1 DVPCNTL_1
1MR2J-1-GP I FOR M52P,M54P,M56P
SC27P50V2JN-2-GP
1 2 AF3 DVPCNTL_2 TXVSSR_1 AJ7 1 2 2D5V_S0

2
MB88154_XO AG1 DVPCLK A TXVSSR_2 AK7 0R0603-PAD CONNECT TO +2.5V

12
2
C580 82.30034.211 1KR2J-1-GP
SC27P50V2JN-2-GP
AG2 DVPDATA_0 TXVSSR_3 AL7

AG3 DVPDATA_1 TXVSSR_4 AM7
Modulation Rate AH2 DVPDATA_2 TXVSSR_5 AK8
2
ANY UNUSED GPIO CAN OPTIONALLY BE AH3 DVPDATA_3

Center PANEL TYPE CONFIG STRAPS AJ2 DVPDATA_4
SEL1 SEL0 Spread AJ1 DVPDATA_5 R AK24 ATI_RED 14
AK2 DAC / CRT AM24 ATI_GREEN 14
DVPDATA_6 G
L L +-0.5% 3D3V_S0
AK1 DVPDATA_7 B AL24 ATI_BLUE 14
VIP Host/External TMDS

C AK3 C
DVPDATA_8
1
R1101
R1091
L H +-1.0%
R107
AL2 DVPDATA_9 HSYNC AJ23 ATI_HSY 14
AL3 DVPDATA_10 VSYNC AJ22 ATI_VSY 14
H L +-1.5% AM3 DVPDATA_11 GENERICA AK22
4
3
150R2F-1-GP
150R2F-1-GP
150R2F-1-GP
AE6 DVPDATA_12
H H No Spread RN14 AF4 AF23 VGA_GENERICB R134 1 2 1KR2F-3-GP
DVPDATA_13 GENERICB
2
2
2
SRN4K7J-8-GP AF5 DVPDATA_14
AG4 AL22 VGA_CRT_RSET R105 1 2 510R2F-L-GP
DVPDATA_15 RSET R539
AJ3 DVPDATA_16
AH4 AL25 VGA_AVDD C107 1 2
1 DVPDATA_17 AVDD_1 2D5V_S0
2
1
EDID_DAT AJ4 AM25 HCB1608KF121T30-GP FOR M26X AVDD
13 EDID_DAT DVPDATA_18 AVDD_2
EDID_CLK AG5
13 EDID_CLK DVPDATA_19 SC1U6D3V2KX-GP
CONNECT TO +1.8V
45 MEM_ID3 AH5 DVPDATA_20 AVSSQ AK23
FOR M52P,M54P,M56P
2
45 MEM_ID2 AF6 DVPDATA_21 AVSSN_1 AK25
ANY UNUSED GPIO CAN OPTIONALLY BE45 MEM_ID1 AE7 DVPDATA_22 AVSSN_2 AJ24 CONNECT TO +2.5V
AG6 R108
MEMORY TYPE CONFIG STRAPS 45 MEM_ID0 DVPDATA_23 VGA_VDD1DI C104
VDD1DI AM23 1 2 2D5V_S0
1
C103 C106 0R0603-PAD
SCD1U10V2KX-4GP
FOR M26X VDD1DI
SC1U6D3V2KX-GP
AD4
SC1U6D3V2ZY-GP
45 GPIO0 GPIO_0 General
45 GPIO1 AD2 GPIO_1 VSS1DI AL23 CONNECT TO +1.8V
AD1 Purpose
45 GPIO2 GPIO_2 FOR M52P,M54P,M56P
2
I/O
45 GPIO3 AD3 GPIO_3 R2 AK15
3D3V_S0 AC1 DAC2 (TV/CRT2) AM15 CONNECT TO +2.5V
45 GPIO4 GPIO_4 G2
45 GPIO5 AC2 GPIO_5 B2 AL15
45 GPIO6 AC3 GPIO_6
1
1 AB2 AF15 DAC2_HSY DAC2_HSY 45 DAC2 CAN BE TV SIGNALS OR SECONDARY CRT

R91 TPAD28 TP6 GPIO_7_BLON H2SYNC DAC2_VSY
45 GPIO8 AC6 GPIO_8 V2SYNC AG15 DAC2_VSY 45 SIGNALS AS CONTROLLED BY AN INTERNAL MUX
499R2F-2-GP AC5
45 GPIO9 GPIO_9
AC4 GPIO_10 Y AJ15 ATI_TV_LUMA 14
45 GPIO11 AB3 GPIO_11 C AJ13 ATI_TV_CRMA 14
2
B B
45 GPIO12 AB4 GPIO_12 COMP AH15 ATI_TV_COMP 14
AB5
SCD1U10V2KX-4GP45 GPIO13
AD5
GPIO_13
AK14 VGA_TV_RSET R102 1 2 715R2F-GP
GPIO_14 R2SET
1
C137 52 GPIO_PWRCNTL 1 R484 2 POW_SW AB8 R103

GPIO_15
1
R1011
R981
R127 10KR2J-3-GP VGA_GPIO16 AA8 VGA_A2VDD C101 C102 1 2 0R3-0-U-GP
R100
GPIO_16 A2VDD_1 AM16 2D5V_S0
1
499R2F-2-GP 1VGA_ALERT# SC1U6D3V2KX-GP
SCD1U10V2KX-4GP
2 AB7 GPIO_17 A2VDD_2 AL16
2
3D3V_S0 2K2R2J-2-GP R48 AB6 TV TV

NC_AB6
PLACE VREF DIVIDER AND CAP CLOSE TO ASIC FOR M26X A2VDDQ
150R2F-1-GP
150R2F-1-GP
150R2F-1-GP
A2VSSN_1 AM17
2
2
VGA_VREF AC8 AL17
VREFG A2VSSN_2 CONNECT TO +1.8V
2
2
2
19 G792_DXP3 FOR M52P,M54P,M56P
1
FOR M26X PVDD AG12 AL14 VGA_A2VDDQ 1 TPAD28 TP70

DPLUS NC_A2VDDQ
CONNECT TO +1.8V C65 Thermal IT IS NO CONNECT
SC2200P50V2KX-2GP
AH12 Diode AK13
FOR M52P,M54P,M56P 19 G792_DXN3 DMINUS A2VSSQ
2
VGA_PVDD R62 TV
1
CONNECT TO +2.5V AJ14 PVDD VDD2DI AJ16 VGA_VDD2DI C100 1 2 0R3-0-U-GP 2D5V_S0
1
R57 C66 C98 PLL & C94 C99
SCD1U10V2KX-4GP
FOR M26X VDD2DI
SC1U6D3V2KX-GP
SC1U6D3V2ZY-GP
1 2 SC10U10V5ZY-1GP SC1U6D3V2KX-GP AH14 XTAL AJ17
2D5V_S0 PVSS VSS2DI CONNECT TO +1.8V
2
0R0603-PAD
FOR M52P,M54P,M56P
2
R591 VGA_MPVDD A6 MPVDD
VGA_CORE_S0 1 2 C656 C657 A5 MPVSS CONNECT TO +2.5V
1
0R0603-PAD SC1U6D3V2KX-GP Monitor AF11 1 R743 2

SCD1U10V2KX-4GP VGA_XTALIN Interface HPD1 100KR2J-1-GP
FOR M26X MPVDD AL26 XTALIN
TPAD28 TP71 1AM26
CONNECT TO +1.8V XTALOUT
2
DDC1DATA AH22 ATI_DDCDAT 14

FOR M52P,M54P,M56P AG14 AH23 For CRT
R132 PLLTEST DDC1CLK ATI_DDCCLK 14
CONNECT TO VDDC
1 2 VGA_TESTEN AG22 AH13
1KR2J-1-GP TESTEN Test DDC2DATA
DDC2CLK AG13 For DVI
A <Variant Name> A
VOLTAGE DIVIDER 3.3V MEM SS 3D3V_S0 1 R94 2 AC7 ROMCSb DDC3DATA AE12
10KR2J-3-GP ROM AF12 For THERMAL SENSOR
MODOUT TO 1.2V XTALIN/OUT DDC3CLK
DY Wistron Corporation
adjust SWING at 1.2v External GENERICC AE23 GENERICC 45 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
AK17 SSC Taipei Hsien 221, Taiwan, R.O.C.
LVSSR_1
AJ19 LVSSR_2 LVDS PLL LPVSS AE18
AF18 FOR M26X GENERICC Title
LVSSR_3 and I/O
AH17
AG17
LVSSR_4 GND
AF22
NO CONNECT OR ATI M5X-P IO 2/4
LVSSR_5 LVDS PLL LVSSR_10 EXT SPREAD SPECTRUM INPUT Size Document Number Rev
AG19 LVSSR_6 and I/O LVSSR_9 AF17
FOR M52P,M54P,M56P A3
AH19
M52P-GP LVSSR_7 GND LVSSR_8 AF21
IT IS GPIO
AG1 -1M
5 4 3 2 1
5 4 3 2 1
U70C Ch-A U70D Ch-B

Part 3 of 7
FOR M52P,M54P,M26X Part 4 of 7
FOR M52P,M54P,M26X
PIN B25 IS MA12 (BA0) PIN H2 IS MAB12 (BA0)
M31 DQA_0 MAA_0 D26 PIN C25 IS MA13 (BA1) MDB0 B12 DQB_0 MAB_0 G4 MAB0 PIN H3 IS MAB13 (BA1)
M30 F28 MDB1 C12 E6 MAB1
DQA_1 MAA_1 PIN E29 IS MA15 (BA2) MDB2 DQB_1 MAB_1 MAB2
PIN D5 IS MAB15 (BA2)
D L31 D28 B11 E4 D
L30
DQA_2 MAA_2
D25 PIN E27 IS MA14 MDB3 C11
DQB_2 MAB_2
H4 MAB3 PIN F5 IS MAB14
DQA_3 MAA_3 DQB_3 MAB_3
H30 DQA_4 MAA_4 E24 FOR M56P MDB4 C8 DQB_4 MAB_4 J5 MAB4 FOR M56P
G31 E26 PIN B25 IS MA14 (BA0) MDB5 B7 G5 MAB5 PIN H2 IS MA14 (BA0)
DQA_5 MAA_5 DQB_5 MAB_5
MEMORY INTERFACE A
G30 D27 MDB6 C7 F4 MAB6
DQA_6 MAA_6 PIN C25 IS MA15 (BA1) MDB7 DQB_6 MAB_6 MAB7 PIN H3 IS MA15 (BA1)
MEMORY INTERFACE B
F31 DQA_7 MAA_7 F25 B6 DQB_7 MAB_7 H6
M27 C26 PIN E29 IS MA13 (BA2) MDB8 F12 G3 MAB8 PIN D5 IS MA13 (BA2)
DQA_8 MAA_8 MDB9 DQB_8 MAB_8 MAB9
M29 DQA_9 MAA_9 B26 PIN E27 IS MA12 D12 DQB_9 MAB_9 G2 PIN F5 IS MAB12
L28 D29 MDB10 E11 D4 MAB10
DQA_10 MAA_10 MDB11 DQB_10 MAB_10 MAB11
L27 DQA_11 MAA_11 B27 F11 DQB_11 MAB_11 F2
J27 E27 MDB12 F9 F5 MAB12_14 50,51
DQA_12 MAA_12 MDB13 DQB_12 MAB_12 TP10 TPAD28
H29 DQA_13 MAA_13 E29 D8 DQB_13 MAB_13 D5 1
G29 B25 MDB14 D7 H2 B_BA0 50,51
DQA_14 MAA_14 MDB15 DQB_14 MAB_14
G27 DQA_15 MAA_15 C25 F7 DQB_15 MAB_15 H3 B_BA1 50,51
M26 MDB16 G12
DQA_16 MDB17 DQB_16
L26 DQA_17 G11 DQB_17
M25 H31 MDB18 H12 B8 DQMB#0
DQA_18 DQMAb_0 MDB19 DQB_18 DQMBb_0 DQMB#1 RASB0#
L25 DQA_19 DQMAb_1 J29 H11 DQB_19 DQMBb_1 D9 50 RASB0#
J25 J26 MDB20 H9 G9 DQMB#2 RASB1#
DQA_20 DQMAb_2 MDB21 DQB_20 DQMBb_2 DQMB#3 50,51 RASB1#
G28 DQA_21 DQMAb_3 G23 E7 DQB_21 DQMBb_3 K7
H27 E21 MDB22 F8 M5 DQMB#4 CASB0#
DQA_22 DQMAb_4 MDB23 DQB_22 DQMBb_4 DQMB#5 50 CASB0# CASB1#
H26 DQA_23 DQMAb_5 B15 G8 DQB_23 DQMBb_5 V2 50,51 CASB1#
F26 D14 MDB24 G6 W4 DQMB#6
DQA_24 DQMAb_6 MDB25 DQB_24 DQMBb_6 DQMB#7 WEB0#
G26 DQA_25 DQMAb_7 J17 G7 DQB_25 DQMBb_7 T9 50 WEB0#
H25 MDB26 H8 WEB1#
DQA_26 MDB27 DQB_26 50,51 WEB1#
H24 DQA_27 J8 DQB_27
H23 MDB28 K8 CSB0_0#
DQA_28 MDB29 DQB_28 RDQSB0 50 CSB0_0#
H22 DQA_29 QSA_0 J31 L8 DQB_29 QSB_0 B9
J23 K29 MDB30 K9 D10 RDQSB1 CSB1_0#
C DQA_30 QSA_1 MDB31 DQB_30 QSB_1 RDQSB2 50,51 CSB1_0# C
J22 DQA_31 QSA_2 K25 L9 DQB_31 QSB_2 H10
E23 F23 MDB32 K5 K6 RDQSB3
DQA_32 QSA_3 MDB33 DQB_32 QSB_3 RDQSB4 CKEB0
D22 D20 L4 N4
read strobe
DQA_33 QSA_4 MDB34 DQB_33 QSB_4 RDQSB5 50 CKEB0 CKEB1

D23 B16 K4 U2
read strobe
DQA_34 QSA_5 MDB35 DQB_34 QSB_5 RDQSB6 50,51 CKEB1
E22 DQA_35 QSA_6 D16 L5 DQB_35 QSB_6 U4
E20 H15 MDB36 N5 V8 RDQSB7
DQA_36 QSA_7 MDB37 DQB_36 QSB_7
F20 DQA_37 N6 DQB_37
D19 MDB38 P4
DQA_38 MDB39 DQB_38 WDQSB0 CLKB0
D18 DQA_39 QSA_0B K31 R4 DQB_39 QSB_0B B10 50 CLKB0
MDB40 WDQSB1 CLKB0#
B19
B18
DQA_40 QSA_1B K28
K26 MDB41
P2
R2
DQB_40 QSB_1B E10
G10 WDQSB2
For GDDR2 50 CLKB0#
DQA_41 QSA_2B DQB_41 QSB_2B
write strobe
write strobe
C17 G24 MDB42 T3 J7 WDQSB3 CLKB1
DQA_42 QSA_3B MDB43 DQB_42 QSB_3B WDQSB4 51 CLKB1 CLKB1#
B17 DQA_43 QSA_4B D21 T2 DQB_43 QSB_4B M4 51 CLKB1#
C14 C16 MDB44 W3 U3 WDQSB5
DQA_44 QSA_5B MDB45 DQB_44 QSB_5B WDQSB6
B14 DQA_45 QSA_6B D15 W2 DQB_45 QSB_6B V4
C13 J15 MDB46 Y3 V9 WDQSB7
DQA_46 QSA_7B MDB47 DQB_46 QSB_7B RDQSB[7..0]
B13 DQA_47 Y2 DQB_47 50,51 RDQSB[7..0]
D17 F29 MDB48 T4 D6 ODTB0 ODTB0 50
DQA_48 ODTA MDB49 DQB_48 ODTB ODTB1 DQMB#[7..0]
E18 DQA_49 ODTA1 D24 R5 DQB_49 ODTB1 J4 ODTB1 50,51 50,51 DQMB#[7..0]
E17 MDB50 T5
DQA_50 MDB51 DQB_50 MDB[63..0]
F17 DQA_51 T6 DQB_51 50,51 MDB[63..0]
E15 D31 MDB52 V5 B4 CLKB0
DQA_52 CLKA0 MDB53 DQB_52 CLKB0 CLKB0# MAB[11..0]
E14 DQA_53 CLKA0b E31 W5 DQB_53 CLKB0b B5 50,51 MAB[11..0]
F14 MDB54 W6
DQA_54 MDB55 DQB_54 CKEB0 WDQSB[7..0]
D13 DQA_55 CKEA0 B30 Y4 DQB_55 CKEB0 C2 50,51 WDQSB[7..0]
H18 MDB56 R8
DQA_56 MDB57 DQB_56 RASB0#
H17 DQA_57 RASA0b B28 T8 DQB_57 RASB0b E2
G18 MDB58 R7
DQA_58 1D8V_S0 MDB59 DQB_58 CASB0#
G17 DQA_59 CASA0b C29 T7 DQB_59 CASB0b D3
B MDB60 B
G15 DQA_60 V7 DQB_60
G14 B31 MDB61 W7 B2 WEB0#
DQA_61 WEA0b MDB62 DQB_61 WEB0b
H14 DQA_62 W8 DQB_62
1
J14 B29 MDB63 W9 D2 CSB0_0#

DQA_63 CSA0b_0 R581 DQB_63 CSB0b_0 CSB0_1# TP9 TPAD28
CSA0b_1 C28 CSB0b_1 E3 1
C31 100R2F-L1-GP-U
MVREFD_0 CLKB1
C30 MVREFS_0 CLKA1 B20 CLKB1 N2
2
C19 MVREFD1 B3 P3 CLKB1#

CLKA1b C666 MVREFS1 MVREFD_1 CLKB1b
C3 MVREFS_1
1
CKEB1
SCD1U10V2KX-4GP
CKEA1 C22 CKEB1 L3

R590
B24 AA3 J2 RASB1#
RASA1b DRAM_RST RASB1b
2
100R2F-L1-GP-U
B22 AA5 L2 CASB1#
CASA1b TEST_MCLK CASB1b
2
B21 AA2 M2 WEB1#

WEA1b 1D8V_S0 TEST_YCLK WEB1b
B23 AA7 K2 CSB1_0#
CSA1b_0 MEMTEST CSB1b_0 CSB1_1# TP8 TPAD28
CSA1b_1 C23 CSB1b_1 K3 1
1
4
3
M52P-GP R580 RN15 M52P-GP

SRN4K7J-8-GP R714
100R2F-L1-GP-U 243R3F-GP
2
1
2
C665 SC Modify
1
1
SCD1U10V2KX-4GP
A PLACE MVREF DIVIDERS R589

<Variant Name> A
AND CAPS CLOSE TO ASIC

2
100R2F-L1-GP-U
PLACE MVREF DIVIDERS Wistron Corporation
2

AND CAPS CLOSE TO ASIC Taipei Hsien 221, Taiwan, R.O.C.
Title
ATI M5X-P MEM 3/4
A3
AG1 SC
5 4 3 2 1
5 4 3 2 1
U70E
U70F VGA_PCIE_PVDD12 1 R153 2 1D2V_S0
1D8V_S0 -1 Modify PART 5 OF 7
Part 6 of 7 C209 C156 0R0805-PAD
SC4D7U6D3V3KX-GP
1
1
SCD1U10V2KX-4GP
C224 FOR M26X PCIE_VDDR12
SC1KP16V2KX-GP
C1 VDDR1_1 PCIE_PVDD_12_1 V23 CONNECT TO +1.8V
AH27 AD16 J1 N23
PCIE_VSS_1 VSS_38 VDDR1_2 PCIE_PVDD_12_2 FOR M52P,M54P,M56P
2
1
1
AC23 AA6 C253 C203 C180 C194 M1 P23
1SC10U6D3V5MX-3GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
PCIE_VSS_2 VSS_39 VDDR1_3 PCIE_PVDD_12_3 CONNECT TO +1.2V
AL27 PCIE_VSS_3 VSS_40 P7 R1 VDDR1_4 PCIE_PVDD_12_4 U23
R23 PCIE_VSS_4 VSS_41 P5 V1 VDDR1_5
2
P25 M3 AA1 N29 VGA_PCIE_VDDR12_1 1 R150 2
SC4D7U6D3V3KX-GP SC4D7U6D3V3KX-GP
PCIE_VSS_5 VSS_42 VDDR1_6 PCIE_VDDR_12_10 C217 0R0805-PAD
R25 M9 A3 N28
1 SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
PCIE_VSS_6 VSS_43 VDDR1_7 PCIE_VDDR_12_11
1
C218 C216 C213
SC1KP16V2KX-GP
T26 PCIE_VSS_7 VSS_44 L7 P9 VDDR1_8 PCIE_VDDR_12_12 N27
U26 PCIE_VSS_8 VSS_45 M7 J10 VDDR1_9 PCIE_VDDR_12_13 N26
W26 AD17 N9 N25
SCD01U25V2KX-3GP
SCD01U25V2KX-3GP
SCD01U25V2KX-3GP
2
D
Y26 PCIE_VSS_10 VSS_47 AH11 P10 VDDR1_11 D
1
AB26 A8 C211 C250 C196 C658 C246 C252 A9 AL31
AC26 U7 Y10 AM31
PCI-Express
PCIE_VSS_12 VSS_49 VDDR1_13 PCIE_VDDR_12_2 VGA_PCIE_VDDR12_2
AD25 PCIE_VSS_13 VSS_50 C10 P8 VDDR1_14 PCIE_VDDR_12_3 AM30 1 R116 2
2
AE26 E9 R9 AL32 0R0805-PAD
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
1
AF26 F3 Y9 AL30 C112 C111
C109 C108C110
AD26 PCIE_VSS_16 VSS_53 J9 J11 VDDR1_17 PCIE_VDDR_12_6 AM28
AG25 PCIE_VSS_17 VSS_54 N7 A21 VDDR1_18 PCIE_VDDR_12_7 AL29
2
AH26 PCIE_VSS_18 VSS_55 N3 M10 VDDR1_20 PCIE_VDDR_12_8 AM29
Memory I/O
AC28 PCIE_VSS_19 VSS_56 Y5 N10 VDDR1_21 PCIE_VDDR_12_9 AM27
1
Y28 AM13 C214 C199 C215 Y8
PCIE_VSS_20 VSS_57 TC19 VDDR1_22
U28 PCIE_VSS_21 VSS_58 AC10 J18 VDDR1_23
P28 Y6 ST100U6D3VDM-5 J19 AC11
PCIE_VSS_22 VSS_59 VDDR1_24 VDDC_1 VGA_CORE_S0
2
AH29 PCIE_VSS_23 VSS_60 U6 K21 VDDR1_25 VDDC_2 AC12
AF28 E5 A12 P14 C198 C207 C204 C144 C152 C153
PCIE_VSS_24 VSS_61 VDDR1_26 VDDC_3
1
SCD1U10V2KX-4GPSCD1U10V2KX-4GP
V29 PCIE_VSS_25 VSS_62 AL13 H13 VDDR1_27 VDDC_4 U15
AC29 PCIE_VSS_26 VSS_63 A11 A15 VDDR1_28 VDDC_5 W14
W27 PCIE_VSS_27 VSS_64 U8 J20 VDDR1_29 VDDC_6 W15
2
AB27 PCIE_VSS_28 VSS_65 U9 J13 VDDR1_30 VDDC_7 R17
PCI-Express GND
V26 PCIE_VSS_29 VSS_66 U10 K11 VDDR1_31 VDDC_8 R15

AJ26 PCIE_VSS_30 VSS_67 R6 K19 VDDR1_32 VDDC_9 V15
AJ32 PCIE_VSS_31 VSS_68 AD6 A18 VDDR1_33 VDDC_10 V16
AK29 V6 L23 T16 C140 C145 C143 C205 C200 C201 C208
1
SCD1U10V2KX-4GP
P26 PCIE_VSS_33 VSS_70 AD14 K20 VDDR1_35 VDDC_12 U16
P29 PCIE_VSS_34 VSS_71 AD13 K24 VDDR1_36 P VDDC_13 T17
FOR M26X VDD25
Core
R29 PCIE_VSS_35 VSS_72 D11 L24 VDDR1_37 VDDC_14 U17
2
T29 PCIE_VSS_36 VSS_73 J12 H19 VDDR1_38 O VDDC_15 V14 CONNECT TO +1.5V
U29 K12 A24 R18
W29
PCIE_VSS_37 VSS_74
A13 K13
VDDR1_39
W VDDC_16
T18 FOR M52P,M54P,M56P
PCIE_VSS_38 VSS_75 VDDR1_40 VDDC_17 CONNECT TO +2.5V
Y29 F13 J32 V18
AA29
PCIE_VSS_39
PCIE_VSS_40
VSS_76
VSS_77 E13 A30
VDDR1_41
VDDR1_42
E VDDC_18
VDDC_19 P18
AB29 F15 C32 P19 VGA_VDD25 C146 C148 1 R130 2
R 2D5V_S0
SC1U6D3V2ZY-GP
1
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
AD29 K16 F32 R19 C150 0R0603-PAD
AE29 PCIE_VSS_43 VSS_80 J21 L32 VDDR1_46 VDDC_22 W19
AF29 PCIE_VSS_44 VSS_81 H16 VDDC_23 AD11
2
AG29 PCIE_VSS_45 VSS_82 T15
AJ29 PCIE_VSS_46 VSS_83 V17 FOR M26X VDDPLL
AK26 PCIE_VSS_47 VSS_84 C15 VDD25_1 AC13 CONNECT TO VDDC
C AK30 C4 AC16 C
AG26
PCIE_VSS_48 VSS_85
U14
VDD25_2
AC18 FOR M52P,M54P,M56P
PCIE_VSS_49 VSS_86 VDD25_3 CONNECT TO +1.2V
N30 PCIE_VSS_50 VSS_87 P15
R31 A16 AB9 AC15 VGA_VDDPLL C147 1 R136 2
I/O Internal
SC4D7U6D3V3KX-GP
PCIE_VSS_51 VSS_88 VDDR3_1 VDDPLL 1D2V_S0
1
SCD1U10V2KX-4GP
AF30 E16 AB10 C172 0R0603-PAD
PCIE_VSS_52 VSS_89 VGA_VDDR3 C138 VDDR3_2
AC30 PCIE_VSS_53 VSS_90 G13 AA9 VDDR3_3 VDDCI_1 W10
1
SCD1U10V2KX-4GP
V31 G16 C141 C139 AC19 T14
PCIE_VSS_54 VSS_91 VDDR3_4 VDDCI_2
2
P30 PCIE_VSS_55 VSS_92 P17 AD18 VDDR3_5 VDDCI_3 W17
AA31 R16 SC1U6D3V2KX-GP
SC1U6D3V2KX-GP AC20 P16
2
U30 R14 AD19 T23 VGA_VDDCI 1 R147 2 VGA_CORE_S0
1
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
AD31 W16 AD20 K14 C212 C202 C206 C197 0R0805-PAD
AK32 PCIE_VSS_59 VSS_96 C18 VDDCI_7 U19
I/0
AJ28 PCIE_VSS_60 VSS_97 F16 R536
2
Y30 PCIE_VSS_61 VSS_98 W18 FOR M26X LPVDD
AJ30 U18 1 2 VGA_VDDR4 AJ5 VGA_LPVDD C149 1 R152 2 CONNECT TO +1.8V
SC1U6D3V2ZY-GP
PCIE_VSS_62 VSS_99 1 VDDR4_1 2D5V_S0
1
SCD1U10V2KX-4GP
AK31 AE16 0R0603-PAD C95 C96 AM5 0R0603-PAD
AA23
PCIE_VSS_63 VSS_100
AE17 SC1U6D3V2KX-GP AL5
VDDR4_2
AE19 FOR M52P,M54P,M56P
PCIE_VSS_64 VSS_101 VDDR4_3 LPVDD/VDDL0 CONNECT TO +2.5V
AG31 PCIE_VSS_65 VSS_102 A19 AK5 VDDR4_4
2
2
N24 PCIE_VSS_66 VSS_103 H32 R92 LVDDR/VDDL0_1 AF20
AB23 PCIE_VSS_67 VSS_104 F19 AE2 VDDR5_1 LVDDR/VDDL0_2 AE20
P24 G19 1 2 VGA_VDDR5 AE3 AF19 VGA_LVDDRL0 1 R67 2 2D5V_S0 FOR M26X LVDDR PINS
PCIE_VSS_68 VSS_105 VDDR5_2 LVDDR/VDDL0_3
1
1
R24 N8 0R0603-PAD C91 C93 AE4 C97 C151 0R0805-PAD
AE20,AF20,AF19
SC1U6D3V2ZY-GP
PCIE_VSS_69 VSS_106 VDDR5_3
LVDS PLL, I/O
1
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
T24 Y7 AE5 C67
U24
PCIE_VSS_70 VSS_107
T19 SC1U6D3V2KX-GP VDDR5_4
AC21 CONNECT TO +1.8V
PCIE_VSS_71 VSS_108 LVDDR/VDDL1_1
2
V24 PCIE_VSS_72 VSS_109 V19 SC1U6D3V2ZY-GP 2 LVDDR/VDDL1_2 AC22 FOR M52P,M54P,M56P
2
W24 PCIE_VSS_73 VSS_110 G21 A27 VDDRH0 LVDDR/VDDL1_3 AD22 CONNECT TO +2.5V
Clock
I/O
Memory
Y24 PCIE_VSS_74 VSS_111 C21 F1 VDDRH1 LVDDR/VDDL2_1 AE21
AC24 PCIE_VSS_75 VSS_112 F21 VDDR4 AND VDDR5 LVDDR/VDDL2_2 AD21
AH24 AE14 AE22 VGA_LVDDRL1 1 R131 2 FOR M26X LVDDR PINS
PCIE_VSS_76 VSS_113 IN M26X CAN BE 1.8V OR 3.3V LVDDR/VDDL2_3 C154 0R0805-PAD
2D5V_S0
V25 AK16 A28 AC21,AC22,AD21,AD22,AE21,AE22
SC1U6D3V2ZY-GP
PCIE_VSS_77 VSS_114 DEPENDING ON M26X DVOMODE VSSRH0
1
SCD1U10V2KX-4GP
AA25 U5 E1 C155
R26
PCIE_VSS_78 VSS_115
F22 OR M52P,M54P,M56P REGISTER VSSRH1 CONNECT TO +2.8V
PCIE_VSS_79 VSS_116 FOR M52P,M54P,M56P
AA26 PCIE_VSS_80 VSS_117 F18 CONFIGURATION
2
T27 PCIE_VSS_81 VSS_118 K30 M52P-GP CONNECT TO +2.5V
AE27 C24 1 R172 2 VGA_VDDRH0
PCIE_VSS_82 VSS_119 1D8V_S0
1
F24 0R0603-PAD C251

VSS_120
W23 PCIE_PVSS VSS_121 M24
A25 SC1U6D3V2KX-GP
VSS_122
2
B B
B1 VSS_1 VSS_123 D30
H1 VSS_2 VSS_124 E25
L1 G25 1 R171 2 VGA_VDDRH1
VSS_3 VSS_125
1
P1 G20 0R0603-PAD C244

VSS_4 VSS_126
U1 VSS_5 VSS_127 G22
CORE GND
Y1 F27 SC1U6D3V2KX-GP
VSS_6 VSS_128
2
AD7 VSS_7 VSS_129 E28

AE8 VSS_8 VSS_130 H21 DY
AL1 VSS_9 VSS_131 C27 2 R166 1
A2 E32 0R3-0-U-GP BLON CAN ALSO BE A PWM OUTPUT
VSS_10 VSS_132 U70G
AM2 VSS_11 VSS_133 H28 FOR BRIGHTNESS CONTROL
AD10 VSS_12 VSS_134 J30 Q10 PART 7 OF 7
E8 VSS_13 VSS_135 K17 SI2301BDS-T1-GP SA rework 0924
H5 K27 Forward Control and External SSC AD12 BLON_IN
VSS_14 VSS_136 VARY_BL BLON_IN 31
K10 VSS_15 VSS_137 M32 D S 3D3V_S0 Compatibility DIGON AE11 ATI_LCDVDD_ON 13
M8 VSS_16 VSS_138 A22 GENERICD AD23
T10 VSS_17 VSS_139 C20
2
1
E12 VSS_18 VSS_140 E19 M56P FOR M26X GENERICD
G
AC9 H20 R205 R148 AJ21 R129

VSS_19 VSS_141 100KR2J-1-GP VGA_BBN TXCLK_UP ATI_TXBCLK+ 13 NO CONNECT OR
AF14 J24 1 2 Y23 AK21 ATI_TXBCLK- 13 10KR2J-3-GP
AD8
VSS_20 VSS_142
M28 K15
BBN_4
Only used in TXCLK_UN
AH21 EXT SPREAD SPECTRUM OUTPUT
VSS_21 VSS_143 0R2J-2-GP BBN_3 TXOUT_U3P FOR M52P,M54P
C5 VSS_22 VSS_144 J28 R10 BBN_2 dual-channel TXOUT_U3N AG21
1
2
F10 J16 R149 AC17 AG20 ATI_TXBOUT2+ 13 IT IS A GPIO
VSS_23 VSS_145 PWROK# VGA_BBP BBN_1 LVDS mode. TXOUT_U2P
J3 VSS_24 VSS_146 F30 VGA_CORE_S0 1 2 AC14 BBP_4 TXOUT_U2N AH20 ATI_TXBOUT2- 13 FOR M56P
L6 VSS_25 VSS_147 L29 M56P 0R2J-2-GP
M23 BBP_3 TXOUT_U1P AK20 ATI_TXBOUT1+ 13
IT IS A BACK BIAS REGULATOR CONTROL
M6 VSS_26 VSS_148 A31 V10 BBP_2 TXOUT_U1N AJ20 ATI_TXBOUT1- 13
P6 B32 D K18 LVDS channel AG18
VSS_27 VSS_149 BBP_1 TXOUT_U0P ATI_TXBOUT0+ 13
AA4 VSS_28 VSS_150 E30 BACK BIASING APPLIES TO M56P ONLY TXOUT_U0N AH18 ATI_TXBOUT0- 13
3
AG11 VSS_29 VSS_151 AE15 IF BACK BIAS NOT USED ON M56,CONNECT

V3 AG23 Q11 AK19 ATI_TXAOUT0- 13
AG16
VSS_30 VSS_152
AD9 2N7002-8-GP
BBN PINS TO VSS AND BBP PINS TO VDDC TXOUT_L0N
AL19
VSS_31 VSS_153 TXOUT_L0P ATI_TXAOUT0+ 13
R3 AF16 1 BBN,BBP PINS ARE NO CONNECT FOR L10 AL20 ATI_TXAOUT1- 13
VSS_32 VSS_154 VDD25_4 TXOUT_L1N
C6 VSS_33 VSS_155 AH10 G M26X,M54P,M52P K22 VDD25_5
This channel is TXOUT_L1P AM20 ATI_TXAOUT1+ 13
C9 VSS_34 VSS_156 AJ10 AA10 VDD25_6 used as the TXOUT_L2N AL21 ATI_TXAOUT2- 13
2
F6 VSS_35 VSS_157 AD15 transmitting TXOUT_L2P AM21 ATI_TXAOUT2+ 13

H7 AH16 S AK18
VSS_36 VSS_158 channel in single TXOUT_L3N
J6 VSS_37 TXOUT_L3P AJ18
A K23 channel LVDS mode. AL18 ATI_TXACLK- 13 A
VSS_159 TXCLK_LN
TXCLK_LP AM18 ATI_TXACLK+ 13
M52P-GP
1 R167 2 VGATE_PWRGD 7,16,38 M52P-GP <Variant Name>

0R0402-PAD
1 R206 2 CPUCORE_ON 38,40,41,43 2D5V_S0
0R2J-2-GPDY C210 C142 CONNECT THESE VDD25 PINS TO 2.5V FOR M52P,M54P,M56P
Wistron Corporation
SC1U6D3V2ZY-GP
1
1
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
C195
THESE VDD25 PINS ARE NO CONNECT FOR M26X 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
2
Title
ATI M5X-P Power 4/4
C
AG1 -1
5 4 3 2 1
5 4 3 2 1
Ideal Power Up Sequence Real Power Up Sequence

D D
VBBN VBBN
VBBP VBBP
VDDC VDDC
MVDDC MVDDC
1mS
PCIE_VDDR_12 PCIE_VDDR_12
PCIE_PVDD_12 PCIE_PVDD_12
C C
VDD25 VDD25
VDDR1 VDDR1
<5mS
VDDR3 VDDR3
RESISTOR General Guidelines:

• BBN and BBP must ramp up before or at the same time as VDDC but not after.
Symbol name Value Tolerance Rating Size
B • VDDC and MVDDC must be ramped up first, followed by PCIE_VDDR_12, PCIE_PVDD12, VDD25, VDDR1 and B
0402=> 1/16W, 25V 2=>0402, 3=>0603, 5=>0805, VDDR3 (and other I/O powers).
(J: 5%, F: 1%, D: 0.5%, B: 0.1 %) 0603 => 1/16W, 75V 6=>1206, 0=>1210 • All powers must be ramped up within 5ms of each other (from the ramp of VDDC to 90% of VDDR3).
0805 => 1/10W, 100V • VDD25 can be ramped with VDDC or VDDR1 but it cannot be ramped later than VDDR1.
• The power down is the opposite of the power on sequence: VDDR3/VDDR1 -> VDD25
10KR3 10K Ohm If no letter, it means J: 5% 1/16W, 75V 0603 ->VDDC/MVDDC/BBN/BBP.
Due to the level shifter design in the memory I/Os, in order to avoid over-stressing the thin oxide transistors when
VDDR1 is powered on but VDDC is not, VDDC must ramp up before VDDR1. Similarly, VDDC must ramp up before
33D3R5 33.3 Ohm If no letter, it means J: 5% 1/10W, 100V 0805 VDDR3. The level shifter design is a function of the transistor types used in 90nm technology and of the voltage level support.
The drawback of ramping up VDDC before the I/O voltages (such as VDDR1 and VDDR3) is that parasitic P/N junctions
1KR3F 1K Ohm F: 1% 1/16W, 75V 0603 are forward biased, thus creating a conduction path. These conduction paths will pump up VDDR1 (from the memory
IOs) and VDDR3 (from the GPIOs).
The real power up sequence will appear as follows:
The naming rule is value + R + size + tolerance
Figure 2-2. Real Power Up Sequence
For the value, it can be read by the number before R. (R means resistor)
As long as MVDDC ramps up with VDDC, the pump voltage on VDDR1 should be all right since the DRAM spec will
For the tolerance, it can be read from the last letter.
not be violated.
For the rating, we don't show on the symbol name.
For the size, R2=>0402, R3=>0603, R5=>0805,....
CAPACITOR
Symbol name Value Tolerance Rating Size The naming rule is
A (J: +/-5, K: +/-10, ( X5R / X7R < 80%, 2=>0402, 3=>0603, 5=>0805,
Capacitor type + value + rating + size + tolerance + material
SCD1U10V2MX-1
<Variant Name>
A
M: +/-20, Z: +80/-20) Y5V/Y5U/Z5U < 1/3 ) 6=>1206, 0=>1210
SC=> SMT Ceremic, TC=> POS cap or SP cap
D1U => 0.1uF Wistron Corporation
SCD1U10V2MX-1 0.1uF M/X5R 10V 0402 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
10V => the voltage rating is 10V Taipei Hsien 221, Taiwan, R.O.C.
2=> 0402, 3=>0603, 5=>0805
SC10U6D3V5MX 10uF M/X5R 6.3V 0805 M=>tolerance J, K, M, Z Title
X=> X7R/X5R, Y=> Y5V
-1 => symbol version, nonsense to EE characteristic
ATI M5X-P POWER SEQUENCE
SC2D2U16V5ZY 2.2uF Z/Y5V 16V 0805 Size Document Number Rev
A3
AG1 SA
5 4 3 2 1
CHAN B DDR2 84BGA 32MX16 MEMORY
D D
1D8V_S0
1
C189 C664 C186 C185 C190 C188 C182 C192
SCD1U10V2KX-4GP
SC1U6D3V2KX-GP
SCD1U10V2KX-4GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SC1U6D3V2KX-GP
2
2
DDR_VREF_S0
M56P
1D8V_S0 RN22
MAB2 1 8
1
C577 C654 C663 C191 C662 C652 C578 C655 MAB7 2 7
MAB3
SCD1U10V2KX-4GP
SC1U6D3V2KX-GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SCD1U10V2KX-4GP
SC1U6D3V2KX-GP
3 6
MAB1 4 5
2
SRN56J-2-GP RN93
MAB10 1 8
MAB9 2 7
MAB5 3 6
MAB0 4 5
SRN56J-2-GP RN92
MAB4 1 8
MAB6 2 7
MAB8 3 6
MAB11 4 5
U23 U69 SRN56J-2-GP
C L2 B9 MDB7 B_BA0 L2 B9 MDB27 B_BA0 R552 1 256R2J-4-GP C
47,51 B_BA0 BA0 DQ15 MDB0 B_BA1 BA0 DQ15 MDB28 B_BA1 R551 1
47,51 B_BA1 L3 BA1 DQ14 B1 L3 BA1 DQ14 B1 256R2J-4-GP
D9 MDB5 D9 MDB24 MAB12_14 R550 1 256R2J-4-GP
DQ13 MDB2 MAB12_14 DQ13 MDB31
47,51 MAB12_14 R2 A12 DQ12 D1 R2 A12 DQ12 D1
MAB11 P7 D3 MDB3 MAB11 P7 D3 MDB30 ODTB0 R572 1 256R2J-4-GP
MAB10 A11 DQ11 MDB4 MAB10 A11 DQ11 MDB25 47 ODTB0 ODTB1 R82 1
M2 A10/AP DQ10 D7 M2 A10/AP DQ10 D7 47,51 ODTB1 256R2J-4-GP
MAB9 P3 C2 MDB1 MAB9 P3 C2 MDB29
MAB8 A9 DQ9 MDB6 MAB8 A9 DQ9 MDB26 RASB0# R574 1
P8 A8 DQ8 C8 P8 A8 DQ8 C8 47 RASB0# 256R2J-4-GP
MAB7 P2 F9 MDB23 MAB7 P2 F9 MDB15 RASB1# R83 1 256R2J-4-GP
MAB6 A7 DQ7 MDB18 MAB6 A7 DQ7 MDB9 47,51 RASB1#
N7 A6 DQ6 F1 N7 A6 DQ6 F1
MAB5 N3 H9 MDB20 MAB5 N3 H9 MDB12 CASB0# R571 1 256R2J-4-GP
MAB4 A5 DQ5 MDB16 MAB4 A5 DQ5 MDB8 47 CASB0# CASB1# R81 1
N8 A4 DQ4 H1 N8 A4 DQ4 H1 47,51 CASB1# 256R2J-4-GP
MAB3 N2 H3 MDB17 MAB3 N2 H3 MDB11
MAB2 A3 DQ3 MDB21 MAB2 A3 DQ3 MDB13 WEB0# R577 1
M7 A2 DQ2 H7 M7 A2 DQ2 H7 47 WEB0# 256R2J-4-GP
MAB1 M3 G2 MDB19 MAB1 M3 G2 MDB10 WEB1# R555 1 256R2J-4-GP
MAB0 A1 DQ1 MDB22 MAB0 A1 DQ1 MDB14 47,51 WEB1#
M8 A0 DQ0 G8 M8 A0 DQ0 G8
CSB0_0# R570 1 256R2J-4-GP
47 CSB0_0# CSB1_0# R84 1
47,51 CSB1_0# 256R2J-4-GP
CLKB0# K8 A9 CLKB0# K8 A9
CLKB0 CK VDDQ1 47 CLKB0# CLKB0 CK VDDQ1 CKEB0 R576 1
J8 CK VDDQ2 C1 47 CLKB0 J8 CK VDDQ2 C1 47 CKEB0 256R2J-4-GP
C3 C3 CKEB1 R86 1 256R2J-4-GP
CKEB0 VDDQ3 CKEB0 VDDQ3 47,51 CKEB1
K2 CKE VDDQ4 C7 K2 CKE VDDQ4 C7
VDDQ5 C9 VDDQ5 C9
1
1
VDDQ6 E9 VDDQ6 E9
G1 1D8V_S0 R573 R575 G1 1D8V_S0
CSB0_0# VDDQ7 56R2J-4-GP 56R2J-4-GP CSB0_0# VDDQ7
L8 CS VDDQ8 G3 L8 CS VDDQ8 G3 FOR M56P AT DDR2 MEMORY SPEEDS ABOVE 350MHZ
VDDQ9 G7 VDDQ9 G7 MEMORY CONTROL SIGNALS WE,CAS,RAS,CS,CKE,ODT
WEB0# K3 G9 WEB0# K3 G9
CLOSE TO MEM !!
WE VDDQ10 WE VDDQ10 AND MEMORY ADDRESS SIGNALS REQUIRE 55 OHM PULLUP

2
2
B B
RASB0# K7 RAS VDD1 A1 RASB0# K7 RAS VDD1 A1 TO A VTT RAIL (50% OF VDDQ)
VDD2 E1 VDD2 E1
CASB0# L7 J9 CASB0# L7 J9
BC857_1
CAS VDD3 CAS VDD3

VDD4 M9 VDD4 M9
DQMB#2 F3 R1 C650 DQMB#1 F3 R1
LDM VDD5 LDM VDD5
1
DQMB#0 B3 DQMB#3 B3
UDM UDM
SC470P50V2KX-3GP
VDDL J1 VDDL J1
VSSDL J7 VSSDL J7
2
1
1
ODTB0 K9 ODTB0 K9 CLKB0
ODT C183 ODT C184 47 CLKB0 CLKB0#
47 CLKB0#
2
2
RDQSB2 F7 SCD1U10V2KX-4GP RDQSB1 F7 SCD1U10V2KX-4GP
1D8V_S0 WDQSB2 LDQS 1D8V_S0 WDQSB1 LDQS RDQSB[7..0]
E8 LDQS VSSQ1 A7 E8 LDQS VSSQ1 A7 47,51 RDQSB[7..0]
VSSQ2 B2 VSSQ2 B2
B8 B8 DQMB#[7..0]
VSSQ3 VSSQ3 47,51 DQMB#[7..0]
1
VSSQ4 D2 VSSQ4 D2
R143 RDQSB0 B7 D8 R579 RDQSB3 B7 D8 MDB[63..0]
1KR2F-3-GP WDQSB0 UDQS VSSQ5 1KR2F-3-GP WDQSB3 UDQS VSSQ5 47,51 MDB[63..0]
A8 UDQS VSSQ6 E7 A8 UDQS VSSQ6 E7
F2 F2 MAB[11..0]
VSSQ7 VSSQ7 47,51 MAB[11..0]
VSSQ8 F8 VSSQ8 F8
2
VRAM_VREF1 J2 H2 VRAM_VREF2 J2 H2 WDQSB[7..0]

VREF VSSQ9 VREF VSSQ9 47,51 WDQSB[7..0]
VSSQ10 H8 VSSQ10 H8
1
(SSTL-1.8) VREF = .5*VDDQ A2 (SSTL-1.8) VREF = .5*VDDQ A2

NC#A2 NC#A2
1
R144 E2 A3 R578 E2 A3
1KR2F-3-GP C181 NC#E2 VSS1 1KR2F-3-GP C653 NC#E2 VSS1
L1 NC#L1 VSS2 E3 L1 NC#L1 VSS2 E3
R3 NC#R3 VSS3 J3 R3 NC#R3 VSS3 J3
2
SCD1U10V2KX-4GP R7 N1 SCD1U10V2KX-4GP R7 N1
NC#R7 VSS4 NC#R7 VSS4
2
R8 NC#R8 VSS5 P9 R8 NC#R8 VSS5 P9

A <Variant Name> A
HY5PS561621A-25GP HY5PS561621A-25GP
72.55616.C0U 72.55616.C0U
Wistron Corporation
72.55616.C0U IC VRAM HY5PS561621AFP-25 FBGA(16M*16, 350Mhz) Hynix-128M Taipei Hsien 221, Taiwan, R.O.C.
72.18256.B0U IC VRAM HYB18T256161AFL25 BGA (16M*16, 350Mhz) Infineon-128M Title
72.18512.A0U IC VRAM HYB18T512161BF-25 BGA (32M*16, 400Mhz) Infineon-256M
VRAM 1/2
A3
AG1 SC
5 4 3 2 1
5 4 3 2 1
D D
-1 Modify
1D8V_S0
C92
1
C661 C193 C88 C187 C89 C86 C90
SC1KP16V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SCD1U10V2KX-4GP
SC1U6D3V2KX-GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SC10U6D3V5MX-3GP
2
2
1D8V_S0
C635
1
C630 C634 C632 C633 C85 C84 C651
SC1KP16V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SCD1U10V2KX-4GP
SC1U6D3V2KX-GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SC10U6D3V5MX-3GP
2
2
C C
U21
B_BA0 L2 B9 MDB39 U68
47,50 B_BA0 B_BA1 BA0 DQ15 MDB32 B_BA0 MDB59
47,50 B_BA1 L3 BA1 DQ14 B1 L2 BA0 DQ15 B9
D9 MDB38 B_BA1 L3 B1 MDB60
MAB12_14 DQ13 MDB34 BA1 DQ14 MDB58
47,50 MAB12_14 R2 A12 DQ12 D1 DQ13 D9
MAB11 P7 D3 MDB33 MAB12_14 R2 D1 MDB62
MAB10 A11 DQ11 MDB37 MAB11 A12 DQ12 MDB63
M2 A10/AP DQ10 D7 P7 A11 DQ11 D3
MAB9 P3 C2 MDB35 MAB10 M2 D7 MDB56
MAB8 A9 DQ9 MDB36 MAB9 A10/AP DQ10 MDB61 RASB1#
P8 A8 DQ8 C8 P3 A9 DQ9 C2 47,50 RASB1#
MAB7 P2 F9 MDB44 MAB8 P8 C8 MDB57
N7 A6 DQ6 F1 P2 A7 DQ7 F9
MAB5 N3 H9 MDB47 MAB6 N7 F1 MDB53 CASB1#
MAB4 A5 DQ5 MDB40 MAB5 A6 DQ6 MDB48 47,50 CASB1#
N8 A4 DQ4 H1 N3 A5 DQ5 H9
MAB3 N2 H3 MDB41 MAB4 N8 H1 MDB55
MAB2 A3 DQ3 MDB46 MAB3 A4 DQ4 MDB52 WEB1#
M7 A2 DQ2 H7 N2 A3 DQ3 H3 47,50 WEB1#
MAB1 M3 G2 MDB42 MAB2 M7 H7 MDB49
M8 A0 DQ0 G8 M3 A1 DQ1 G2
MAB0 M8 G8 MDB50 CSB1_0#
A0 DQ0 47,50 CSB1_0#
CLKB1# K8 A9 CKEB1
CLKB1 CK VDDQ1 CLKB1# 47,50 CKEB1
J8 CK VDDQ2 C1 47 CLKB1# K8 CK VDDQ1 A9
C3 CLKB1 J8 C1 ODTB1
CKEB1 VDDQ3 47 CLKB1 CK VDDQ2 47,50 ODTB1
K2 CKE VDDQ4 C7 VDDQ3 C3
C9 CKEB1 K2 C7
VDDQ5 CKE VDDQ4 CLKB1
VDDQ6 E9 VDDQ5 C9 47 CLKB1
1D8V_S0
1
VDDQ7 G1 1 VDDQ6 E9 47 CLKB1#
CLKB1#
CSB1_0# L8 G3 R554 R556 G1 1D8V_S0
CS VDDQ8 56R2J-4-GP 56R2J-4-GP CSB1_0# VDDQ7
VDDQ9 G7 L8 CS VDDQ8 G3
B WEB1# B
K3 WE VDDQ10 G9 VDDQ9 G7
WEB1# K3 G9 RDQSB[7..0]
WE VDDQ10 47,50 RDQSB[7..0]
2
2
RASB1# K7 A1
CLOSE TO MEM !!
RAS VDD1 RASB1# DQMB#[7..0]

VDD2 E1 K7 RAS VDD1 A1 47,50 DQMB#[7..0]
CASB1# L7 J9 E1
CAS VDD3 CASB1# VDD2 MDB[63..0]
M9 L7 J9
BC856_1
DQMB#5 VDD4 CAS VDD3 47,50 MDB[63..0]

F3 LDM VDD5 R1 VDD4 M9
DQMB#4 B3 C631 DQMB#6 F3 R1 MAB[11..0]
UDM LDM VDD5 47,50 MAB[11..0]
1
J1 DQMB#7 B3
VDDL UDM WDQSB[7..0]
SC470P50V2KX-3GP
VSSDL J7 VDDL J1 47,50 WDQSB[7..0]

1
ODTB1 K9 J7
ODT VSSDL
2
1
C83 ODTB1 K9 ODT C629 C628
2
RDQSB5 F7 SCD1U10V2KX-4GP SC1U10V3KX-3GP

LDQS
2
1D8V_S0 WDQSB5 E8 A7 RDQSB6 F7 SCD1U10V2KX-4GP
LDQS VSSQ1 1D8V_S0 WDQSB6 LDQS
VSSQ2 B2 E8 LDQS VSSQ1 A7
VSSQ3 B8 VSSQ2 B2
1
VSSQ4 D2 VSSQ3 B8
1
R90 RDQSB4 B7 D8 D2
1KR2F-3-GP WDQSB4 UDQS VSSQ5 R87 RDQSB7 VSSQ4
A8 UDQS VSSQ6 E7 B7 UDQS VSSQ5 D8
F2 1KR2F-3-GP WDQSB7 A8 E7
VSSQ7 UDQS VSSQ6
VSSQ8 F8 VSSQ7 F2
2
VRAM_VREF3 J2 H2 F8
VREF VSSQ9 VSSQ8
2
H8 VRAM_VREF4 J2 H2
VSSQ10 VREF VSSQ9
1
(SSTL-1.8) VREF = .5*VDDQ A2 H8

NC#A2 VSSQ10
1
R89 E2 A3 (SSTL-1.8) VREF = .5*VDDQ A2

NC#E2 VSS1 NC#A2
1
1KR2F-3-GP C87 L1 E3 R85 E2 A3

NC#L1 VSS2 1KR2F-3-GP C82 NC#E2 VSS1
R3 NC#R3 VSS3 J3 L1 NC#L1 VSS2 E3
2
SCD1U10V2KX-4GP R7 N1 R3 J3
A NC#R7 VSS4 NC#R3 VSS3 <Variant Name> A
2
R8 P9 SCD1U10V2KX-4GP R7 N1
NC#R8 VSS5 NC#R7 VSS4
2
R8 NC#R8 VSS5 P9
HY5PS561621A-25GP Wistron Corporation
72.55616.C0U HY5PS561621A-25GP 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
72.55616.C0U Taipei Hsien 221, Taiwan, R.O.C.
Title
VRAM 2/2
A3
AG1 -1
5 4 3 2 1
5 4 3 2 1
VGA_CORE_S0 VGA_CORE_PWR VGA_CORE_S0
G2 G61
1 2 1 2
G1 GAP-CLOSE-PWRG62 GAP-CLOSE-PWR
DCBATOUT DCBATOUT_5234 1 2 1 2
G11 G3 GAP-CLOSE-PWRG60 GAP-CLOSE-PWR

1 2 1 2 1 2
D D
GAP-CLOSE-PWR GAP-CLOSE-PWRG63 GAP-CLOSE-PWR
G10 1 2
1 2
G4
FAN5234 FOR VGA_Core

GAP-CLOSE-PWR
GAP-CLOSE-PWR 1 2
G9
1 2 G5 GAP-CLOSE-PWR
1 2
GAP-CLOSE-PWR
G12 G64 GAP-CLOSE-PWR
1 2 1 2
DCBATOUT_5234
GAP-CLOSE-PWR G6 GAP-CLOSE-PWR
G14 1 2
1 2
5V_S5 G7 GAP-CLOSE-PWR
1
GAP-CLOSE-PWR C22 C556 C23 1 2
1
G13
1 2 G8 GAP-CLOSE-PWR
SC10U35V0ZY-1GP
SC10U35V0ZY-1GP
SCD1U25V3ZY-1GP
2
1 2
2
1
1
GAP-CLOSE-PWR
5
6
7
8
C45 C47 G66 GAP-CLOSE-PWR
D
D
D
D
SC10U10V5ZY-1GP SCD1U16V2ZY-2GP U63 Id=11A 1 2
2
AO4422-1-GP
Qg=9.8nC G65 GAP-CLOSE-PWR
Rdson=19.6~24mohm 1 2
C46
D5 GAP-CLOSE-PWR
M52:1.0V
G
S
S
S
C 5V_S0 1 2 5234_BOOT 1 2 SC C
4
3
2
1
SSM5818SLPT-GP
M54:1.1V
16,18,30,31,36,41,43 PM_SLP_S3# SCD1U25V3KX-GP
1
R499 U8
L1 Panasonic M56: 1.1V
Vout Setting:
DUMMY-R2 1 2 Iomax=17A
16 FPWM PGND 9 L-D56UH-U DY 0.9V/Rlow=(Vout-0.9V)/Rhigh
5234_SS
15 BOOT AGND 8
R36
OCP>28A
7 SS
2
5234_ILIM 1K2R3F-GP VGA_CORE_PWR

1 R498 5234_EN
4 ILIM 5234_ISEN
L2 Vosetting=1.0809V
2 3 EN ISNS 12 1 2 TAI-TECH
13 5234_SW 1 2
10KR2J-3-GP DCBATOUT_5234 SW IND-1UH-48-GP
6 14 5234_HDRV
VSEN HDRV 5234_LDRV 5V_S0
5 VOUT LDRV 10
1
R12 2 5234_VIN
SCD01U16V2KX-3GP
1 1 VIN
5
6
7
8
1
0R0603-PAD 11 2 C42 R11 R33
VCC PGOOD
1
D
D
D
D
U64 300KHz 655R3F-GP C555 TC18 TC17
97K6R3F-GP
1
R13 442R2F-GP SCD1U25V3ZY-1GP SE330U2VDM-L2GP SE330U2VDM-L2GP
2
C41 R34 FAN5234MTCX-1GP 74.05234.A7G TP67 AO4430-1-GP 10KR2J-3-GP
DY
2
1
SCD22U16V3ZY-GP TPAD30
SC
2
C21
SC
2
1
SCD1U25V3KX-GP
Non-M52 M52P
G
S
S
S
2
C44 Panasonic V Size 330uF 2V
4
3
2
1
1
SC2200P50V2KX-2GP
SC Id=18A ESR=9mohm, Iripple=3.0A

2
R14
PWM Mode: Qg=48nC DUMMY-R3 USD:0.250 (Q3/05)
FPWM (High)=>Fixed PWM Mode. Rdson=6.2~7.5mohm
1
B B
FPWM (Low)=>Hysteretic Mode.
2
R35
2KR2F-3-GP
5234_VSEN
2
3D3V_S0
POWERPLAY:
Rilim=(11.2/Iilim)*((100+Rsense)/Rdson) : 1.0V
1
high (3.3V) = set lower core voltage (e.g. VDDC = 1.0V) R481
M52P Q9 10KR2J-3-GP Non-M52
low (0V) = set higher core voltage (e.g. VDDC = 1.2V)
1
2N7002-8-GP
High :R35 + R31 set Vout to 0.9994V.
3
R32 R31 D
2
Low : R35 set Vout to 1.19925V. 5K9R2F-GP 1 R497
4K02R2F-GP
1 2
Non-M52 G 20KR2J-L2-GP
C
1
Non-M52
S C566
Non-M52
2
M54/M56 : 0.95V Q35 B GPIO_PWRCNTL 46
SC4D7U10V5ZY-3GP CHT2222APT-GPNon-M52
High :R35 + R31 set Vout to 1.0989V.
2
Low : R35 set Vout to 0.9503V. Non-M52
1 E
1
R485 R483
M52 : 0.95V, but don't card it.(1.0V) 1KR2J-1-GP 100KR2J-1-GP
don't mount Q9 Non-M52
R35 + R31 set Vout to 0.9994V.
2
A ATI M5x VGA Core <Variant Name> A
VGA Ver. Normal PowerPlay

Wistron Corporation
M52 A12 1.0 0.95/1.0 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
M54 A12 1.1 0.95/0.95
Title
1.2 0.95
M56 VGA CORE 1D1V
B24 1.1 0.95/0.95 Size Document Number Rev
A3
AG1 -1
5 4 3 2 1
A B C D E
EMI CAP
5V_S0 5V_S0
4 DCBATOUT BT+ 4
U59C U59D
14
10
14
13
SCD1U25V3ZY-1GP
SCD1U25V3ZY-1GP
SCD1U25V3ZY-1GP
SCD1U25V3ZY-1GP
SCD1U25V3ZY-1GP
SCD1U25V3ZY-1GP
SCD1U25V3ZY-1GP
SCD1U25V3ZY-1GP
SCD1U25V3ZY-1GP
SCD1U25V3ZY-1GP
SCD1U25V3ZY-1GP
1
1
9 8 12 11 EC22 EC37 EC38 EC39 EC40 EC47 EC44 EC43 EC46 EC45 EC48
TSAHCT125PW-GP TSAHCT125PW-GP
2
7
7
3D3V_S0
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
1
1
EC67 EC42 EC61 EC66 EC41 EC58 EC63 EC62 EC60 EC59 EC57 EC65 EC64
2
New Card CPU Thermal Module
TOP SIDE:
H17 H7 H12 H13
K1 K3 K4
1 1 1
3 3
SPRING-U3 SPRING-9-GP SPRING-9-GP
DY DY
1
34.4A901.001 34.4A908.001 34.40U07.001 34.49U23.001
FOR MDC IO Bracket IO Bracket VGA UMA FOR MINIC MINIC MINIC
BOTTOM SIDE:
H24 H26 H31 H34 H27 H32 H30 H28 H29
K2
1
SPRING-23-GP
1
1
34.4A902.001 34.4A903.001 34.4A904.001 34.4A905.001 34.4A906.001 34.4A907.001 34.39S07.001
2 2
H10 H16 H20 H4 H2 H1 H6 H9 H3 H11 H14 H8 H5 H18 H15

HOLE HOLE HOLE HOLE HOLE HOLE HOLE HOLE HOLE HOLE HOLE HOLE HOLE HOLE HOLE
1
1
H35 H33 H19 H36 H22 H21
HOLE HOLE HOLE HOLE HOLE HOLE
1
AUD_AGND
1 <Variant Name> 1
Wistron Corporation
Title
SPRING & BOSS

A3
AG1 -1
A B C D E

Acer 5560

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Acer 5560

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A B C D E

Garda-D Block Diagram

DDR2 LVDS 14"WSXGA+ 1D8V_S3

4 LDRQ[0], LDRQ[1]/GPIO[41], 0 0 1 0 -1.50 Down CFG[4:3] Reserved 4

3 Termination Resistors Global R-comp Disable

DPRSLPVR Reserved This signal should not be pull high.

2 R158 1 3D3V_CLKPLL_S0 2 R213 1 3D3V_48MPWR_S0 3D3V_CLKGEN_S0 2 R155 1

RN35 1 4 SRN33J-5-GP-U CLK_MCH_3GPLL 7

32 PCLK_SIO R209 1 2 33R2J-2-GP PCLKCLK3 5 19 CLK_MCH_3GPLL_1

16 CLK_ICHPCI R211 1 2 33R2J-2-GP ITP_EN 8 23 CLK_PCIE_ICH_1#

PCLK_FWH & PCLK_PCM 11,18 SMBC_ICH 46 31 CLK_PCIE_NEW_1 2 NEW 3 CLK_PCIE_NEW# 30

SC20P50V2JN-1GP X2 R154 470R2J-2-GP 41

1 2 53 CPU_SEL2 CPU_SEL2 4,7

A24 0R2J-2-GP H_D#18 P26 AB22 H_D#50

B4 A22 PM_THRMTRIP# H_D#25 P22 AD24 H_D#57

RSVD[05] RSVD[13] 6 H_DSTBN#1 DSTBN[1]# DSTBN[3]# H_DSTBN#3 6

XDP_TDI R284 1 2 150R2F-1-GP

XDP_TMS R282 1 2 39D2R3F-2-GP

XDP_TCK R299 1 2 27D4R2F-L1-GP Wistron Corporation

All place within 2" to CPU Title

E17 VCC[039] VCCP[05] M6 E24 VSS[043] VSS[124] AB19

F7 M21 SCD1U10V2KX-4GP F11 AC3

AA12 C674 68.00230.041 H6 AD11

AB9 VCC[060] VID[5] AF2 H_VID5 38 J25 VSS[064] VSS[145] AE1

AB15 VCC[065] L3 VSS[069] VSS[150] AE16

BGA479-SKT6-GPU1 Layout Note: M2 AF3

H_D#23 W9 B12 H_A#26

H_XSWING H_D#28 U5 D14 H_A#31 R274

3 R644 H_D#31 T5 B9 H_ADSTB#0 4

H_D#45 AA6 W8 H_DINV#1

H_D#50 AC9 T7 H_DSTBN#1

H_YSCOMP H_XRCOMP E1 H_REQ#[4..0] 4

H_SLPCPU# E3 1 R646 2 H_CPUSLP# 4,15

H_YSWING E7 0R0402-PAD H_TRDY# 4

1 Place them near to the chip ( < 0.5") <Variant Name> 1

F15 CFG5 AA38 PEG_RXN13

E16 CFG10 0 1 0 200M F38 PEG_RXP1

H15 CFG17 G30 P34 PEG_RXP8

C737 C667 A27 J26 CFG20 V38 PEG_RXP11

AG37 DMI_TXN_2 NC5 BA39 EXP_A_TXN_14 1 2

16 DMI_RXP[3..0] NC8 BA1 E23 CRT_BLUE EXP_A_TXP_0 D36 GTXP0 1 2 PEG_TXP0

1 R2532 CFG7 0=Moby Dick ,1=Calistoga (default)

DUMMY-R2 When Low choice

DUMMY-R2 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

M_A_DQ33 SA_DQ32 SA_MA_1 M_A_A2 M_B_DQ36 SB_DQ35 SB_MA_3 M_B_A4

AN9 SA_DQ45 M_A_RAS# 11,12 BA10 SB_DQ48 SB_RCVENIN# AK16

R41 VCC3G4 VTT_9 L14

68.00230.041 1D5V_S0 C28 R8

68.00230.041 SC10U10V5ZY-1GP SCD1U10V2KX-4GP R6

C336 C314 C330 C334 AF14

AB20 VCC_89 VCC_SM_85 AH12 N35 VSS_88 B13 VSS_264 VSS_357 H2

P20 BA8 SC10U10V5ZY-1GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP J35 K12 AL1

N18 VCC_102 VCC_SM_98 AV6

TC21 DY C736 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

L18 VCC_104 VCC_SM_100 AR6

N17 VCC_106 VCC_SM_102 AN6

M17 AL6 Title

8,12 M_A_A[13..0] DM2

VREF VSS VSS VSS

2 196 C696 BC10

DDR2-200P-5-GP 62.10017.771 Title

PARALLEL TERMINATION Decoupling Capacitor

RN67 Wistron Corporation