Академический Документы
Профессиональный Документы
Культура Документы
OBJECTIVES : (i) Identification and verification of NAND gate (IC chip #7400) and NOR gate
(IC chip #7402).
(ii) Construction and Verification of all other gate (AND, OR, NOT, XOR) USING
a) Only NOR gate
b) Only NAND gate
MATERIAL REQUIRED :
THEORY :
NAND Gate : The NAND gate is a contraction of AND-NOT. The output is high when both
inputs are low and any one of the input is low .The output is low level when both inputs are
high.
Universal Gates: Universal Gates are those gates from which all other gates can be made.
NAND & NOR gates are called as Universal gates.
A Y =A'
A
B
Y=A B
Y=A+B
B
XOR Gate Using NAND:
A'
B
Y = A'B+AB'
A
B'
A
Y =A'
B Y=A B
B Y=A+B
A'
B'
Y= A'B +AB'
A
B
PROCEDURE :
OBSERVATION TABLE:
INPUT OUTPUT
INPUT OUTPUT -----
--- A B Y= A+B
A B Y= AB
0 0 1
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 0
Truth Table Of NOT Using NAND/NOR Gate Truth Table Of AND Using NAND/NOR Gate
0 1 0 0 0
1 0 0 1 0
1 0 0
1 1 1
Truth Table Of OR Using NAND/NOR Gate
A B Y= A+B
INPUT OUTPUT
0 0 0 Y= A XOR B
A B
0 1 1
1 0 1 0 0 0
1 1 1 0 1 1
1 0 1
1 1 0
RESULT :
EXPERIMENT - 2
TITLE : Basic gates, Code Convertor & Parity Generator and checker.
OBJECTIVES :
(i) Identification & verification of NOT (7404), AND (7408) OR (7432) & XOR (7486)
gates.
(ii) Designing, construction and verification of Binary to Gray convertor and Grey to
Binary convertor.
(ii) Design, construction and verification of 3-bit Parity Generator and 4-bit odd parity
checker circuit.
MATERIAL REQUIRED:
Sl. No. Equipment/ Component Name Specification Qty.
1 NOT Gate IC # 7404 1
2 AND Gate IC # 7408 1
3 OR Gate IC # 7432 1
4 XOR Gate IC # 7486 1
5 LED - 3
6 Resistor 330 Ω 3
7 Breadboard - 1
8 DC Power Supply 5 Volt 1
9 Connecting Wires - -
THEORY :
NOT Gate : The NOT gate is called an inverter. The output is high when the input is low.
The output is low when the input is high.
Truth Table:
Logic Functions: G2 = B2
G1 = B2 XOR B1
G0 = B1 XOR B0
Logic Diagram:
B2 G2
G1
B1
G0
B0
Truth Table:
B1 = B2 XOR G1
B0 = B1 XOR G0
Logic Diagram:
G2
B2
G1 B1
B0
G0
Basic Principle to generate the parity bit is “the module sum of even number of 1’s is
0 and the module sum of odd number of 1’s is 1. Parity Generator generates a bit to pair
with the code group so as to make the number of 1’s either odd or even as desired at the
transmitter side.
Truth Table:
Input Output
X Y Z Peven Podd
0 0 0 0 1
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 0
Podd = X (Y Z)
X
Y
P
Z even
Logic Diagram for 3 Bit Odd Parity Generator:
X
Y
P
Z odd
At Receiver, checks each code group to see that the total number of 1’s (including
Parity bit) is consistent with the agreed upon type of Parity (with Transmitter).
Logic Diagram:
X
Y
P
(Parity Bit) P
checker
1 (Even)
0 (Odd)
PROCEDURE:
OBSERVATION TABLE:
0 1 0 0 0
1 0 0 1 0
1 0 0
1 1 1
Truth Table of OR Gate: Truth Table Of 3 Bit Binary to Gray Code
Converter
Input Output
X Y Z P Pchecker
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
PRECAUTION:
RESULT:
EXPERIMENT – 3
OBJECTIVES:
(i) Design, construction and verification of Half Adder and Half Subtractor circuit.
(ii) Design, construction and verification of Full Adder and Full Subtractor circuit.
(iii) Design, construction and verification of 1-bit and 4-bit Magnitude comparator.
MATERIAL REQUIRED:
THEORY:
Half Adder: It adds two binary digits (A & B) results Sum output (S) and a Carry Output (C).
Truth Table:
Input Output
A B S C
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
Logic Diagram:
A
S
B
Half Subtractor: It subtracts two binary digits (X & Y) results Difference output (D) & a
Borrow Output (B).
Truth Table:
Input Output
X Y D B
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0
Logic Diagram:
X
D
Y
Full Adder: It adds three binary digits (A , B & Cin). Cin is the carry resulted from the
previous addition. It gives a sum Output (S) and a Carry output (Cout).
Truth Table:
Input Output
A B Cin S Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
-- -- -- -- -- --
Logic Functions: S = A B Cin + A B Cin + A B Cin + A B Cin
-- -- -- -- --
= Cin (A B + A B) + Cin (A B + A B)
= Cin A B
-- -- --
Cout = A B Cin + A B Cin + A B Cin + A B Cin
-- --
= Cin (A B + A B) + A B
= Cin (A B) + A B
Logic Diagram:
A
B
S
Cin
Cout
Full Subtractor: It subtracts three binary digits (X , Y & Bin). Bin is the borrow input. It gives
a Difference Output (D) and a Borrow output (Bout).
Truth Table:
Input Output
X Y Bin D Bout
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
-- -- -- -- -- --
Logic Functions: D = X Y Bin + X Y Bin + X Y Bin + X Y Bin
-- -- -- -- --
= Bin (X Y + X Y ) + Bin (X Y + X Y)
= Bin X Y
-- -- -- -- --
Bout = X Y Bin + X Y Bin + X Y Bin + X Y Bin
------------ ---
= Bin (X Y)+XY
Logic Diagram:
X
Y
D
Bin
Bout
Magnitude Comparator:
It is a combinational logic circuit that compares two input binary quantities and
generates output to indicate which one has greater magnitude.
Input Output
A B A>B A=B A<B
0 0 0 1 0
0 1 0 0 1
1 0 1 0 0
1 1 0 1 0
A < B = AB’
Logic Diagram:
A<B
A
A=B
B
A>B
7485 is a 4 Bit Magnitude Comparator IC. A0, A1, A2, A3 and B0, B1, B2, B3 are the
two binary inputs to be compared.
15 A3 (A>B)OUT 5
1 B3 (A=B)OUT 6
13 A2 (A<B)OUT 7
14 B2
12 A1
11 B1
10 A0
7485N
9 B0
4 (A>B)IN
3 (A=B)IN
2 (A<B)IN
PROCEDURE:
EXPERIMENT – 4
TITLE: Decoder, MUX & DMUX
OBJECTIVES: (i) Construction and verification of BCD to 7-segment decoder using IC # 7447
(ii) Verification of 4:1 MUX, 8:1 MUX & 16:1 MUX.
(iii) Verification of 1:4 DMUX, 1:8 DMUX
MATERIAL REQUIRED:
THEORY:
OBJECTIVE 1:
BCD to 7 Segment Decoder Driver:
VCC 5V
U2
7 Com
13
A OA U3
A 1 12
B OB SEVEN_SEG_COM_K
2
B C OC
11
6 10
C D OD
9 A B CDE F G
D 3 OE
15
5 LT OF
14
4 RBI OG
BI/RBO
7447N
OBJECTIVE-2:
Multiplexer: It selects one input among many at a time and sends it to the output line.
For an n – input MUX, m select inputs are required, where n = 2m.
4:1 MUX: 4 inputs (I0, I1, I2, I3) and 2 select inputs (S0, S1)
Block Diagram of 4:1 MUX:
I0
I1
I2 Y
I3
74151N
8 E0 W 10
7 E1
6 E2
5 E3
4 E4
3 E5
2 E6
1 E7
23 E8
22 E9
21 E10
20 E11
19 E12
18 E13
17 E14
16 E15
15 A
14 B
13 C
11 D
9 G
74150N
OBJECTIVE - 3
DEMULTIPLEXER: Accepts a single input and distributes it on one among several outputs according
to selector input value.
1:4 DEMUX: 2 select inputs and 4 output lines.
Block Diagram:
I
Y0
Y1
Y2
Y3
OBSERVATION TABLE:
OBJECTIVE – 1: BCD to 7 Segment Decoder
Decimal
BCD Input 7 Segment Display Output Digit
Display
D C B A a b c d e f g
0 0 0 0 1 1 1 1 1 1 0
0 0 0 1 0 1 1 0 0 0 0
.
.
.
.
1 0 0 1
OBJECTIVE – 2: Truth Table of 4:1 Multiplexer Truth Table of 8:1 Multiplexer
RESULT: By 7447 and seven segment display, the display of decimal digits from 0 to 9 is done and
the truth tables of multiplexer and de-multiplexer are verified.
EXPERIMENT – 5
OBJECTIVES:
(i) Construction and Verification of a Latch circuit using NAND/NOR gates.
(ii) Construction and Verification of S-R Flip Flop using above Latch circuits.
(iii) Verification of J-K Flip Flop using IC # 7476 (Dual J-KFF)
(iv) Construction and Verification of D-Flip Flop and T-Flip Flop using J-K FF(IC #7476).
(v) Construction and Verification of Master Slave J-K Flip Flop.
MATERIAL REQUIRED:
THEORY:
OBJECTIVE-1:
LATCH: 1 Bit information can be locked or latched. It consists of two inverters. There is no
provision to get any desired digital information we wish to store in the latch.
Q'
Q'
OBJECTIVE – 2
S -R Flip Flop:
S
Q
CLK
Q'
R
OBJECTIVE – 3
J-K Flip Flop: 7476 is a dual negative edge triggered J-K Flip-flop IC.
2
~PRE
4 J Q 15
1 CLK
16 1K ~Q 14
~CLR
3
OBJECTIVE – 4
2
~PRE
D 4 15
J Q
1 CLK
16 1K ~Q 14
~CLR
3
2
~PRE
4 J Q 15
T
1 CLK
16 1K ~Q 14
~CLR
3
OBJECTIVE – 5:
OBSERVATION TABLES:
OBJECTIVE- 1: LATCH
Q Q’
0 1
1 0
CLK D Q Q’
Π 0 0 1
Π 1 1 0
Truth Table of T FF
RESULT: Latch using NAND and NOR gates, and different flip-flops are constructed and verified their
truth tables.
EXPERIMENT – 6
MATERIAL REQUIRED:
3 CLK1 ~Q1 6
~CLR1
1
~CLR1 ~CLR2
1 1
Data
Output
4 4
Data
~PRE1 Q1 Input ~PRE2
Q2
2 D1 Q1 5 2 D2 Q2 5
~CLR1 ~CLR2
1 1
OBJECTIVE- 4:
4 4
Q2
~PRE1 ~PRE2
Serial Data Input Serial Data Output
2 D1 Q1 5 2 D2 Q2 5
~CLR1 ~CLR2
1 1
4 Q1 4
Q2
~PRE1 ~PRE2
Serial Data Input
2 D1 Q1 5 2 D2 Q2 5
~CLR1 ~CLR2
1 1
Shift/Load D2
4 4
D1 ~PRE1 ~PRE2
Q2 Serial Data Output
2 D1 Q1 5 2 D2 Q2 5
~CLR1 ~CLR2
1 1
D1 D2
4 4
~PRE1 ~PRE2
2 D1 Q1 5 2 D2 Q2 5
~CLR1 ~CLR2
1 1
Q1 Q2
Parallel Output Data
PROCEDURE:
OBSERVATION TABLE:
CLK Data Q1 Q2
1 0 0
1 1 0
Π
Π 1
For 2 Bit Left Shift Register
CLK Q1 Q2 Data
0 0 1
Π 0 1 1
Π 1 1
RESULT:
EXPERIMENT – 7
OBJECTIVES:
(i) Construction and verification of 2-bit Ripple counter using J-K FF.
(ii) Construction and verification of Mod-3 up and Mod-3 down synchronous counter.
(iii) Construction and verification of 2-bit Ring counter using J-K FF.
(iv) Construction and verification of 2-bit twisted Ring (Johnson) counter using J-K FF.
MATERIAL REQUIRED:
THEORY
Ripple counter is the simplest type of counter in which flip-flops are not clocked
simultaneously. The output of previous FF becomes the clock input for next FF. The inputs J and K of
the FF are connected to logic 1.
1 1 1 1
~PRE ~PRE
J0 Q0 J1 Q1
CLK CLK
K0 ~Q0 K1 ~Q1
CLK
~CLR ~CLR
1
1
Counting Table:
Synchronous counters are the counters which are clocked such that each FF in the counter is
triggered at the same time.
Design
00
10 01
Step-2:
For J1 For K1
Q0 Q0
Q1 0 1 Q1 0 1
0 0 1 0 X X
1 X X J1 = Q0 1 1 X K1 = 1
For J0 For K0
Q0 Q0
Q1 0 1 Q1 0 1
0 1 X 0 X 1
1 0 X J0 = Q1’ 1 X X K0 = 1
Q0 Q1
1 1
~PRE ~PRE
J0 Q0 J1 Q1
CLK CLK
K0 ~Q0 K1 ~Q1
CLK 1 1
~CLR ~CLR
1
1
Similar way we can design the circuit for Mod 3 down synchronous counter
Q0 Q1
1 1
~PRE ~PRE
J0 Q0 J1 Q1
CLK CLK
K0 ~Q0 K1 ~Q1
CLK 1 1
~CLR ~CLR
1
1
Ring Counter is a SISO shift register with the output of last flip-flop is connected back to
input of the first flip-flop.
1 1
~PRE ~PRE
J0 Q0 J1 Q1
CLK CLK
K0 ~Q0 K1 ~Q1
CLK
~CLR ~CLR
1
1
Counting Table:
In this, output of each flip-flop stage is connected to the input of next stage but Q’ output of
last stage is connected to input of first stage.
Q0 Q1
1 1
~PRE ~PRE
J0 Q0 J1 Q1
CLK CLK
K0 ~Q0 K1 ~Q1
CLK
~CLR ~CLR
1
1
Counting Table:
CLK Q1 Q0
0 0
Π 0 1
Π 1 1
Π 1 0
PROCEDURE: Π 0 0
PRECAUTIONS:
RESULT:
EXPERIMENT -8
MATERIAL REQUIRED:
THEORY:
OBJECTIVE -1
Pin Diagram of 555 Timer:
GND + Vcc
Discharge
Trigger
IC 555
Threshold
output
Control voltage
Reset
ASTABLE MULTIVIBRATOR
An astable multivibrator is a multivibrator with no stable state. It has two states and both of
them are quasi-stable. The moment it is connected to the supply, it keeps on switching back and
forth between its quasi-stable states.
Astable Multivibrator Using 555 Timer:
Circuit Diagram:
Vcc = 5V/12V
RA
33kohm
8
4 VCC
RB RST
7 3
Vout
30-60Kohm
6 DIS OUT
2 THR 555
TRI
5 TIMER
CON
GND
1
0.01uF
0.01uF
The capacitor C1 charges through the resistance RA and RB and discharges through the resistance RB
only. The capacitor charges and discharges between 1/3 Vcc to 2/3 Vcc.
Charging time of the capacitor is given by = TON = 0.693 (RA+RB) C1
Discharging time of the capacitor = TOFF = 0.693 RB C1
Time Period = T = TON +TOFF = 0.693 (RA + 2 RB) C1
Frequency of Oscillation = f = 1 / T.
% of Duty Cycle = (TON/ T) x 100.
PROCEDURE:
1 30
2 60
OBJECTIVE – 2
MONOSTABLE MULTIVIBRATOR:
It has one stable state. When triggered, it changes from its stable state to quasi-stable state
and returns back to its stable state.
Circuit Diagram:
+Vcc
8
50%
4 VCC
RST
7 3
6 DIS OUT Vout
2 THR
C TRI
5
8200pF
CON
GND
Trigger 1
C2
2200pF
When Timer 555 is connected in monostable mode, trigger input is given through pin 2.
OBSERVATION TABLE:
1 30
2 40
3 50
PRECAUTION:
RESULT:
EXPERIMENT – 9
TITLE: Digital to Analog Converter (DAC) and Analog to Digital Converter (ADC).
THEORY:
Circuit Diagram:
4 Binary inputs (B0, B1, B2 and B3) results, 24 = 16 analog output values.
Working:
o/p voltage op-amp (Vout) due to all four inputs (B0, B1, B2 and B3) is
= V1 +V2+ V3 + V4
= -Vref { (B0/16) + (B1/8) + (B2/4) + (B3/2)}
Circuit Diagram: