EXPERIMENT - 1

TITLE : Universal Gates

OBJECTIVES : (i) Identification and verification of NAND gate (IC chip #7400) and NOR gate
(IC chip #7402).
(ii) Construction and Verification of all other gate (AND, OR, NOT, XOR) USING
a) Only NOR gate
b) Only NAND gate
MATERIAL REQUIRED :

Sl. No. Equipment/ Component Name Specification Qty.

1 NAND Gate IC IC #7400 2
2 NOR Gate IC IC #7402 2
3 LED - 1
4 Resistor 330 Ω 1
5 Breadboard - 1
6 DC Power Supply 5 Volt 1
7 Connecting Wires - -

THEORY :

NAND Gate : The NAND gate is a contraction of AND-NOT. The output is high when both
inputs are low and any one of the input is low .The output is low level when both inputs are
high.

Pin Diagram Of IC # 7400 (Quad 2 Input NAND Gate) :

NOR Gate : The NOR gate is a contraction of OR-NOT. The output is high when both inputs
are low. The output is low when one or both inputs are high.

Pin Diagram Of IC # 7402 IC (Quad 2 Input NOR Gate)

Universal Gates: Universal Gates are those gates from which all other gates can be made.
NAND & NOR gates are called as Universal gates.

NOT Gate Using NAND:

A Y =A'

AND Gate Using NAND:

A
B
Y=A B

OR Gate Using NAND:

Y=A+B
B
 XOR Gate Using NAND:

A'
B

Y = A'B+AB'
A
B'

NOT Gate Using NOR:

A
Y =A'

AND Gate Using NOR:

B Y=A B

OR Gate Using NOR:

B Y=A+B

XOR Gate Using NOR:

A'
B'
Y= A'B +AB'
A
B

PROCEDURE :

1. Collect the components necessary to accomplish this experiment.

2. Plug the IC chip into the breadboard.
3. Connect the supply voltage and ground lines to the chips. PIN7 = Ground
and PIN14 = +5V.
4. According to the pin diagram of each IC mentioned above, wire only one
gate to verify its truth table.
5. Connect the inputs of the gate to the input switches of the LED.
6. Connect the output of the gate to the output LEDs.
7. Once all connections have been done, turn on the power switch of the
 breadboard
8. . Operate the switches and fill in the truth table ( Write "1" if LED is ON and
"0" if LED is OFF Apply the various combination of inputs according to the truth table
and observe the condition of Output LEDs.

OBSERVATION TABLE:

Truth Table Of NAND Gate Truth Table Of NOR Gate

INPUT OUTPUT
INPUT OUTPUT -----
--- A B Y= A+B
A B Y= AB
0 0 1
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 0

Truth Table Of NOT Using NAND/NOR Gate Truth Table Of AND Using NAND/NOR Gate

INPUT OUTPUT INPUT OUTPUT

-- Y= AB
A Y= A A B

0 1 0 0 0
1 0 0 1 0
1 0 0
1 1 1
Truth Table Of OR Using NAND/NOR Gate

Truth Table Of XOR Using NAND/NOR Gate

INPUT OUTPUT

A B Y= A+B
INPUT OUTPUT
0 0 0 Y= A XOR B
A B
0 1 1
1 0 1 0 0 0
1 1 1 0 1 1
1 0 1
1 1 0

PRECAUTION : All the connections should be made properly.

RESULT :
EXPERIMENT - 2

TITLE : Basic gates, Code Convertor & Parity Generator and checker.
OBJECTIVES :
(i) Identification & verification of NOT (7404), AND (7408) OR (7432) & XOR (7486)
gates.
(ii) Designing, construction and verification of Binary to Gray convertor and Grey to
Binary convertor.
(ii) Design, construction and verification of 3-bit Parity Generator and 4-bit odd parity
checker circuit.

MATERIAL REQUIRED:
Sl. No. Equipment/ Component Name Specification Qty.
1 NOT Gate IC # 7404 1
2 AND Gate IC # 7408 1
3 OR Gate IC # 7432 1
4 XOR Gate IC # 7486 1
5 LED - 3
6 Resistor 330 Ω 3
7 Breadboard - 1
8 DC Power Supply 5 Volt 1
9 Connecting Wires - -

THEORY :

NOT Gate : The NOT gate is called an inverter. The output is high when the input is low.
The output is low when the input is high.

Pin Diagram Of IC # 7404 (Hex Inverter) :

AND Gate : The AND gate performs a logical multiplication commonly known as AND
function. The output is high when both the inputs are high. The output is low level when any
one of the inputs is low.

Pin Diagram Of IC # 7408 (Quad 2 Input AND Gate) :

OR Gate: The OR gate performs a logical addition commonly known as OR function.

The output is high when any one of the inputs is high. The output is low level when both
the inputs are low.

Pin Diagram Of IC # 7432 (Quad 2 Input OR Gate):

3 Bit Binary To Gray Code Converter:

Truth Table:

Binary Input Gray Code O/P

B2 B1 B0 G2 G1 G0
0 0 0 0 0 0
0 0 1 0 0 1
0 1 0 0 1 1
0 1 1 0 1 0
1 0 0 1 1 0
1 0 1 1 1 1
1 1 0 1 0 1
1 1 1 1 0 0

Logic Functions: G2 = B2

G1 = B2 XOR B1

G0 = B1 XOR B0

Logic Diagram:

B2 G2

G1
B1

G0
B0

3 Bit Gray To Binary Code Converter:

Truth Table:

Gray Code Input Binary Code O/P

G2 G1 G0 B2 B1 B0
0 0 0 0 0 0
0 0 1 0 0 1
0 1 0 0 1 1
0 1 1 0 1 0
1 0 0 1 1 1
1 0 1 1 1 0
1 1 0 1 0 0
1 1 1 1 0 1
 Logic Function: B2 = G2

B1 = B2 XOR G1

B0 = B1 XOR G0

Logic Diagram:

G2
B2

G1 B1

B0
G0

3 Bit Even/Odd Parity Generator:

Basic Principle to generate the parity bit is “the module sum of even number of 1’s is
0 and the module sum of odd number of 1’s is 1. Parity Generator generates a bit to pair
with the code group so as to make the number of 1’s either odd or even as desired at the
transmitter side.

Truth Table:

Input Output
X Y Z Peven Podd
0 0 0 0 1
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 0

Logic Function: Peven = X Y Z

Podd = X (Y Z)

Logic Diagram for 3 Bit Even Parity Generator:

X
Y
P
Z even
 Logic Diagram for 3 Bit Odd Parity Generator:

X
Y
P
Z odd

4 Bit Even/Odd Parity Checker:

At Receiver, checks each code group to see that the total number of 1’s (including
Parity bit) is consistent with the agreed upon type of Parity (with Transmitter).

Logic Diagram:

X
Y

P
(Parity Bit) P
checker
1 (Even)
0 (Odd)

PROCEDURE:

1. Connect the circuit as shown in the circuit diagram.

2. Before switching ON power Supply, make sure that the connections are
correct.
3. Apply the input logic as per Truth table in terms of +5 volts for state-1 and 0
volts for state-0.
4. Observe the Output state.
5. Verify the truth table.
6. Repeat steps from 3 to 5 for all possible combination.

OBSERVATION TABLE:

Truth Table of NOT Gate: Truth Table of AND Gate:

INPUT OUTPUT INPUT OUTPUT

--
Y= A A B Y= AB
A

0 1 0 0 0
1 0 0 1 0
1 0 0
1 1 1
Truth Table of OR Gate: Truth Table Of 3 Bit Binary to Gray Code
Converter

Binary Input Gray Code O/P

INPUT OUTPUT
B2 B1 B0 G2 G1 G0
A B Y= A+B 0 0 0 0 0 0
0 0 1 0 0 1
0 0 0 0 1 0 0 1 1
0 1 1 0 1 1 0 1 0
1 0 1 1 0 0 1 1 0
1 1 1 1 0 1 1 1 1
1 1 0 1 0 1
1 1 1 1 0 0

Truth Table of 3 Bit Gray to Binary Code

Converter Truth Table of 3 Bit Even/Odd Parity Generator

Gray Code Input Binary Code O/P Input Output

G2 G1 G0 B2 B1 B0 X Y Z Peven Podd
0 0 0 0 0 0 0 0 0 0 1
0 0 1 0 0 1 0 0 1 1 0
0 1 0 0 1 1 0 1 0 1 0
0 1 1 0 1 0 0 1 1 0 1
1 0 0 1 1 1 1 0 0 1 0
1 0 1 1 1 0 1 0 1 0 1
1 1 0 1 0 0 1 1 0 0 1
1 1 1 1 0 1 1 1 1 1 0

Truth Table Of Parity Checker:

Input Output
X Y Z P Pchecker
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1

PRECAUTION:

RESULT:
EXPERIMENT – 3

TITLE: Design, construction of Adder, Subtractor, Parity Generator/Checkers, Magnitude

comparator circuits.

OBJECTIVES:

(i) Design, construction and verification of Half Adder and Half Subtractor circuit.
(ii) Design, construction and verification of Full Adder and Full Subtractor circuit.
(iii) Design, construction and verification of 1-bit and 4-bit Magnitude comparator.

MATERIAL REQUIRED:

Sl. No. Equipment/ Component Name Specification Qty.

1 NOT Gate IC # 7404 1
2 AND Gate IC # 7408 1
3 OR Gate IC # 7432 1
4 XOR Gate IC # 7486 1
5 LED - 2
6 Resistor 330 Ω 2
7 Breadboard - 1
8 DC Power Supply 5 Volt 1
9 Connecting Wires - -

THEORY:

Half Adder: It adds two binary digits (A & B) results Sum output (S) and a Carry Output (C).

Truth Table:
Input Output
A B S C
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

Logic Functions: S = A B and C = AB

Logic Diagram:
 A
S
B

Half Subtractor: It subtracts two binary digits (X & Y) results Difference output (D) & a
Borrow Output (B).

Truth Table:
Input Output
X Y D B
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0

Logic Functions: D = X Y and B = X’Y

Logic Diagram:

X
D
Y

Full Adder: It adds three binary digits (A , B & Cin). Cin is the carry resulted from the
previous addition. It gives a sum Output (S) and a Carry output (Cout).

Truth Table:

Input Output
A B Cin S Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
 -- -- -- -- -- --
Logic Functions: S = A B Cin + A B Cin + A B Cin + A B Cin
-- -- -- -- --
= Cin (A B + A B) + Cin (A B + A B)

= Cin A B

-- -- --
Cout = A B Cin + A B Cin + A B Cin + A B Cin
-- --
= Cin (A B + A B) + A B

= Cin (A B) + A B

Logic Diagram:

A
B
S
Cin

Cout

Full Subtractor: It subtracts three binary digits (X , Y & Bin). Bin is the borrow input. It gives
a Difference Output (D) and a Borrow output (Bout).
Truth Table:

Input Output
X Y Bin D Bout
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

-- -- -- -- -- --
Logic Functions: D = X Y Bin + X Y Bin + X Y Bin + X Y Bin
-- -- -- -- --
= Bin (X Y + X Y ) + Bin (X Y + X Y)

= Bin X Y
 -- -- -- -- --
Bout = X Y Bin + X Y Bin + X Y Bin + X Y Bin
------------ ---
= Bin (X Y)+XY

Logic Diagram:

X
Y
D
Bin

Bout

Magnitude Comparator:

It is a combinational logic circuit that compares two input binary quantities and
generates output to indicate which one has greater magnitude.

Truth Table of 1 bit Magnitude Comparator:

Input Output
A B A>B A=B A<B
0 0 0 1 0
0 1 0 0 1
1 0 1 0 0
1 1 0 1 0

Logic Functions: A > B = A’B

A=B = A’B’ + AB = A XNOR B

A < B = AB’

Logic Diagram:
 A<B

A
A=B
B

A>B

4 Bit Magnitude Comparator:

7485 is a 4 Bit Magnitude Comparator IC. A0, A1, A2, A3 and B0, B1, B2, B3 are the
two binary inputs to be compared.

Pin Diagram of 7485 IC:

15 A3 (A>B)OUT 5
1 B3 (A=B)OUT 6
13 A2 (A<B)OUT 7
14 B2
12 A1
11 B1
10 A0
7485N
9 B0
4 (A>B)IN
3 (A=B)IN
2 (A<B)IN

PROCEDURE:

1. Verify the gates.

2. Make the connections as per the circuit diagram.
3. Switch on VCC and apply various combinations of input according to truth table.
4. Note down the output readings for half/full adder and half/full subtractor,
Sum/difference and the carry/borrow bit for different combinations of inputs verify their
truth tables.
5. Also verify the truth table of Parity Generator & Checker & Magnitude comparator
circuits.
PRECAUTION:

1. All the connections should be made properly.

2. IC should not be reversed.

RESULT : Combinational logic circuits like Half-adder, Full-adder, Half-subtractor, Full-subtractor,

Parity Generator, Parity Checker & Magnitude Comparator are constructed and truth
tables are verified.

EXPERIMENT – 4
TITLE: Decoder, MUX & DMUX
OBJECTIVES: (i) Construction and verification of BCD to 7-segment decoder using IC # 7447
(ii) Verification of 4:1 MUX, 8:1 MUX & 16:1 MUX.
(iii) Verification of 1:4 DMUX, 1:8 DMUX
MATERIAL REQUIRED:

Sl. No. Equipment/ Component Name Specification Qty.

1 NOT Gate IC # 7404 1
2 AND Gate IC # 7408 1
3 OR Gate IC # 7432 1
4 BCD to 7 Segment Decoder Driver IC IC #7447 1
5 8:1 MUX IC IC # 74151 1
6 16:1 MUX IC IC # 74150 1
7 1:8 DEMUX IC IC # 74138 1
5 7 Segment Display (Common Anode - 1
type)
5 LED - 4
6 Resistor 330 Ω 4
7 Breadboard - 1
8 DC Power Supply 5 Volt 1
9 Connecting Wires - -

THEORY:
OBJECTIVE 1:
BCD to 7 Segment Decoder Driver:

7447 is a BCD to 7 Segment decoder driver IC.

D C B A are the BCD inputs. D is MSB and A is LSB of the BCD input.
a, b, c, d, e, f, g are active low outputs of the IC.
Display test is an active low input. When Display Test = 0, all the output of the ICs becomes low. This
input is used to test all the segments of display working or not.
Blank output and Blank input are used to blank the digit zero on the display.

VCC 5V

U2
7 Com
13
A OA U3
A 1 12
B OB SEVEN_SEG_COM_K
2
B C OC
11
6 10
C D OD
9 A B CDE F G
D 3 OE
15
5 LT OF
14
4 RBI OG
BI/RBO
7447N

CIRCUIT DIAGRAM OF SEVEN SEGMENT DISPLAY USING IC 7447

OBJECTIVE-2:
Multiplexer: It selects one input among many at a time and sends it to the output line.
For an n – input MUX, m select inputs are required, where n = 2m.
4:1 MUX: 4 inputs (I0, I1, I2, I3) and 2 select inputs (S0, S1)
Block Diagram of 4:1 MUX:

Logic Function: Y = S1’ S0’ I0 + S1’ S0 I1 + S1 S0’ I2 + S1 S0 I3

Logic Circuit diagram of 4:1 MUX:
S1 S0

I0

I1

I2 Y

I3

8:1 MUX: 74151 is 8:1 multiplexer IC.

 4 I0 Y 5
3 I1
2 I2 ~W 6
1 I3
15 I4
14 I5
13 I6
12 I7
11 S0
10 S2
9 S1
7 E

74151N

16:1 MUX: 74150 is 16:1 multiplexer IC

8 E0 W 10
7 E1
6 E2
5 E3
4 E4
3 E5
2 E6
1 E7
23 E8
22 E9
21 E10
20 E11
19 E12
18 E13
17 E14
16 E15
15 A
14 B
13 C
11 D
9 G

74150N

OBJECTIVE - 3
DEMULTIPLEXER: Accepts a single input and distributes it on one among several outputs according
to selector input value.
1:4 DEMUX: 2 select inputs and 4 output lines.
Block Diagram:

Logic Function: D0 = S1’ S0’ I D1 = S1’ S0 I D2 = S1 S0’ I D3 = S1 S0 I

Logic Circuit Diagram of 1:4 DEMUX:
S1 S0

I
Y0

Y1

Y2

Y3

74138 IC can be used as 1:8 DEMUX.

PROCEDURE:
1. Connect the circuit as shown in the circuit diagram.
2. Before switching ON power supply, make sure that the connection are correct.
3. Verify the displayed digit with decimal equivalent of applied input BCD code.
4. For Multiplexer and De-multiplexer, apply the input logic state code mentioned in
observation Table in terms of +5 volts for state-1 and 0 volts for state-0.
5. Observe the output states.
6. Repeat steps from 4 to 5 for all possible combination.

OBSERVATION TABLE:
OBJECTIVE – 1: BCD to 7 Segment Decoder

Decimal
BCD Input 7 Segment Display Output Digit
Display
D C B A a b c d e f g
0 0 0 0 1 1 1 1 1 1 0
0 0 0 1 0 1 1 0 0 0 0
.
.
.
.
1 0 0 1
OBJECTIVE – 2: Truth Table of 4:1 Multiplexer Truth Table of 8:1 Multiplexer

Select Select Inputs Output

Output
Inputs
S2 S1 S0 Y
S1 S0 Y
0 0 0 I0
0 0 I0
0 0 1 I1
0 1 I1
0 1 0 I2
1 0 I2
0 1 1 I3
1 1 I3
1 0 0 I4
1 0 1 I5
1 1 0 I6
1 1 1 I7

OBJECTIVE – 3: Truth Table of 1:4 De-Multiplexer:

Data Input Select Inputs Outputs

I S1 S0 Y0 Y1 Y2 Y3
1 0 0 1 0 0 0
1 0 1 0 1 0 0
1 1 0 0 0 1 0
1 1 1 0 0 0 1

PRECAUTIONS: All the connections should be made properly.

RESULT: By 7447 and seven segment display, the display of decimal digits from 0 to 9 is done and
the truth tables of multiplexer and de-multiplexer are verified.
EXPERIMENT – 5

TITLE: Latches and Flip Flops

OBJECTIVES:
(i) Construction and Verification of a Latch circuit using NAND/NOR gates.
(ii) Construction and Verification of S-R Flip Flop using above Latch circuits.
(iii) Verification of J-K Flip Flop using IC # 7476 (Dual J-KFF)
(iv) Construction and Verification of D-Flip Flop and T-Flip Flop using J-K FF(IC #7476).
(v) Construction and Verification of Master Slave J-K Flip Flop.

MATERIAL REQUIRED:

Sl. No. Equipment/ Component Name Specification Qty.

1 NAND Gate IC # 7400 1
2 NOR Gate IC # 7402 1
3 NOT Gate IC # 7404 1
4 J K FF IC # 7476 1
5 LED - 2
6 Resistor 330 Ω 2
7 Breadboard - 1
8 DC Power Supply 5 Volt 1
9 Connecting Wires - -

THEORY:

OBJECTIVE-1:

LATCH: 1 Bit information can be locked or latched. It consists of two inverters. There is no
provision to get any desired digital information we wish to store in the latch.

Latch circuit using NAND Gates:

Q'

Latch circuit using NOR Gates:

 Q

Q'

OBJECTIVE – 2

S -R Flip Flop:

S
Q

CLK

Q'
R

Clock input determines when the state of the flip-flop to be changed.

OBJECTIVE – 3

J-K Flip Flop: 7476 is a dual negative edge triggered J-K Flip-flop IC.

Pin Diagram of 7476 IC:

Block Diagram of J-K FF:

2
~PRE
4 J Q 15
1 CLK
16 1K ~Q 14

~CLR
3
OBJECTIVE – 4

D Flip-flop using J-K (7476 IC):

2
~PRE
D 4 15
J Q
1 CLK
16 1K ~Q 14

~CLR
3

T Flip-flop using J-K (7476 IC):

2
~PRE
4 J Q 15
T
1 CLK
16 1K ~Q 14

~CLR
3

OBJECTIVE – 5:

Master Slave J-K FF:

PROCEDURE:

1. Connections are made as per the circuit diagram

2. Switch on the power supply

3. Apply different combinations of inputs and observe the outputs.

OBSERVATION TABLES:

OBJECTIVE- 1: LATCH

Q Q’
0 1
1 0

OBJECTIVE-2: Truth Table of S-R FF

CLK S R Qn+1 Qn+1’

1 0 0 Qn Qn’ No Change
1 0 1 0 1 Set
1 1 0 1 0 Reset
1 1 1 1 1 Invalid

Qn+1 = Next Output State, Qn = Present Output State

OBJECTIVE-3: Truth Table of J-K FF

PRE CLR CLK J K Qn+1 Qn+1’

0 1 Π x x 1 0 Set
1 0 Π x x 0 1 Reset
1 1 Π 0 0 Qn Qn’ No Change
1 1 Π 0 1 0 1 Set
1 1 Π 1 0 1 0 Reset
1 1 Π 1 1 Qn’ Qn Toggle

OBJECTIVE-4: Truth Table of D FF

CLK D Q Q’
Π 0 0 1
Π 1 1 0

Truth Table of T FF

CLK T Qn+1 Qn+1’

 Π 0 Qn Qn’ No change
Π 1 Qn’ Qn Toggle

OBJECTIVE-5: Truth Table of Master Slave J-K FF

CLK J K Qn+1 Qn+1’

Π 0 0 Qn Qn’ No Change
Π 0 1 0 1 Set
Π 1 0 1 0 Reset
Π 1 1 Qn’ Qn Toggle

PRECAUTIONS: All the connections should be made properly.

RESULT: Latch using NAND and NOR gates, and different flip-flops are constructed and verified their
truth tables.
EXPERIMENT – 6

TITLE: Shift Registers

OBJECTIVES: (i) Verification of D-FF using IC # 7474 (Dual D- FF).

(ii) Construction and verification of a 2-bit Shift Right Register using IC # 7474.
(iii) Construction and verification of a 2-bit Shift Left Register using IC # 7474.
(iv) Verification of SISO, SIPO, PISO & PIPO Shift Registers.

MATERIAL REQUIRED:

Sl. No. Equipment/ Component Name Specification Qty.

1 D Flip flop IC # 7474 1
2 AND Gate IC # 7408 1
3 NOT Gate IC # 7404 1
4 OR Gate IC # 7432 1
5 LED - 2
6 Resistor 330 Ω 2
7 Breadboard - 1
8 DC Power Supply 5 Volt 1
9 Function Generator (Clk Pulse) 3 MHz 1
10 Connecting Wires Single Strand -

THEORY: OBJECTIVE-1: D Flip-flop:

7474 is D Flip-flop IC. It consists of two positive triggered D Flip-flops.

Pin Diagram of 7474 IC:

Block Diagram of D Flip-flop:

 4
~PRE1
2 D1 Q1 5

3 CLK1 ~Q1 6

~CLR1
1

OBJECTIVE-2: 2 Bit Shift Right Register using D Flip-flops:

4 Q1 4
Q2
~PRE1 ~PRE2
Data Input Data Output
2 D1 Q1 5 2 D2 Q2 5

3 CLK1 ~Q1 6 3 CLK2 ~Q2 6

~CLR1 ~CLR2
1 1

OBJECTIVE-3: 2 Bit Shift left Register using D Flip-flops:

Data
Output
4 4
Data
~PRE1 Q1 Input ~PRE2
Q2
2 D1 Q1 5 2 D2 Q2 5

3 CLK1 ~Q1 6 3 CLK2 ~Q2 6

~CLR1 ~CLR2
1 1

OBJECTIVE- 4:

Serial In Serial out (SISO) Shift Register:

4 4
Q2
~PRE1 ~PRE2
Serial Data Input Serial Data Output
2 D1 Q1 5 2 D2 Q2 5

3 CLK1 ~Q1 6 3 CLK2 ~Q2 6

~CLR1 ~CLR2
1 1

Serial in Parallel out (SIPO) Shift Register:

 Parallel Output Data

4 Q1 4
Q2
~PRE1 ~PRE2
Serial Data Input
2 D1 Q1 5 2 D2 Q2 5

3 CLK1 ~Q1 6 3 CLK2 ~Q2 6

~CLR1 ~CLR2
1 1

Parallel In Serial Out (PISO) Shift Register:

Shift/Load = 0, input data D1 & D2 load into the Flip-flop.

Shift/Load = 1, data shifted from one flip-flop to other.

Shift/Load D2

4 4

D1 ~PRE1 ~PRE2
Q2 Serial Data Output
2 D1 Q1 5 2 D2 Q2 5

3 CLK1 ~Q1 6 3 CLK2 ~Q2 6

~CLR1 ~CLR2
1 1

Parallel in Parallel out (PIPO) Shift Register:

Parallel Input Data

D1 D2
4 4
~PRE1 ~PRE2
2 D1 Q1 5 2 D2 Q2 5

3 CLK1 ~Q1 6 3 CLK2 ~Q2 6

~CLR1 ~CLR2
1 1

Q1 Q2
Parallel Output Data

PROCEDURE:

Serial In Serial Out (SISO):

1. Connections are made as per circuit diagram.

 2. Load the shift register with 2 bits of data one by one serially.
3. At the end of 2nd clock pulse the first data ‘d1’ appears at Q2.
4. Apply another clock pulse; the second data ‘d2’ appears at Q2.
5. Thus the data applied serially at the input D1 comes out serially at Q2.

Serial In Parallel Out (SIPO):

1. Connections are made as per circuit diagram.

2. Apply the data at serial data i/p.
3. Apply one clock pulse at clock (Right Shift) observe this data at Q1.
4. Apply the next data at serial i/p.
5. Apply one clock pulse at clock, observe that the data on Q1 will shift to
Q2 and the new data applied will appear at Q1.

Parallel In Serial Out (PISO):

1. Connections are made as per circuit diagram.

2. Apply the desired 2 bit data at D1 and D2.
3. Keeping the control input Shift/Load = 0 apply one clock pulse. The data
applied at D1 and D2 will appear at Q1 and Q2 respectively.
4. Now keep the control input Shift/Load = 1, apply clock pulses one by
one and observe the Data coming out serially at Q2.

Parallel In Parallel Out (PIPO):

1. Connections are made as per circuit diagram.

2. Apply the 2 bit data at D1 and D2.
3. Apply one clock pulse at clock input, the 2 bit data at D1 and D2 appears at Q1 and Q2
respectively.

OBSERVATION TABLE:

OBJECTIVE-1: Truth table of D Flip-flop:

PRE CLR CLK D Q Q’

1 1 Π 0 0 1
1 1 Π 1 1 0
OBJECTIVE-2: For 2 Bit Right Shift Register

CLK Data Q1 Q2
1 0 0

1 1 0
Π

Π 1
For 2 Bit Left Shift Register

CLK Q1 Q2 Data

0 0 1

Π 0 1 1

Π 1 1

OBJECTIVE-3: Serial in Serial out Shift Register

Serial Serial Data

CLK Data I/P Q1 O/P
(D1) (Q2)
1 0 0
Π 1 1 0
Π 1 1 1

Serial in Parallel out Shift Register

Serial Parallel Data

CLK
Data I/P o/p
D1 Q1 Q2
1 0 0
Π 1 1 0
Π 1 1 1

Parallel in Serial out Shift Register

Parallel Data Serial Data

Input Output
Shift/Load CLK D1 D2 Q1 Q2
0 1 1 0 0
 0 Π 1 1 1 1
1 Π 0 0 0 1

Parallel in Parallel out shift Register

Parallel Data Parallel Data

Input Output
CLK D1 D2 Q1 Q2
1 1 0 0
Π 1 1 1 1

PRECAUTION: All the connections should be made properly.

RESULT:
EXPERIMENT – 7

TITLE: Synchronous & Asynchronous Counters

OBJECTIVES:
(i) Construction and verification of 2-bit Ripple counter using J-K FF.
(ii) Construction and verification of Mod-3 up and Mod-3 down synchronous counter.
(iii) Construction and verification of 2-bit Ring counter using J-K FF.
(iv) Construction and verification of 2-bit twisted Ring (Johnson) counter using J-K FF.

MATERIAL REQUIRED:

Sl. No. Equipment/ Component Name Specification Qty.

1 J K FF IC # 7476 1
2 LED - 2
3 Resistor 330 Ω 2
4 Breadboard - 1
5 DC Power Supply 5 Volt 1
6 Function Generator (Clock Pulse) 3 MHz 1
7 Connecting Wires Single Strand -

THEORY

OBJECTIVE-1: Ripple Counter:

Ripple counter is the simplest type of counter in which flip-flops are not clocked
simultaneously. The output of previous FF becomes the clock input for next FF. The inputs J and K of
the FF are connected to logic 1.

2 Bit Ripple Counter Using J-K Flip-flop:

2 Flip-flops are required.

Logic Circuit Diagram:

 Q0 Q1

1 1 1 1
~PRE ~PRE

J0 Q0 J1 Q1
CLK CLK
K0 ~Q0 K1 ~Q1
CLK
~CLR ~CLR

1
1

Counting Table:

CLK Q1 Q0 Counting State

0 0 0
Π 0 1 1
Π 1 0 2
Π 1 1 3

OBJECTIVE-2: Mod 3 UP Synchronous Counter:

Synchronous counters are the counters which are clocked such that each FF in the counter is
triggered at the same time.

For Mod 3 Counter, 2 FFs are required.

Design

Step -1 : State Transtion Diagram

00

10 01

Step-2:

Present Counting Next Required Flip-Flop

State Counting State
Inputs
Q1 Q0 Q1 Q0 J1 K1 J0 K0
0 0 0 1 0 X 1 X
0 1 1 0 1 X X 1
1 0 0 0 X 1 0 X
Step-3: Using K-map, Find the desired value for J0, K0, J1 & K1

For J1 For K1
 Q0 Q0
Q1 0 1 Q1 0 1
0 0 1 0 X X
1 X X J1 = Q0 1 1 X K1 = 1

For J0 For K0

Q0 Q0
Q1 0 1 Q1 0 1
0 1 X 0 X 1
1 0 X J0 = Q1’ 1 X X K0 = 1

LOGIC CIRCUIT DIAGRAM (3 Bit Up Synchronous Counter):

Q0 Q1

1 1
~PRE ~PRE

J0 Q0 J1 Q1
CLK CLK
K0 ~Q0 K1 ~Q1
CLK 1 1
~CLR ~CLR

1
1

Similar way we can design the circuit for Mod 3 down synchronous counter

Logic Circuit Diagram (3 Bit down synchronous counter):

Q0 Q1

1 1
~PRE ~PRE

J0 Q0 J1 Q1
CLK CLK
K0 ~Q0 K1 ~Q1
CLK 1 1
~CLR ~CLR

1
1

OBJECTIVE-3: 2 Bit Ring Counter

Ring Counter is a SISO shift register with the output of last flip-flop is connected back to
input of the first flip-flop.

Logic Circuit Diagram:

 Q0 Q1

1 1
~PRE ~PRE

J0 Q0 J1 Q1
CLK CLK
K0 ~Q0 K1 ~Q1
CLK
~CLR ~CLR

1
1

Counting Table:

PRE1 CLR1 CLK Q1 Q0

Initial 0 1 X 1 0
Setting
1 1 Π 0 1
1 1 Π 1 0
1 1 Π 0 1

OBJECTIVE-4: 2 Bit Twisted Ring (Johnson) Counter

In this, output of each flip-flop stage is connected to the input of next stage but Q’ output of
last stage is connected to input of first stage.

Logic circuit diagram:

Q0 Q1

1 1
~PRE ~PRE

J0 Q0 J1 Q1
CLK CLK
K0 ~Q0 K1 ~Q1
CLK
~CLR ~CLR

1
1

Counting Table:

CLK Q1 Q0
0 0
Π 0 1
Π 1 1
Π 1 0
PROCEDURE: Π 0 0

1. Connections are made as per the logic circuit diagram.

2. Switch on the power supply.

 3. Apply clock pulses and note the outputs after each clock pulse of counters.

4. Verify the counting table.

PRECAUTIONS:

1. All the connections should be made properly.

2. IC should not be reversed.

RESULT:
EXPERIMENT -8

TITLE: TIMER 555

OBJECTIVES: 1. Construction of Astable MV using Timer-555 and measuring the following
parameters on CRO and compare them with their theoretical values:
a) Charging time TON = 0.693 (RA + RB)C1 (Theoretical)
b) Discharging time TOFF = 0.693 RB C1 (Theoretical)
c) Total time period and Frequency, T = (TON+TOFF), f = 1/T
d) % Duty cycle = (TON / T )x 100
2. Construction of Monostable MV using Timer-555 and measuring the time period
and frequency of waveform on CRO and compare them with their theoretical
values.
a) Time period TP = 1.1 RC (theoretical)
b) Frequency f = 1 / TP

MATERIAL REQUIRED:

Sl. No. Equipment/ Component Name Specification Qty.

1 555 Timer 555 1
2 Resistor 2
3 Capacitor 0.01µF 2
4 Breadboard - 1
5 Cathode Ray Oscilloscope 30 MHz 1
6 DC Power Supply 5 Volt 1
7 Connecting Wires Single Strand -

THEORY:
OBJECTIVE -1
Pin Diagram of 555 Timer:

GND + Vcc

Discharge
Trigger
IC 555
Threshold
output
Control voltage
Reset

ASTABLE MULTIVIBRATOR
An astable multivibrator is a multivibrator with no stable state. It has two states and both of
them are quasi-stable. The moment it is connected to the supply, it keeps on switching back and
forth between its quasi-stable states.
Astable Multivibrator Using 555 Timer:
Circuit Diagram:

Vcc = 5V/12V

RA
33kohm
8

4 VCC
RB RST
7 3
Vout
30-60Kohm
6 DIS OUT

2 THR 555
TRI
5 TIMER
CON
GND
1
0.01uF
0.01uF

Fig. ASTABLE MULTIVIBRATOR USING TIMER 555

The capacitor C1 charges through the resistance RA and RB and discharges through the resistance RB
only. The capacitor charges and discharges between 1/3 Vcc to 2/3 Vcc.
Charging time of the capacitor is given by = TON = 0.693 (RA+RB) C1
Discharging time of the capacitor = TOFF = 0.693 RB C1
Time Period = T = TON +TOFF = 0.693 (RA + 2 RB) C1
Frequency of Oscillation = f = 1 / T.
% of Duty Cycle = (TON/ T) x 100.

PROCEDURE:

1. Connect the circuit diagram as shown in the circuit diagram.

2. Before switch ON the power supply, make sure that the connections are correct.
3. Connect the C.R.O. probe at terminals 3 and ground.
4. Observe the output waveform for different RB (Take RB = 30 K ohm and 60 K ohm).
5. Tabulate the reading of TON, TOFF and T in Observation Table.
6. Calculate % duty cycle.
OBSERVATION TABLE:

At Vcc =5 V and RA = 33 KΩ.

Sl No RB Theoretical Value Measured Time Peroid Time Period % Duty

Value from Cycle
(K) CRO (Theoritical (Measured
Value) = (TON/ T)
Value) x 100
TON (ms) TOFF TON TOFF
T = TON +TOFF
(ms) (ms) (ms) T = TON +TOFF

1 30

2 60

OBJECTIVE – 2

MONOSTABLE MULTIVIBRATOR:

It has one stable state. When triggered, it changes from its stable state to quasi-stable state
and returns back to its stable state.

MONOSTABLE MULTIVIBRATOR USING 555 TIMER.

Circuit Diagram:

+Vcc

8
50%
4 VCC
RST
7 3
6 DIS OUT Vout
2 THR

C TRI
5
8200pF
CON
GND
Trigger 1
C2
2200pF

Fig. MONOSTABLE MULTIVIBRATOR USING TIMER 555

When Timer 555 is connected in monostable mode, trigger input is given through pin 2.

Time Period of the pulse =TP = 1.1 RC, frequency = f = 1/ TP

PROCEDURE:

1. Connect the circuit diagram as shown in the circuit diagram.

2. Before switch ON Power Supply, make sure that the connections are correct.
3. Connect the C.R.O. probe at terminals 3 and ground.
4. Observe the output waveforms for different values of R.
5. Tabulate the reading of Pulse Width as TP in observation table.

OBSERVATION TABLE:

Sl R Theoretical Pulse Measured Pulse Width

Width
No. (K) From CRO
TP=1.1 x Rx C

1 30

2 40

3 50

PRECAUTION:

RESULT:
EXPERIMENT – 9

TITLE: Digital to Analog Converter (DAC) and Analog to Digital Converter (ADC).

OBJECTIVES: Construction & Verification of D/A converters using following methods.

a) Weighted Resistor type
b) R-2R ladder network type
Construction & Verification of A/D Converter using following methods.
a) Counter type
b) Successive Approximation type.

THEORY:

4 Bit Weighted Resistor Type DAC:

Circuit Diagram:

Op-amp is connected in the inverting mode.

4 Binary inputs (B0, B1, B2 and B3) results, 24 = 16 analog output values.

Working:

Voltage across 8R resistor due to B0 input is Vref x B0.

Vout due to B0 input will be V1 = - (Vref/16).B0

Voltage across 4R resistor due to B1 input is Vref x B1.

Vout due to B1 input will be V2 = - (Vref/8).B1

Voltage across 2R resistor due to B2 input is Vref x B1.

Vout due to B2 input will be V3 = - (Vref/4).B2.

Voltage across R resistor due to B3 input is Vref x B3.

Vout due to B3 input will be V2 = - (Vref/2).B3.

According to superposition principle,

o/p voltage op-amp (Vout) due to all four inputs (B0, B1, B2 and B3) is

= V1 +V2+ V3 + V4
= -Vref { (B0/16) + (B1/8) + (B2/4) + (B3/2)}

R – 2R Ladder type DAC

Circuit Diagram: