A B C D E

ZZZ1 ZZZ3 ZZZ4 ZZZ5 ZZZ6 PJP1 PJP1

PCB LA-4241P LS-4243P LS-4244P LS-4249P 14W_DCIN 15W_DCIN

14WDAZ@ 14WDA@ 14WDA@ 14WDA@ 14WDA@
14W_45@ 15W_45@

1 1

12/21 Add PJP1 for DCIN Cable on 45 Level

ZZZ2 ZZZ8 ZZZ9 ZZZ10 ZZZ11 ZZZ12 ZZZ13
One for 14W DCIN , PN: DC301001Y00
Another for 15W DCIN , PN: DC301001V00

PCB LA-4241P LS-4242P LS-4243P LS-4244P LS-4245P LS-4246P

15WDAZ@ 15WDA@ 15WDA@ 15WDA@ 15WDA@ 15WDA@ 15WDA@

05/20 Add DAZ PCB Panel P/N

Compal Confidential
2
JHXXX Schematics Document 2

Intel Penryn Processor with Cantiga + DDRII + ICH9M

(With nVIDIA MXM/B)

2008-06-03

3
REV: 1.0 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/18 Deciphered Date 2008/8/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JHXXX M/B LA-4241P Schematic
Date: Tuesday, June 03, 2008 Sheet 1 of 49
A B C D E
 A B C D E

Compal Confidential
Thermal Sensor Clock Generator
Model Name : JHXXX Fan Control Intel Penryn Processor
page 4 ADT7421 ICS9LPRS387
page 4 page 16
File Name : LA-4241P uPGA-478 Package
1
page 4,5,6 1

FSB
H_A#(3..35) 667/800MHz H_D#(0..63)

LVDS
LCD Conn.
page 18 Memory BUS(DDRII) 200pin DDRII-SO-DIMM X2
HDMI Intel Cantiga
Dual Channel BANK 0, 1, 2, 3 page 14,15
page 25
CRT
page 19 1.8V DDRII 533/667
uFCBGA-1329
PCI-Express
page 7,8,9,10,11,12,13

MXM II VGA/B DMI

X4 mode USB conn x3 Bluetooth CMOS Camera Finger Print
page 17 TO I/O/Bpage 35
Conn page 34 page 40
Conn page 40
2 2
PCI-Express USB
Intel ICH9-M 3.3V 48MHz

3.3V 24.576MHz/48Mhz HD Audio

BGA-676
S-ATA
page 20,21,22,23
New Card MINI Card x3 LAN(GbE) port 0 GMCH HDA MDC 1.5 HDA Codec
Socket WLAN,
RTL8111C/8102E Card Reader page 8
Conn
page 40
ALC268
page 36
page 31 TV-Tuner
JMB385
Robson page 30 page 28 page 26
S-ATA HDD S-ATA ODD
Conn. page 24 Conn. page 24
3 in 1 Audio AMP
RJ45 socket page 37
3
page 29 page 26 LPC BUS 3

RTC CKT.
page 21 ENE KB926
Function/B page 32

Power On/Off CKT. Power USB/B

page 33
page 35
Touch Pad Int.KBD
page 34 page 33
USB I/O Conn.
DC/DC Interface CKT. CIR BIOS SCREW
page 41 page 39
LID SW page 34

Power Circuit DC/DC Debug port

4
page 35 4
page 41,42,43,45
46,47,48
TPM
CHARGER LED Security Classification Compal Secret Data Compal Electronics, Inc.
page 44 page 40
Issued Date 2007/08/18 Deciphered Date 2008/8/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagrams
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JHXXX M/B LA-4241P Schematic
Date: Friday, April 11, 2008 Sheet 2 of 49
A B C D E
 A B C D E

Voltage Rails
Power Plane Description S1 S3 S5

VIN Adapter power supply (19V) N/A N/A N/A

B+ AC or battery power rail for power circuit. N/A N/A N/A
1 1
+CPU_CORE Core voltage for CPU ON OFF OFF
+0.9VS ( Actual +0.9V ) 0.9V switched power rail for DDR terminator ON ON OFF
+1.05VS 1.05V switched power rail ON OFF OFF
+1.5VS 1.5V switched power rail ON OFF OFF
+1.8V 1.8V power rail for DDR ON ON OFF
+1.8VS 1.8V switched power rail ON OFF OFF
+3VALW 3.3V always on power rail ON ON ON*
+3VS 3.3V switched power rail ON OFF OFF
EC SM Bus1 address EC SM Bus2 address
+5VALW 5V always on power rail ON ON ON*
+5VS 5V switched power rail ON OFF OFF Device Address Device Address
+VSB VSB always on power rail ON ON ON* Smart Battery 0001 011X b ADI ADM1032 1001 100X b
+RTCVCC RTC power ON ON ON EEPROM(24C16/02) 1010 000X b NVIDIA NB8X

ICH9M SM Bus address

2 2

Device Address
SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Clock Generator 1101 001Xb
(ICS9LPRS325AKLFT_MLF72)
Full ON HIGH HIGH HIGH HIGH ON ON ON ON
DDR DIMM0 1010 000Xb
S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW DDR DIMM1 1010 010Xb
R472 R472 R472 R472 R472
S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF

S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF

SKU ID Table 4.7K_0402_5% 10K_0402_5% 18K_0402_5% 27K_0402_5% 39K_0402_5%
S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF H_14_C@ H_14_MP@ H_15_B@ H_15_C@ H_15_MP@
Vcc 3.3V +/- 5%
Rb 47K +/- 5% R472 R472 R472 R472 R472

Rb~ R470
PROJECT ID Table Ra~ R472 56K_0402_5% 82K_0402_5% 120K_0402_5% 220K_0402_5% 470K_0402_5%
L_14_B@ L_14_C@ L_14_MP@ L_15_B@ L_15_C@

ID1 ID0 Board ID Rb Ra V AD_BID min V AD_BID typ V AD_BID max Ra BOM Structure
3 3

JHT00 ( 00@ ) R361 R357 1 NA 4.7K +/- 5% 0 V 0 V 0 V H_14_B@

JHT01 ( 01@ ) R361 R355 2 47K(RB@) 4.7K +/- 5% 0.274 V 0.300 V 0.328 V H_14_C@
JHL90 ( 10@ ) R360 R357 3 47K(RB@) 10K +/- 5% 0.553V 0.578 V 0.628 V H_14_MP@
JHL91 ( 11@ ) R360 R355 4 47K(RB@) 18K +/- 5% 0.849V 0.913V 0.981 V H_15_B@
5 47K(RB@) 27K +/- 5% 1.129 V 1.204 V 1.282 V H_15_C@
6 47K(RB@) 39K +/- 5% 1.415 V 1.496 V 1.579 V H_15_MP@
7 47K(RB@) 56K +/- 5% 1.712 V 1.794 V 1.876 V L_14_B@
MIC ID Table 8 47K(RB@) 82K +/- 5% 2.020V 2.097 V 2.173 V L_14_C@
9 47K(RB@) 120K +/- 5% 2.303 V 2.371 V 2.437 V L_14_MP@
R Structure
10 47K(RB@) 220K +/- 5% 2.670 V 2.719 V 2.765 V L_15_B@
R585 Single MIC SINGLE@
11 47K(RB@) 470K +/- 5% 2.972 V 3.000 V 3.026 V L_15_C@
R583 Array MIC DUAL@
12 47K(RB@) NA 3.135 V 3.300 V 3.465 V NA for L_15_MP

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/18 Deciphered Date 2008/8/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JHXXX M/B LA-4241P Schematic
Date: Tuesday, June 03, 2008 Sheet 3 of 49
A B C D E
 5 4 3 2 1

+1.05VS
EMI Recommend
Which to follow?
H_IERR# R12 56_0402_5%
Checklist CRB 1 2
D D
ITP_TMS R13 54.9_0402_1%
TCK 55_5% 54.9_1% 1 2
H_A#[3..35] ITP_TDI R14 54.9_0402_1%
<7> H_A#[3..35] TDI 55_5% 54.9_1% 1 2
H_REQ#[0..4] H_PROCHOT# R15 56_0402_5%
<7> H_REQ#[0..4] TMS 55_1% 54.9_1% 1 2
H_RS#[0..2] ITP_TCK R16 54.9_0402_1%
<7> H_RS#[0..2] TRST# 55_5% 54.9_1% 1 2

JCPU1A ITP_TRST# R17 54.9_0402_1%

H_A#3 J4 H1
PREQ# x 54.9_1% 1 2
A[3]# ADS# H_ADS# <7>

ADDR GROUP 0
H_A#4 L5 E2
H_A#5 A[4]# BNR# H_BNR# <7>
L4 A[5]# BPRI# G5 H_BPRI# <7>
H_A#6 K5
H_A#7 A[6]#
M3 A[7]# DEFER# H5 H_DEFER# <7>
H_A#8 N2 F21
H_A#9 A[8]# DRDY# H_DRDY# <7>
J1 E1
H_A#10 N3
A[9]# DBSY# H_DBSY# <7> 1/29 change to EMC1402 pn
H_A#11
H_A#12
P5
P2
A[10]#
A[11]# BR0# F1 H_BR0# <7> EMC1402 +3VS
U1
A[12]#

CONTROL
H_A#13 L2 D20 H_IERR# C1
H_A#14 A[13]# IERR# 0.1U_0402_16V4Z
P4 A[14]# INIT# B3 H_INIT# <21>
H_A#15 P1 1 2
H_A#16 A[15]#
R1 A[16]# LOCK# H4 H_LOCK# <7>
M1 LM95245CIMMX NOPB MSOP 8P
<7> H_ADSTB#0 ADSTB[0]# H_RESET# NS@
RESET# C1 H_RESET# <7>
H_REQ#0 K3 F3 H_RS#0
H_REQ#1 REQ[0]# RS[0]# H_RS#1 U1
H2 REQ[1]# RS[1]# F4 1
H_REQ#2 K2 G3 H_RS#2 C2 1 8
REQ[2]# RS[2]# VDD SCLK EC_SMB_CK2 <17,32>
C H_REQ#3 J3 G2 C
REQ[3]# TRDY# H_TRDY# <7>
H_REQ#4 L1 2200P_0402_50V7K THERMDA 2 7
REQ[4]# 2 D+ SDATA EC_SMB_DA2 <17,32>
HIT# G6 H_HIT# <7>
H_A#17 Y2 E4 THERMDC 3 6 2 1 +3VS
H_A#18 A[17]# HITM# H_HITM# <7> R19 R20 D- ALERT/THERM2 R706 10K_0402_5%
U5 A[18]#
H_A#19 R3 AD4 +3VS 1 2 4 5
A[19]# BPM[0]# THERM GND
ADDR GROUP 1

H_A#20 W6 AD3 R18 10K_0402_5%

H_A#21 A[20]# BPM[1]#
U4 AD1
XDP/ITP SIGNALS

H_A#22 A[21]# BPM[2]# ADT7421ARMZ-REEL_MSOP8

Y5 A[22]# BPM[3]# AC4
H_A#23 U1 AC2 EMI Recommend Address:100_1100 SMSC@
H_A#24 A[23]# PRDY# 0_0402_5% 0_0402_5%
R4 A[24]# PREQ# AC1
H_A#25 T5 AC5 ITP_TCK NS@ NS@
H_A#26 A[25]# TCK ITP_TDI
T3 A[26]# TDI AA6
H_A#27 W2 AB3
H_A#28 A[27]# TDO ITP_TMS
W5 A[28]# TMS AB5
H_A#29 Y4 AB6 ITP_TRST#
H_A#30 A[29]# TRST# ITP_DBRESET#
U2 C20
H_A#31
H_A#32
V4
W3
A[30]#
A[31]#
DBR# ITP_DBRESET# <22>
FAN1 Conn
A[32]# H_PROCHOT# <48>
H_A#33 AA4 THERMAL
H_A#34 A[33]#
AB2 A[34]#
H_A#35 AA3 D21 H_PROCHOT#
A[35]# PROCHOT# THERMDA_R R19 SMSC@ 100_0402_5% THERMDA
<7> H_ADSTB#1 V1 ADSTB[1]# THERMDA A24
B25 THERMDC_R R20 SMSC@ 100_0402_5% THERMDC
THERMDC +5VS
<21> H_A20M# A6 A20M# +5VS
ICH

A5 C7 1 2 C3 10U_0805_10V4Z
<21> H_FERR# FERR# THERMTRIP# H_THERMTRIP# <8,21>
C4 R705 0_0402_5% 1 2
<21> H_IGNNE# IGNNE#

1
<21> H_STPCLK# D5 STPCLK#
B U2 D1 B
<21> H_INTR C6 LINT0 H CLK
<21> H_NMI B4 LINT1 BCLK[0] A22 CLK_CPU_BCLK <16> 1 VEN GND 8 BAS16_SOT23-3
<21> H_SMI# A3 SMI# BCLK[1] A21 CLK_CPU_BCLK# <16> 2 VIN GND 7
+VCC_FAN1 3 6

2
VO GND
M4 RSVD[01] <32> EN_FAN1 1 R815 2 EN_FAN1_R 4 VSET GND 5 D2
N5 RSVD[02] 1 2

1
T2 330_0402_5% C769 G990P11U_SOP8
RSVD[03] BAS16_SOT23-3
V3 RSVD[04]
B2 Layout Note: 0.047U_0402_16V7K
RESERVED

2
RSVD[05] C4 10U_0805_10V4Z
C3 RSVD[06]
D2 THERMDA&THERMDC Trace / Space = 10 / 10 mil 1 2
RSVD[07]
D22 RSVD[08] THERMDA_R&THERMDC_R Trace / Space = 10 / 10 mil +3VS C5
D3 RSVD[09]
F6 1000P_0402_50V7K
RSVD[10]
1 2

1
R21
Merom Ball-out Rev 1a 10K_0402_5%
CONN@ 40mil JP7

2
+VCC_FAN1 1 1
<32> FAN_SPEED1 2 2
3 3
1
C6 4
1000P_0402_50V7K GND
5 GND
2
ACES_85205-03001
A A

CONN@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/18 Deciphered Date 2008/08/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Penryn (1/3)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JHXXX M/B LA-4241P Schematic
Date: Tuesday, June 03, 2008 Sheet 4 of 49
5 4 3 2 1
 5 4 3 2 1

H_D#[0..63] JCPU1C
H_D#[0..63] <7>
+CPU_CORE A7 VCC[001] VCC[068] AB20 +CPU_CORE
JCPU1B A9 AB7
H_D#0 H_D#32 VCC[002] VCC[069]
E22 D[0]# D[32]# Y22 A10 VCC[003] VCC[070] AC7
D H_D#1 F24 AB24 H_D#33 A12 AC9 D
H_D#2 D[1]# D[33]# H_D#34 VCC[004] VCC[071]
E26 D[2]# D[34]# V24 A13 VCC[005] VCC[072] AC12
H_D#3 G22 V26 H_D#35 A15 AC13
D[3]# D[35]# VCC[006] VCC[073]

DATA GRP 0
H_D#4 F23 V23 H_D#36 A17 AC15
H_D#5 D[4]# D[36]# H_D#37 VCC[007] VCC[074]
G25 D[5]# D[37]# T22 A18 VCC[008] VCC[075] AC17
H_D#6 E25 U25 H_D#38 A20 AC18
H_D#7 D[6]# D[38]# H_D#39 VCC[009] VCC[076]
E23 D[7]# D[39]# U23 B7 VCC[010] VCC[077] AD7
H_D#8 K24 Y25 H_D#40 B9 AD9

DATA GRP 2
H_D#9 D[8]# D[40]# H_D#41 VCC[011] VCC[078]
G24 D[9]# D[41]# W22 B10 VCC[012] VCC[079] AD10
H_D#10 J24 Y23 H_D#42 B12 AD12
H_D#11 D[10]# D[42]# H_D#43 VCC[013] VCC[080]
J23 D[11]# D[43]# W24 B14 VCC[014] VCC[081] AD14
H_D#12 H22 W25 H_D#44 B15 AD15
H_D#13 D[12]# D[44]# H_D#45 VCC[015] VCC[082]
F26 D[13]# D[45]# AA23 B17 VCC[016] VCC[083] AD17
H_D#14 K22 AA24 H_D#46 B18 AD18
H_D#15 D[14]# D[46]# H_D#47 VCC[017] VCC[084]
H23 D[15]# D[47]# AB25 B20 VCC[018] VCC[085] AE9
<7> H_DSTBN#0 J26 DSTBN[0]# DSTBN[2]# Y26 H_DSTBN#2 <7> C9 VCC[019] VCC[086] AE10
<7> H_DSTBP#0 H26 DSTBP[0]# DSTBP[2]# AA26 H_DSTBP#2 <7> C10 VCC[020] VCC[087] AE12
<7> H_DINV#0 H25 DINV[0]# DINV[2]# U22 H_DINV#2 <7> C12 VCC[021] VCC[088] AE13
C13 VCC[022] VCC[089] AE15
C15 VCC[023] VCC[090] AE17
H_D#16 N22 AE24 H_D#48 C17 AE18
H_D#17 D[16]# D[48]# H_D#49 VCC[024] VCC[091]
K25 D[17]# D[49]# AD24 C18 VCC[025] VCC[092] AE20
H_D#18 P26 AA21 H_D#50 D9 AF9
H_D#19 D[18]# D[50]# H_D#51 VCC[026] VCC[093]
R23 D[19]# D[51]# AB22 D10 VCC[027] VCC[094] AF10 330u
H_D#20 L23 AB21 H_D#52 D12 AF12
D[20]# D[52]# VCC[028] VCC[095] ESR 9m ohm

DATA GRP 1
H_D#21 M24 AC26 H_D#53 D14 AF14
H_D#22 D[21]# D[53]# H_D#54 VCC[029] VCC[096] Package(L*W*H)7.3*4.3*1.8
L22 D[22]# D[54]# AD20 D15 VCC[030] VCC[097] AF15
H_D#23 M23 AE22 H_D#55 D17 AF17 Rating 2.5V
H_D#24 D[23]# D[55]# H_D#56 VCC[031] VCC[098]
P25 D[24]# D[56]# AF23 D18 VCC[032] VCC[099] AF18
C H_D#25 P23 AC25 H_D#57 E7 AF20 C
+1.05VS H_D#26 D[25]# D[57]# H_D#58 VCC[033] VCC[100]
P22 AE21 E9

DATA GRP 3
H_D#27 D[26]# D[58]# H_D#59 VCC[034]
T24 D[27]# D[59]# AD21 E10 VCC[035] VCCP[01] G21 +1.05VS
H_D#28 R24 AC22 H_D#60 E12 V6
H_D#29 D[28]# D[60]# H_D#61 VCC[036] VCCP[02]
L25 D[29]# D[61]# AD23 E13 VCC[037] VCCP[03] J6 1
2

H_D#30 T25 AF22 H_D#62 E15 K6

R22 H_D#31 D[30]# D[62]# H_D#63 VCC[038] VCCP[04] + C7
N25 D[31]# D[63]# AC23 E17 VCC[039] VCCP[05] M6
1K_0402_1% <7> H_DSTBN#1 L26 DSTBN[1]# DSTBN[3]# AE25 H_DSTBN#3 <7> E18 VCC[040] VCCP[06] J21
<7> H_DSTBP#1 M26 AF24 E20 K21 330U_D2E_2.5VM_R9
DSTBP[1]# DSTBP[3]# H_DSTBP#3 <7> VCC[041] VCCP[07] 2
<7> H_DINV#1 N24 AC20 H_DINV#3 <7> F7 M21
1

DINV[1]# DINV[3]# VCC[042] VCCP[08]

Trace Close CPU < 0.5' GTL_REF0 COMP0 R23 27.4_0402_1%
F9 VCC[043] VCCP[09] N21
AD26 GTLREF COMP[0] R26 1 2 F10 VCC[044] VCCP[10] N6
R24 2 1 @ 1K_0402_5% TEST1 C23 MISC U26 COMP1 R25 1 2 54.9_0402_1% F12 R21
R26 TEST1 COMP[1] VCC[045] VCCP[11]
2 1 @ 1K_0402_5% TEST2 D25 TEST2 COMP[2] AA1 COMP2 R27 1 2 27.4_0402_1% F14 VCC[046] VCCP[12] R6
2

Width=4 mil , T1 PAD @ TEST3 C24 Y1 COMP3 R29 1 2 54.9_0402_1% F15 T21
R28 C8 TEST4 TEST3 COMP[3] VCC[047] VCCP[13]
1 2 AF26 F17 T6
Spacing: 15mil 2K_0402_1% @
T2 PAD @ TEST5 AF1
TEST4
E5 H_DPRSTP# <8,21,48> F18
VCC[048] VCCP[14]
V21
0.1U_0402_16V4Z @ TEST6 TEST5 DPRSTP# VCC[049] VCCP[15]
(55Ohm) T3 PAD A26 TEST6 DPSLP# B5 H_DPSLP# <21> F20 VCC[050] VCCP[16] W21
D24 H_DPWR# <7> AA7 20mils
1

DPWR# H_PWRGOOD VCC[051]

<16> CPU_BSEL0 B22 BSEL[0] PWRGOOD D6 H_PWRGOOD <21> AA9 VCC[052] VCCA[01] B26 +1.5VS
B23 D7 H_CPUSLP# AA10 C26
<16> CPU_BSEL1 BSEL[1] SLP# H_CPUSLP# <7> VCC[053] VCCA[02]
<16> CPU_BSEL2 C21 BSEL[2] PSI# AE6 H_PSI# <48> AA12 VCC[054] 1 1
AA13 AD6 C9 C10
VCC[055] VID[0] CPU_VID0 <48>
Merom Ball-out Rev 1a AA15 AF5
VCC[056] VID[1] CPU_VID1 <48>
CONN@ AA17 AE5 10U_0805_10V4Z
VCC[057] VID[2] CPU_VID2 <48> 2 2
TRACE CLOSELY CPU < 0.5' AA18 VCC[058] VID[3] AF4 CPU_VID3 <48>
0.01U_0402_16V7K
AA20 VCC[059] VID[4] AE3 CPU_VID4 <48>
COMP0, COMP2 layout : Width 18mils and Space 25mils (27.4Ohms) AB9 VCC[060] VID[5] AF3 CPU_VID5 <48>
COMP1, COMP3 layout : Width 4mils and Space 25mils (55Ohms) AC10 VCC[061] VID[6] AE2 CPU_VID6 <48>
B B
AB10 VCC[062] 1 2 +CPU_CORE
AB12 R30 100_0402_1%
VCC[063] VCCSENSE
AB14 VCC[064] VCCSENSE AF7 VCCSENSE <48>
AB15 VCC[065]
AB17 VCC[066]
AB18 AE7 VSSSENSE
VCC[067] VSSSENSE VSSSENSE <48>
H_PSI# C739 1 2 @ 100P_0402_50V8J
Merom Ball-out Rev 1a 1 2
layout note: Route TEST3 & TEST5 traces on ground referenced layer to the TPs H_DPRSTP# 1 2 CONN@ . R31 100_0402_1%
C762 470P_0402_50V7K

CPU_BSEL CPU_BSEL2 CPU_BSEL1 CPU_BSEL0

166 0 1 1
Place PU and PD within 1 inch of CPU (CRB recommend)
Route VCCSENSE and VSSSENSE traces at 27.4 Ohms with 50 mils spacing.
200 0 1 0
For 6 layer
266 0 0 0
Z=27.4 ohm
Length matching within 25 mils (Compal Common Design)
VCCSENSE, VSSSENSE/ 14mils (MS),
Trace width/space/other is 20/7/25
16mils (SL) width, 7mils space, 25mils
Place these 2 resisters closk to CPU pins within 500 mils
A space to other signals Mismatch =25mils. A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/18 Deciphered Date 2008/08/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Penryn (2/3)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JHXXX M/B LA-4241P Schematic
Date: Wednesday, May 28, 2008 Sheet 5 of 49
5 4 3 2 1
 5 4 3 2 1

330u
ESR 9m ohm
Package(L*W*H)7.3*4.3*1.8
+CPU_CORE
Rating 2.5V +CPU_CORE
JCPU1D 2 x 330uF(9mOhm/3) 2 x 330uF(9mOhm/3)
A4 VSS[001] VSS[082] P6
A8 VSS[002] VSS[083] P21 1 1 1 1 1 1
A11 VSS[003] VSS[084] P24
A14 R2 C11 + C12 + C13 + C14 + C15 + + C16
VSS[004] VSS[085] @ 330U_D2E_2.5VM_R9 @ @
A16 VSS[005] VSS[086] R5
A19 R22 330U_D2E_2.5VM_R9 330U_D2E_2.5VM_R9 330U_D2E_2.5VM_R9
VSS[006] VSS[087] 2 2
330U_D2E_2.5VM_R9 2 2 2
330U_D2E_2.5VM_R9 2
D A23 VSS[007] VSS[088] R25 D
AF2 VSS[008] VSS[089] T1
B6 VSS[009] VSS[090] T4
B8 VSS[010] VSS[091] T23 South Side Secondary North Side Secondary
B11 VSS[011] VSS[092] T26
B13 VSS[012] VSS[093] U3
B16 U6 +CPU_CORE
VSS[013] VSS[094]
B19 VSS[014] VSS[095] U21
B21 VSS[015] VSS[096] U24
B24 VSS[016] VSS[097] V2
C5 VSS[017] VSS[098] V5 1 1 1 1 1 1 1 1
C8 V22 C17 C18 C19 C20 C21 C22 C23 C24
VSS[018] VSS[099]
C11 VSS[019] VSS[100] V25
C14 W1 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
VSS[020] VSS[101] 2 2 2 2 2 2 2 2
C16 VSS[021] VSS[102] W4
C19 W23 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
VSS[022] VSS[103]
C2 VSS[023] VSS[104] W26
C22 VSS[024] VSS[105] Y3 (Place these capacitors on South side,Secondary Layer)
C25 VSS[025] VSS[106] Y6
D1 VSS[026] VSS[107] Y21
D4 Y24 +CPU_CORE
VSS[027] VSS[108]
D8 VSS[028] VSS[109] AA2
D11 VSS[029] VSS[110] AA5
D13 VSS[030] VSS[111] AA8
D16 VSS[031] VSS[112] AA11 1 1 1 1 1 1 1 1
D19 AA14 C25 C26 C27 C28 C29 C30 C31 C32
VSS[032] VSS[113]
D23 VSS[033] VSS[114] AA16
D26 AA19 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
VSS[034] VSS[115] 2 2 2 2 2 2 2 2
E3 VSS[035] VSS[116] AA22
C E6 AA25 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M C
VSS[036] VSS[117]
E8 VSS[037] VSS[118] AB1
E11 VSS[038] VSS[119] AB4 (Place these capacitors on North side,Secondary Layer)
E14 VSS[039] VSS[120] AB8
E16 VSS[040] VSS[121] AB11
E19 AB13 +CPU_CORE
VSS[041] VSS[122]
E21 VSS[042] VSS[123] AB16
E24 VSS[043] VSS[124] AB19
F5 VSS[044] VSS[125] AB23
F8 VSS[045] VSS[126] AB26 1 1 1 1 1 1 1 1
F11 AC3 C33 C34 C35 C36 C37 C38 C39 C40
VSS[046] VSS[127] @ @
F13 VSS[047] VSS[128] AC6
F16 AC8 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
VSS[048] VSS[129] 2 2 2 2 2 2 2 2
F19 VSS[049] VSS[130] AC11
F2 AC14 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
VSS[050] VSS[131]
F22 VSS[051] VSS[132] AC16
F25 VSS[052] VSS[133] AC19 (Place these capacitors on South side,Primary Layer)
G4 VSS[053] VSS[134] AC21
G1 VSS[054] VSS[135] AC24
G23 AD2 +CPU_CORE
VSS[055] VSS[136]
G26 VSS[056] VSS[137] AD5
H3 VSS[057] VSS[138] AD8
H6 VSS[058] VSS[139] AD11
H21 VSS[059] VSS[140] AD13 1 1 1 1 1 1 1 1
H24 AD16 C41 C42 C43 C44 C45 C46 C47 C48
VSS[060] VSS[141] @ @
J2 VSS[061] VSS[142] AD19
J5 AD22 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
VSS[062] VSS[143] 2 2 2 2 2 2 2 2
J22 VSS[063] VSS[144] AD25
J25 AE1 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
B VSS[064] VSS[145] B
K1 VSS[065] VSS[146] AE4
K4 VSS[066] VSS[147] AE8 (Place these capacitors on North side,Primary Layer)
K23 VSS[067] VSS[148] AE11
K26 VSS[068] VSS[149] AE14
L3 VSS[069] VSS[150] AE16
L6 VSS[070] VSS[151] AE19 +CPU-CORE C,uF ESR, mohm ESL,nH
L21 AE23
L24
VSS[071] VSS[152]
AE26 Decoupling
VSS[072] VSS[153]
M2 VSS[073] VSS[154] A2 SPCAP,Polymer 6X330uF 9m ohm/6 1.8nH/6
M5 VSS[074] VSS[155] AF6
M22 VSS[075] VSS[156] AF8 32X22uF 3m ohm/32 0.6nH/32
M25 VSS[076] VSS[157] AF11 MLCC 0805 X5R
N1 VSS[077] VSS[158] AF13 32X10uF 3m ohm/32 0.6nH/32
N4 VSS[078] VSS[159] AF16
N23 VSS[079] VSS[160] AF19
N26 VSS[080] VSS[161] AF21
P3 VSS[081] VSS[162] A25
VSS[163] AF25
+1.05VS
Merom Ball-out Rev 1a
CONN@ .

1 1 1 1 1 1
C49 C50 C51 C52 C53 C54

0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

2 2 2 2 2 2
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
A A

(Place these capacitors inside socket cavity in 2 row on North side Secondary)

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/18 Deciphered Date 2008/8/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Penryn (3/3)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JHXXX M/B LA-4241P Schematic
Date: Friday, April 11, 2008 Sheet 6 of 49
5 4 3 2 1
 5 4 3 2 1

Change U3 from SA00001P900 to SA00001P930

3/4 Change U3 from SA00001P930 to SA00002JT10 (B0 to B2)

H_A#[3..35] <4>
<5> H_D#[0..63] U3A
A14 H_A#3
H_D#0 H_A#_3 H_A#4
F2 H_D#_0 H_A#_4 C15
H_D#1 G8 F16 H_A#5
H_D#2 H_D#_1 H_A#_5 H_A#6
F8 H_D#_2 H_A#_6 H13
H_D#3 E6 C18 H_A#7
H_D#4 H_D#_3 H_A#_7 H_A#8
D G2 H_D#_4 H_A#_8 M16 D
H_D#5 H6 J13 H_A#9 U3
H_D#6 H_D#_5 H_A#_9 H_A#10
H2 H_D#_6 H_A#_10 P16
H_D#7 F6 R16 H_A#11
H_D#8 H_D#_7 H_A#_11 H_A#12
D4 H_D#_8 H_A#_12 N17
H_D#9 H3 M13 H_A#13
H_D#10 H_D#_9 H_A#_13 H_A#14
M9 H_D#_10 H_A#_14 E17
H_D#11 M11 P17 H_A#15 965PM
H_D#12 H_D#_11 H_A#_15 H_A#16 PM@
J1 H_D#_12 H_A#_16 F17
H_D#13 J2 G20 H_A#17
H_D#14 H_D#_13 H_A#_17 H_A#18
N12 H_D#_14 H_A#_18 B19
H_D#15 J6 J16 H_A#19 3/4 Change U3 PM@ from SA00001ZO30
H_D#16 H_D#_15 H_A#_19 H_A#20
P2 E20
H_D#17 L2
H_D#_16 H_A#_20
H16 H_A#21 to SA00002JJ00 (B0 to B2)
H_D#18 H_D#_17 H_A#_21 H_A#22
R2 H_D#_18 H_A#_22 J20
H_D#19 N9 L17 H_A#23
H_D#20 H_D#_19 H_A#_23 H_A#24
L6 H_D#_20 H_A#_24 A17
H_D#21 M5 B17 H_A#25
H_D#22 H_D#_21 H_A#_25 H_A#26
J3 H_D#_22 H_A#_26 L16
H_D#23 N2 C21 H_A#27
H_D#24 H_D#_23 H_A#_27 H_A#28
R1 H_D#_24 H_A#_28 J17
H_D#25 N5 H20 H_A#29
H_D#26 H_D#_25 H_A#_29 H_A#30
N6 H_D#_26 H_A#_30 B18
H_D#27 P13 K17 H_A#31
H_D#28 H_D#_27 H_A#_31 H_A#32
N8 H_D#_28 H_A#_32 B20
H_D#29 L7 F21 H_A#33
H_D#30 H_D#_29 H_A#_33 H_A#34
N10 H_D#_30 H_A#_34 K21
+1.05VS H_D#31 M3 L20 H_A#35
H_D#32 H_D#_31 H_A#_35
Y3 H_D#_32
C H_D#33 AD14 H12 H_ADS# C
H_D#_33 H_ADS# H_ADS# <4>
1

H_D#34 Y6 B16 H_ADSTB#0

H_D#_34 H_ADSTB#_0 H_ADSTB#0 <4>
R32 H_D#35 Y10 G17 H_ADSTB#1
H_D#_35 H_ADSTB#_1 H_ADSTB#1 <4>
H_D#36 Y12 A9 H_BNR#
H_D#_36 H_BNR# H_BNR# <4>

HOST
221_0402_1% H_D#37 Y14 F11 H_BPRI#
H_D#_37 H_BPRI# H_BPRI# <4>
H_D#38 Y7 G12 H_BR0#
H_BR0# <4>
2

H_SWING H_D#39 H_D#_38 H_BREQ# H_DEFER#

W2 H_D#_39 H_DEFER# E9 H_DEFER# <4>
H_D#40 AA8 B10 H_DBSY#
H_D#_40 H_DBSY# H_DBSY# <4>
width=10mil H_D#41 Y9 AH7 CLK_MCH_BCLK
H_D#_41 HPLL_CLK CLK_MCH_BCLK <16>
2

1 H_D#42 AA13 AH6 CLK_MCH_BCLK#

H_D#_42 HPLL_CLK# CLK_MCH_BCLK# <16>
R33 C55 H_D#43 AA9 J11 H_DPWR#
H_D#_43 H_DPWR# H_DPWR# <5>
H_D#44 AA11 F9 H_DRDY#
H_D#_44 H_DRDY# H_DRDY# <4>
100_0402_1% 0.1U_0402_16V4Z H_D#45 AD11 H9 H_HIT#
2 H_D#_45 H_HIT# H_HIT# <4>
H_D#46 AD10 E12 H_HITM#
H_HITM# <4>
1

H_D#47 H_D#_46 H_HITM# H_LOCK#

AD13 H_D#_47 H_LOCK# H11 H_LOCK# <4>
H_D#48 AE12 C9 H_TRDY#
H_D#49 H_D#_48 H_TRDY# H_TRDY# <4>
Near C5 pin AE9 H_D#_49
H_D#50 AA2
H_RCOMP H_D#51 H_D#_50
AD8 H_D#_51
H_D#52 AA3
H_D#53 H_D#_52 H_DINV#0
AD3 H_D#_53 H_DINV#_0 J8 H_DINV#0 <5>
1

H_D#54 AD7 L3 H_DINV#1

H_D#_54 H_DINV#_1 H_DINV#1 <5>
R34 width / space =10mil / 20mil H_D#55 AE14 Y13 H_DINV#2
H_D#_55 H_DINV#_2 H_DINV#2 <5>
H_D#56 AF3 Y1 H_DINV#3
H_D#_56 H_DINV#_3 H_DINV#3 <5>
24.9_0402_1% H_D#57 AC1
H_D#58 H_D#_57 H_DSTBN#0
AE3 L10 H_DSTBN#0 <5>
2

H_D#59 H_D#_58 H_DSTBN#_0 H_DSTBN#1

AC3 H_D#_59 H_DSTBN#_1 M7 H_DSTBN#1 <5>
H_D#60 AE11 AA5 H_DSTBN#2
H_D#_60 H_DSTBN#_2 H_DSTBN#2 <5>
H_D#61 AE8 AE6 H_DSTBN#3
B H_D#_61 H_DSTBN#_3 H_DSTBN#3 <5> B
H_D#62 AG2
H_D#63 H_D#_62 H_DSTBP#0
AD6 H_D#_63 H_DSTBP#_0 L9 H_DSTBP#0 <5>
M8 H_DSTBP#1
H_DSTBP#_1 H_DSTBP#1 <5>
AA6 H_DSTBP#2
H_DSTBP#_2 H_DSTBP#2 <5>
H_SWING C5 AE5 H_DSTBP#3
H_SWING H_DSTBP#_3 H_DSTBP#3 <5>
Layout Note: H_RCOMP E3
+1.05VS H_RCOMP H_REQ#[0..4] <4>
B15 H_REQ#0
H_RCOMP / H_VREF / H_SWING H_REQ#_0
K13 H_REQ#1
H_REQ#_1 H_REQ#2
trace width and spacing is 10/20 H_REQ#_2 F13
2

B13 H_REQ#3
R35 H_RESET# H_REQ#_3 H_REQ#4
<4> H_RESET# C12 H_CPURST# H_REQ#_4 B14
H_CPUSLP# E11
<5> H_CPUSLP# H_CPUSLP# H_RS#[0..2] <4>
1K_0402_1% B6 H_RS#0
H_RS#_0 H_RS#1
F12
1

H_VREF H_RS#_1 H_RS#2

A11 H_AVREF H_RS#_2 C8
B11 H_DVREF
1

1
R36 C56 width:spacing=10mil:20mil (<0.5") CANTIGA ES_FCBGA1329
@ GM@
2K_0402_1% 0.1U_0402_16V4Z
2
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/18 Deciphered Date 2008/8/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cantiga (1/7)-GTL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JHXXX M/B LA-4241P Schematic
Date: Tuesday, June 03, 2008 Sheet 7 of 49
5 4 3 2 1
 5 4 3 2 1

U3B

M36 RSVD1 SA_CK_0 AP24 DDRA_CLK0 <14>

N36 AT21 CLK_DREF_96M# 1 2
RSVD2 SA_CK_1 DDRA_CLK1 <14>
R33 AV24 R37 PM@ 0_0402_5%
RSVD3 SB_CK_0 DDRB_CLK0 <15>
T33 AU20 CLK_DREF_SSC# 1 2

COMPENSATION
+1.8V RSVD4 SB_CK_1 DDRB_CLK1 <15>
AH9 R40 PM@ 0_0402_5%
RSVD5 CLK_DREF_96M
AH10 RSVD6 SA_CK#_0 AR24 DDRA_CLK0# <14> 1 2
AH12 AR21 R41 PM@ 0_0402_5%
RSVD7 SA_CK#_1 DDRA_CLK1# <14>
AH13 AU24 CLK_DREF_SSC 1 2
RSVD8 SB_CK#_0 DDRB_CLK0# <15>
R38 K12 AV20 R42 PM@ 0_0402_5%
RSVD9 SB_CK#_1 DDRB_CLK1# <15>
1K_0402_1% AL34 RSVD10
AK34 RSVD11 SA_CKE_0 BC28 DDRA_CKE0 <14>
AN35 RSVD12 SA_CKE_1 AY28 DDRA_CKE1 <14>
D SM_RCOMP_VOH D
AM35 RSVD13 SB_CKE_0 AY36 DDRB_CKE0 <15> SM_DRAMRST# would be
T24 RSVD14 SB_CKE_1 BB36 DDRB_CKE1 <15> needed for DDR3 only
C57 C59 BA17
SA_CS#_0 DDRA_SCS0# <14>
R43 AY16
SA_CS#_1 DDRA_SCS1# <14>
3.01K_0402_1% 2.2U_0603_6.3V6K 0.01U_0402_16V7K B31 AV16 For Cantiga 80 Ohm
RSVD15 SB_CS#_0 DDRB_SCS0# <15>
B2 RSVD16 SB_CS#_1 AR13 DDRB_SCS1# <15>

DDR CLK/ CONTROL/

M1 RSVD17 CFG[17:3] have internal pull up

RSVD
BD17

SM_RCOMP_VOL
SA_ODT_0
SA_ODT_1 AY17
DDRA_ODT0
DDRA_ODT1
<14>
<14> CFG[19:18] have internal pull down Strap Pin Table
AY21 RSVD20 SB_ODT_O BF15 DDRB_ODT0 <15> +1.8V
SB_ODT_1 AY13 DDRB_ODT1 <15>
R39 C60 C58 BG22 SMRCOMP R45 80.6_0402_1% 011 = 667MT/s FSB 000 = 1066MT/s FSB
1K_0402_1% SM_RCOMP SMRCOMP# R46 80.6_0402_1%
2.2U_0603_6.3V6K 0.01U_0402_16V7K
BG23 RSVD22 SM_RCOMP# BH21 CFG[2:0] 010 = 800MT/s FSB
BF23 RSVD23
BH18 BF28 SM_RCOMP_VOH 0 = DMI x 2
RSVD24 SM_RCOMP_VOH SM_RCOMP_VOL
BF18 RSVD25 SM_RCOMP_VOL BH28
R49
CFG5 1 = DMI x 4 * (Default)
SM_VREF
20mil
SM_VREF AV42
SM_PWROK R48
1 2 +1.8V 0 = The ITPM Host Interface is enabled
SM_PWROK AR36 1 2 10K_0402_1% CFG6 1 = The ITPM Host Interface is disabled *

2
BF17 SM_REXT R50 1 2 499_0402_1% 1 1K_0402_1%
SM_REXT C61 R51
SM_DRAMRST# BC36 0 = AMT Firmware will use TLS
0.1U_0402_16V4Z 1K_0402_1%
CFG7 cipher suite with no confidentiality
CLK_DREF_96M 2
B38 CLK_DREF_96M <16> 1 = AMT Firmware will use TLS

1
DPLL_REF_CLK CLK_DREF_96M#
DPLL_REF_CLK# A38 CLK_DREF_96M# <16> Layout Note:
E41 CLK_DREF_SSC
CLK_DREF_SSC <16> SM_VREF trace
cipher suite with confidentiality
DPLL_REF_SSCLK CLK_DREF_SSC#
DPLL_REF_SSCLK# F41 CLK_DREF_SSC# <16> width and spacing 0 = Lane Reversal Enable
CFG9

CLK
F43 CLK_MCH_3GPLL is 20/20. 1 = Normal Operation * (Default)
PEG_CLK CLK_MCH_3GPLL <16>
E43 CLK_MCH_3GPLL# 0 = PCIE Loopback Enable
C PEG_CLK# CLK_MCH_3GPLL# <16> C
CFG10 1 = Disable * (Default)
SM_PWROK: Pull L for DDR2
DMI_ITX_MRX_N0
Driven by platform for DDR3 00 = Reserved
DMI_RXN_0 AE41
DMI_ITX_MRX_N1
DMI_ITX_MRX_N0 <22> CFG[13:12] 01 = XOR Mode Enabled
AE37 DMI_ITX_MRX_N1 <22>
DMI_RXN_1
AE47 DMI_ITX_MRX_N2 10 = All Z Mode Enabled
DMI_RXN_2 DMI_ITX_MRX_N2 <22> 11 = Normal Operation * (Default)
AH39 DMI_ITX_MRX_N3
DMI_RXN_3 DMI_ITX_MRX_N3 <22>
DMI_ITX_MRX_P0
0 = Dynamic ODT Disabled
MCH_CLKSEL0 DMI_RXP_0 AE40
DMI_ITX_MRX_P1
DMI_ITX_MRX_P0 <22> CFG16 1 = Dynamic ODT Enabled * (Default)
<16> MCH_CLKSEL0
MCH_CLKSEL1
T25 CFG_0 DMI_RXP_1 AE38
DMI_ITX_MRX_P2
DMI_ITX_MRX_P1 <22> * (Default)
<16> MCH_CLKSEL1
MCH_CLKSEL2
R25 CFG_1 DMI_RXP_2 AE48
DMI_ITX_MRX_P3
DMI_ITX_MRX_P2 <22> 0 = Normal Operation *(Default)
<16> MCH_CLKSEL2 P25 CFG_2 DMI_RXP_3 AH40 DMI_ITX_MRX_P3 <22> CFG19 1 = DMI Lane Reversal Enable
P20 CFG_3
P24 AE35 DMI_MTX_IRX_N0 0 = Only PCIE or SDVO is operational.
CFG_4 DMI_TXN_0 DMI_MTX_IRX_N0 <22> *
MCH_CFG_5 DMI_MTX_IRX_N1 CFG20

DMI
C25 CFG_5 DMI_TXN_1 AE43 DMI_MTX_IRX_N1 <22>
MCH_CFG_6 N24 AE46 DMI_MTX_IRX_N2
DMI_MTX_IRX_N2 <22>
(Default)
MCH_CFG_7 M24
CFG_6 DMI_TXN_2
AH42 DMI_MTX_IRX_N3 (PCIE/SDVO select) 1 = PCIE/SDVO are operating simu.
CFG_7 DMI_TXN_3 DMI_MTX_IRX_N3 <22>
MCH_CFG_9
E21
C23
CFG_8
CFG_9
CFG DMI_TXP_0 AD35 DMI_MTX_IRX_P0
DMI_MTX_IRX_P0 <22> 0 = No SDVO Device Present * (Default)
MCH_CFG_10 C24 AE44 DMI_MTX_IRX_P1 SDVO_CTRLDATA
CFG_10 DMI_TXP_1 DMI_MTX_IRX_P1 <22>
N21 AF46 DMI_MTX_IRX_P2 1 = SDVO Device Present
CFG_11 DMI_TXP_2 DMI_MTX_IRX_P2 <22>
Use VGATE for GMCH_PWROK MCH_CFG_12 P21 AH43 DMI_MTX_IRX_P3
CFG_12 DMI_TXP_3 DMI_MTX_IRX_P3 <22>
MCH_CFG_13 T21
VGATE GMCH_PWROK CFG_13
<16,22,48> VGATE 1 2 R20 CFG_14
R52 @ 0_0402_5% M20
ICH_PWROK 1 MCH_CFG_16 CFG_15
<22,32> ICH_PWROK 2 L21 CFG_16
R53 0_0402_5% H21 CFG_17
P29
GRAPHICS VID

MCH_CFG_19 CFG_18 MCH_CFG_5

R28 CFG_19 1 2
MCH_CFG_20 T28 B33 R54 @ 2.21K_0402_1%
CFG_20 GFX_VID_0 MCH_CFG_9
GFX_VID_1 B32 1 2
G33 R55 @ 2.21K_0402_1%
B GFX_VID_2 MCH_CFG_12 B
GFX_VID_3 F33 1 2
R57 1 2 0_0402_5% PM_BMBUSY#_R R29 E33 R56 @ 2.21K_0402_1%
<22> PM_BMBUSY# PM_SYNC# GFX_VID_4
R58 1 2 0_0402_5% PM_DPRSTP#_R B7 MCH_CFG_13 1 2
<5,21,48> H_DPRSTP# PM_DPRSTP#
PM_EXTTS#0 N33 R59 @ 2.21K_0402_1%
<14> PM_EXTTS#0 PM_EXT_TS#_0
PM

PM_EXTTS#1 P32 10/22 intel recommend 2.21K MCH_CFG_16 1 2

<15> PM_EXTTS#1 PM_EXT_TS#_1
GMCH_PWROK AT40 C34 R60 @ 2.21K_0402_1%
R61 100_0402_5% MCH_RSTIN# PWROK GFX_VR_EN iTPM spec use 10K MCH_CFG_10
<17,20,26,28,30,40> PLT_RST_BUF# AT11 RSTIN# 1 2
R63 +1.05VS
<4,21> H_THERMTRIP# 1 2 0_0402_5% THERMTRIP#_R T20 THERMTRIP#
R62 @ 2.21K_0402_1%
R64 1 2 0_0402_5% DPRSLPVR_R R32 MCH_CFG_6 1 2
<22,48> PM_DPRSLPVR_D DPRSLPVR R65 @ 2.21K_0402_1%

2
MCH_CFG_7 1 2
BG48 AH37 R66 R67 @ 2.21K_0402_1%
NC_1 CL_CLK CL_CLK0 <22>
BF48 NC_2 CL_DATA AH36 CL_DATA0 <22> Add follow CRB
ME

BD48 AN36 ICH_PWROK 1K_0402_1%

NC_3 CL_PWROK
BC48 AJ35 CL_RST#0 <22> Change R from 4.02K to 2.21K following CRB

1
NC_4 CL_RST# CL_VREF
BH47 NC_5 CL_VREF AH34
BG47 NC_6

2
BE47 NC_7
BH46 N28 C62 1 R68
NC_8 DDPC_CTRLCLK
NC

BF46 NC_9 DDPC_CTRLDATA M28

BG45 G36 HDMICLK_NB 511_0402_1%
+3VS +3VS NC_10 SDVO_CTRLCLK HDMICLK_NB <25>
BH44 E36 HDMIDAT_NB 0.1U_0402_16V4Z MCH_CFG_19 +3VS
HDMIDAT_NB <25>

1
NC_11 SDVO_CTRLDATA MCH_CLKREQ# 2 R69 @ 4.02K_0402_1%
BH43 NC_12 CLKREQ# K36 MCH_CLKREQ# <16>
MISC

BH6 H36 MCH_CFG_20

NC_13 ICH_SYNC# MCH_ICH_SYNC# <22>
1

BH5 R70 @ 4.02K_0402_1%

R71 R72 NC_14
BG4 NC_15
1K_0402_5% 1K_0402_5% BH3 B12 MCH_TSATN# PM_EXTTS#0 +3VS
+1.05VS @ NC_16 TSATN# R73 10K_0402_5%
BF3 NC_17
BH2 PM_EXTTS#1
2

NC_18 R74 10K_0402_5%

MCH_TSATN#_EC <32> BG2 NC_19
1

BE2 B28 GMCH_HDA_BITCLK

NC_20 HDA_BCLK GMCH_HDA_BITCLK <10>
1

R76 C BG1 B30 GMCH_HDA_RST#

A NC_21 HDA_RST# GMCH_HDA_RST# <10> A
54.9_0402_1% 2 Q1 BF1 B29 MCH_HDA_SDIN R78 1 GM@ 2 33_0402_5%
B NC_22 HDA_SDI GMCH_HDA_SDIN2 <10>
MMBT3904_SOT23-3 BD1 C29 GMCH_HDA_SDOUT HDMICLK_NB 1 2
R81 NC_23 HDA_SDO GMCH_HDA_SDOUT <10>
1

C E @ BC1 A28 GMCH_HDA_SYNC R80 @ 0_0402_5%

HDA

GMCH_HDA_SYNC <10>
2

MCH_TSATN# @ Q2 NC_24 HDA_SYNC HDMIDAT_NB

1 2 2 F1 NC_25 1 2
B MMBT3904_SOT23-3 A47 R83 @ 0_0402_5%
330_0402_5% E @ NC_26
When ICH9M VCCHDA and VCCSUSHDA tie to 3V, don't stuff these resisters (follow CRB)
3

CANTIGA ES_FCBGA1329
GM@
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/08/18 Deciphered Date 2008/8/18 Title
PM_DPRSLPVR_D 1
C760
2
470P_0402_50V7K
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cantiga (2/7)-DMI/DDR
H_DPRSTP# 1 2 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C761 470P_0402_50V7K Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JHXXX M/B LA-4241P Schematic
Date: Tuesday, June 03, 2008 Sheet 8 of 49
5 4 3 2 1
 5 4 3 2 1

DDRA_SDQ[0..63] DDRB_SDQ[0..63]
<14> DDRA_SDQ[0..63] <15> DDRB_SDQ[0..63]
DDRA_SDM[0..7] DDRB_SDM[0..7]
<14> DDRA_SDM[0..7] <15> DDRB_SDM[0..7]
D DDRA_SMA[0..14] DDRB_SMA[0..14] D
<14> DDRA_SMA[0..14] <15> DDRB_SMA[0..14]

U3D U3E
DDRA_SDQ0 AJ38 BD21 DDRB_SDQ0 AK47 BC16
SA_DQ_0 SA_BS_0 DDRA_SBS0 <14> SB_DQ_0 SB_BS_0 DDRB_SBS0 <15>
DDRA_SDQ1 AJ41 BG18 DDRB_SDQ1 AH46 BB17
SA_DQ_1 SA_BS_1 DDRA_SBS1 <14> SB_DQ_1 SB_BS_1 DDRB_SBS1 <15>
DDRA_SDQ2 AN38 AT25 DDRB_SDQ2 AP47 BB33
SA_DQ_2 SA_BS_2 DDRA_SBS2 <14> SB_DQ_2 SB_BS_2 DDRB_SBS2 <15>
DDRA_SDQ3 AM38 DDRB_SDQ3 AP46
DDRA_SDQ4 SA_DQ_3 DDRB_SDQ4 SB_DQ_3
AJ36 SA_DQ_4 SA_RAS# BB20 DDRA_SRAS# <14> AJ46 SB_DQ_4
DDRA_SDQ5 AJ40 BD20 DDRB_SDQ5 AJ48 AU17
SA_DQ_5 SA_CAS# DDRA_SCAS# <14> SB_DQ_5 SB_RAS# DDRB_SRAS# <15>
DDRA_SDQ6 AM44 AY20 DDRB_SDQ6 AM48 BG16
SA_DQ_6 SA_WE# DDRA_SWE# <14> SB_DQ_6 SB_CAS# DDRB_SCAS# <15>
DDRA_SDQ7 AM42 DDRB_SDQ7 AP48 BF14
SA_DQ_7 SB_DQ_7 SB_WE# DDRB_SWE# <15>
DDRA_SDQ8 AN43 DDRB_SDQ8 AU47
DDRA_SDQ9 SA_DQ_8 DDRB_SDQ9 SB_DQ_8
AN44 SA_DQ_9 AU46 SB_DQ_9
DDRA_SDQ10 AU40 DDRB_SDQ10 BA48
DDRA_SDQ11 SA_DQ_10 DDRB_SDQ11 SB_DQ_10
AT38 SA_DQ_11 AY48 SB_DQ_11
DDRA_SDQ12 AN41 DDRB_SDQ12 AT47
DDRA_SDQ13 SA_DQ_12 DDRA_SDM0 DDRB_SDQ13 SB_DQ_12
AN39 SA_DQ_13 SA_DM_0 AM37 AR47 SB_DQ_13
DDRA_SDQ14 AU44 AT41 DDRA_SDM1 DDRB_SDQ14 BA47
DDRA_SDQ15 SA_DQ_14 SA_DM_1 DDRA_SDM2 DDRB_SDQ15 SB_DQ_14 DDRB_SDM0
AU42 SA_DQ_15 SA_DM_2 AY41 BC47 SB_DQ_15 SB_DM_0 AM47
DDRA_SDQ16 AV39 AU39 DDRA_SDM3 DDRB_SDQ16 BC46 AY47 DDRB_SDM1
DDRA_SDQ17 SA_DQ_16 SA_DM_3 DDRA_SDM4 DDRB_SDQ17 SB_DQ_16 SB_DM_1 DDRB_SDM2
AY44 SA_DQ_17 SA_DM_4 BB12 BC44 SB_DQ_17 SB_DM_2 BD40
DDRA_SDQ18 BA40 AY6 DDRA_SDM5 DDRB_SDQ18 BG43 BF35 DDRB_SDM3
C DDRA_SDQ19 SA_DQ_18 SA_DM_5 DDRA_SDM6 DDRB_SDQ19 SB_DQ_18 SB_DM_3 DDRB_SDM4 C
BD43 SA_DQ_19 SA_DM_6 AT7 BF43 SB_DQ_19 SB_DM_4 BG11
DDRA_SDQ20 AV41 AJ5 DDRA_SDM7 DDRB_SDQ20 BE45 BA3 DDRB_SDM5
DDRA_SDQ21 SA_DQ_20 SA_DM_7 DDRB_SDQ21 SB_DQ_20 SB_DM_5 DDRB_SDM6
AY43 BC41 AP1

B
SA_DQ_21 SB_DQ_21 SB_DM_6
A

DDRA_SDQ22 BB41 DDRB_SDQ22 BF40 AK2 DDRB_SDM7

DDRA_SDQ23 SA_DQ_22 DDRA_SDQS0 DDRB_SDQ23 SB_DQ_22 SB_DM_7
BC40 SA_DQ_23 SA_DQS_0 AJ44 DDRA_SDQS0 <14> BF41 SB_DQ_23
DDRA_SDQ24 AY37 AT44 DDRA_SDQS1 DDRB_SDQ24 BG38
SA_DQ_24 SA_DQS_1 DDRA_SDQS1 <14> SB_DQ_24
DDRA_SDQ25 BD38 BA43 DDRA_SDQS2 DDRB_SDQ25 BF38 AL47 DDRB_SDQS0
SA_DQ_25 SA_DQS_2 DDRA_SDQS2 <14> SB_DQ_25 SB_DQS_0 DDRB_SDQS0 <15>

MEMORY
DDRA_SDQ26 DDRA_SDQS3 DDRB_SDQ26 DDRB_SDQS1
MEMORY

AV37 SA_DQ_26 SA_DQS_3 BC37 DDRA_SDQS3 <14> BH35 SB_DQ_26 SB_DQS_1 AV48 DDRB_SDQS1 <15>
DDRA_SDQ27 AT36 AW12 DDRA_SDQS4 DDRB_SDQ27 BG35 BG41 DDRB_SDQS2
SA_DQ_27 SA_DQS_4 DDRA_SDQS4 <14> SB_DQ_27 SB_DQS_2 DDRB_SDQS2 <15>
DDRA_SDQ28 AY38 BC8 DDRA_SDQS5 DDRB_SDQ28 BH40 BG37 DDRB_SDQS3
SA_DQ_28 SA_DQS_5 DDRA_SDQS5 <14> SB_DQ_28 SB_DQS_3 DDRB_SDQS3 <15>
DDRA_SDQ29 BB38 AU8 DDRA_SDQS6 DDRB_SDQ29 BG39 BH9 DDRB_SDQS4
SA_DQ_29 SA_DQS_6 DDRA_SDQS6 <14> SB_DQ_29 SB_DQS_4 DDRB_SDQS4 <15>
DDRA_SDQ30 AV36 AM7 DDRA_SDQS7 DDRB_SDQ30 BG34 BB2 DDRB_SDQS5
SA_DQ_30 SA_DQS_7 DDRA_SDQS7 <14> SB_DQ_30 SB_DQS_5 DDRB_SDQS5 <15>
DDRA_SDQ31 AW36 DDRB_SDQ31 BH34 AU1 DDRB_SDQS6
SA_DQ_31 SB_DQ_31 SB_DQS_6 DDRB_SDQS6 <15>
DDRA_SDQ32 BD13 DDRB_SDQ32 BH14 AN6 DDRB_SDQS7
SA_DQ_32 SB_DQ_32 SB_DQS_7 DDRB_SDQS7 <15>
DDRA_SDQ33 AU11 AJ43 DDRA_SDQS0# DDRB_SDQ33 BG12
SA_DQ_33 SA_DQS#_0 DDRA_SDQS0# <14> SB_DQ_33
DDRA_SDQ34 BC11 AT43 DDRA_SDQS1# DDRB_SDQ34 BH11
SA_DQ_34 SA_DQS#_1 DDRA_SDQS1# <14> SB_DQ_34
DDRA_SDQ35 BA12 BA44 DDRA_SDQS2# DDRB_SDQ35 BG8 AL46 DDRB_SDQS0#
SA_DQ_35 SA_DQS#_2 DDRA_SDQS2# <14> SB_DQ_35 SB_DQS#_0 DDRB_SDQS0# <15>

SYSTEM
DDRA_SDQ36
SYSTEM

AU13 BD37 DDRA_SDQS3# DDRB_SDQ36 BH12 AV47 DDRB_SDQS1#

SA_DQ_36 SA_DQS#_3 DDRA_SDQS3# <14> SB_DQ_36 SB_DQS#_1 DDRB_SDQS1# <15>
DDRA_SDQ37 AV13 AY12 DDRA_SDQS4# DDRB_SDQ37 BF11 BH41 DDRB_SDQS2#
SA_DQ_37 SA_DQS#_4 DDRA_SDQS4# <14> SB_DQ_37 SB_DQS#_2 DDRB_SDQS2# <15>
DDRA_SDQ38 BD12 BD8 DDRA_SDQS5# DDRB_SDQ38 BF8 BH37 DDRB_SDQS3#
SA_DQ_38 SA_DQS#_5 DDRA_SDQS5# <14> SB_DQ_38 SB_DQS#_3 DDRB_SDQS3# <15>
DDRA_SDQ39 BC12 AU9 DDRA_SDQS6# DDRB_SDQ39 BG7 BG9 DDRB_SDQS4#
SA_DQ_39 SA_DQS#_6 DDRA_SDQS6# <14> SB_DQ_39 SB_DQS#_4 DDRB_SDQS4# <15>
DDRA_SDQ40 BB9 AM8 DDRA_SDQS7# DDRB_SDQ40 BC5 BC2 DDRB_SDQS5#
SA_DQ_40 SA_DQS#_7 DDRA_SDQS7# <14> SB_DQ_40 SB_DQS#_5 DDRB_SDQS5# <15>
DDRA_SDQ41 BA9 DDRB_SDQ41 BC6 AT2 DDRB_SDQS6#
SA_DQ_41 SB_DQ_41 SB_DQS#_6 DDRB_SDQS6# <15>
DDRA_SDQ42 AU10 DDRB_SDQ42 AY3 AN5 DDRB_SDQS7#
SA_DQ_42 SB_DQ_42 SB_DQS#_7 DDRB_SDQS7# <15>
DDRA_SDQ43 AV9 DDRB_SDQ43 AY1
DDRA_SDQ44 SA_DQ_43 DDRA_SMA0 DDRB_SDQ44 SB_DQ_43
BA11 SA_DQ_44 SA_MA_0 BA21 BF6 SB_DQ_44
DDRA_SDQ45 BD9 BC24 DDRA_SMA1 DDRB_SDQ45 BF5 AV17 DDRB_SMA0

DDR
SA_DQ_45 SA_MA_1 SB_DQ_45 SB_MA_0
DDR

DDRA_SDQ46 AY8 BG24 DDRA_SMA2 DDRB_SDQ46 BA1 BA25 DDRB_SMA1

DDRA_SDQ47 SA_DQ_46 SA_MA_2 DDRA_SMA3 DDRB_SDQ47 SB_DQ_46 SB_MA_1 DDRB_SMA2
BA6 SA_DQ_47 SA_MA_3 BH24 BD3 SB_DQ_47 SB_MA_2 BC25
B DDRA_SDQ48 DDRA_SMA4 DDRB_SDQ48 DDRB_SMA3 B
AV5 SA_DQ_48 SA_MA_4 BG25 AV2 SB_DQ_48 SB_MA_3 AU25
DDRA_SDQ49 AV7 BA24 DDRA_SMA5 DDRB_SDQ49 AU3 AW25 DDRB_SMA4
DDRA_SDQ50 SA_DQ_49 SA_MA_5 DDRA_SMA6 DDRB_SDQ50 SB_DQ_49 SB_MA_4 DDRB_SMA5
AT9 SA_DQ_50 SA_MA_6 BD24 AR3 SB_DQ_50 SB_MA_5 BB28
DDRA_SDQ51 AN8 BG27 DDRA_SMA7 DDRB_SDQ51 AN2 AU28 DDRB_SMA6
DDRA_SDQ52 SA_DQ_51 SA_MA_7 DDRA_SMA8 DDRB_SDQ52 SB_DQ_51 SB_MA_6 DDRB_SMA7
AU5 SA_DQ_52 SA_MA_8 BF25 AY2 SB_DQ_52 SB_MA_7 AW28
DDRA_SDQ53 AU6 AW24 DDRA_SMA9 DDRB_SDQ53 AV1 AT33 DDRB_SMA8
DDRA_SDQ54 SA_DQ_53 SA_MA_9 DDRA_SMA10 DDRB_SDQ54 SB_DQ_53 SB_MA_8 DDRB_SMA9
AT5 SA_DQ_54 SA_MA_10 BC21 AP3 SB_DQ_54 SB_MA_9 BD33
DDRA_SDQ55 AN10 BG26 DDRA_SMA11 DDRB_SDQ55 AR1 BB16 DDRB_SMA10
DDRA_SDQ56 SA_DQ_55 SA_MA_11 DDRA_SMA12 DDRB_SDQ56 SB_DQ_55 SB_MA_10 DDRB_SMA11
AM11 SA_DQ_56 SA_MA_12 BH26 AL1 SB_DQ_56 SB_MA_11 AW33
DDRA_SDQ57 AM5 BH17 DDRA_SMA13 DDRB_SDQ57 AL2 AY33 DDRB_SMA12
DDRA_SDQ58 SA_DQ_57 SA_MA_13 DDRA_SMA14 DDRB_SDQ58 SB_DQ_57 SB_MA_12 DDRB_SMA13
AJ9 SA_DQ_58 SA_MA_14 AY25 AJ1 SB_DQ_58 SB_MA_13 BH15
DDRA_SDQ59 AJ8 DDRB_SDQ59 AH1 AU33 DDRB_SMA14
DDRA_SDQ60 SA_DQ_59 DDRB_SDQ60 SB_DQ_59 SB_MA_14
AN12 SA_DQ_60 AM2 SB_DQ_60
DDRA_SDQ61 AM13 DDRB_SDQ61 AM3
DDRA_SDQ62 SA_DQ_61 DDRB_SDQ62 SB_DQ_61
AJ11 SA_DQ_62 AH3 SB_DQ_62
DDRA_SDQ63 AJ12 DDRB_SDQ63 AJ3
SA_DQ_63 SB_DQ_63
GM@ CANTIGA ES_FCBGA1329 GM@ CANTIGA ES_FCBGA1329

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/18 Deciphered Date 2008/8/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cantiga (3/7)-DDRII
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JHXXX M/B LA-4241P Schematic
Date: Tuesday, June 03, 2008 Sheet 9 of 49
5 4 3 2 1
 5 4 3 2 1

U3C 20/25mils R492 Close to GMCH < 0.5'

L32 L_BKLT_CTRL
1 2 LBKLT_EN G32 T37 PEG_COMP 1 2 +1.05VS_PEG
<18> GMCH_ENBKL L_BKLT_EN PEG_COMPI
R84 GM@ 0_0402_5% LCTLA_CLK M32 T36 R85 49.9_0402_1%
LCTLB_DATA L_CTRL_CLK PEG_COMPO
M33 L_CTRL_DATA
<18> GMCH_LCD_CLK GMCH_LCD_CLK K33
GMCH_LCD_DATA L_DDC_CLK PCIE_GTX_C_MRX_N0
<18> GMCH_LCD_DATA J33 L_DDC_DATA PEG_RX#_0 H44
GMCH_ENVDD M29 J46 PCIE_GTX_C_MRX_N1
<18> GMCH_ENVDD L_VDD_EN PEG_RX#_1
L44 PCIE_GTX_C_MRX_N2
LVDS_IBG PEG_RX#_2 PCIE_GTX_C_MRX_N3 PCIE_MTX_C_GRX_N[0..15]
D 1 2 1 2 C44 LVDS_IBG PEG_RX#_3 L40 PCIE_MTX_C_GRX_N[0..15] <17,25> D
C63 @ 100P_0402_50V8J R86 GM@ 2.37K_0402_1% B43 N41 PCIE_GTX_C_MRX_N4
LVDS_VBG PEG_RX#_4 PCIE_GTX_C_MRX_N5 PCIE_MTX_C_GRX_P[0..15]
E37 LVDS_VREFH PEG_RX#_5 P48 PCIE_MTX_C_GRX_P[0..15] <17,25>
E38 N44 PCIE_GTX_C_MRX_N6
LVDS_VREFL PEG_RX#_6 PCIE_GTX_C_MRX_N7 PCIE_GTX_C_MRX_N[0..15]
Change to @ state GMCH_TZCLK- PEG_RX#_7 T43
PCIE_GTX_C_MRX_N8
PCIE_GTX_C_MRX_N[0..15] <17>
<18> GMCH_TZCLK- C41 LVDSA_CLK# PEG_RX#_8 U43
GMCH_TZCLK+ C40 Y43 PCIE_GTX_C_MRX_N9 PCIE_GTX_C_MRX_P[0..15]
<18> GMCH_TZCLK+ LVDSA_CLK PEG_RX#_9 PCIE_GTX_C_MRX_P[0..15] <17>
GMCH_TXCLK- B37 Y48 PCIE_GTX_C_MRX_N10
<18> GMCH_TXCLK- LVDSB_CLK# PEG_RX#_10
GMCH_TXCLK+ A37 Y36 PCIE_GTX_C_MRX_N11
<18> GMCH_TXCLK+ LVDSB_CLK PEG_RX#_11

LVDS
AA43 PCIE_GTX_C_MRX_N12
GMCH_TZOUT0- PEG_RX#_12 PCIE_GTX_C_MRX_N13
<18> GMCH_TZOUT0- H47 LVDSA_DATA#_0 PEG_RX#_13 AD37
GMCH_TZOUT1- E46 AC47 PCIE_GTX_C_MRX_N14
<18> GMCH_TZOUT1-
<18> GMCH_TZOUT2-
GMCH_TZOUT2- G40
LVDSA_DATA#_1
LVDSA_DATA#_2
PEG_RX#_14
PEG_RX#_15 AD39 PCIE_GTX_C_MRX_N15 Routing notice:
A40 LVDSA_DATA#_3
H43 PCIE_GTX_C_MRX_P0 GM@
GMCH_TZOUT0+ PEG_RX_0 PCIE_GTX_C_MRX_P1 PCIE_GTX_C_MRX_P3 R87
<18> GMCH_TZOUT0+ H48 LVDSA_DATA_0 PEG_RX_1 J44 1 2 0_0402_5% TMDS_B_HPD# <25>
GMCH_TZOUT1+ D45 L43 PCIE_GTX_C_MRX_P2
<18> GMCH_TZOUT1+ LVDSA_DATA_1 PEG_RX_2

GRAPHICS
GMCH_TZOUT2+ F40 L41 PCIE_GTX_C_MRX_P3
<18> GMCH_TZOUT2+ LVDSA_DATA_2 PEG_RX_3
B40 N40 PCIE_GTX_C_MRX_P4
LVDSA_DATA_3 PEG_RX_4 PCIE_GTX_C_MRX_P5
PEG_RX_5 P47
GMCH_TXOUT0- A41 N43 PCIE_GTX_C_MRX_P6 NB Ext VGA
<18> GMCH_TXOUT0- LVDSB_DATA#_0 PEG_RX_6
GMCH_TXOUT1- H38 T42 PCIE_GTX_C_MRX_P7
<18> GMCH_TXOUT1- LVDSB_DATA#_1 PEG_RX_7
GMCH_TXOUT2- G37 U42 PCIE_GTX_C_MRX_P8 R
<18> GMCH_TXOUT2- LVDSB_DATA#_2 PEG_RX_8
J37 Y42 PCIE_GTX_C_MRX_P9
LVDSB_DATA#_3 PEG_RX_9 PCIE_GTX_C_MRX_P10
GMCH_TXOUT0+ PEG_RX_10 W47
PCIE_GTX_C_MRX_P11
CH7318
<18> GMCH_TXOUT0+ B42 LVDSB_DATA_0 PEG_RX_11 Y37
GMCH_TXOUT1+ G38 AA42 PCIE_GTX_C_MRX_P12
<18> GMCH_TXOUT1+ LVDSB_DATA_1 PEG_RX_12
GMCH_TXOUT2+ F37 AD36 PCIE_GTX_C_MRX_P13
<18> GMCH_TXOUT2+ LVDSB_DATA_2 PEG_RX_13
K37 AC48 PCIE_GTX_C_MRX_P14
LVDSB_DATA_3 PEG_RX_14

PCI-EXPRESS
C AD40 PCIE_GTX_C_MRX_P15 C
PEG_RX_15
J41 PCIE_MTX_GRX_N0 C64 1 2 0.1U_0402_10V7K PCIE_MTX_C_GRX_N0
PEG_TX#_0 PCIE_MTX_C_GRX_N0 <17,25>
M46 PCIE_MTX_GRX_N1 C65 1 2 0.1U_0402_10V7K PCIE_MTX_C_GRX_N1
PEG_TX#_1 PCIE_MTX_C_GRX_N1 <17,25>
R88 1 2 150_0402_1% GMCH_TV_COMPS F25 M47 PCIE_MTX_GRX_N2 C66 1 2 0.1U_0402_10V7K PCIE_MTX_C_GRX_N2
TVA_DAC PEG_TX#_2 PCIE_MTX_C_GRX_N2 <17,25>
R89 1 2 150_0402_1% GMCH_TV_LUMA H25 M40 PCIE_MTX_GRX_N3 C67 1 2 0.1U_0402_10V7K PCIE_MTX_C_GRX_N3
TVB_DAC PEG_TX#_3 PCIE_MTX_C_GRX_N3 <17,25>
R90 1 2 150_0402_1% GMCH_TV_CRMA K25 M42 PCIE_MTX_GRX_N4 C68 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N4
TVC_DAC PEG_TX#_4 PCIE_MTX_GRX_N5 C69 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N5
PEG_TX#_5 R48 1 2

TV
H24 N38 PCIE_MTX_GRX_N6 C70 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N6
TV_RTN PEG_TX#_6 PCIE_MTX_GRX_N7 C71 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N7
PEG_TX#_7 T40 1 2
U37 PCIE_MTX_GRX_N8 C72 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N8
PEG_TX#_8 PCIE_MTX_GRX_N9 C73 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N9
PEG_TX#_9 U40 1 2
TV_DCONSEL_0 C31 Y40 PCIE_MTX_GRX_N10 C74 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N10
TV_DCONSEL_1 TV_DCONSEL_0 PEG_TX#_10 PCIE_MTX_GRX_N11 C75 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N11
E32 TV_DCONSEL_1 PEG_TX#_11 AA46 1 2
AA37 PCIE_MTX_GRX_N12 C76 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N12
PEG_TX#_12 PCIE_MTX_GRX_N13 C77 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N13
PEG_TX#_13 AA40 1 2
AD43 PCIE_MTX_GRX_N14 C78 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N14
PEG_TX#_14 PCIE_MTX_GRX_N15 C79 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N15
PEG_TX#_15 AC46 1 2
Conntc to 0 Ohm when use PM chip PCIE_MTX_GRX_P0 C80 0.1U_0402_10V7K PCIE_MTX_C_GRX_P0
<19> GMCH_CRT_B E28 CRT_BLUE PEG_TX_0 J42 1 2 PCIE_MTX_C_GRX_P0 <17,25>
2 1 L46 PCIE_MTX_GRX_P1 C81 1 2 0.1U_0402_10V7K PCIE_MTX_C_GRX_P1
PEG_TX_1 PCIE_MTX_C_GRX_P1 <17,25>
R91 GM@ 150_0402_1% G28 M48 PCIE_MTX_GRX_P2 C82 1 2 0.1U_0402_10V7K PCIE_MTX_C_GRX_P2
<19> GMCH_CRT_G CRT_GREEN PEG_TX_2 PCIE_MTX_C_GRX_P2 <17,25>
2 1 M39 PCIE_MTX_GRX_P3 C83 1 2 0.1U_0402_10V7K PCIE_MTX_C_GRX_P3
PEG_TX_3 PCIE_MTX_C_GRX_P3 <17,25>

VGA
R92 GM@ 150_0402_1% J28 M43 PCIE_MTX_GRX_P4 C84 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P4
<19> GMCH_CRT_R CRT_RED PEG_TX_4
2 1 R47 PCIE_MTX_GRX_P5 C85 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P5
R93 GM@ 150_0402_1% PEG_TX_5 PCIE_MTX_GRX_P6 C86 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P6
G29 CRT_IRTN PEG_TX_6 N37 1 2
T39 PCIE_MTX_GRX_P7 C87 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P7
GMCH_CRT_CLK PEG_TX_7 PCIE_MTX_GRX_P8 C88 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P8
<19> GMCH_CRT_CLK H32 CRT_DDC_CLK PEG_TX_8 U36 1 2
<19> GMCH_CRT_DATA GMCH_CRT_DATA J32 U39 PCIE_MTX_GRX_P9 C89 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P9
B R94 CRT_HSYNC CRT_DDC_DATA PEG_TX_9 PCIE_MTX_GRX_P10 C90 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P10 B
<19> GMCH_CRT_HSYNC J29 CRT_HSYNC PEG_TX_10 Y39 1 2
GM@ 30_0402_5% CRT_IREF E29 Y46 PCIE_MTX_GRX_P11 C91 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P11
CRT_TVO_IREF PEG_TX_11 PCIE_MTX_GRX_P12 C92 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P12
PEG_TX_12 AA36 1 2
AA39 PCIE_MTX_GRX_P13 C93 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P13
R95 CRT_VSYNC PEG_TX_13 PCIE_MTX_GRX_P14 C94 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P14
<19> GMCH_CRT_VSYNC L29 CRT_VSYNC PEG_TX_14 AD42 1 2
GM@ 30_0402_5% AD46 PCIE_MTX_GRX_P15 C95 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P15
PEG_TX_15
100P_0402_50V8J

100P_0402_50V8J

R98 GM@ CANTIGA ES_FCBGA1329

10/22 follow CRB and Checklist 1 1
1.02K_0402_1%
recommend use 30 Ohm (SD028300A80) RP60
Reserved for 1.5V level shift circuit
1

2 2 +3.3VS +1.5VS HDA_BITCLK_NB GMCH_HDA_BITCLK

5 4
Common design recommend H/VSYNC width=8 mil HDA_RST_NB# 6 3 GMCH_HDA_RST#
C96 C97 HDA_SDOUT_NB 7 2 GMCH_HDA_SDOUT
@ @ 1 1 HDA_SYNC_NB 8 1 GMCH_HDA_SYNC
+3VS R99 1 2 PM@ 0_0402_5% GMCH_LCD_CLK C748 C747
0_0804_8P4R_5%
R100 1 2 PM@ 0_0402_5% GMCH_LCD_DATA 0.1U_0402_16V4Z 0.1U_0402_16V4Z
R101 1 GM@ 2 2.2K_0402_5% GMCH_LCD_CLK @ 2 @ 2 HDA_SDIN2 1 R786 2 GMCH_HDA_SDIN2
R102 1 2 PM@ 0_0402_5% LCTLB_DATA 0_0402_5%
R103 1 GM@ 2 2.2K_0402_5% GMCH_LCD_DATA U67
R104 1 2 PM@ 0_0402_5% LCTLA_CLK 16 1 R787
R105 1 GM@ VCCB VCCA
2 10K_0402_5% LCTLB_DATA 15 CLK_OUT CLK_IN 2 1 2 10K_0402_5%
R106 1 2 PM@ 0_0402_5% GMCH_CRT_CLK HDA_BITCLK_NB 14 3 GMCH_HDA_BITCLK
<21> HDA_BITCLK_NB CMD_B CMD_A GMCH_HDA_BITCLK <8>
R107 1 GM@ 2 10K_0402_5% LCTLA_CLK HDA_RST_NB# 13 4 GMCH_HDA_RST#
<21> HDA_RST_NB# B0 A0 GMCH_HDA_RST# <8>
R108 1 2 PM@ 0_0402_5% GMCH_CRT_DATA HDA_SDOUT_NB 12 5 GMCH_HDA_SDOUT
<21> HDA_SDOUT_NB B1 A1 GMCH_HDA_SDOUT <8>
HDA_SYNC_NB 11 6 GMCH_HDA_SYNC
<21> HDA_SYNC_NB B2 A2 GMCH_HDA_SYNC <8>
R109 1 2 0_0402_5% TV_DCONSEL_0 HDA_SDIN2 10 7 GMCH_HDA_SDIN2
A <21> HDA_SDIN2 B3 A3 GMCH_HDA_SDIN2 <8> A
9 GND OE 8 +1.5VS
R91 R92 R93 R110 1 2 0_0402_5% TV_DCONSEL_1
U67 pn is SA00002CT00 for 030 used FXL2SD106BQX_DQFN16_2P5X3P5~D
@

Security Classification Compal Secret Data Compal Electronics, Inc.

0_0402_5% 0_0402_5% 0_0402_5% Issued Date 2007/08/18 Deciphered Date 2008/8/18 Title
PM@ PM@ PM@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cantiga (4/7)-VGA/LVDS/TV
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JHXXX M/B LA-4241P Schematic
Date: Tuesday, June 03, 2008 Sheet 10 of 49
5 4 3 2 1
 5 4 3 2 1

U3F
+VCC_AXG
+1.8V
Checklist 220u ESR max 15m ohm
VCC_AXG_NTCF_1 W28 330u ESR max 12m ohm
AP33 VCC_SM_1 VCC_AXG_NCTF_2 V28
AN33 VCC_SM_2 VCC_AXG_NCTF_3 W26
BH32 VCC_SM_3 VCC_AXG_NCTF_4 V26
BG32 VCC_SM_4 VCC_AXG_NCTF_5 W25
BF32 V25 +1.05VS
D VCC_SM_5 VCC_AXG_NCTF_6 U3G D
BD32 VCC_SM_6 VCC_AXG_NCTF_7 W24
BC32 VCC_SM_7 VCC_AXG_NCTF_8 V24
BB32 VCC_SM_8 VCC_AXG_NCTF_9 W23 AG34 VCC_1

VCC
BA32 VCC_SM_9 VCC_AXG_NCTF_10 V23 AC34 VCC_2
AY32 VCC_SM_10 VCC_AXG_NCTF_11 AM21 AB34 VCC_3
+1.05VS
AW32 VCC_SM_11 VCC_AXG_NCTF_12 AL21 VCC: 2898.52mA AA34 VCC_4
AV32 VCC_SM_12 VCC_AXG_NCTF_13 AK21 220u Y34 VCC_5
AU32 W21 (220UF*1, 22UF*1, 0.22UF*2, 0.1UF*1) V34

VCC CORE
VCC_SM_13 VCC_AXG_NCTF_14 ESR 15m ohm VCC_6
AT32 V21 1 U34

SM
VCC_SM_14 VCC_AXG_NCTF_15 Package(L*W*H)7.3*4.3*1.9 VCC_7
AR32 VCC_SM_15 VCC_AXG_NCTF_16 U21 1 1 AM33 VCC_8
AP32 AM20 C106 + C107 C108 C109 C110 AK33
VCC_SM_16 VCC_AXG_NCTF_17 Rating 4V VCC_9
AN32 VCC_SM_17 VCC_AXG_NCTF_18 AK20 AJ33 VCC_10
BH31 W20 220U_D2_4VM_R15 0.22U_0603_16V7K 0.1U_0402_16V4Z AG33
VCC_SM_18 VCC_AXG_NCTF_19 2 2 2 VCC_11
BG31 VCC_SM_19 VCC_AXG_NCTF_20 U20 AF33 VCC_12
BF31 AM19 10U_0805_10V4Z 0.22U_0603_16V7K
VCC_SM_20 VCC_AXG_NCTF_21
BG30 VCC_SM_21 VCC_AXG_NCTF_22 AL19
BH29 VCC_SM_22 VCC_AXG_NCTF_23 AK19
BG29 VCC_SM_23 VCC_AXG_NCTF_24 AJ19 AE33 VCC_13
BF29 VCC_SM_24 VCC_AXG_NCTF_25 AH19 AC33 VCC_14
BD29 VCC_SM_25 VCC_AXG_NCTF_26 AG19
+1.8V VCC_SM: 3300mA AA33 VCC_15
BC29 VCC_SM_26 VCC_AXG_NCTF_27 AF19
(330UF*1,22UF*2, 0.1UF*1) 9/14 add for reservation Y33 VCC_16
BB29 VCC_SM_27 VCC_AXG_NCTF_28 AE19 W33 VCC_17
330u (IFTXX)

POWER
BA29 VCC_SM_28 VCC_AXG_NCTF_29 AB19 V33 VCC_18
AY29 VCC_SM_29 VCC_AXG_NCTF_30 AA19 ESR 15m ohm 1 U33 VCC_19
GFX NCTF

AW29 Y19 C111 1 1 1 AH28

VCC_SM_30 VCC_AXG_NCTF_31 Package(L*W*H)7.3*4.3*1.8 + C112 C113 C114 C115 C116 C117 VCC_20
AV29 VCC_SM_31 VCC_AXG_NCTF_32 W19 AF28 VCC_21
AU29 VCC_SM_32 VCC_AXG_NCTF_33 V19 Rating 2.5V AC28 VCC_22
AT29 U19 330U_D2E_2.5VM 10U_0805_10V4Z 1U_0603_10V4Z 1U_0603_10V4Z AA28
VCC_SM_33 VCC_AXG_NCTF_34 2 2 2 2 @ VCC_23
AR29 VCC_SM_34 VCC_AXG_NCTF_35 AM17 AJ26 VCC_24
AP29 AK17 @ 22U_0805_6.3V6M 4.7U_0805_10V4Z @ 0.1U_0402_16V4Z AG26
VCC_SM_35 VCC_AXG_NCTF_36 VCC_25
VCC_AXG_NCTF_37 AH17 AE26 VCC_26
VCC_AXG_NCTF_38 AG17 AC26 VCC_27
C
AF17 AH25 +1.05VS C
VCC_AXG_NCTF_39 VCC_28
BA36 VCC_SM_36/NC VCC_AXG_NCTF_40 AE17 AG25 VCC_29
BB24 VCC_SM_37/NC VCC_AXG_NCTF_41 AC17 AF25 VCC_30
VCC

BD16 VCC_SM_38/NC VCC_AXG_NCTF_42 AB17 AG24 VCC_31 VCC_NCTF_1 AM32

BB21 VCC_SM_39/NC VCC_AXG_NCTF_43 Y17 AJ23 VCC_32 VCC_NCTF_2 AL32
AW16 VCC_SM_40/NC VCC_AXG_NCTF_44 W17 AH23 VCC_33 VCC_NCTF_3 AK32
AW13 VCC_SM_41/NC VCC_AXG_NCTF_45 V17
+VCC_AXG VCC_AXG: 8700mA AF23 VCC_34 VCC_NCTF_4 AJ32
AT13 VCC_SM_42/NC VCC_AXG_NCTF_46 AM16 T32 VCC_35 VCC_NCTF_5 AH32
AL16 (330UF*2,22UF*1, 10UF*1, 1U*1, 0.47U*1, 0.1UF*2) AG32
VCC_AXG_NCTF_47 VCC_NCTF_6
AK16 330u AE32
POWER

VCC_AXG_NCTF_48 VCC_NCTF_7
VCC_AXG_NCTF_49 AJ16 ESR 15m ohm 1 1 VCC_NCTF_8 AC32
+VCC_AXG AH16 C118 C119 C120 1 C121 1 C122 C123 C124 1 C125 1 C126 AA32
VCC_AXG_NCTF_50 Package(L*W*H)7.3*4.3*1.8 + + R114 VCC_NCTF_9
VCC_AXG_NCTF_51 AG16 VCC_NCTF_10 Y32
VCC_AXG_NCTF_52 AF16 Rating 2.5V VCC_NCTF_11 W32
Y26 AE16 330U_D2E_2.5VM 10U_0805_10V4Z 1U_0603_10V4Z 0.1U_0402_16V4Z 0_0805_5% 1U_0603_10V4Z U32
VCC_AXG_1 VCC_AXG_NCTF_53 GM@ 2 GM@ 2 GM@ 2 GM@ 2 GM@ GM@ GM@ 2 GM@ 2 PM@ @ VCC_NCTF_12
AE25 VCC_AXG_2 VCC_AXG_NCTF_54 AC16 VCC_NCTF_13 AM30
AB25 AB16 330U_D2E_2.5VM 10U_0805_10V4Z 0.47U_0603_16V4Z 0.1U_0402_16V4Z AL30
VCC_AXG_3 VCC_AXG_NCTF_55 VCC_NCTF_14
AA25 VCC_AXG_4 VCC_AXG_NCTF_56 AA16 VCC_NCTF_15 AK30
AE24 VCC_AXG_5 VCC_AXG_NCTF_57 Y16 VCC_NCTF_16 AH30
AC24 VCC_AXG_6 VCC_AXG_NCTF_58 W16 VCC_NCTF_17 AG30
AA24 VCC_AXG_7 VCC_AXG_NCTF_59 V16 VCC_NCTF_18 AF30
Y24 VCC_AXG_8 VCC_AXG_NCTF_60 U16 VCC_NCTF_19 AE30
AE23 AC30

NCTF
VCC_AXG_9 VCC_NCTF_20
AC23 VCC_AXG_10 Add these caps around PCI-E bus of NB VCC_NCTF_21 AB30
AB23 VCC_AXG_11 VCC_NCTF_22 AA30
AA23 +1.05VS Y30
VCC_AXG_12 VCC_NCTF_23
AJ21 VCC_AXG_13 VCC_NCTF_24 W30
AG21 VCC_AXG_14 VCC_NCTF_25 V30
AE21 VCC_AXG_15 1 1 1 1 1 VCC_NCTF_26 U30

VCC
AC21 C763 C764 C765 C766 C767 AL29
VCC_AXG_16 VCC_NCTF_27
AA21 VCC_AXG_17 VCC_NCTF_28 AK29
Y21 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z AJ29
VCC_AXG_18 2 2 2 2 2 VCC_NCTF_29
VCC

B B
AH20 VCC_AXG_19 VCC_NCTF_30 AH29
AF20 VCC_AXG_20 VCC_NCTF_31 AG29
AE20 VCC_AXG_21 VCC_NCTF_32 AE29
AC20 VCC_AXG_22 VCC_NCTF_33 AC29
AB20 VCC_AXG_23 VCC_NCTF_34 AA29
AA20 Y29
GFX

VCC_AXG_24 VCC_NCTF_35
T17 VCC_AXG_25 VCC_NCTF_36 W29
T16 VCC_AXG_26 10/05 This is for GM@ (IFTXX) VCC_NCTF_37 V29
AM15 VCC_AXG_27 VCC_NCTF_38 AL28
AL15 VCC_AXG_28 Remember open stencil at GM@ VCC_NCTF_39 AK28
AE15 VCC_AXG_29 VCC_NCTF_40 AL26
AJ15 VCC_AXG_30 VCC_NCTF_41 AK26
AH15 VCC_AXG_31 VCC_NCTF_42 AK25
AG15 VCC_AXG_32 VCC_NCTF_43 AK24
AF15 VCC_AXG_33 VCC_NCTF_44 AK23
AB15 VCC_AXG_34
AA15 VCC_AXG_35
Y15 +1.05VS +VCC_AXG
VCC_AXG_36 J1
V15 VCC_AXG_37
U15 VCC_AXG_38 1 2
AN14 VCC_AXG_39
AM14 PAD-OPEN 3x3m
VCC_AXG_40 VCCSM_LF1 GM@
U14 AV44
VCC SM LF

VCC_AXG_41 VCC_SM_LF1 VCCSM_LF2

T14 VCC_AXG_42 VCC_SM_LF2 BA37 2 1
AM40 VCCSM_LF3 J5 GM@ JOPEN CANTIGA ES_FCBGA1329
VCC_SM_LF3 VCCSM_LF4 GM@
VCC_SM_LF4 AV21 2 1
AY5 VCCSM_LF5 J6 GM@ JOPEN
@ VCC_SM_LF5 VCCSM_LF6
T22 PAD AJ14 VCC_AXG_SENSE VCC_SM_LF6 AM10 2 1
T23 PAD @ AH14 BB13 VCCSM_LF7 J7 GM@ JOPEN
VSS_AXG_SENSE VCC_SM_LF7
1 1 1 1
C127 C128 C129 C130 C131 C132 C133

A 0.1U_0402_16V4Z 0.22U_0402_6.3V6K 0.47U_0603_16V4Z 1U_0603_10V4Z A

2 2 2 2
0.1U_0402_16V4Z 0.22U_0402_6.3V6K 1U_0603_10V4Z
CANTIGA ES_FCBGA1329 1/25 Change J5, J6, J7 from 43x79 to 43x39
GM@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/18 Deciphered Date 2008/8/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cantiga GMCH(5/7)-GTL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JHXXX M/B LA-4241P Schematic
Date: Tuesday, June 03, 2008 Sheet 11 of 49
5 4 3 2 1
 5 4 3 2 1

+1.05VS_DPLLA
Checklist 220u ESR max 15m ohm 220u
220u ESR 15m ohm
+1.05VS_HPLL
L1 1 ESR 15m ohm Package(L*W*H)7.3*4.3*1.9
+1.05VS 2 @
+1.05VS L2 1 2 10U_FLC-453232-100K_0.25A_10%
0.1U_0402_16V4Z
1 10U_0805_10V4Z Package(L*W*H)7.3*4.3*1.9 Rating 4V

1
MBK1608121YZF_0603 1 1 10uH 10% 201005-548 1 1 Rating 4V
VCCA_HPLL: 24mA C134 C135 GM@ L55 1 2 C136 + C137 R115 C705 U3H VTT: 852mA
MBK1608121YZF_0603 @ GM@ PM@ GM@ +1.05VS
(4.7UF*1, 0.1UF*1) 852mA (270UF*1, 4.7UF*2, 2.2UF*1, 0.47UF*1)
4.7U_0805_10V4Z 220U_D2_4VM_R15
2 2 2 2 2
0_0402_5%
Please check Power VCCA_DPLLA 73mA U13

2
0.1U_0402_16V4Z VTT_1
source if want VCCA_DPLLB: 64.8mA +3VS_CRTDAC B27 VCCA_CRT_DAC_1 VTT_2 T13 1
Please check Power A26 VCCA_CRT_DAC_2 VTT_3 U12 1 1 1
support IAMT (220UF*1, 0.1UF*1) T12 C138 + C139 C140 C141 C145
+1.05VS_MPLL source if want GM@ L56 VTT_4
1 2 VTT_5 U11
120Ohm@100MHz support IAMT MBK1608121YZF_0603 +1.05VS_DPLLB
5mA T11 220U_D2_4VM_R15 4.7U_0805_10V4Z 0.47U_0603_16V4Z
VTT_6 2 2 2 2

CRT
D L3 1 D
2 +3VS_DACBG A25 VCCA_DAC_BG VTT_7 U10
MBK1608121YZF_0603 1 L4 1 2 @ T10 4.7U_0805_10V4Z 2.2U_0603_6.3V6K
VTT_8

1
VCCA_MPLL: 139.2mA C146 10U_FLC-453232-100K_0.25A_10%
1 0.1U_0402_16V4Z 10U_0805_10V4Z B25 U9
VSSA_DAC_BG VTT_9

1
R116 10uH 10% 201005-548 1 1 T9
(22UF*1, 0.1UF*1) 0.1U_0402_16V4Z C142 + C143 R117 C706 VTT_10
U8
1_0603_1% 2 @ GM@ PM@ GM@ VTT_11
64.8mA VTT_12 T8

VTT
220u 220U_D2_4VM_R15 +1.05VS_DPLLA F47 U7

2
2 2 2 VCCA_DPLLA VTT_13
1 ESR 15m ohm T7

2
C147 0_0402_5% VTT_14
+1.05VS_DPLLB L48 VCCA_DPLLB VTT_15 U6
Package(L*W*H)7.3*4.3*1.9 T6
24mA VTT_16

PLL
10U_0805_10V4Z Rating 4V +1.05VS_HPLL AD1 U5
2 R118 VCCA_HPLL VTT_17
+1.8V_TX_LVDS VTT_18 T5
@ 0_0603_5% 1 AE1 139.2mA V3
+1.05VS_MPLL VCCA_MPLL VTT_19
+3VS 1 2 C144 U3
GM@ VTT_20
+VCCA_PEG_BG
VCCA_LVDS: 13.2mA 13.2mA VTT_21 V2

A PEG A LVDS
R119 1000P_0402_50V7K J48 U2 Please check Power
0_0603_5% 2 (1000PF*1) VCCA_LVDS VTT_22
T2
VTT_23 source if want
+3VS_CRTDAC +1.5VS 1 2 J47 VSSA_LVDS VTT_24 V1
+1.05VS_AXF
VCC_AXF: 321.35mA support IAMT
VCCA_CRT_DAC: 73mA (0.1UF*1, 0.01UF*1) 1 VCCA_PEG_BG: 0.414mA VTT_25 U1 (10UF*1, 1UF*1)
Please check Power C148 0.414mA
1 2
(0.1UF*1) AD48 1 2
+3VS_TV_CRT_DAC
R120
source if want 0.1U_0402_16V4Z VCCA_PEG_BG R122
+1.05VS

1
0_0603_5% 1 1
support IAMT 2
1 1 0_0603_5%
GM@ C149 C150 R121 50mA C152 C153
GM@ GM@ 0_0402_5% AA48 @
0.1U_0402_16V4Z PM@ L5 1 +1.05VS_A_PEGPLL VCCA_PEG_PLL 10U_0805_6.3V6M 1U_0402_6.3V4Z
+1.05VS 2
2 2 MBK1608221YZF_0603 2 2
1 VCCA_PEG_PLL: 50mA
2
0.01U_0402_16V7K C154 2 1 1 2 C151
R123 (10UF*1,0.1UF*1)
Close to Ball A26, B27 10U_0805_10V4Z 1_0402_1% 0.1U_0402_16V4Z 720mA VCC_SM_CK: 124mA
2
AR20 VCCA_SM_1
POWER +1.8V_SM_CK
( 10UF*1,0.1UF*1) 1uH 30%
220u +1.05VS_A_SM VCCA_SM: AP20
C VCCA_SM_2 C
ESR 15m ohm (22UF*2, 4.7UF*1, 1UF*1) AN20 VCCA_SM_3 321.35mA 1 2 +1.8V
+1.05VS 1 2 AR17 L6
Package(L*W*H)7.3*4.3*1.9 VCCA_SM_4

A SM
NO_STUFF
1 R124 1 1 1 1 AP17 1 MBK1608121YZF_0603
0_0603_5% C156 C157 C158 C159 VCCA_SM_5 C160
Rating 4V AN17 VCCA_SM_6 VCC_AXF_1 B22

AXF
Please check Power C155 + AT16 B21 1 2 1 2
22U_0805_6.3V6M 4.7U_0805_10V4Z VCCA_SM_7 VCC_AXF_2 0.1U_0402_16V4Z R125 C161
source if want AR16 VCCA_SM_8 VCC_AXF_3 A21
220U_D2_4VM_R15 @ 2 2 2 2 2 1_0402_1% 10U_0805_10V4Z
AP16 VCCA_SM_9
support IAMT 2 10U_0805_10V4Z 1U_0402_6.3V4Z
124mA
Please check Power
source if want VCC_SM_CK_1 BF21

SM CK
VCCA_DAC_BG: 2.6833333mA support IAMT +1.05VS_A_SM_CK VCC_SM_CK_2 BH20
+1.8V_TX_LVDS
(0.1UF*1, 0.01UF*1) +3VS_DACBG
VCCA_SM_CK: 24mA VCC_SM_CK_3 BG20 +1.8V_TX_LVDS: 118.8mA
(22UF*1, 2.2UF*1,0.1UF*1) 26mA VCC_SM_CK_4 BF20 (22UF*1, 1000PF*1) 0.1uH 20%
+1.05VS 1 2 AP28 VCCA_SM_CK_1 1 2 +1.8V
+3VS_TV_CRT_DAC 1 2 R126 1 1 AN28 L7 GM@ MBK1608121YZF_0603
VCCA_SM_CK_2

1
R127 0_0603_5% C162 C167 C163 AP25 1 1
VCCA_SM_CK_3
1

0_0603_5% 1 1 1 @ AN25 118.8mA R129 C168 C169

GM@ C164 C165 C166 R128 2.2U_0603_6.3V6K 0.1U_0402_16V4Z VCCA_SM_CK_4 PM@ GM@ GM@
AN24 VCCA_SM_CK_5 VCC_TX_LVDS K47
2 2

A CK
GM@ GM@ GM@ 0_0402_5% AM28 0_0402_5% 1000P_0402_50V7K 10U_0805_10V4Z
0.1U_0402_16V4Z 10U_0805_10V4Z PM@ 10U_0805_10V4Z VCCA_SM_CK_NCTF_1 2 2
AM26 105.3mA VCC_HV: 105.3mA

2
2 2 2 VCCA_SM_CK_NCTF_2
AM25 (0.1UF*1) CRB use 0.1uH, should we?
2

0.01U_0402_16V7K VCCA_SM_CK_NCTF_3
NO_STUFF AL25 VCCA_SM_CK_NCTF_4 VCC_HV_1 C35 +3VS
AM24 VCCA_SM_CK_NCTF_5 VCC_HV_2 B35 1 Please check Power

HV
Close to Ball A25 AL24 A35 C170
VCCA_SM_CK_NCTF_6 VCC_HV_3 source if want
AM23 VCCA_SM_CK_NCTF_7
AL23 1782mA 0.1U_0402_16V4Z support IAMT
VCCA_SM_CK_NCTF_8 2
1 2
VCCA_TV_DAC: 40mA (0.1UF*1, VCC_PEG_1 V48 +1.05VS_PEG: 1782mA +1.05VS_PEG R733
+3VS 1 2 U48 0_0805_5%
0.01UF*1 for each DAC) +3VS_TV_CRT_DAC VCC_PEG_2 (220UF*1, 22UF*1, 4.7UF*1)

PEG
R131 V47 1 2 +1.05VS
0_0603_5% VCC_PEG_3 R130
B
79mA VCC_PEG_4 U47 1
B
GM@ L8 1 2 +3VS_TV_CRT_DAC B24 U46 1 1 0_0805_5%
MBK1608221YZF_0603 VCCA_TV_DAC_1 VCC_PEG_5 C171 C172 + C173
A24 VCCA_TV_DAC_2
1

TV
180Ohm@100MHz GM@ 1 1
C174 C175 R133 +1.5VS_HDA VCCD_HDA: 50mA 456mA 2 2 2
GM@ GM@ 0_0402_5% 50mA 10U_0805_10V4Z 220u
0.1U_0402_16V4Z PM@ 1 2
(0.1UF*1) A32 AH48 4.7U_0805_10V4Z 220U_V_6.3VM_R15
2 2 +1.5VS VCC_HDA VCC_DMI_1 ESR 15m ohm

HDA
R132 1 AF48
2

VCC_DMI_2
1

+1.05VS_DMI Package(L*W*H)7.3*6.6*5.9

DMI
0.01U_0402_16V7K 0_0603_5% C176 Close to A32 AH47
GM@ R134 GM@ VCC_DMI_3
VCC_DMI_4 AG47 Rating 6.3V
0_0402_5% 0.1U_0402_16V4Z 35mA 1 2 +1.05VS_PEG
PM@ 2 R135
+1.5VS_TVDAC M25 VCCD_TVDAC VCC_DMI: 456mA 1

D TV/CRT
C177 0_0805_5%
(0.1UF*1)
2

L28 1mA
+1.5VS_QDAC VCCD_QDAC 0.1U_0402_16V4Z
2
VCCD_HPLL: 157.2mA (0.1UF*1) 157.2mA
VCCD_TVDAC: 58.696mA +1.5VS_TVDAC +1.05VS AF1 VCCD_HPLL
1 A8 VTTLF_CAP1
(0.1UF*1, 0.01UF*1) C178 +1.05VS_A_PEGPLL AA47 50mA VTTLF1
L1 VTTLF_CAP2
VCCD_PEG_PLL VTTLF2

VTTLF
+1.5VS 1 2 Please check Power 1 VTTLF3 AB2 VTTLF_CAP3 CRB have reserved another filter for +VCC_DMI
R136 1 1 0.1U_0402_16V4Z C179 Close to AA47 60.31mA
0_0603_5% C183 C184
source if want 2 separated from +1.05VS_PEG, should we?
Also power for internal M38 VCCD_LVDS_1 1 1 1
support IAMT

LVDS
0.1U_0402_16V4Z L37 C180 C181 C182
0.1U_0402_16V4Z
Thermal Sensor 2 VCCD_LVDS_2
2 2
Close to AF1
VCCD_PEG_PLL: 50mA 0.47U_0603_16V4Z 0.47U_0603_16V4Z
0.022U_0402_16V7K 2 2 2
(0.1UF*1) CANTIGA ES_FCBGA1329 0.47U_0603_16V4Z
+1.8V 1 2 +1.8V_LVDS GM@
R137
1

0_0402_5% 1
+3VS copy G913CF_SOT23-5 GM@ C185 R138
+1.5VS GM@ 0_0402_5%
Footprint PM@
TV+CRT use Ivccd_qdac = 0.5u+0.5u =1mA
A 2 A
VCCD_QDAC: 48.363mA R139
2

1 2 +1.5VS_QDAC 1U_0402_6.3V4Z D3
U36 @ (0.1UF*1, 0.01UF*1) 2 1 1 @ 2
+1.05VS +3VS
1 4 +1.5VS_LDO R681 0_0402_5% L9 1 2 VCCD_LVDS: 60.31mA
Vin Vout MBK1608221YZF_0603 @ 10_0603_5%
1 1 (1UF*1)
3 1 @ 2 180Ohm@100MHz C186 C187 CH751H-40PT_SOD323-2
SHDN
1
C707 2 GND SET 5 R679 2K_0402_1% C710 0.1U_0402_16V4Z
@ @ 2 2 Security Classification Compal Secret Data Compal Electronics, Inc.
1U_0402_6.3V4Z G916T1UF 1 @ 2 4.7U_0805_10V4Z 0.01U_0402_16V7K Issued Date 2007/08/18 2008/8/18 Title
2 Deciphered Date
R680 10K_0402_1%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cantiga GMCH(6/7)-GTL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JHXXX M/B LA-4241P Schematic 0.4
Date: Tuesday, June 03, 2008 Sheet 12 of 49
5 4 3 2 1
 5 4 3 2 1

U3I U3J

AU48 VSS_1 VSS_100 AM36 BG21 VSS_199 VSS_297 AH8

AR48 VSS_2 VSS_101 AE36 L12 VSS_200 VSS_298 Y8
AL48 VSS_3 VSS_102 P36 AW21 VSS_201 VSS_299 L8
BB47 VSS_4 VSS_103 L36 AU21 VSS_202 VSS_300 E8
AW47 VSS_5 VSS_104 J36 AP21 VSS_203 VSS_301 B8
AN47 VSS_6 VSS_105 F36 AN21 VSS_204 VSS_302 AY7
AJ47 VSS_7 VSS_106 B36 AH21 VSS_205 VSS_303 AU7
AF47 VSS_8 VSS_107 AH35 AF21 VSS_206 VSS_304 AN7
AD47 VSS_9 VSS_108 AA35 AB21 VSS_207 VSS_305 AJ7
AB47 VSS_10 VSS_109 Y35 R21 VSS_208 VSS_306 AE7
Y47 VSS_11 VSS_110 U35 M21 VSS_209 VSS_307 AA7
T47 VSS_12 VSS_111 T35 J21 VSS_210 VSS_308 N7
D D
N47 VSS_13 VSS_112 BF34 G21 VSS_211 VSS_309 J7
L47 VSS_14 VSS_113 AM34 BC20 VSS_212 VSS_310 BG6
G47 VSS_15 VSS_114 AJ34 BA20 VSS_213 VSS_311 BD6
BD46 VSS_16 VSS_115 AF34 AW20 VSS_214 VSS_312 AV6
BA46 VSS_17 VSS_116 AE34 AT20 VSS_215 VSS_313 AT6
AY46 VSS_18 VSS_117 W34 AJ20 VSS_216 VSS_314 AM6
AV46 VSS_19 VSS_118 B34 AG20 VSS_217 VSS_315 M6
AR46 VSS_20 VSS_119 A34 Y20 VSS_218 VSS_316 C6
AM46 VSS_21 VSS_120 BG33 N20 VSS_219 VSS_317 BA5
V46 VSS_22 VSS_121 BC33 K20 VSS_220 VSS_318 AH5
R46 VSS_23 VSS_122 BA33 F20 VSS_221 VSS_319 AD5
P46 VSS_24 VSS_123 AV33 C20 VSS_222 VSS_320 Y5
H46 VSS_25 VSS_124 AR33 A20 VSS_223 VSS_321 L5
F46 VSS_26 VSS_125 AL33 BG19 VSS_224 VSS_322 J5
BF44 VSS_27 VSS_126 AH33 A18 VSS_225 VSS_323 H5
AH44 VSS_28 VSS_127 AB33 BG17 VSS_226 VSS_324 F5
AD44 VSS_29 VSS_128 P33 BC17 VSS_227 VSS_325 BE4
AA44 VSS_30 VSS_129 L33 AW17 VSS_228
Y44 VSS_31 VSS_130 H33 AT17 VSS_229 VSS_327 BC3
U44 VSS_32 VSS_131 N32 R17 VSS_230 VSS_328 AV3
T44 VSS_33 VSS_132 K32 M17 VSS_231 VSS_329 AL3
M44 VSS_34 VSS_133 F32 H17 VSS_232 VSS_330 R3
F44
BC43
VSS_35
VSS_36
VSS_134
VSS_135
C32
A31
C17 VSS_233 VSS VSS_331
VSS_332
P3
F3
AV43 VSS_37 VSS_136 AN29 BA16 VSS_235 VSS_333 BA2
AU43 VSS_38 VSS_137 T29 VSS_334 AW2
AM43 VSS_39 VSS_138 N29 AU16 VSS_237 VSS_335 AU2
J43 VSS_40 VSS_139 K29 AN16 VSS_238 VSS_336 AR2
C43 VSS_41 VSS_140 H29 N16 VSS_239 VSS_337 AP2
BG42
AY42
VSS_42
VSS_43
VSS VSS_141
VSS_142
F29
A29
K16
G16
VSS_240
VSS_241
VSS_338
VSS_339
AJ2
AH2
AT42 VSS_44 VSS_143 BG28 E16 VSS_242 VSS_340 AF2
C C
AN42 VSS_45 VSS_144 BD28 BG15 VSS_243 VSS_341 AE2
AJ42 VSS_46 VSS_145 BA28 AC15 VSS_244 VSS_342 AD2
AE42 VSS_47 VSS_146 AV28 W15 VSS_245 VSS_343 AC2
N42 VSS_48 VSS_147 AT28 A15 VSS_246 VSS_344 Y2
L42 VSS_49 VSS_148 AR28 BG14 VSS_247 VSS_345 M2
BD41 VSS_50 VSS_149 AJ28 AA14 VSS_248 VSS_346 K2
AU41 VSS_51 VSS_150 AG28 C14 VSS_249 VSS_347 AM1
AM41 VSS_52 VSS_151 AE28 BG13 VSS_250 VSS_348 AA1
AH41 VSS_53 VSS_152 AB28 BC13 VSS_251 VSS_349 P1
AD41 VSS_54 VSS_153 Y28 BA13 VSS_252 VSS_350 H1
AA41 VSS_55 VSS_154 P28
Y41 VSS_56 VSS_155 K28 VSS_351 U24
U41 VSS_57 VSS_156 H28 AN13 VSS_255 VSS_352 U28
T41 VSS_58 VSS_157 F28 AJ13 VSS_256 VSS_353 U25
M41 VSS_59 VSS_158 C28 AE13 VSS_257 VSS_354 U29
G41 VSS_60 VSS_159 BF26 N13 VSS_258
B41 VSS_61 VSS_160 AH26 L13 VSS_259 VSS_NCTF_1 AF32
BG40 VSS_62 VSS_161 AF26 G13 VSS_260 VSS_NCTF_2 AB32
BB40 VSS_63 VSS_162 AB26 E13 VSS_261 VSS_NCTF_3 V32
AV40 VSS_64 VSS_163 AA26 BF12 VSS_262 VSS_NCTF_4 AJ30
AN40 VSS_65 VSS_164 C26 AV12 VSS_263 VSS_NCTF_5 AM29
H40 VSS_66 VSS_165 B26 AT12 VSS_264 VSS_NCTF_6 AF29
E40 VSS_67 VSS_166 BH25 AM12 VSS_265 VSS_NCTF_7 AB29
AT39 BD25 AA12 U26

VSS NCTF
VSS_68 VSS_167 VSS_266 VSS_NCTF_8
AM39 VSS_69 VSS_168 BB25 J12 VSS_267 VSS_NCTF_9 U23
AJ39 VSS_70 VSS_169 AV25 A12 VSS_268 VSS_NCTF_10 AL20
AE39 VSS_71 VSS_170 AR25 BD11 VSS_269 VSS_NCTF_11 V20
N39 VSS_72 VSS_171 AJ25 BB11 VSS_270 VSS_NCTF_12 AC19
L39 VSS_73 VSS_172 AC25 AY11 VSS_271 VSS_NCTF_13 AL17
B39 VSS_74 VSS_173 Y25 AN11 VSS_272 VSS_NCTF_14 AJ17
BH38 VSS_75 VSS_174 N25 AH11 VSS_273 VSS_NCTF_15 AA17
BC38 VSS_76 VSS_175 L25 VSS_NCTF_16 U17
B B
BA38 VSS_77 VSS_176 J25 Y11 VSS_275
AU38 VSS_78 VSS_177 G25 N11 VSS_276
AH38 VSS_79 VSS_178 E25 G11 VSS_277 VSS_SCB_1 BH48
AD38 VSS_80 VSS_179 BF24 C11 VSS_278 VSS_SCB_2 BH1
AA38 VSS_81 VSS_180 AD12 BG10 VSS_279 VSS_SCB_3 A48
Y38 AY24 AV10 C1
VSS SCB
VSS_82 VSS_181 VSS_280 VSS_SCB_4
U38 VSS_83 VSS_182 AT24 AT10 VSS_281 VSS_SCB_5 A3
T38 VSS_84 VSS_183 AJ24 AJ10 VSS_282
J38 VSS_85 VSS_184 AH24 AE10 VSS_283
F38 VSS_86 VSS_185 AF24 AA10 VSS_284
C38 VSS_87 VSS_186 AB24 M10 VSS_285
BF37 VSS_88 VSS_187 R24 BF9 VSS_286 NC_26 E1
BB37 VSS_89 VSS_188 L24 BC9 VSS_287 NC_27 D2
AW37 VSS_90 VSS_189 K24 AN9 VSS_288 NC_28 C3
AT37 VSS_91 VSS_190 J24 AM9 VSS_289 NC_29 B4
AN37 VSS_92 VSS_191 G24 AD9 VSS_290 NC_30 A5
AJ37 VSS_93 VSS_192 F24 G9 VSS_291 NC_31 A6
H37 VSS_94 VSS_193 E24 B9 VSS_292 NC_32 A43
C37 VSS_95 VSS_194 BH23 BH8 VSS_293 NC_33 A44
BG36 VSS_96 VSS_195 AG23 BB8 VSS_294 NC_34 B45
BD36 Y23 AV8 C46
NC

VSS_97 VSS_196 VSS_295 NC_35

AK15 VSS_98 VSS_197 B23 AT8 VSS_296 NC_36 D47
AU36 VSS_99 VSS_198 A23 NC_37 B47
VSS_199 AJ6 NC_38 A46
NC_39 F48
GM@ CANTIGA ES_FCBGA1329 E48
NC_40
NC_41 C48
NC_42 B48

GM@ CANTIGA ES_FCBGA1329

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/18 Deciphered Date 2008/8/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cantiga GMCH(7/7)-GTL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JHXXX M/B LA-4241P Schematic
Date: Tuesday, June 03, 2008 Sheet 13 of 49
5 4 3 2 1
 5 4 3 2 1

+1.8V +1.8V 11/12 Change to HEL80's

JDIMM1 +1.8V
+DIMM_VREF 1 VREF VSS 2
3 4 DDRA_SDQ4
VSS DQ4

1
DDRA_SDQ0 5 6 DDRA_SDQ5
DDRA_SDQ1 DQ0 DQ5 R141
7 DQ1 VSS 8
9 10 DDRA_SDM0 +DIMM_VREF
DDRA_SDQS0# VSS DM0 1K_0402_1%
<9> DDRA_SDQS0#
DDRA_SDQS0
11 DQS0# VSS 12
DDRA_SDQ6
20mils
<9> DDRA_SDQS0 13 14

2
DQS0 DQ6 DDRA_SDQ7
15 VSS DQ7 16 +DIMM_VREF
DDRA_SDQ2 17 18 1
DQ2 VSS

1
DDRA_SDQ3 19 20 DDRA_SDQ12 C188 C189 1
D DQ3 DQ12 DDRA_SDQ13 R142 C190 D
21 VSS DQ13 22
DDRA_SDQ8 23 24 0.1U_0402_16V4Z
DDRA_SDQ9 DQ8 VSS DDRA_SDM1 2 2.2U_0603_6.3V6K 1K_0402_1% 220P_0402_50V7K
25 DQ9 DM1 26
2 @
27 28

2
DDRA_SDQS1# VSS VSS
<9> DDRA_SDQS1# 29 DQS1# CK0 30 DDRA_CLK0 <8>
<9> DDRA_SDQS1 DDRA_SDQS1 31 32
DQS1 CK0# DDRA_CLK0# <8>
33 VSS VSS 34
DDRA_SDQ10 35 36 DDRA_SDQ14
DDRA_SDQ11 DQ10 DQ14 DDRA_SDQ15
37 DQ11 DQ15 38 330u
39 VSS VSS 40 ESR 15m ohm
Package(L*W*H)7.3*4.3*1.8
41 VSS VSS 42 Rating 2.5V
DDRA_SDQ16 43 44 DDRA_SDQ20
DDRA_SDQ17 DQ16 DQ20 DDRA_SDQ21
45 DQ17 DQ21 46
47 VSS VSS 48
<9> DDRA_SDQS2# DDRA_SDQS2# 49 50 R143 1 2 0_0402_5%
DQS2# NC PM_EXTTS#0 <8> DDRA_SMA[0..14]
<9> DDRA_SDQS2 DDRA_SDQS2 51 52 DDRA_SDM2 Layout Note:
DQS2 DM2 <9> DDRA_SMA[0..14]
53 VSS VSS 54
DDRA_SDQ18 55 56 DDRA_SDQ22 <9> DDRA_SDQ[0..63]
DDRA_SDQ[0..63] Place near JP34
DDRA_SDQ19 DQ18 DQ22 DDRA_SDQ23
57 DQ19 DQ23 58
59 60 DDRA_SDM[0..7] +1.8V
VSS VSS <9> DDRA_SDM[0..7]
DDRA_SDQ24 61 62 DDRA_SDQ28
DDRA_SDQ25 DQ24 DQ28 DDRA_SDQ29
63 DQ25 DQ29 64
65 VSS VSS 66
DDRA_SDM3 67 68 DDRA_SDQS3# 1
DM3 DQS3# DDRA_SDQS3# <9>
EC_TX_P80_DATA 69 70 DDRA_SDQS3 C191 C192 C193 C194 C195 C196
<15,32> EC_TX_P80_DATA NC DQS3 DDRA_SDQS3 <9> +
71 72 @
DDRA_SDQ26 VSS VSS DDRA_SDQ30 2.2U_0603_6.3V6K 2.2U_0603_6.3V6K 2.2U_0603_6.3V6K
73 DQ26 DQ30 74
DDRA_SDQ27 75 76 DDRA_SDQ31 2.2U_0603_6.3V6K 2.2U_0603_6.3V6K 330U_D2E_2.5VM
DQ27 DQ31 +0.9VS 2
77 VSS VSS 78
DDRA_CKE0 79 80 DDRA_CKE1
C <8> DDRA_CKE0 CKE0 NC/CKE1 DDRA_CKE1 <8> C
81 82 DDRA_CKE0 1 4
EC_RX_P80_CLK VDD VDD DDRA_SBS2
<15,32> EC_RX_P80_CLK 83 NC NC/A15 84 2 3
DDRA_SBS2 85 86 DDRA_SMA14 RP1 56_0404_4P2R_5%
<9> DDRA_SBS2 BA2 NC/A14 +1.8V
87 VDD VDD 88
DDRA_SMA12 89 90 DDRA_SMA11 DDRA_SMA12 1 4
DDRA_SMA9 A12 A11 DDRA_SMA7 DDRA_SMA9
91 A9 A7 92 2 3
DDRA_SMA8 93 94 DDRA_SMA6 RP2 56_0404_4P2R_5%
A8 A6
95 VDD VDD 96 1 1 1 1
DDRA_SMA5 97 98 DDRA_SMA4 DDRA_SMA8 1 4 C197 C198 C199 C200
DDRA_SMA3 A5 A4 DDRA_SMA2 DDRA_SMA5
99 A3 A2 100 2 3
DDRA_SMA1 101 102 DDRA_SMA0 RP3 56_0404_4P2R_5% 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
A1 A0 2 2 2 2
103 VDD VDD 104
DDRA_SMA10 105 106 DDRA_SBS1 DDRA_SMA3 1 4
A10/AP BA1 DDRA_SBS1 <9>
DDRA_SBS0 107 108 DDRA_SRAS# DDRA_SMA1 2 3
<9> DDRA_SBS0 BA0 RAS# DDRA_SRAS# <9>
DDRA_SWE# 109 110 DDRA_SCS0# RP4 56_0404_4P2R_5%
<9> DDRA_SWE# WE# S0# DDRA_SCS0# <8>
111 VDD VDD 112
DDRA_SCAS# 113 114 DDRA_ODT0 DDRA_SMA10 1 4
<9> DDRA_SCAS# CAS# ODT0 DDRA_ODT0 <8>
DDRA_SCS1# 115 116 DDRA_SMA13 DDRA_SBS0 2 3
<8> DDRA_SCS1# NC/S1# NC/A13
117 118 RP5 56_0404_4P2R_5%
DDRA_ODT1 VDD VDD +0.9VS
<8> DDRA_ODT1 119 NC/ODT1 NC 120
121 122 DDRA_SWE# 1 4
DDRA_SDQ32 VSS VSS DDRA_SDQ36 DDRA_SCAS#
123 DQ32 DQ36 124 2 3
DDRA_SDQ33 125 126 DDRA_SDQ37 RP6 56_0404_4P2R_5%
DQ33 DQ37
127 VSS VSS 128 1 1 1 1 1
<9> DDRA_SDQS4# DDRA_SDQS4# 129 130 DDRA_SDM4 DDRA_SCS1# 1 4 C201 C202 C203 C204 C205
DDRA_SDQS4 DQS4# DM4 DDRA_ODT1
<9> DDRA_SDQS4 131 DQS4 VSS 132 2 3
133 134 DDRA_SDQ38 RP7 56_0404_4P2R_5% 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
DDRA_SDQ34 VSS DQ38 DDRA_SDQ39 2 2 2 2 2
135 DQ34 DQ39 136
DDRA_SDQ35 137 138
DQ35 VSS DDRA_SDQ44
139 VSS DQ44 140
DDRA_SDQ40 141 142 DDRA_SDQ45 DDRA_SMA11 1 4
DDRA_SDQ41 DQ40 DQ45 DDRA_SMA14
143 DQ41 VSS 144 2 3
B
145 146 DDRA_SDQS5# RP8 56_0404_4P2R_5% +0.9VS B
VSS DQS5# DDRA_SDQS5# <9>
DDRA_SDM5 147 148 DDRA_SDQS5
DM5 DQS5 DDRA_SDQS5 <9>
149 150 DDRA_SMA6 1 4
DDRA_SDQ42 VSS VSS DDRA_SDQ46 DDRA_SMA7
151 DQ42 DQ46 152 2 3
DDRA_SDQ43 153 154 DDRA_SDQ47 RP9 56_0404_4P2R_5% 1 1 1 1 1
DQ43 DQ47 C206 C207 C208 C209 C210
155 VSS VSS 156
DDRA_SDQ48 157 158 DDRA_SDQ52 DDRA_SMA2 1 4
DDRA_SDQ49 DQ48 DQ52 DDRA_SDQ53 DDRA_SMA4 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
159 DQ49 DQ53 160 2 3
EC_RX_P80_CLK R144 1 2 2 2 2 2
2 0_0402_5% 161 VSS VSS 162 RP10 56_0404_4P2R_5%
EC_RX_P80_CLK_R 163 164
<15> EC_RX_P80_CLK_R NC,TEST CK1 DDRA_CLK1 <8>
165 166 DDRA_SBS1 1 4
VSS CK1# DDRA_CLK1# <8>
<9> DDRA_SDQS6# DDRA_SDQS6# 167 168 DDRA_SMA0 2 3
DDRA_SDQS6 DQS6# VSS DDRA_SDM6 RP11 56_0404_4P2R_5%
<9> DDRA_SDQS6 169 DQS6 DM6 170
171 172 +0.9VS
DDRA_SDQ50 VSS VSS DDRA_SDQ54 DDRA_SCS0#
173 DQ50 DQ54 174 1 4
DDRA_SDQ51 175 176 DDRA_SDQ55 DDRA_SRAS# 2 3
DQ51 DQ55 RP12 56_0404_4P2R_5%
177 VSS VSS 178
DDRA_SDQ56 179 180 DDRA_SDQ60 1 1 1 1
DDRA_SDQ57 DQ56 DQ60 DDRA_SDQ61 DDRA_SMA13 C211 C212 C213 C702
181 DQ57 DQ61 182 1 4
183 184 DDRA_ODT0 2 3
DDRA_SDM7 VSS VSS DDRA_SDQS7# RP13 56_0404_4P2R_5% 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
185 DM7 DQS7# 186 DDRA_SDQS7# <9>
DDRA_SDQS7 2 2 2 2
187 VSS DQS7 188 DDRA_SDQS7 <9>
DDRA_SDQ58 189 190 DDRA_CKE1 1 2
DDRA_SDQ59 DQ58 VSS DDRA_SDQ62 R145 56_0402_5%
191 DQ59 DQ62 192
193 194 DDRA_SDQ63
D_CK_SDATA VSS DQ63
<15,16> D_CK_SDATA 195 SDA VSS 196
<15,16> D_CK_SCLK D_CK_SCLK 197 198 R146 1 2 10K_0402_5%
SCL SA0 R147 1
+3VS 199 VDDSPD SA1 200 2 10K_0402_5%
Layout Note:
FOX_ASOA426-M2RN-7F
Place these resistor
closely JP35,all Layout Note:
CONN@
A +3VS trace length Max=1.5" Place one cap close to every 2 pullup A

resistors terminated to +0.9VS

DIMM1 STD H:5.2mm (BOT)
1
C214 C215

0.1U_0402_16V4Z
2.2U_0603_6.3V6K 2
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/08/18 Deciphered Date 2008/8/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRII-SODIMM1
Size Document Number Rev
12/22 Change from 0805 to 0603 (IFTXX) AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JHXXX M/B LA-4241P Schematic
Date: Wednesday, May 28, 2008 Sheet 14 of 49
5 4 3 2 1
 A B C D E

11/12 Change DIMM1 as HEL80's

+1.8V +1.8V
+DIMM_VREF
JDIMM2
+DIMM_VREF 1 VREF VSS 2
3 4 DDRB_SDQ4
DDRB_SDQ0 VSS DQ4 DDRB_SDQ5 DDRB_SMA[0..14]
5 DQ0 DQ5 6 <9> DDRB_SMA[0..14] 1
DDRB_SDQ1 7 8 C216 C217
DQ1 VSS DDRB_SDM0 DDRB_SDQ[0..63]
9 VSS DM0 10 <9> DDRB_SDQ[0..63]
<9> DDRB_SDQS0# DDRB_SDQS0# 11 12 2.2U_0603_6.3V6K 0.1U_0402_16V4Z
1 DDRB_SDQS0 DQS0# VSS DDRB_SDQ6 DDRB_SDM[0..7] 2 1
<9> DDRB_SDQS0 13 DQS0 DQ6 14 <9> DDRB_SDM[0..7]
15 16 DDRB_SDQ7
DDRB_SDQ2 VSS DQ7
17 DQ2 VSS 18
DDRB_SDQ3 19 20 DDRB_SDQ12
DQ3 DQ12 DDRB_SDQ13
21 VSS DQ13 22
DDRB_SDQ8 23 24
DDRB_SDQ9 DQ8 VSS DDRB_SDM1
25 DQ9 DM1 26
27 VSS VSS 28
<9> DDRB_SDQS1# DDRB_SDQS1# 29 30
DQS1# CK0 DDRB_CLK0 <8>
<9> DDRB_SDQS1 DDRB_SDQS1 31 32
DQS1 CK0# DDRB_CLK0# <8>
33 VSS VSS 34
DDRB_SDQ10 35 36 DDRB_SDQ14
DDRB_SDQ11 DQ10 DQ14 DDRB_SDQ15
37 DQ11 DQ15 38
39 VSS VSS 40 330u
ESR 15m ohm
41 42 Package(L*W*H)7.3*4.3*1.8
DDRB_SDQ16 VSS VSS DDRB_SDQ20
43 DQ16 DQ20 44 Rating 2.5V
DDRB_SDQ17 45 46 DDRB_SDQ21
DQ17 DQ21 0_0402_5%
47 VSS VSS 48
<9> DDRB_SDQS2# DDRB_SDQS2# 49 50 R148 1 2
DQS2# NC PM_EXTTS#1 <8>
<9> DDRB_SDQS2 DDRB_SDQS2 51 52 DDRB_SDM2 Layout Note:
DQS2 DM2
53 VSS VSS 54
DDRB_SDQ18 55 56 DDRB_SDQ22 Place near JP35
DDRB_SDQ19 DQ18 DQ22 DDRB_SDQ23 +1.8V
57 DQ19 DQ23 58
59 VSS VSS 60
DDRB_SDQ24 61 62 DDRB_SDQ28
DDRB_SDQ25 DQ24 DQ28 DDRB_SDQ29
63 DQ25 DQ29 64 1
65 VSS VSS 66
DDRB_SDM3 67 68 DDRB_SDQS3# C218 C219 C220 C221 C222C223 +
DM3 DQS3# DDRB_SDQS3# <9>
EC_TX_P80_DATA 69 70 DDRB_SDQS3 @
<14,32> EC_TX_P80_DATA NC DQS3 DDRB_SDQS3 <9>
71 72 330U_D2E_2.5VM
2 DDRB_SDQ26 VSS VSS DDRB_SDQ30 +0.9VS 2.2U_0603_6.3V6K 2.2U_0603_6.3V6K 2.2U_0603_6.3V6K 2 2
73 DQ26 DQ30 74
DDRB_SDQ27 75 76 DDRB_SDQ31 2.2U_0603_6.3V6K 2.2U_0603_6.3V6K
DQ27 DQ31
77 VSS VSS 78
DDRB_CKE0 79 80 DDRB_CKE1 DDRB_CKE0 1 4
<8> DDRB_CKE0 CKE0 NC/CKE1 DDRB_CKE1 <8>
81 82 DDRB_SBS2 2 3
EC_RX_P80_CLK VDD VDD RP14 56_0404_4P2R_5% +1.8V
<14,32> EC_RX_P80_CLK 83 NC NC/A15 84
DDRB_SBS2 85 86 DDRB_SMA14
<9> DDRB_SBS2 BA2 NC/A14
87 88 DDRB_SMA12 1 4
DDRB_SMA12 VDD VDD DDRB_SMA11 DDRB_SMA9
89 A12 A11 90 2 3
DDRB_SMA9 91 92 DDRB_SMA7 RP15 56_0404_4P2R_5% 1 1 1 1
DDRB_SMA8 A9 A7 DDRB_SMA6 C224 C225 C226 C227
93 A8 A6 94
95 96 DDRB_SMA8 1 4
DDRB_SMA5 VDD VDD DDRB_SMA4 DDRB_SMA5 0.1U_0402_16V4Z 0.1U_0402_16V4Z
97 A5 A4 98 2 3
DDRB_SMA3 DDRB_SMA2 RP16 56_0404_4P2R_5% 2
0.1U_0402_16V4Z 2 2
0.1U_0402_16V4Z 2
99 A3 A2 100
DDRB_SMA1 101 102 DDRB_SMA0
A1 A0 DDRB_SMA3
103 VDD VDD 104 1 4
DDRB_SMA10 105 106 DDRB_SBS1 DDRB_SMA1 2 3
A10/AP BA1 DDRB_SBS1 <9>
DDRB_SBS0 107 108 DDRB_SRAS# RP17 56_0404_4P2R_5%
<9> DDRB_SBS0 BA0 RAS# DDRB_SRAS# <9>
DDRB_SWE# 109 110 DDRB_SCS0#
<9> DDRB_SWE# WE# S0# DDRB_SCS0# <8>
111 112 DDRB_SMA10 1 4
DDRB_SCAS# VDD VDD DDRB_ODT0 DDRB_SBS0
<9> DDRB_SCAS# 113 CAS# ODT0 114 DDRB_ODT0 <8> 2 3
DDRB_SCS1# 115 116 DDRB_SMA13 RP18 56_0404_4P2R_5% +0.9VS
<8> DDRB_SCS1# NC/S1# NC/A13
117 VDD VDD 118
DDRB_ODT1 119 120 DDRB_SWE# 1 4
<8> DDRB_ODT1 NC/ODT1 NC
121 122 DDRB_SCAS# 2 3
DDRB_SDQ32 VSS VSS DDRB_SDQ36 RP19 56_0404_4P2R_5%
123 DQ32 DQ36 124 1 1 1 1 1
DDRB_SDQ33 125 126 DDRB_SDQ37 C228 C229 C230 C231 C232
DQ33 DQ37 DDRB_SCS1#
127 VSS VSS 128 1 4
<9> DDRB_SDQS4# DDRB_SDQS4# 129 130 DDRB_SDM4 DDRB_ODT1 2 3 0.1U_0402_16V4Z 0.1U_0402_16V4Z
DDRB_SDQS4 DQS4# DM4 RP20 56_0404_4P2R_5% 2
0.1U_0402_16V4Z 2 2
0.1U_0402_16V4Z 2 2
0.1U_0402_16V4Z
<9> DDRB_SDQS4 131 DQS4 VSS 132
133 134 DDRB_SDQ38
DDRB_SDQ34 VSS DQ38 DDRB_SDQ39
135 DQ34 DQ39 136
3 DDRB_SDQ35 DDRB_SMA11 3
137 DQ35 VSS 138 1 4
139 140 DDRB_SDQ44 DDRB_SMA14 2 3
DDRB_SDQ40 VSS DQ44 DDRB_SDQ45 RP21 56_0404_4P2R_5% +0.9VS
141 DQ40 DQ45 142
DDRB_SDQ41 143 144
DQ41 VSS DDRB_SDQS5# DDRB_SMA6
145 VSS DQS5# 146 DDRB_SDQS5# <9> 1 4
DDRB_SDM5 147 148 DDRB_SDQS5 DDRB_SMA7 2 3
DM5 DQS5 DDRB_SDQS5 <9>
149 150 RP22 56_0404_4P2R_5% 1 1 1 1 1
DDRB_SDQ42 VSS VSS DDRB_SDQ46 C233 C234 C235 C236 C237
151 DQ42 DQ46 152
DDRB_SDQ43 153 154 DDRB_SDQ47 DDRB_SMA2 1 4
DQ43 DQ47 DDRB_SMA4 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
155 VSS VSS 156 2 3
DDRB_SDQ48 DDRB_SDQ52 RP23 56_0404_4P2R_5% 2 2
0.1U_0402_16V4Z 2 2
0.1U_0402_16V4Z 2
157 DQ48 DQ52 158
DDRB_SDQ49 159 160 DDRB_SDQ53
DQ49 DQ53 DDRB_SBS1
161 VSS VSS 162 1 4
EC_RX_P80_CLK_R 163 164 DDRB_SMA0 2 3
<14> EC_RX_P80_CLK_R NC,TEST CK1 DDRB_CLK1 <8> +0.9VS
165 166 RP24 56_0404_4P2R_5%
VSS CK1# DDRB_CLK1# <8>
<9> DDRB_SDQS6# DDRB_SDQS6# 167 168
DDRB_SDQS6 DQS6# VSS DDRB_SDM6 DDRB_SCS0#
<9> DDRB_SDQS6 169 DQS6 DM6 170 1 4
171 172 DDRB_SRAS# 2 3
DDRB_SDQ50 VSS VSS DDRB_SDQ54 RP25 56_0404_4P2R_5%
173 DQ50 DQ54 174 1 1 1
DDRB_SDQ51 175 176 DDRB_SDQ55 C238 C239 C240
DQ51 DQ55 DDRB_SMA13
177 VSS VSS 178 1 4
DDRB_SDQ56 179 180 DDRB_SDQ60 DDRB_ODT0 2 3 0.1U_0402_16V4Z 0.1U_0402_16V4Z
DDRB_SDQ57 DQ56 DQ60 DDRB_SDQ61 RP26 56_0404_4P2R_5% 2 2
0.1U_0402_16V4Z 2
181 DQ57 DQ61 182
183 VSS VSS 184
DDRB_SDM7 185 186 DDRB_SDQS7# DDRB_CKE1 1 2
DM7 DQS7# DDRB_SDQS7# <9>
187 188 DDRB_SDQS7 R149 56_0402_5%
VSS DQS7 DDRB_SDQS7 <9>
DDRB_SDQ58 189 190
DDRB_SDQ59 DQ58 VSS DDRB_SDQ62
191 DQ59 DQ62 192
193 194 DDRB_SDQ63
D_CK_SDATA VSS DQ63
<14,16> D_CK_SDATA 195 SDA VSS 196 Layout Note:
D_CK_SCLK 197 198 R150 1 2 10K_0402_5% Layout Note:
<14,16> D_CK_SCLK SCL SAO R151
Place these resistor
+3VS 199 VDDSPD SA1 200 1 2 10K_0402_5% +3VS
4 closely JP35,all Place one cap close to every 2 pullup 4
trace length Max=1.5" resistors terminated to +0.9VS
P-TWO_A5692B-A0G16-P
CONN@
Change PCB Footprint

DIMM2 STD H:9.2mm (BOT) Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/08/18 Deciphered Date 2008/8/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRII-SODIMM2
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JHXXX M/B LA-4241P Schematic 0.4
Date: Wednesday, May 28, 2008 Sheet 15 of 49
A B C D E
 A B C D E F G H

+CLK_VDD
R152
+3VS
+3VS
1 1 1 1 1 1 1
C241 C242 C243 C244 C245 C246 C247
0_0805_5% R153 R154
10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 2 2 2 2 2.2K_0402_5% 2.2K_0402_5%
+1.05VS 2N7002DW-T/R7_SOT363-6
R156 +CLK_VDDSRC Q3A

2
+1.05VS <22,30,31> ICH_SMBDATA 6 1 D_CK_SDATA
R155 1 1 1 1 1 1 1
C248 C249 C250 C251 C252 C253 C254
1 R157 56_0402_5% 0_0805_5% 1

2
2.2K_0402_5% @ 10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z +3VS

1
FSA 2 2 2 2 2 2 2 2
1 1 2 MCH_CLKSEL0 <8>

5
1 2 R158
<5> CPU_BSEL0
R159 1K_0402_5% <22,30,31> ICH_SMBCLK 3 4 D_CK_SCLK
0_0402_5% 10/3 Change symbol
1
Q3B
R160 11/29 Modify symbol to have additional pin 73 2N7002DW-T/R7_SOT363-6
U4
1K_0402_5%
@ +CLK_VDD
2

9 D_CK_SDATA
SDATA D_CK_SDATA <14,15>
6 VDDREF
10 D_CK_SCLK
SCLK D_CK_SCLK <14,15>
19 VDD48
72 71 CLK_CPU_BCLK
+1.05VS VDDCPU CPUT0_LPR_F CLK_CPU_BCLK <4>
12 70 CLK_CPU_BCLK#
VDDPCI CPUC0_LPR_F CLK_CPU_BCLK# <4>
2

27 VDDPLL3
R161 68 CLK_MCH_BCLK
CPUT1_LPR_F CLK_MCH_BCLK <7>
55 VDDSRC
1K_0402_5% 67 CLK_MCH_BCLK#
CPUC1_LPR_F CLK_MCH_BCLK# <7>
@
1

FSB 1 2 +CLK_VDDSRC 52
MCH_CLKSEL1 <8> VDDSRC_IO
24 R_CLK_DOT R163 1 2 GM@ 0_0402_5%
SRCT0_LPR/DOTT_96_LPR CLK_DREF_96M <8>
1 2 R162 38 R164 1 2 PM@ 0_0402_5%
<5> CPU_BSEL1 VDDSRC_IO CLK_PCIE_VGA <17>
R168 1K_0402_5% 25 R_CLK_DOT# R165 1 2 GM@ 0_0402_5%
SRCC0_LPR/DOTC_96_LPR CLK_DREF_96M# <8>
0_0402_5% 62 R166 1 2 PM@ 0_0402_5%
VDDSRC_IO CLK_PCIE_VGA# <17>
1

2 R167 CLK_PCIE0 R169 GM@ 0_0402_5% 2

31 VDDPLL3_IO 27MHz_NonSS/SRCT1_LPR/SE1 28 1 2 CLK_DREF_SSC <8>
R170 1 2 @ 0_0402_5%
CLK_27M_VGA <17>
0_0402_5% 66 29 CLK_PCIE0# R171 1 2 GM@ 0_0402_5%
VDDCPU_IO 27MHz_SS/SRCC1_LPR/SE2 CLK_DREF_SSC# <8>
@ R172 1 2 @ 0_0402_5%
CLK_27M_VGA# <17>
2

23 VDD96_IO
32 CLK_PCIE_SATA
SRCT2_LPR/SATAT_LPR CLK_PCIE_SATA <21>
33 CLK_PCIE_SATA#
SRCC2_LPR/SATAC_LPR CLK_PCIE_SATA# <21>
PM_STP_CPU# 53
<22> PM_STP_CPU# CPU_STOP#
Follow CRB and Checklist +1.05VS PM_STP_PCI# CLK_PCIE_ICH
<22> PM_STP_PCI# 54 PCI_STOP# SRCT3_LPR 35 CLK_PCIE_ICH <22>
36 CLK_PCIE_ICH#
SRCC3_LPR CLK_PCIE_ICH# <22>
2

R173
33_0402_5% 1 2 R174 PCI1 13 39 CLK_MCH_3GPLL
<32> CLK_PCI_EC PCI1 SRCT4_LPR CLK_MCH_3GPLL <8>
R175 1K_0402_5%
10K_0402_5% @ TME 14 40 CLK_MCH_3GPLL#
CLK_MCH_3GPLL# <8>
1

FSC PCI2/TME SRCC4_LPR

2 1 1 2 MCH_CLKSEL2 <8>
33_0402_5% 1 2 R704 PCI_TPM 15
<40> CLK_PCI_TPM PCI3
1 2 R176 57 CLK_PCIE_EXP
<5> CPU_BSEL2 SRCT6_LPR CLK_PCIE_EXP <31>
R177 1K_0402_5% 33_0402_5% 1 2 R178 27_SEL 16
<35> CLK_PCI_DB PCI4/27_SELECT
0_0402_5% 56 CLK_PCIE_EXP#
SRCC6_LPR CLK_PCIE_EXP# <31>
1

33_0402_5% 1 2 R180 ITP_EN 17

<20> CLK_PCI_ICH PCI_F5/ITP_EN
R179
<8,22,48> VGATE @ R623 1 2 0_0402_5% 61 CLK_PCIE_LAN
SRCT7_LPR CLK_PCIE_LAN <28>
0_0402_5% <48> CLK_EN# @ R624 1 2 0_0402_5% 1
@ R625 CK_PWRGD/PD#
<22> CK_PWRGD 1 2 0_0402_5% 60 CLK_PCIE_LAN#
CLK_PCIE_LAN# <28>
2

SRCC7_LPR

CLK_XTAL_IN 5 64 CLK_PCIE_CARD
X1 CPUT2_ITP_LPR/SRCT8_LPR CLK_PCIE_CARD <26>
3 CLK_XTAL_OUT CLK_PCIE_CARD# 3
FSLC FSLB FSLA CPU SRC PCI 4 X2 CPUC2_ITP_LPR/SRCC8_LPR 63 CLK_PCIE_CARD# <26>
CLKSEL2 CLKSEL1 CLKSEL0 MHz MHz MHz CLK_PCIE_WLAN
11 NC SRCT9_LPR 44 CLK_PCIE_WLAN <30>
0 1 1 166.6 100 33.3 45 CLK_PCIE_WLAN#
SRCC9_LPR CLK_PCIE_WLAN# <30>
33_0402_5% 1 2 R181 FSA 20
<22> CLK_ICH_48M USB_48MHz/FSLA
0 1 0 200 100 33.3 50 CLK_PCIE_NAND
SRCT10_LPR CLK_PCIE_NAND <30>
FSB 2 FSLB/TEST_MODE CLK_PCIE_NAND#
SRCC10_LPR 51 CLK_PCIE_NAND# <30>
0 0 0 266.6 100 33.3 <22> CLK_ICH_14M 33_0402_5% 1 2 R182 FSC 7 FSLC/TEST_SEL/REF0

<35> CLK_14M_SIO 33_0402_5% 1 2 R183 REF1 8 48 CLK_PCIE_3G

REF1 SRCT11_LPR CLK_PCIE_3G <30>
For ITP_EN, 0 =SRC8/SRC8#; 1 = ITP/ITP# 73 47 CLK_PCIE_3G#
Thermal GND SRCC11_LPR CLK_PCIE_3G# <30>
For 27_SEL, 0 = Enable DOT96 & SRC1, 69 R184 1 2 10K_0402_5% +3VS
GNDCPU
1= Enable SRC0 & 27MHz 3 GNDREF CR#3 37 MCH_CLKREQ# <8>
For TME, 0 = Overclocking of CPU and SRC allowed 18 41 R186 1 2 10K_0402_5% +3VS
GNDPCI CR#4
1 = Overclocking of CPU and SRC NOT allowed 22 GND48 CR#6 58 EXP_CLKREQ# <31>
30 GND CR7# 65 LAN_CLKREQ# <28>
+3VS +3VS +3VS
26 43 CR#9 R796 1 2 0_0402_5% R190 1 2 10K_0402_5% +3VS
GND CR#9
WLAN_CLKREQ# <30>
2

34 GNDSRC CR10# 49 1 2 +3VS

CLK_XTAL_IN R191 R192 R193 R194 10K_0402_5%
C255 18P_0402_50V8J 59 46 CR#11 1 2 3G_CLKREQ#
GNDSRC CR#11 3G_CLKREQ# <30>
1

4 10K_0402_5% 10K_0402_5% 10K_0402_5% R799 @ 0_0402_5% 4

Y1 @ PM@ @ 42 21 CR#A 1 2 @ SATA_CLKREQ#
SATA_CLKREQ# <22>
1

GNDSRC CR#A R797 0_0402_5%

14.31818MHZ_16PF_DSX840GA
ITP_EN 27_SEL TME 3G_CLKREQ# C750 1 2 @ 100P_0402_50V8J
2

CLK_XTAL_OUT ICS9LPRS387AKLFT_MLF72_10x10
C256 18P_0402_50V8J WLAN_CLKREQ# C749 100P_0402_50V8J
Rev:B 1 2
2

R195 R196 R197

10K_0402_5% 10K_0402_5% 10K_0402_5%

Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/08/18 Deciphered Date 2008/8/18 Title
<BOM Structure> GM@
Clock generator-ICS9LPRS387
1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Routing the trace at least 10mil AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JHXXX M/B LA-4241P Schematic
Date: Wednesday, May 28, 2008 Sheet 16 of 49
A B C D E F G H
 5 4 3 2 1

PCIE_MTX_C_GRX_N[0..15]
<10,25> PCIE_MTX_C_GRX_N[0..15]
PCIE_MTX_C_GRX_P[0..15]
<10,25> PCIE_MTX_C_GRX_P[0..15]
9/13 modify this footprint from ACES_88990-2D08_230P to ACES_88990-2D28_230P
PCIE_GTX_C_MRX_N[0..15]
<10> PCIE_GTX_C_MRX_N[0..15]
12/19 modify this footprint from ACES_88990-2D28_230P to QUASA_CA0330-230N20_230P
PCIE_GTX_C_MRX_P[0..15]
<10> PCIE_GTX_C_MRX_P[0..15]
0208 : Modify this footprint from QUASA_CA0330-230N20_230P to QUASA_CA0330-230N20_230P-S
12/10 footprint QUASA_CA0330-230N20_230P JMXM1B
D D
PCIE_GTX_C_MRX_N1 109 110
JMXM1A PCIE_GTX_C_MRX_P1 PEX_RX1# GND PCIE_MTX_C_GRX_N1
111 PEX_RX1 PEX_TX1# 112
113 114 PCIE_MTX_C_GRX_P1
PCIE_GTX_C_MRX_N0 GND PEX_TX1
B+ 1 PWR_SRC 1V8RUN 2 115 PEX_RX0# GND 116
3 4 PCIE_GTX_C_MRX_P0 117 118 PCIE_MTX_C_GRX_N0
PWR_SRC 1V8RUN PEX_RX0 PEX_TX0# PCIE_MTX_C_GRX_P0
5 PWR_SRC 1V8RUN 6 119 GND PEX_TX0 120
7 8 CLK_PCIE_VGA# 121 122
PWR_SRC 1V8RUN <16> CLK_PCIE_VGA# PEX_REFCLK# PRSNT1#
9 10 CLK_PCIE_VGA 123 124 VGA_TV_CRMA PAD
PWR_SRC 1V8RUN <16> CLK_PCIE_VGA PEX_REFCLK TV_C/HDTV_Pr T4
11 12 125 126 @
PWR_SRC 1V8RUN CLK_REQ# GND VGA_TV_LUMA
13 PWR_SRC 1V8RUN 14 <8,20,26,28,30,40> PLT_RST_BUF# 127 PEX_RST# TV_Y/HDTV_Y 128 PAD T5
15 16 HDA_SYNC_MXM 129 130 @
PWR_SRC RUNPWROK SUSP# <31,32,41,46,47> <21> HDA_SYNC_MXM RSVD GND
17 18 +5VS HDA_BITCLK_MXM 131 132 VGA_TV_COMPS PAD
GND 5VRUN <21> HDA_BITCLK_MXM RSVD TV_CVBS/HDTV_Pb T6
19 20 <4,32> EC_SMB_DA2 133 134 HDA_RST_NB9X# @
GND GND SMB_DAT GND VGA_CRT_R
21 GND GND 22 <4,32> EC_SMB_CK2 135 SMB_CLK VGA_RED 136 VGA_CRT_R <19>
23 24 VGA_THERM# 137 138
GND GND <32> VGA_THERM# THERM# GND
VGA_CRT_HSYNC 139 140 VGA_CRT_G
<19> VGA_CRT_HSYNC VGA_HSYNC VGA_GRN VGA_CRT_G <19>
VGA_CRT_VSYNC 141 142
<19> VGA_CRT_VSYNC VGA_VSYNC GND
<19> VGA_DDC_CLK VGA_DDC_CLK 143 144 VGA_CRT_B
DDCA_CLK VGA_BLU VGA_CRT_B <19>
<19> VGA_DDC_DATA VGA_DDC_DATA 145 146
HDA_SDIN3 DDCA_DAT GND TXCLK-
<21> HDA_SDIN3 147 IGP_UCLK# LVDS_UCLK# 148 TXCLK- <18>
HDA_SDOUT_MXM 149 150 TXCLK+
<21> HDA_SDOUT_MXM IGP_UCLK LVDS_UCLK TXCLK+ <18>
PCIE_GTX_C_MRX_N15 25 26 151 152
PCIE_GTX_C_MRX_P15 PEX_RX15# PRSNT2# PCIE_MTX_C_GRX_N15 CLK_27M_VGA# GND GND
27 PEX_RX15 PEX_TX15# 28 <16> CLK_27M_VGA# 153 RSVD LVDS_UTX3# 154 10/3 for HDMI
29 30 PCIE_MTX_C_GRX_P15 CLK_27M_VGA 155 156
GND PEX_TX15 <16> CLK_27M_VGA RSVD LVDS_UTX3
PCIE_GTX_C_MRX_N14 31 32 VGA_AC_DET 157 158 SPDIFO
PEX_RX14# GND <32> VGA_AC_DET RSVD GND SPDIFO <36>
PCIE_GTX_C_MRX_P14 33 34 PCIE_MTX_C_GRX_N14 HDA_RST_030 159 160 TXOUT2-
PEX_RX14 PEX_TX14# IGP_UTX2# LVDS_UTX2# TXOUT2- <18>
35 36 PCIE_MTX_C_GRX_P14 161 162 TXOUT2+
GND PEX_TX14 IGP_UTX2 LVDS_UTX2 TXOUT2+ <18>
PCIE_GTX_C_MRX_N13 37 38 163 164
C PCIE_GTX_C_MRX_P13 PEX_RX13# GND PCIE_MTX_C_GRX_N13 GND GND TXOUT1- C
39 PEX_RX13 PEX_TX13# 40 165 IGP_UTX1# LVDS_UTX1# 166 TXOUT1- <18>
41 42 PCIE_MTX_C_GRX_P13 167 168 TXOUT1+
GND PEX_TX13 IGP_UTX1 LVDS_UTX1 TXOUT1+ <18>
PCIE_GTX_C_MRX_N12 43 44 169 170
PCIE_GTX_C_MRX_P12 PEX_RX12# GND PCIE_MTX_C_GRX_N12 GND GND TXOUT0-
45 PEX_RX12 PEX_TX12# 46 171 IGP_UTX0# LVDS_UTX0# 172 TXOUT0- <18>
47 48 PCIE_MTX_C_GRX_P12 173 174 TXOUT0+
GND PEX_TX12 IGP_UTX0 LVDS_UTX0 TXOUT0+ <18>
PCIE_GTX_C_MRX_N11 49 50 175 176
PCIE_GTX_C_MRX_P11 PEX_RX11# GND PCIE_MTX_C_GRX_N11 GND GND TZCLK-
51 PEX_RX11 PEX_TX11# 52 177 IGP_LCLK#/DVI_B_CLK# LVDS_LCLK# 178 TZCLK- <18>
53 54 PCIE_MTX_C_GRX_P11 179 180 TZCLK+
GND PEX_TX11 IGP_LCLK/DVI_B_CLK LVDS_LCLK TZCLK+ <18>
PCIE_GTX_C_MRX_N10 55 56 181 182
PCIE_GTX_C_MRX_P10 PEX_RX10# GND PCIE_MTX_C_GRX_N10 DVI_B_HPD/GND GND
57 PEX_RX10 PEX_TX10# 58 183 RSVD LVDS_LTX3# 184
59 60 PCIE_MTX_C_GRX_P10 185 186
PCIE_GTX_C_MRX_N9 GND PEX_TX10 RSVD LVDS_LTX3
61 PEX_RX9# GND 62 187 GND GND 188
PCIE_GTX_C_MRX_P9 63 64 PCIE_MTX_C_GRX_N9 189 190 TZOUT2-
PEX_RX9 PEX_TX9# IGP_LTX2#/DVI_B_TX2# LVDS_LTX2# TZOUT2- <18>
65 66 PCIE_MTX_C_GRX_P9 191 192 TZOUT2+
GND PEX_TX9 IGP_LTX2/DVI_B_TX2 LVDS_LTX2 TZOUT2+ <18>
PCIE_GTX_C_MRX_N8 67 68 193 194
PCIE_GTX_C_MRX_P8 PEX_RX8# GND PCIE_MTX_C_GRX_N8 GND GND TZOUT1-
69 PEX_RX8 PEX_TX8# 70 195 IGP_LTX1#/DVI_B_TX1# LVDS_LTX1# 196 TZOUT1- <18>
71 72 PCIE_MTX_C_GRX_P8 197 198 TZOUT1+
GND PEX_TX8 IGP_LTX1/DVI_B_TX1 LVDS_LTX1 TZOUT1+ <18>
PCIE_GTX_C_MRX_N7 73 74 199 200
PCIE_GTX_C_MRX_P7 PEX_RX7# GND PCIE_MTX_C_GRX_N7 GND GND TZOUT0-
75 PEX_RX7 PEX_TX7# 76 201 IGP_LTX0#/DVI_B_TX0# LVDS_LTX0# 202 TZOUT0- <18>
77 78 PCIE_MTX_C_GRX_P7 203 204 TZOUT0+
GND PEX_TX7 IGP_LTX0/DVI_B_TX0 LVDS_LTX0 TZOUT0+ <18>
PCIE_GTX_C_MRX_N6 79 80 VGA_HDMI_DETECT 205 206
PEX_RX6# GND <25> VGA_HDMI_DETECT DVI_A_HPD GND
PCIE_GTX_C_MRX_P6 81 82 PCIE_MTX_C_GRX_N6 VGA_HDMI_CLK- 207 208 I2CC_SDA
PEX_RX6 PEX_TX6# <25> VGA_HDMI_CLK- DVI_A_CLK# DDCC_DAT I2CC_SDA <18>
83 84 PCIE_MTX_C_GRX_P6 VGA_HDMI_CLK+ 209 210 I2CC_SCL
GND PEX_TX6 <25> VGA_HDMI_CLK+ DVI_A_CLK DDCC_CLK I2CC_SCL <18>
PCIE_GTX_C_MRX_N5 85 86 211 212 ENVDD
PEX_RX5# GND GND LVDS_PPEN ENVDD <18>
PCIE_GTX_C_MRX_P5 87 88 PCIE_MTX_C_GRX_N5 VGA_HDMI_TX2- 213 214
PEX_RX5 PEX_TX5# <25> VGA_HDMI_TX2- DVI_A_TX2# LVDS_BL_BRGHT
89 90 PCIE_MTX_C_GRX_P5 VGA_HDMI_TX2+ 215 216 VGA_ENBKL
GND PEX_TX5 <25> VGA_HDMI_TX2+ DVI_A_TX2 LVDS_BLEN VGA_ENBKL <18>
PCIE_GTX_C_MRX_N4 91 92 217 218 VGA_HDMIDAT VGA_HDMIDAT <25>
PCIE_GTX_C_MRX_P4 PEX_RX4# GND PCIE_MTX_C_GRX_N4 VGA_HDMI_TX1- GND DDCB_DAT VGA_HDMICLK
93 PEX_RX4 PEX_TX4# 94 <25> VGA_HDMI_TX1- 219 DVI_A_TX1# DDCB_CLK 220 VGA_HDMICLK <25>
95 96 PCIE_MTX_C_GRX_P4 VGA_HDMI_TX1+ 221 222
B GND PEX_TX4 <25> VGA_HDMI_TX1+ DVI_A_TX1 2V5RUN B
PCIE_GTX_C_MRX_N3 97 98 223 224
PCIE_GTX_C_MRX_P3 PEX_RX3# GND PCIE_MTX_C_GRX_N3 VGA_HDMI_TX0- GND GND
99 PEX_RX3 PEX_TX3# 100 <25> VGA_HDMI_TX0- 225 DVI_A_TX0# 3V3RUN 226 +3VS
101 102 PCIE_MTX_C_GRX_P3
<25> VGA_HDMI_TX0+
VGA_HDMI_TX0+ 227 228 10/3 for HDMI
PCIE_GTX_C_MRX_N2 GND PEX_TX3 DVI_A_TX0 3V3RUN
103 PEX_RX2# GND 104 229 GND 3V3RUN 230
PCIE_GTX_C_MRX_P2 105 106 PCIE_MTX_C_GRX_N2
PEX_RX2 PEX_TX2# PCIE_MTX_C_GRX_P2
107 GND PEX_TX2 108
ACES_88990-2D08

ACES_88990-2D08

B+ +3VS +5VS SPDIFO R198 1 2 0_0402_5%

GM@

2 1 1 1
C257 C260 C261 C263
HDA_RST_NB9X#
0.1U_0603_25V7K 4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
1
R693 NB9X@
2
0_0402_5%
R693 R694
PM@ 1 PM@ 2 2 PM@ 2 PM@ HDA_RST_MXM#
<21> HDA_RST_MXM#
1 2 HDA_RST_030
NB9X Mount No stuff
R694 PM@ 0_0402_5%
A 030 NB9X No stuff Mount A

NB8X No stuff No stuff

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/18 Deciphered Date 2008/8/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MXM Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JHXXX M/B LA-4241P Schematic
Date: Wednesday, May 28, 2008 Sheet 17 of 49
5 4 3 2 1
 5 4 3 2 1

LCD POWER CIRCUIT

+3VALW +3VS Routing Diagram

+LCDVDD
W=60mils
MXMII Conn.

1
1

1
R199 2 C264 LVDS Bus
300_0603_5% R200 C265 LVDS R NB
D 4.7U_0805_10V4Z D
100K_0402_5%
0.1U_0402_10V7K 2

1 2
1

3
D S
G
Q4 2 2 1 2 Q5
SSM3K7002FU_SC70-3 G R201 100K_0402_5% SI2301BDS_SOT23 Use Daisy chain to route
S

3
D

1
1
GM@ D +LCDVDD
<10> GMCH_ENVDD R202 1 2 0_0402_5% 2 Q6 W=60mils
PM@ G SSM3K7002FU_SC70-3
<17> ENVDD R203 1 2 0_0402_5% S

3
1
1 1
@ C266 C267 I2CC_SCL 1 4 GMCH_LCD_CLK
GMCH_LCD_CLK <10>
R204 I2CC_SDA 2 3 GMCH_LCD_DATA
GMCH_LCD_DATA <10>
100K_0402_5% 4.7U_0805_10V4Z 0.1U_0402_16V4Z RP27 GM@ 0_0404_4P2R_5%
2 2 TXOUT0+ GMCH_TXOUT0+
1 4 GMCH_TXOUT0+ <10>

2
TXOUT0- 2 3 GMCH_TXOUT0-
GMCH_TXOUT0- <10>
RP28 GM@ 0_0404_4P2R_5%
TXOUT1- 1 4 GMCH_TXOUT1-
GMCH_TXOUT1- <10>
TXOUT1+ 2 3 GMCH_TXOUT1+
GMCH_TXOUT1+ <10>
RP29 GM@ 0_0404_4P2R_5%
LCD/PANEL BD. Conn. TXOUT2-
TXOUT2+
1 4 GMCH_TXOUT2-
GMCH_TXOUT2+
GMCH_TXOUT2- <10>
2 3 GMCH_TXOUT2+ <10>
(IFTXX) TXCLK+
RP30
1 4
GM@ 0_0404_4P2R_5%
GMCH_TXCLK+
GMCH_TXCLK+ <10>
JLVDS1 TXCLK- 2 3 GMCH_TXCLK-
GMCH_TXCLK- <10>
TZOUT0+ 1 2 TXOUT0+ RP31 GM@ 0_0404_4P2R_5%
<17> TZOUT0+ 1 2 TXOUT0+ <17>
TZOUT0- 3 4 TXOUT0- TZOUT0+ 1 4 GMCH_TZOUT0+
<17> TZOUT0- 3 4 TXOUT0- <17> GMCH_TZOUT0+ <10>
5 6 TZOUT0- 2 3 GMCH_TZOUT0-
5 6 GMCH_TZOUT0- <10>
TZOUT1+ 7 8 TXOUT1+ RP32 GM@ 0_0404_4P2R_5%
C <17> TZOUT1+ 7 8 TXOUT1+ <17> C
<17> TZOUT1- TZOUT1- 9 10 TXOUT1- TZOUT1+ 1 4 GMCH_TZOUT1+
+3VS 9 10 TXOUT1- <17> GMCH_TZOUT1+ <10>
11 12 TZOUT1- 2 3 GMCH_TZOUT1-
11 12 GMCH_TZOUT1- <10>
TZOUT2+ 13 14 TXOUT2+ RP33 GM@ 0_0404_4P2R_5%
<17> TZOUT2+ 13 14 TXOUT2+ <17>
TZOUT2- 15 16 TXOUT2- TZOUT2- 1 4 GMCH_TZOUT2-
<17> TZOUT2- 15 16 TXOUT2- <17> GMCH_TZOUT2- <10>
1 17 18 TZOUT2+ 2 3 GMCH_TZOUT2+
17 18 GMCH_TZOUT2+ <10>
C268 TZCLK+ 19 20 TXCLK+ RP34 GM@ 0_0404_4P2R_5%
<17> TZCLK+ 19 20 TXCLK+ <17>
TZCLK- 21 22 TXCLK- TZCLK+ 1 4 GMCH_TZCLK+
<17> TZCLK- 21 22 TXCLK- <17> GMCH_TZCLK+ <10>
0.1U_0402_16V4Z 23 24 TZCLK- 2 3 GMCH_TZCLK-
2 23 24 GMCH_TZCLK- <10>
+LCDVDD L10 2 1 +LCDVDD_L 25 26 I2CC_SDA RP35 GM@ 0_0404_4P2R_5%
25 26 I2CC_SDA <17>
(60 MIL) 27 28 I2CC_SCL
27 28 I2CC_SCL <17>
FBMA-L11-201209-221LMA30T_0805 +3VS 29 30 +3VS
29 30
1 1
C269 31 C270
GND1
32 GND2
220P_0402_50V7K 220P_0402_50V7K
2 ACES_88242-3001 2
CONN@ INVERTER Conn. 12/18 modified from
<EMI> <EMI>
+LCDVDD_L 220p @ to 470p mount
Follow HEL80's pin definition
0208 Add C796 , C797 for EMI by EMI request
1
C271
1
C272
Except pin 29

10U_0805_10V4Z 0.1U_0402_16V4Z DAC_BRIG 1 2 <EMI>

2 2 JP37 C273 470P_0402_50V7K
INVT_PWM 1 2 <EMI>
1 C274 470P_0402_50V7K
2 DISPOFF#
<32> INVT_PWM 3 1 2 <EMI>
DISPOFF# C275 470P_0402_50V7K
4
LTCX000G500 footprint is still use ACES_88242-3001 <32> DAC_BRIG 5
+INVPWR_B+ 6
B 7 B
MOLEX_53780-0790 +3VS
CONN@

1
R205

D4 4.7K_0402_5%
CH751H-40PT_SOD323-2

2
BKOFF# 1 2 DISPOFF#
<32> BKOFF#

2 1 ENBKL
<10> GMCH_ENBKL ENBKL <32>
R206 GM@ 0_0402_5%

2
<17> VGA_ENBKL 2 1
R207 PM@ 0_0402_5% R208

100K_0402_5%

1
+INVPWR_B+

L11 2 1 B+
KC FBM-L11-201209-221LMAT_0805
<EMI>
L12 2 1
KC FBM-L11-201209-221LMAT_0805
1 <EMI>
C276 C277

A 0.1U_0603_50V4Z 68P_0402_50V8K A
2 @
12/22 Change to SE071680J80

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/18 Deciphered Date 2008/8/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LVDS & DVI Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JHXXX M/B LA-4241P Schematic
Date: Wednesday, May 28, 2008 Sheet 18 of 49
5 4 3 2 1
 A B C D E

+5VS

Checklist recommend: 2-pole filter on R/G/B signals

CRT Connector C-L-C-L-C D5 D6 D7

2
@ @ @
DAN217_SC59 DAN217_SC59 DAN217_SC59 L13
10p - 47 Ohm/100MHz - 22p - 47 Ohm/100MHz - 10p KC FBM-L11-201209-221LMAT_0805

1
+R_CRT_VCC +CRT_VCC
W=40mils

1
D8 F1 W=40mils
+L_CRT_VCC 2 1 1 2

3
RB491D_SC59-3 1.1A_6VDC_FUSE

1
Place closed to chipset
12/15 Modified. Note L26~L30 are 0 Ohm resisters +3VS 1
1
C278
(IFTXX) 0.1U_0402_16V4Z
2
R734 1 2 PM@ 0_0402_5% VGA_CRT_R1 CRT_R_1 L15 1 2 CRT_R_2 JCRT1
<17> VGA_CRT_R
R209 1 2 GM@ 0_0402_5% L14 0_0603_5% FBMA-L10-160808-800LMT_0603 6
<10> GMCH_CRT_R
11
R735 1 2 PM@ 0_0402_5% VGA_CRT_G1 CRT_G_1 L17 1 2 CRT_G_2 1
<17> VGA_CRT_G
R210 1 2 GM@ 0_0402_5% L16 0_0603_5% FBMA-L10-160808-800LMT_0603 7
<10> GMCH_CRT_G
12
R736 1 2 PM@ 0_0402_5% VGA_CRT_B1 CRT_B_1 L19 1 2 CRT_B_2 2
<17> VGA_CRT_B
R211 1 2 GM@ 0_0402_5% L18 0_0603_5% FBMA-L10-160808-800LMT_0603 8
<10> GMCH_CRT_B

1
13

1
R212 R213 1 1 1 1 1 1 3
R214 C279 C280 C281 C282 C283 C285 1 1 1 9
14
150_0402_1% C284 C286 C287 4

2
2 2 2 2 2 2 10P_0402_50V8J 10P_0402_50V8J 10P_0402_50V8J 10 16

2
150_0402_1% 10P_0402_50V8J 10P_0402_50V8J 22P_0402_50V8J 2 2 2
15 17
150_0402_1% 22P_0402_50V8J 22P_0402_50V8J 1 5
10P_0402_50V8J
SUYIN_070546FR015S233CR
+CRT_VCC CRT_HSYNC_2 C288
1 2
L20 FCM1608C-121T_0603 <EMI> 2
1 2 2 1 <EMI> 100P_0402_50V8J DSUB_12
C289 0.1U_0402_16V4Z R215 10K_0402_5% 1 2 CRT_VSYNC_2
L21 FCM1608C-121T_0603 1

1
U5 <EMI> C290
1 1 <EMI>

OE#
1 2 VGA_CRT_HSYNC1 2 4 CRT_HSYNC_0 1 2 CRT_HSYNC_1 C292 68P_0402_50V8K
<17> VGA_CRT_HSYNC A Y 2
R737 PM@ 0_0402_5% R216 39_0402_1% C291

G
1 2 10P_0402_50V8J 10P_0402_50V8J DSUB_15
2 <10> GMCH_CRT_HSYNC 2 2 <EMI> 2
R217 GM@ 0_0402_5% TC7SET125FUF_SC70 <EMI>

3
+CRT_VCC 1
C293
Place closed to chipset 68P_0402_50V8K
1 2
C294 0.1U_0402_16V4Z 2

1
U6
<EMI>

OE#
1 2 VGA_CRT_VSYNC1 2 4 CRT_VSYNC_0 1 2 CRT_VSYNC_1 12/22 Change to SE071680J80
<17> VGA_CRT_VSYNC A Y
R738 PM@ 0_0402_5% R218 39_0402_1%

G
<10> GMCH_CRT_VSYNC 1 2 (IFTXX)

1
R219 GM@ 0_0402_5% TC7SET125FUF_SC70

3
D9 D10 Add IFTXX
<EMI> <EMI>
DAN217_SC59 DAN217_SC59
Andy_1102
@ @

3
+5VS

+3VS
+CRT_VCC

1
R220

+3VS 2.2K_0402_5%

1
3 3

2
R221 R222
VGA_DDC_DATA <17>
2.2K_0402_5% 2.2K_0402_5%

2
DSUB_12 6 1 2 1 GMCH_CRT_DATA <10>
R223 GM@ 0_0402_5%
Q44A

5
2N7002DW-T/R7_SOT363-6

DSUB_15 3 4 2 1 GMCH_CRT_CLK <10>

R224 GM@ 0_0402_5%
Q44B
2N7002DW-T/R7_SOT363-6
VGA_DDC_CLK <17>

1
10/5 Change to SB00000AR00 R225

2.2K_0402_5%

2
+3VS

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/18 Deciphered Date 2008/8/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRT Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JHXXX M/B LA-4241P Schematic
Date: Wednesday, May 28, 2008 Sheet 19 of 49
A B C D E
 5 4 3 2 1

+3VS

DMI for ESI-compatible operation

RP40
1 8 PCI_REQ#2 Low= DMI for ESI-compatible operation
2 7 PCI_FRAME# PCI_GNT#1 High= Default* (Internal pull-up)
3 6 PCI_REQ#1
4 5 PCI_DEVSEL#
3/4 Change U7 from SA00002AN10 to SA00002JH00 (A2 to A3)
D 8.2K_1206_8P4R_5% D

RP41 U7B
1 8 PCI_PLOCK# D11 F1 PCI_REQ#0
PCI_IRDY# AD0 REQ0# PCI_GNT#0
2 7 C8 AD1 GNT0# G4
PCI_PIRQD# PCI_REQ#1
3
4
6
5 PCI_PERR#
D9
E12
AD2 PCI REQ1#/GPIO50 B6
A7 PCI_GNT#1 @
AD3 GNT1#/GPIO51 PAD T7
E9 F13 PCI_REQ#2
8.2K_1206_8P4R_5% AD4 REQ2#/GPIO52 PCI_GNT#2 @
C9 AD5 GNT2#/GPIO53 F12 PAD T8
E10 E6 PCI_REQ#3
AD6 REQ3#/GPIO54 PCI_GNT#3
B7 AD7 GNT3#/GPIO55 F6
C7 AD8
C5 AD9 C/BE0# D8
+3VS G11 B4
AD10 C/BE1#
F8 AD11 C/BE2# D6
RP42 F11 A5
PCI_PIRQA# AD12 C/BE3#
1 8 E7 AD13
2 7 PCI_PIRQB# A3 D3 PCI_IRDY#
PCI_PIRQE# AD14 IRDY#
3 6 D2 AD15 PAR E3
4 5 PCI_SERR# F10 R1 PCIRST# Place closely pin D4
AD16 PCIRST# PCI_DEVSEL#
D5 AD17 DEVSEL# C6
8.2K_1206_8P4R_5% D10 E4 PCI_PERR#
AD18 PERR# PCI_PLOCK# CLK_PCI_ICH
B3 AD19 PLOCK# C2
RP43 F7 J4 PCI_SERR#
AD20 SERR#

2
1 8 PCI_PIRQG# C3 A4 PCI_STOP#
PCI_PIRQH# AD21 STOP# PCI_TRDY#
2 7 F3 AD22 TRDY# F5
3 6 PCI_PIRQC# F4 D7 PCI_FRAME# R240
PCI_PIRQF# AD23 FRAME# 10_0402_5%
4 5 C1 AD24
G7 C14 PLT_RST# @

1
C 8.2K_1206_8P4R_5% AD25 PLTRST# CLK_PCI_ICH C
H7 AD26 PCICLK D4 CLK_PCI_ICH <16>
D1 R2 PCI_PME# 1
AD27 PME# PCI_PME# <32>
RP44 G5 C295
PCI_STOP# AD28 10P_0402_50V8J
1 8 H6 AD29
2 7 PCI_REQ#3 G1 @
PCI_TRDY# AD30 2
3 6 H3 AD31
4 5 PCI_REQ#0

8.2K_1206_8P4R_5%
PCI_PIRQA# J5
Interrupt I/F H4 PCI_PIRQE#
PCI_PIRQB# PIRQA# PIRQE#/GPIO2 PCI_PIRQF#
E1 PIRQB# PIRQF#/GPIO3 K6
PCI_PIRQC# J6 F2 PCI_PIRQG#
PCI_PIRQD# PIRQC# PIRQG#/GPIO4 PCI_PIRQH#
C4 PIRQD# PIRQH#/GPIO5 G2
ICH9-M ES_FCBGA676

R247 1 2 1K_0402_5% PCI_GNT#3 +3V_AND1 1 2 +3VS

@ R248 @ 0_0402_5%
1 2 +3VALW
R250 1 2 1K_0402_5% PCI_GNT#0 R249 @ 0_0402_5%
@ 1 2
C296 @ 0.1U_0402_16V4Z
R251 1 2 1K_0402_5% U8
SPI_CS#1 <22>

5
@ NC7SZ08P5X_NL_SC70-5
PLT_RST# 2 @

P
B B B
Y 4 PLT_RST_BUF# <8,17,26,28,30,40>
1 A

1
3
R252

100K_0402_5%
1 2 @
A16 Swap Override Strap

2
R253 0_0402_5%
Low= A16 swap override Enable
PCI_GNT#3 High= Default* Update Footprint +3V_AND2 1 2 +3VS
R254 @ 0_0402_5%
1 2 +3VALW
R255 @ 0_0402_5%
1 2
C297 @ 0.1U_0402_16V4Z
U9

5
NC7SZ08P5X_NL_SC70-5
PCIRST# 2 @

P
B
CRB: GNT#0 and SPI_CS#1 have a weak internal pull up Y 4 PCI_RST# <31,32,35>
1 A

G
Boot BIOS Strap

3
PCI_GNT#0 SPI_CS#1 Boot BIOS Loaction
1 2
R257 0_0402_5%
A 0 1 SPI A

1 0 PCI

1 1 LPC* Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/18 Deciphered Date 2008/8/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH9M(1/4)-PCI
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JHXXX M/B LA-4241P Schematic
Date: Tuesday, June 03, 2008 Sheet 20 of 49
5 4 3 2 1
 5 4 3 2 1

ICH9M Internal VR Enable Strap

+RTCVCC 12/7 Modified X4 to SJ100001U00 10ppm (Internal VR for VccSus1.05, VccSus1.5, VccCL1.5)
C299 Low = Internal VR Disabled
15P_0402_50V8J ICH_INTVRMEN High = Internal VR Enabled(Default)
1 2 SM_INTRUDER# 2 1 ICH_RTCX1
R258 1M_0402_5% ICH9M LAN100 SLP Strap

10M_0402_5%
X1
(Internal VR for VccLAN1.05 and VccCL1.05)

1
3 NC OUT 4

R263
1 2 ICH_INTVRMEN Low = Internal VR Disabled
R262 330K_0402_5% 2 1 ICH_LAN100_SLP High = Internal VR Enabled(Default)
NC IN
32.768KHZ_12.5P_1TJS125BJ2A251 U7A

2
D 1 2 LAN100_SLP C23 RTCX1 FWH0/LAD0 K5 LPC_AD0
LPC_AD0 <32,35,40> D
R265 330K_0402_5% 2 1 ICH_RTCX2 C24 K4 LPC_AD1
RTCX2 FWH1/LAD1 LPC_AD1 <32,35,40> +1.05VS
C30215P_0402_50V8J L6 LPC_AD2
FWH2/LAD2 LPC_AD2 <32,35,40>
+RTCVCC 1 2 ICH_RTCRST# A25 K2 LPC_AD3
+3VS RTCRST# FWH3/LAD3 LPC_AD3 <32,35,40>
R266 +RTCVCC 1 2 ICH_SRTCRST# F20 H_DPRSTP# 2 1
20K_0402_5% R267 SM_INTRUDER# SRTCRST# LPC_FRAME# R268 @ 56_0402_5%
C22 INTRUDER# FWH4/LFRAME# K3 LPC_FRAME# <32,35,40>
180K_0402_5% H_DPSLP# 2 1

RTC

LPC
close to RAM door close to RAM door ICH_INTVRMEN B22 J3 LPC_DRQ0# R272 @ 56_0402_5%
INTVRMEN LDRQ0# LPC_DRQ0# <35>
1 2 SATA_LED# LAN100_SLP A22 J1 H_FERR# 2 1
R664 10K_0402_5% @ LAN100_SLP LDRQ1#/GPIO23 R273 2
2 1 1 2 1 8.2K_0402_5% +3VS R270 56_0402_5%

1
J2 @ JOPEN R271 E25 N7 GATEA20
+3VALW GLAN_CLK A20GATE GATEA20 <32>
10K_0603_5% R662 R661 AJ27 H_A20M#
A20M# H_A20M# <4>
C300 C301 @ @ C13
1U_0603_10V4Z 0.1U_0402_16V4Z 0_0402_5% 0_0402_5% LAN_RSTSYNC DPRSTP# R274 1 0_0402_5% H_DPRSTP#
DPRSTP# AJ25 2 H_DPRSTP# <5,8,48>
1 2 1 2 F14 AE23 DPSLP# R275 1 2 0_0402_5% H_DPSLP#
H_DPSLP# <5>

2
LAN_RXD0 DPSLP#
1 2 GPIO56 G13 LAN_RXD1
R675 10K_0402_5% D14 AJ26 FERR# 1 2 H_FERR#
LAN_RXD2 FERR# H_FERR# <4>

LAN / GLAN
R276 56_0402_5%
D13 AD22 H_PWRGOOD
LAN_TXD_0 CPUPWRGD H_PWRGOOD <5>
D12 LAN_TXD_1
E13 AF25 H_IGNNE#
LAN_TXD_2 IGNNE# H_IGNNE# <4>
1 2 GPIO33 Need check GPIO56 B10 AE22 H_INIT# R277 2 1 10K_0402_5%
GPIO56 INIT# H_INIT# <4> +3VS
R663 @ 20K_0402_5% AG25 H_INTR

CPU
INTR H_INTR <4>
+1.5VS 1 2 GLAN_COMP B28 L3 KB_RST#
GLAN_COMPI RCIN# KB_RST# <32>
1 2 HDA_SDIN1 R278 24.9_0402_1% B27
C751 100P_0402_50V8J HDA_BITCLK_ICH GLAN_COMPO H_NMI
<40> HDA_BITCLK_MDC 1 2 NMI AF23 H_NMI <4>
@ R279 33_0402_5% AF6 AF24 H_SMI#
HDA_BIT_CLK SMI# H_SMI# <4>
1 2 HDA_SYNC_ICH AH4 R308 need to place within 2" of ICH9M
<40> HDA_SYNC_MDC HDA_SYNC
C R281 33_0402_5% AH27 H_STPCLK# R310 must be place within 2" of R308 w/o stub. C
STPCLK# H_STPCLK# <4>
1 2 HDA_RST_ICH# AE7
<40> HDA_RST_MDC# HDA_RST#
R282 33_0402_5% AG26 THRMTRIP_ICH# R283 1 2 54.9_0402_1% H_THERMTRIP#
THRMTRIP# H_THERMTRIP# <4,8>
HDA_SDIN0 AF4
<36> HDA_SDIN0 HDA_SDIN0
HDA_SDIN1 AG4 AG27 2 1 +1.05VS
<40> HDA_SDIN1 HDA_SDIN1 TP12
HDA_SDIN2 AH3 SATA ODD R284 56_0402_5%
<10> HDA_SDIN2 HDA_SDIN2
HDA_SDIN3 AE5

IHDA
<17> HDA_SDIN3 HDA_SDIN3
AH11 SATA_DTX_C_IRX_N4 T24 PAD @
SATA4RXN
<40> HDA_SDOUT_MDC 1 2 HDA_SDOUT_ICH AG5 HDA_SDOUT SATA4RXP AJ11 SATA_DTX_C_IRX_P4 T25 PAD @
R285 33_0402_5% AG12 SATA_ITX_DRX_N4 T26 PAD @
@ GPIO33 SATA4TXN SATA_ITX_DRX_P4 T27 PAD @
T9 PAD AG7 HDA_DOCK_EN#/GPIO33 SATA4TXP AF12 MAINPWON <43,45>
AE8 HDA_DOCK_RST#/GPIO34
SATA_LED# AG8 R286
<40> SATA_LED# SATALED#

1
AH9 @ 330_0402_5% C
SATA_DTX_C_IRX_N0 SATA5RXN Q7
<24> SATA_DTX_C_IRX_N0 AJ16 SATA0RXN SATA5RXP AJ9 +1.05VS 1 2 2
SATA_DTX_C_IRX_P0 B
SATA HDD <24> SATA_DTX_C_IRX_P0
SATA_ITX_DRX_N0
AH16 SATA0RXP SATA5TXN AE10
E 2SC2411K_SOT23
AF17 AF10

3
SATA_ITX_DRX_P0 SATA0TXN SATA5TXP @
AG17 SATA0TXP
AH18 CLK_PCIE_SATA#
<24> SATA_DTX_C_IRX_N1 SATA_CLKN CLK_PCIE_SATA# <16>

SATA
SATA_DTX_C_IRX_N1 AH13 AJ18 CLK_PCIE_SATA H_THERMTRIP#
<24> SATA_DTX_C_IRX_P1 SATA1RXN SATA_CLKP CLK_PCIE_SATA <16>
1 2 HDA_BITCLK_ICH SATA_DTX_C_IRX_P1 AJ13 AJ7 SATARBIAS
<36> HDA_BITCLK_AUDIO SATA1RXP SATARBIAS#
R288 33_0402_5% SATA_ITX_DRX_N1 AG14 AH7 R287 2 1 24.9_0402_1%
HDA_SYNC_ICH SATA_ITX_DRX_P1 SATA1TXN SATARBIAS
<36> HDA_SYNC_AUDIO 1
R289
2
33_0402_5%
AF14 SATA1TXP 4mils width less than 500mils
1 2 HDA_RST_ICH#
<36> HDA_RST_AUDIO#
R290 33_0402_5% ICH9-M ES_FCBGA676
1 2 HDA_SDOUT_ICH
<36> HDA_SDOUT_AUDIO
R291 33_0402_5% close ICH9
B B

1 2 HDA_BITCLK_ICH SATA_ITX_C_DRX_N0 1 2 SATA_ITX_DRX_N0 SATA_ITX_DRX_N1 1 2 SATA_ITX_C_DRX_N1

<17> HDA_BITCLK_MXM <24> SATA_ITX_C_DRX_N0 SATA_ITX_C_DRX_N1 <24>
R626 PM@ 33_0402_5% C303 0.01U_0402_16V7K C304 0.01U_0402_16V7K
1 2 HDA_SYNC_ICH SATA_ITX_C_DRX_P0 1 2 SATA_ITX_DRX_P0 SATA_ITX_DRX_P1 1 2 SATA_ITX_C_DRX_P1
<17> HDA_SYNC_MXM <24> SATA_ITX_C_DRX_P0 SATA_ITX_C_DRX_P1 <24>
R627 PM@ 33_0402_5% C305 0.01U_0402_16V7K C306 0.01U_0402_16V7K
1 2 HDA_RST_ICH#
<17> HDA_RST_MXM#
R628 PM@ 33_0402_5%
1 2 HDA_SDOUT_ICH
<17> HDA_SDOUT_MXM
R629 PM@ 33_0402_5%

1 2 HDA_BITCLK_ICH
<10> HDA_BITCLK_NB
R292 GM@ 33_0402_5% Change BATT1 P/N : SP093PA0200 (Panasonic)
<10> HDA_SYNC_NB 1
R293
2 HDA_SYNC_ICH
GM@ 33_0402_5% EMI Request
RTC Battery SP093MX0000 (MAXELL)
1 2 HDA_RST_ICH#
<10> HDA_RST_NB#
R294 GM@ 33_0402_5% H_DPRSTP# HDA_BITCLK_ICH
1 2 HDA_SDOUT_ICH 9/29 modified to follow ISKAA
<10> HDA_SDOUT_NB

2
R295 GM@ 33_0402_5%
D11
+RTC_BATT
Need check R630
10_0402_5%
- BATT1 + R296
2 +CHGRTC
Flash Descriptor Security Override Strap 1
1
2 1 +RTCBATT1 2 1
+3VS C738
Low= Descriptor Security override 511_0603_1% 3
GPIO33 High= Default* (Internal pull-up) 100P_0402_50V8J C648
1 +RTCVCC
2 10P_0402_50V8J ML1220T13RE 1
R297 @ @ BAS40-04_SOT23 C307
1K_0402_5% 2
XOR Chain Entrance Strap 0.1U_0402_16V4Z
A @ A
2
HDA_SDOUT_ICH
ICH_TP3 HDA_SDOUT Description
0 0 RSVD 9/29 Checked. Same as HEL80's
<22> ICH_TP3
0 1 Enter XOR Chain
R298 1 0 Normal Operation
Security Classification Compal Secret Data Compal Electronics, Inc.
1K_0402_5% 2007/08/18 2008/8/18 Title
Issued Date Deciphered Date
@ 1 1 Set PCIE port config bit 1 ICH9M(2/4)-LAN,IDELPC,RTC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JHXXX M/B LA-4241P Schematic
Date: Tuesday, June 03, 2008 Sheet 21 of 49
5 4 3 2 1
 5 4 3 2 1

+3VS R299 1 2 2.2K_0402_5%

8.2K_0402_5%
+3VALW 12/13 Add 10K_0402_5% Place closely pin B2 Place closely pin AC1
R303 1 2 PM_CLKRUN# R300 1 2 2.2K_0402_5% R301 1 2
+3VS
U7C SINGLE@
8.2K_0402_5% ICH_SMBCLK G16 AH23 PROJECT_ID1 R307 CLK_ICH_48M CLK_ICH_14M
<16,30,31> ICH_SMBCLK SMBCLK SATA0GP/GPIO21
R311 1 EC_THERM# ICH_SMBDATA PROJECT_ID0 MIC_ID
2 <16,30,31> ICH_SMBDATA
LINKALERT#
A13 SMBDATA SMB SATA1GP/GPIO19 AF19
MIC_ID
1 2
DUAL@ 10K_0402_5%

SATA
GPIO
E17 LINKALERT#/GPIO60/CLGPIO4 SATA4GP/GPIO36 AE21

1
10K_0402_5% ICH_SMLINK0 C17 AD20 R308 1 2 10K_0402_5%
R304 1 @ PM_STP_PCI# ICH_SMLINK1 SMLINK0 SATA5GP/GPIO37 R309 R310
2 B18 SMLINK1
H1 CLK_ICH_14M 10_0402_5% 10_0402_5%
10K_0402_5% ICH_RI# CLK14 CLK_ICH_48M CLK_ICH_14M <16> @ @
R305 1 @ 2 PM_STP_CPU#
F19 RI# clocks CLK48 AF3 CLK_ICH_48M <16>

2
SUS_STAT# R4 P1 SUS_CLK PAD
<40> SUS_STAT# SUS_STAT#/LPCPD# SUSCLK T11
10K_0402_5% ITP_DBRESET# G19 @ 1 1
<4> ITP_DBRESET# SYS_RESET#
R676 1 @ 2 PM_BMBUSY# C16 PM_SLP_S3# C308 C309
D 10K_0402_5% PM_BMBUSY# SLP_S3# PM_SLP_S4# PM_SLP_S3# <32> 10P_0402_50V8J 10P_0402_50V8J D
<8> PM_BMBUSY# M6 PMSYNC#/GPIO0 SLP_S4# E16 PM_SLP_S4# <32>
R732 1 2 GPIO7 G17 PM_SLP_S5# @ @

SYS / GPIO
RP37 EC_LID_OUT# SLP_S5# PM_SLP_S5# <32> 2 2
<32> EC_LID_OUT# A17 SMBALERT#/GPIO11
5 4 SATA_CLKREQ# C10
OCP# PM_STP_PCI# S4_STATE#/GPIO26
6 3 <16> PM_STP_PCI# A14 STP_PCI#
7 2 D_ACIN PM_STP_CPU# E19 G20 ICH_PWROK
<16> PM_STP_CPU# STP_CPU# PWROK
8 1 CR_WAKE#
PM_CLKRUN# L4 M2 DPRSLPVR 1 2

Power MGT
<32,40> PM_CLKRUN# CLKRUN# DPRSLPVR/GPIO16 PM_DPRSLPVR_D <8,48>
10K_1206_8P4R_5% R313 0_0402_5%
ICH_PCIE_WAKE# E20 B13 PM_BATLOW# IFT use 100 ohm
<28,30,31> ICH_PCIE_WAKE# WAKE# BATLOW#
RP45 SERIRQ M5
<32,35,40> SERIRQ SERIRQ
5 4 SERIRQ EC_THERM# AJ23 R3 PBTN_OUT#
<32> EC_THERM# THRM# PWRBTN# PBTN_OUT# <32>
6 3 GPIO38 PM_DPRSLPVR_D C737 1 2 @
7 2 GPIO48 2 1 ICH_VGATE D21 D20 LAN_RST# 1 2 100P_0402_50V8J
<8,16,48> VGATE VRMPWRGD LAN_RST#
8 1 GPIO39 R316 0_0402_5% R317 0_0402_5%
PAD @ ICH_TP11 A20 D22 EC_RSMRST#R ICH_PCIE_WAKE# C730 1 2 @
+3VALW T12 TP11 RSMRST#
10K_1206_8P4R_5% 100P_0402_50V8J
RP38 CH751H-40PT_SOD323-2 @ OCP# AG19 R5 CK_PWRGD
ICH_RI# D12 1 D_ACIN GPIO1 CK_PWRGD CK_PWRGD <16> VGATE C740 1
5 4 <32,42,44> ACIN 2 AH21 GPIO6 Check 2 @
6 3 ICH_SMLINK1 GPIO7 AG21 R6 CLPWROK 1 2 100P_0402_50V8J
GPIO7 CLPWROK ICH_PWROK <8,32>
7 2 ICH_SMLINK0 EC_SMI# A21 R325 0_0402_5%
<32> EC_SMI# GPIO8
8 1 LINKALERT# C12 B16 PM_SLP_M# PAD ICH_SMBCLK C741 1 2 @
GPIO12 SLP_M# T13
<32> EC_SCI# EC_SCI# C21 @ 100P_0402_50V8J
10K_1206_8P4R_5% GPIO13
AE18 GPIO17 CL_CLK0 F24 CL_CLK0 <8>
GPIO18 K1 B19 ICH_SMBDATA C742 1 2 @

GPIO
Controller Link
<26> GPIO18 GPIO18 CL_CLK1
RP46 PAD @ ICH_GPIO20 AF8 100P_0402_50V8J
T14 GPIO20
5 4 ITP_DBRESET# CR_WAKE# AJ22 F22
<26> CR_WAKE# SCLOCK/GPIO22 CL_DATA0 CL_DATA0 <8>
6 3 GPIO14 A9 C19
GPIO10 GPIO27 CL_DATA1
7 2 D19 GPIO28
8 1 SATA_CLKREQ# L1 C25 CL_VREF0_ICH
<16> SATA_CLKREQ# SATACLKREQ#/GPIO35 CL_VREF0
follow iTPM spec GPIO38 AE19 A19 CL_VREF1_ICH
10K_1206_8P4R_5% GPIO39 SLOAD/GPIO38 CL_VREF1
AG22 SDATAOUT0/GPIO39
C GPIO48 C
AF21 SDATAOUT1/GPIO48 CL_RST0# F21 CL_RST#0 <8>
10K_0402_5% ICH_GPIO49 AH24 D18
R709 1 @ ICH_GPIO57 ICH_GPIO57 GPIO49 CL_RST1#
2 A8 GPIO57/CLGPIO5
+3VS R327 1 @ 2 1K_0402_5% A16
1K_0402_5% SB_SPKR MEM_LED/GPIO24 GPIO10
<36> SB_SPKR M7 SPKR GPIO10/SUS_PWR_ACK C18
R324 1 2 ICH_PCIE_WAKE# MCH_ICH_SYNC# AJ24 C11 GPIO14

MISC
<8> MCH_ICH_SYNC# MCH_SYNC# GPIO14/AC_PRESENT
ICH_TP3 B21 C20
<21> ICH_TP3 TP3 WOL_EN/GPIO9
8.2K_0402_5% AH20
R326 2 1 PM_BATLOW# AJ20
TP8 DMI Termination Voltage
No Reboot Strap AJ21
TP9
TP10 Low= Desktop used
Low= Default* GPIO49
SB_SPKR ICH9-M ES_FCBGA676 High= Mobile* (Internal pull-up)
100K_0402_5%
R329 1 @ ICH_GPIO57
High= "No Reboot" RSMRST circuit
2
U7D
10K_0402_5% PCIE_PTX_C_IRX_N1 N29 V27 DMI_MTX_IRX_N0 R332 0_0402_5%
<31> PCIE_PTX_C_IRX_N1 PERN1 DMI0RXN DMI_MTX_IRX_N0 <8>
R330 1 @ 2 ICH_GPIO49 PCIE_PTX_C_IRX_P1 N28 V26 DMI_MTX_IRX_P0 1 2
<31> PCIE_PTX_C_IRX_P1 PERP1 DMI0RXP DMI_MTX_IRX_P0 <8>
For Express Card C311 2 1 0.1U_0402_10V7K PCIE_ITX_PRX_N1 P27 U29 DMI_ITX_MRX_N0 <EMI>
<31> PCIE_ITX_C_PRX_N1 PETN1 DMI0TXN DMI_ITX_MRX_N0 <8>
100K_0402_5% C312 2 1 0.1U_0402_10V7K PCIE_ITX_PRX_P1 P26 U28 DMI_ITX_MRX_P0 Q8

Direct Media Interface

<31> PCIE_ITX_C_PRX_P1 PETP1 DMI0TXP DMI_ITX_MRX_P0 <8>
R331 1 @ PM_DPRSLPVR_D EC_RSMRST#R

C
2 <32> EC_RSMRST# 3 1
PCIE_PTX_C_IRX_N2 DMI_MTX_IRX_N1

E
<30> PCIE_PTX_C_IRX_N2 L29 PERN2 DMI1RXN Y27 DMI_MTX_IRX_N1 <8>
100K_0402_5% PCIE_PTX_C_IRX_P2 L28 Y26 DMI_MTX_IRX_P1 @ BAV99DW-7_SOT363 @ MMBT3906_SOT23
<30> PCIE_PTX_C_IRX_P2 PERP2 DMI1RXP DMI_MTX_IRX_P1 <8>
R333 1 ICH_VGATE For Robson C313 2 0.1U_0402_10V7K PCIE_ITX_PRX_N2 DMI_ITX_MRX_N1

B
2 <30> PCIE_ITX_C_PRX_N2 1 M27 W29 DMI_ITX_MRX_N1 <8> 1 2 +3VALW

1 2
C314 2 0.1U_0402_10V7K PCIE_ITX_PRX_P2 PETN2 DMI1TXN DMI_ITX_MRX_P1 R334 @ 4.7K_0402_5%
<30> PCIE_ITX_C_PRX_P2 1 M26 PETP2 DMI1TXP W28 DMI_ITX_MRX_P1 <8>

2
PCI - Express
PCIE_PTX_C_IRX_N3 J29 AB27 DMI_MTX_IRX_N2 R335 D13B D13A @
<30> PCIE_PTX_C_IRX_N3 PERN3 DMI2RXN DMI_MTX_IRX_N2 <8>
For Wireless LAN PCIE_PTX_C_IRX_P3 J28 AB26 DMI_MTX_IRX_P2 @ 2.2K_0402_5% BAV99DW-7_SOT363
+3VALW <30> PCIE_PTX_C_IRX_P3 PERP3 DMI2RXP DMI_MTX_IRX_P2 <8>
C315 2 1 0.1U_0402_10V7K PCIE_ITX_PRX_N3 K27 AA29 DMI_ITX_MRX_N2
<30> PCIE_ITX_C_PRX_N3 PETN3 DMI2TXN DMI_ITX_MRX_N2 <8>
C316 2 1 0.1U_0402_10V7K PCIE_ITX_PRX_P3 K26 AA28 DMI_ITX_MRX_P2
<30> PCIE_ITX_C_PRX_P3 DMI_ITX_MRX_P2 <8>

1
RP36 PETP3 DMI2TXP
R336

6
5 4 USB_OC#1 PCIE_PTX_C_IRX_N4 G29 AD27 DMI_MTX_IRX_N3 1 2
<28> PCIE_PTX_C_IRX_N4 PERN4 DMI3RXN DMI_MTX_IRX_N3 <8>
6 3 USB_OC#2 For PCIE LAN PCIE_PTX_C_IRX_P4 G28 AD26 DMI_MTX_IRX_P3
B <28> PCIE_PTX_C_IRX_P4 PERP4 DMI3RXP DMI_MTX_IRX_P3 <8> B
7 2 USB_OC#10 C317 2 1 0.1U_0402_10V7K PCIE_ITX_PRX_N4 H27 AC29 DMI_ITX_MRX_N3 @ 2.2K_0402_5%
<28> PCIE_ITX_C_PRX_N4 PETN4 DMI3TXN DMI_ITX_MRX_N3 <8>
8 1 USB_OC#3 C318 2 1 0.1U_0402_10V7K PCIE_ITX_PRX_P4 H26 AC28 DMI_ITX_MRX_P3
<28> PCIE_ITX_C_PRX_P4 PETP4 DMI3TXP DMI_ITX_MRX_P3 <8>
10K_1206_8P4R_5% PCIE_PTX_C_IRX_N5 E29 T26 CLK_PCIE_ICH#
<26> PCIE_PTX_C_IRX_N5 PERN5 DMI_CLKN CLK_PCIE_ICH# <16>
For CardReader PCIE_PTX_C_IRX_P5 E28 T25 CLK_PCIE_ICH
<26> PCIE_PTX_C_IRX_P5 PERP5 DMI_CLKP CLK_PCIE_ICH <16>
RP39 C319 2 1 0.1U_0402_10V7K PCIE_ITX_PRX_N5 F27
<26> PCIE_ITX_C_PRX_N5 PETN5
5 4 C320 2 1 0.1U_0402_10V7K PCIE_ITX_PRX_P5 F26 AF29 R340 24.9_0402_1% Within 500 mils ICH_PWROK 1 2
<26> PCIE_ITX_C_PRX_P5 PETP5 DMI_ZCOMP
6 3 USB_OC#9 AF28 DMI_IRCOMP 1 2 +1.5VS_PCIE_ICH R338 10K_0402_5%
USB_OC#6 DMI_IRCOMP
7 2 C29 PERN6/GLAN_RXN
8 1 USB_OC#8 C28 AC5 USB20_N0 EC_RSMRST#R 1 2
PERP6/GLAN_RXP USBP0N USB20_N0 <35>
D27 AC4 USB20_P0 USB(IO/B) R342 10K_0402_5%
PETN6/GLAN_TXN USBP0P USB20_P0 <35>
10K_1206_8P4R_5% D26 AD3 USB20_N1
PETP6/GLAN_TXP USBP1N USB20_N1 <40>
follow iTPM spec AD2 USB20_P1 FP
USBP1P USB20_P1 <40>
1 2 ICH_SPI_MOSI ICH_SPI_CLK_R R345 @ 15_0402_5% ICH_SPI_CLK D23 AC1 USB20_N2
<34> ICH_SPI_CLK_R SPI_CLK USBP2N USB20_N2 <40>
R344 @ 20K_0402_5% ICH_SPI_CS0#_R R346 @ 15_0402_5% ICH_SPI_CS0# D24 AC2 USB20_P2 CAMERA
<34> ICH_SPI_CS0#_R SPI_CS0# USBP2P USB20_P2 <40>
1 2 ICH_SPI_MOSI F23 AA5 USB20_N3
<20> SPI_CS#1 SPI_CS1#GPIO58/CLGPIO6 USBP3N USB20_N3 <30>
R347 10K_0402_5% AA4 USB20_P3 WLAN
USBP3P USB20_P3 <30>
ICH_SPI_MOSI_R R348 @ 15_0402_5% ICH_SPI_MOSI
<34> ICH_SPI_MOSI_R
ICH_SPI_MISO
D25
E23
SPI_MOSI SPI USBP4N AB2
AB3 +3VS +3VALW
<34> ICH_SPI_MISO SPI_MISO USBP4P
AA1 USB20_N5
USBP5N USB20_N5 <35>
12/13 Modified USB_OC#04 N4 AA2 USB20_P5 USB(IO/B)
<35> USB_OC#04 OC0#/GPIO59 USBP5P USB20_P5 <35>
ID1 ID0 USB_OC#1 N5 W5 USB20_N6
by Andy OC1#/GPIO40 USBP6N USB20_N6 <34>
USB_OC#2 USB20_P6 R349 R350
USB_OC#3
N6 OC2#/GPIO41 USB USBP6P W4 USB20_P6 <34> BT @
JHT00 ( 00 ) R361 R357 R361 R355
P6 OC3#/GPIO42 USBP7N Y3
3.24K_0402_1% 3.24K_0402_1%
M1 OC4#/GPIO43 USBP7P Y2
JHT01 ( 01 ) R361 R355 N2 W1 USB20_N8
<35> USB_OC#511 OC5#/GPIO29 USBP8N USB20_N8 <30>
USB_OC#6 M4 W2 USB20_P8 TV CL_VREF0_ICH CL_VREF1_ICH
OC6#/GPIO30 USBP8P USB20_P8 <30>
JHL90 ( 10 ) R360 R357 CP_PE# M3 V2
<31> CP_PE# OC7#/GPIO31 USBP9N
USB_OC#8 N3 V3 1 1
USB_OC#9 OC8#/GPIO44 USBP9P USB20_N10 C323 R353 C324 R354
JHL91 ( 11 ) R360 R355 10K_0402_5% 10K_0402_5% USB_OC#10
N1 OC9#/GPIO45 USBP10N U5
USB20_P10
USB20_N10 <31>
@ @
01@ 01@
P5 OC10#/GPIO46 USBP10P U4
USB20_N11
USB20_P10 <31> New Card 0.1U_0402_16V4Z 453_0402_1% 0.1U_0402_16V4Z 453_0402_1%
P3 OC11#/GPIO47 USBP11N U1 USB20_N11 <35>
A USB20_P11 2 2 A
91@ 10K_0402_5% USBRBIAS USBP11P U2 USB20_P11 <35> USB(IO/B)
AG2 USBRBIAS
R355 1 2 2 1 AG1
+3VS USBRBIAS#
R360 R357 R356
00@ 10K_0402_5% 22.6_0402_1% ICH9-M ES_FCBGA676
R357 1 2 PROJECT_ID0 Within 500 mils

91@ 10K_0402_5% Security Classification Compal Secret Data Compal Electronics, Inc.
+3VS
R360 1 2 10K_0402_5% 10K_0402_5% Internal TPM Strap Issued Date 2007/08/18 Deciphered Date 2008/8/18 Title
90@ 90@
00@ 10K_0402_5% Low= Disable ICH9M(3/4)-USB,GPIO,PCIE
R361 1 2 PROJECT_ID1 SPI_MOSI High= iTPM enable by MCH strap*
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JHXXX M/B LA-4241P Schematic
Date: Tuesday, June 03, 2008 Sheet 22 of 49
5 4 3 2 1
 5 4 3 2 1

+5VS +3VS U7F U7E

(1UF*1, 0.1UF*2) 1634mA (0.1UF*2) 220u
+RTCVCC A23 VCCRTC VCC1_05[01] A15 +1.05VS ESR 15m ohm AA26 VSS[001] VSS[107] H5
1 1 VCC1_05[02] B15 1 AA27 VSS[002] VSS[108] J23

2
+ICH_V5REF A6 C15 1 1 Package(L*W*H)7.3*4.3*1.9 AA3 J26
R363 D14 C327 C328 V5REF VCC1_05[03] C325 C329 C330 + VSS[003] VSS[109]
2mA VCC1_05[04] D15 Rating 4V AA6 VSS[004] VSS[110] J27
E15 @ AB1 AC22
100_0402_5% CH751H-40PT_SOD323-2 2 2 +ICH_V5REF_SUS VCC1_05[05] 0.1U_0402_16V4Z 220U_D2_4VM_R15 VSS[005] VSS[111]
AE1 V5REF_SUS VCC1_05[06] F15 AA23 VSS[006] VSS[112] K28
1U_0402_6.3V4Z 0.1U_0402_16V4Z 2 2 2
2mA L11 AB28 K29

1
+ICH_V5REF VCC1_05[07] 0.1U_0402_16V4Z VSS[007] VSS[113]
AA24 VCC1_5_B[01] VCC1_05[08] L12 AB29 VSS[008] VSS[114] L13
2 (0.1UF*1) AA25 VCC1_5_B[02] VCC1_05[09] L14 AB4 VSS[009] VSS[115] L15
C331 AB24 L16 AB5 L2
VCC1_5_B[03] VCC1_05[10] VSS[010] VSS[116]
AB25 VCC1_5_B[04] VCC1_05[11] L17 AC17 VSS[011] VSS[117] L26
0.1U_0402_16V4Z AC24 L18 AC26 L27
1 VCC1_5_B[05] VCC1_05[12] +1.5VS_DMIPLL_ICH +1.5VS_DMIPLL_R VSS[012] VSS[118]
AC25 VCC1_5_B[06] VCC1_05[13] M11 AC27 VSS[013] VSS[119] L5
AD24 VCC1_5_B[07] VCC1_05[14] M18 AC3 VSS[014] VSS[120] L7
L22 1 R364 0_0603_5%

CORE
D AD25 VCC1_5_B[08] VCC1_05[15] P11 2 +1.5VS AD1 VSS[015] VSS[121] M12 D
+5VALW +3VALW MBK1608121YZF_0603
AE25 VCC1_5_B[09] VCC1_05[16] P18 AD10 VSS[016] VSS[122] M13
AE26 VCC1_5_B[10] VCC1_05[17] T11 1 (10UF*1, 0.01UF*1) AD12 VSS[017] VSS[123] M14
AE27 T18 C332 C333 AD13 M15
VCC1_5_B[11] VCC1_05[18] VSS[018] VSS[124]
2

AE28 VCC1_5_B[12] VCC1_05[19] U11 AD14 VSS[019] VSS[125] M16

R362 D15 AE29 U18 10U_0805_10V4Z AD17 M17
VCC1_5_B[13] VCC1_05[20] 2 VSS[020] VSS[126]
220u F25 VCC1_5_B[14] VCC1_05[21] V11 AD18 VSS[021] VSS[127] M23
10_0402_5% CH751H-40PT_SOD323-2 G25 V12 0.01U_0402_16V7K AD21 M28
ESR 15m ohm VCC1_5_B[15] VCC1_05[22] VSS[022] VSS[128]
H24 V14 AD28 M29
1

+ICH_V5REF_SUS Package(L*W*H)7.3*4.3*1.9 VCC1_5_B[16] VCC1_05[23] VSS[023] VSS[129]

H25 VCC1_5_B[17] VCC1_05[24] V16 AD29 VSS[024] VSS[130] N11
2 Rating 4V J24 V17 VCC_DMI R366 0_0603_5% +1.05VS AD4 N12
VCC1_5_B[18] VCC1_05[25] VSS[025] VSS[131]

VCCA3GP
C326 (0.1UF*1) J25 V18 AD5 N13
VCC1_5_B[19] VCC1_05[26] VSS[026] VSS[132]
K24 VCC1_5_B[20] 1 (22UF*1) AD6 VSS[027] VSS[133] N14
0.1U_0402_16V4Z K25 C334 AD7 N15
1 VCC1_5_B[21] VSS[028] VSS[134]
+1.5VS_PCIE_ICH
646mA L23 VCC1_5_B[22] 23mA AD9 VSS[029] VSS[135] N16
L24 R29 4.7U_0805_10V4Z AE12 N17
VCC1_5_B[23] VCCDMIPLL 2 VSS[030] VSS[136]
L23 2
(220UF*1, 22UF*2, 2.2UF*1) L25 VCC1_5_B[24] 48mA AE13 VSS[031] VSS[137] N18
+1.5VS 1 M24 VCC1_5_B[25] VCC_DMI[1] W23 AE14 VSS[032] VSS[138] N26
KC FBM-L11-201209-221LMAT_0805
1 M25 Y23 AE16 N27
VCC1_5_B[26] VCC_DMI[2] VSS[033] VSS[139]
10/22 CRB use 330 Ohm@100Mhz, +
1 1 N23 VCC1_5_B[27] 2mA AE17 VSS[034] VSS[140] P12
C337 C335 C336 C338 N24 AB23 +1.05VS AE2 P13
We use 220 Ohm 3A check! VCC1_5_B[28] V_CPU_IO[1] VSS[035] VSS[141]
N25 VCC1_5_B[29] V_CPU_IO[2] AC23 1 1 AE20 VSS[036] VSS[142] P14
220U_D2_4VM_R15 10U_0805_10V4Z P24 C339 C340 C341(4.7UF*1, 0.1UF*2) AE24 P15
2 2 2 VCC1_5_B[30] VSS[037] VSS[143]
P25 VCC1_5_B[31] VCC3_3[01] AG29 AE3 VSS[038] VSS[144] P16
10U_0805_10V4Z 2.2U_0603_6.3V6K R24 AJ6 4.7U_0805_10V4Z 0.1U_0402_16V4Z AE4 P17
VCC1_5_B[32] VCC3_3[02] 2 2 VSS[039] VSS[145]
R25 VCC1_5_B[33] VCC3_3[07] AC10 AE6 VSS[040] VSS[146] P2
R26 0.1U_0402_16V4Z AE9 P23
VCC1_5_B[34] VSS[041] VSS[147]
R27 VCC1_5_B[35] VCC3_3[03] AD19 AF13 VSS[042] VSS[148] P28

VCCP_CORE
T24 VCC1_5_B[36] VCC3_3[04] AF20 AF16 VSS[043] VSS[149] P29
T27 VCC1_5_B[37] VCC3_3[05] AG24 close to AG29 close to AC20 close to G6 308mA AF18 VSS[044] VSS[150] P4
T28 VCC1_5_B[38] VCC3_3[06] AC20 AF22 VSS[045] VSS[151] P7
T29 VCC1_5_B[39] +3VS AH26 VSS[046] VSS[152] R11
+1.5VS_SATAPLL_R +1.5VS_SATAPLL_ICH U24 AF26 R12
C VCC1_5_B[40] VSS[047] VSS[153] C
(10UF*1, 1UF*1) U25 VCC1_5_B[41] VCC3_3[08] B9 1 1 1 1 1 1 AF27 VSS[048] VSS[154] R13
+1.5VS L24 1 2 V24 F9 C342 C343 C344 C345 C346 C347 (0.1UF*6) AF5 R14
R367 MBK1608121YZF_0603 VCC1_5_B[42] VCC3_3[09] VSS[049] VSS[155]
V25 VCC1_5_B[43] VCC3_3[10] G3 AF7 VSS[050] VSS[156] R15
0_0603_5% 1 1 U23 G6 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z AF9 R16
VCC1_5_B[44] VCC3_3[11] 2 2 2 2 2 2 VSS[051] VSS[157]

PCI
C348 C349 W24 J2 AG13 R17
VCC1_5_B[45] VCC3_3[12] 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z VSS[052] VSS[158]
W25 VCC1_5_B[46] VCC3_3[13] J7 AG16 VSS[053] VSS[159] R18
10U_0805_10V4Z K23 VCC1_5_B[47] VCC3_3[14] K7 AG18 VSS[054] VSS[160] R28
2 1U_0402_6.3V4Z
2
(10UF*1, 1UF*1) Y24 VCC1_5_B[48] close to AD19 close to B9 close to K7 AG20 VSS[055] VSS[161] T12
Y25 VCC1_5_B[49] 11mA +VCC_HDA_ICH
AG23 VSS[056] VSS[162] T13
VCCHDA AJ4 AG3 VSS[057] VSS[163] T14
11mA +3VALW
AG6 VSS[058] VSS[164] T15
47mA AJ3 PM@ +3VS AG9 T16
VCCSUSHDA R368 0_0603_5% VSS[059] VSS[165]
AJ19 VCCSATAPLL (0.1UF*1) 1 AH12 VSS[060] VSS[166] T17
C350 GM@ +1.5VS AH14 T23
VSS[061] VSS[167]
VCCSUS1_05[1] AC8 TP_VCCSUS1_05_ICH_1 @ PAD T15
R369 0_0603_5% AH17 VSS[062] VSS[168] B26

2
+1.5VS AC16 VCC1_5_A[01] VCCSUS1_05[2] F17 TP_VCCSUS1_05_ICH_2 @ PAD T16
0.1U_0402_16V4Z AH19 VSS[063] VSS[169] U12
2 R671
AD15 VCC1_5_A[02] AH2 VSS[064] VSS[170] U13
AD16 TP_VCCSUS1_5_ICH_1 180_0402_1% AH22 U14
1 VCC1_5_A[03] VSS[065] VSS[171]
C351 AE15 AD8 TP_VCCSUS1_5_ICH_1 @ +VCCSUS_HDA_ICH @ AH25 U15
VCC1_5_A[04] VCCSUS1_5[1] PAD T17 VSS[066] VSS[172]

ARX
AF15 1 GM@ 2 AH28 U16

1
1U_0402_6.3V4Z VCC1_5_A[05] +VCCSUS1_5_ICH_INT_2 R798 0_0402_5% VSS[067] VSS[173]
AG15 VCC1_5_A[06] VCCSUS1_5[2] F18 AH5 VSS[068] VSS[174] U17
2
AH15 VCC1_5_A[07] 1 (0.1UF*1) 1 AH8 VSS[069] VSS[175] AD23

2
AJ15 (0.1UF*1) C353 C354 AJ12 U26
VCC1_5_A[08] R670 VSS[070] VSS[176]
1342mA VCCSUS3_3[01] A18 AJ14 VSS[071] VSS[177] U27
+1.5VS AC11 D16 0.1U_0402_16V4Z 0.1U_0402_16V4Z 150_0402_1% AJ17 U3

VCCPSUS
VCC1_5_A[09] VCCSUS3_3[02] 2 2 @ VSS[072] VSS[178]
AD11 VCC1_5_A[10] VCCSUS3_3[03] D17 AJ8 VSS[073] VSS[179] V1
1 AE11 E22 B11 V13

1
C355 VCC1_5_A[11] VCCSUS3_3[04] VSS[074] VSS[180]
AF11 VCC1_5_A[12] B14 VSS[075] VSS[181] V15
ATX

AG10 VCC1_5_A[13] B17 VSS[076] VSS[182] V23

1U_0402_6.3V4Z AG11 B2 V28
2 VCC1_5_A[14] VSS[077] VSS[183]
AH10 VCC1_5_A[15] (0.1UF*1, 0.022UF*2) B20 VSS[078] VSS[184] V29
AJ10 VCC1_5_A[16] VCCSUS3_3[05] AF1 +3VALW B23 VSS[079] VSS[185] V4
B 1 B5 VSS[080] VSS[186] V5 B
AC9 212mA 1 C357 R671 B8 W26
VCC1_5_A[17] C356 VSS[081] VSS[187]
10/22 follow common design 0928 0.1U_0402_16V4Z
C26 VSS[082] VSS[188] W27
AC18 VCC1_5_A[18] C27 VSS[083] VSS[189] W3
0.1U_0402_16V4Z 2
AC19 VCC1_5_A[19] E11 VSS[084] VSS[190] Y1
2
VCCSUS3_3[06] T1 E14 VSS[085] VSS[191] Y28
AC21 VCC1_5_A[20] VCCSUS3_3[07] T2 E18 VSS[086] VSS[192] Y29
+1.5VS VCCSUS3_3[08] T3 0_0402_5% E2 VSS[087] VSS[193] Y4
1 G10 T4 PM@ E21 Y5
C358 VCC1_5_A[21] VCCSUS3_3[09] VSS[088] VSS[194]
G9 VCC1_5_A[22] VCCSUS3_3[10] T5 +3VALW E24 VSS[089] VSS[195] AG28
VCCSUS3_3[11] T6 E5 VSS[090] VSS[196] AH6
0.1U_0402_16V4Z AC12 U6 E8 AF2
VCCPUSB

2 VCC1_5_A[23] VCCSUS3_3[12] C359 VSS[091] VSS[197]

AC13 VCC1_5_A[24] VCCSUS3_3[13] U7 F16 VSS[092] VSS[198] B25
AC14 VCC1_5_A[25] VCCSUS3_3[14] V6 F28 VSS[093]
+1.5VS 11mA V7 4.7U_0805_10V4Z F29
VCCSUS3_3[15] VSS[094]
1 AJ5 VCCUSBPLL VCCSUS3_3[16] W6 G12 VSS[095]
C360 11mA W7 G14 A1
VCCSUS3_3[17] VSS[096] VSS_NCTF[01]
USB CORE

AA7 VCC1_5_A[26] VCCSUS3_3[18] Y6 G18 VSS[097] VSS_NCTF[02] A2

0.1U_0402_16V4Z AB6 Y7 G21 A28
2 VCC1_5_A[27] VCCSUS3_3[19] VSS[098] VSS_NCTF[03]
(0.1UF*1) AB7 VCC1_5_A[28] VCCSUS3_3[20] T7 G24 VSS[099] VSS_NCTF[04] A29
AC6 VCC1_5_A[29] G26 VSS[100] VSS_NCTF[05] AH1
+3VS (0.1UF*1) AC7 VCC1_5_A[30] G27 VSS[101] VSS_NCTF[06] AH29
1 G8 VSS[102] VSS_NCTF[07] AJ1
C362 2 1 +VCCLAN1_05_INT_ICH A10 VCCLAN1_05[1] H2 VSS[103] VSS_NCTF[08] AJ2
C361 0.1U_0402_16V4Z A11 VCCLAN1_05[2] VCCCL1_05 G22 +VCCCL1_05_INT_ICH H23 VSS[104] VSS_NCTF[09] AJ28
19mA VCCCL1_5 G23 +VCCCL1_5_INT_ICH H28 VSS[105] VSS_NCTF[10] AJ29
2
A12 VCCLAN3_3[1] H29 VSS[106] VSS_NCTF[11] B1
0.1U_0402_16V4Z B12 1 1 1 B29
VCCLAN3_3[2] C363 C365 C364 VSS_NCTF[12]
23mA VCCCL3_3[1] A24 +3VS
@ @
(0.1UF*1)
VCCCL3_3[2] B24
GLAN POWER

+1.5VS +VCC_GLANPLL_R 1 2 +VCC_GLANPLL_ICH A27 19mA 1U_0402_6.3V4Z 0.1U_0402_16V4Z ICH9-M ES_FCBGA676

R372 MBK1608121YZF_0603 1 VCCGLANPLL 2 2 2
0_0603_5% L25 C367 D28 0.1U_0402_16V4Z
A
C366 VCCGLAN1_5[1] A
D29 VCCGLAN1_5[2]
(2.2UF*1, 10UF*1) 10U_0805_10V4Z
2
E26 VCCGLAN1_5[3]
E27 VCCGLAN1_5[4] (1UF*1, 0.1UF*1)
2.2U_0603_6.3V6K
80mA A26 VCCGLAN3_3
+1.5VS_PCIE_ICH
ICH9-M ES_FCBGA676
(4.7UF*1) C368 +3VS
1mA
Security Classification Compal Secret Data Compal Electronics, Inc.
4.7U_0805_10V4Z 2007/08/18 2008/8/18 Title
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH9M(4/4)-POWER&GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JHXXX M/B LA-4241P Schematic
Date: Tuesday, June 03, 2008 Sheet 23 of 49
5 4 3 2 1
 A B C D E F G H

14W SATA ODD Conn.

+5VS
1 1
0.1U_0402_16V4Z

1 1 1
C369 C370 C371
14W@ 14W@ 14W@
2 2 2

1000P_0402_50V7K 10U_0805_10V4Z
SATA ODD Conn.
Copy JIWA2 Symbol

JSATA1

1 GND
SATA_ITX_C_DRX_P1 2
<21> SATA_ITX_C_DRX_P1 A+
SATA_ITX_C_DRX_N1 3
<21> SATA_ITX_C_DRX_N1 A-
4 GND
SATA_DTX_IRX_N1 5
SATA_DTX_IRX_P1 B-
6 B+
7 GND

R373 1 @ 2 1K_0402_1% 8 DP
+5VS 9 +5V
10
11
+5V
MD
SATA HDD Conn.
12 GND
13 GND
2 OCTEK_SLS-13SB1G 2
SATA_DTX_C_IRX_N1 1 2 SATA_DTX_IRX_N1
<21> SATA_DTX_C_IRX_N1
C372 0.01U_0402_16V7K

SATA_DTX_C_IRX_P1 1 2 SATA_DTX_IRX_P1 Update FootPrint from

<21> SATA_DTX_C_IRX_P1
C373 0.01U_0402_16V7K
OCTEK_SLS-13SB1G_13P-T to
OCTEK_SLS-13SB1G_13P_RV-T

+5VS +3VS

0.1U_0402_16V4Z 10U_0805_10V4Z

1 1 1 1 1 1
C374 C375 C376 C377 C378 C379

0.1U_0402_16V4Z
2 2 2 2 2 2 @

1000P_0402_50V7K 1U_0603_10V4Z 10U_0805_10V4Z

15W SATA ODD Conn.

+5VS_ODD
JSATA3
0.1U_0402_16V4Z S1
SATA_ITX_C_DRX_P0 GND
<21> SATA_ITX_C_DRX_P0 S2 A+
3 SATA_ITX_C_DRX_N0 3
1 1 1 <21> SATA_ITX_C_DRX_N0 S3 A-
C381 C382 C380 S4
15W@ 15W@ 15W@ SATA_DTX_C_IRX_N0 SATA_DTX_IRX_N0 GND
<21> SATA_DTX_C_IRX_N0 1 2 S5 B-
C383 3900P_0402_50V7K S6
2 2 2 SATA_DTX_C_IRX_P0 SATA_DTX_IRX_P0 B+
1 2 S7

1000P_0402_50V7K 10U_0805_10V4Z
SATA ODD Conn. <21> SATA_DTX_C_IRX_P0
C384 3900P_0402_50V7K GND

Copy JIWA2 Symbol +3VS P1

P2
V33
V33
P3 V33
P4 GND
JSATA2 P5 GND
P6 GND
1 GND +5VS P7 V5
SATA_ITX_C_DRX_P1 R374 2 1 0_0402_5% SATA_ITX_C_DRX_P1_R SATA_ITX_C_DRX_P1_R 2 P8
15W@ SATA_ITX_C_DRX_N1_R A+ V5
3 A- P9 V5
SATA_ITX_C_DRX_N1 R375 2 1 0_0402_5% SATA_ITX_C_DRX_N1_R 4 P10
15W@ SATA_DTX_IRX_N1_R GND GND
5 B- P11 Reserved
SATA_DTX_IRX_N1 R376 2 1 0_0402_5% SATA_DTX_IRX_N1_R SATA_DTX_IRX_P1_R 6 P12
15W@ B+ GND
7 GND P13 V12
SATA_DTX_IRX_P1 R377 2 1 0_0402_5% SATA_DTX_IRX_P1_R P14 23
15W@ V12 GND
P15 V12 GND 24
R378 1 @ 2 1K_0402_1% 8 DP FOX_LD2122H-S43_NR
+5VS_ODD 9 +5V
10 CONN@
+5V
11 MD
12 GND
13 GND
OCTEK_SLS-13SB1G
Update Symbol
SP01000G800
4 FOX_LD2122H-S43_NR 4

+5VS +5VS_ODD Update FootPrint from Manually update pin number

OCTEK_SLS-13SB1G_13P-T to
1 2 OCTEK_SLS-13SB1G_13P_RV-T
R778 15W@ 0_1206_5%
1 2
R779 15W@ 0_1206_5%
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/08/18 Deciphered Date 2008/8/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDD & ODD Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JHXXX M/B LA-4241P Schematic
Date: Wednesday, May 28, 2008 Sheet 24 of 49
A B C D E F G H
 5 4 3 2 1

WCM2012F2SF-121T04_0805 Change L43,L44,L45,L46 from SM070000M00 to WCM2012F2SF-121T04_0805 D16

HDMI_CLK+ HDMI_CLK+_R SM070000K00 HDMI_TX1+ 4 HDMI_TX1+_R
Place close pin 11 and 12 Place close pin 40 and 37
4 4 3 3 4 3 3 3 +5VS
HDMIDAT +VCC3V +3VS
1 Place close pin 21 and 24 R379
2
HDMI_CLK- 1 HDMI_CLK-_R HDMI_TX1- 1 HDMI_TX1-_R +VCC3V
1 2 2 1 2 2 1 2
L43 <EMI> @ L44 <EMI> @ DAN217_SC59

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
<EMI> <EMI> 0_0603_5%
1 2 R643 0_0402_5% 1 2 R651 0_0402_5% @ <EMI> GM@
2 2 2 2 2 2
1 2 R645 0_0402_5% 1 2 R653 0_0402_5% D17
C385 C386 C387 C388 C389 C390
<EMI> U12 <EMI>
3 +5VS GM@ GM@ GM@ GM@ GM@ GM@
HDMICLK 1 1 1 1 1 1
1
2
WCM2012F2SF-121T04_0805
D HDMI_TX2+ 4 HDMI_TX2+_R WCM2012F2SF-121T04_0805 D
4 3 3 CH7318C-BF-TR QFN 48P HDMI_TX0+ 4 HDMI_TX0+_R DAN217_SC59
7318@ 4 3 3 @ <EMI>
HDMI_TX2- 1 2 HDMI_TX2-_R Place close pin 33 and 36
1 2 HDMI_TX0- 1 HDMI_TX0-_R
L45 <EMI> @ Change U12 from SA00001U900(CH7318A) to 1 2 2
<EMI> SA00002D700(PS8101T) L46 <EMI> @ <EMI>
Place close pin 15 and 18 Place close pin 46 and 43
1 2 R647 0_0402_5% Add U12 from SA00001U920(CH7318C) 1 2 R655 0_0402_5%
1 2 R649 0_0402_5% 1 2 R657 0_0402_5%
<EMI> U12 <EMI>

Symbol modified pn to R380 2 @ 1 0_0402_5% +3VS

+3VS 25 R383 2 7318@ 1 0_0402_5% +5VS_HDMI
SD034120180. OE*

Never use this symbol 2 VCC3V HDMICLK

11 VCC3V SCL_SINK 28
for other platform 15 Pull high on VGA/B
+3VS VCC3V HDMIDAT +3VS
21 VCC3V SDA_SINK 29

1
26 VCC3V
33 R384 R385
VCC3V HDMI_DETECT
40 VCC3V HPD_SINK 30
1

+VCC3V 46 2.2K_0402_5% 2.2K_0402_5%

R381 R382 VCC3V R386 2 GM@
32 1 4.7K_0402_5% +3VS

2
DDC_EN

2
R388 R387 2 @ 1 0_0402_5%
2.2K_0402_5% 2.2K_0402_5%
GM@ GM@ 3 34 R800 2 7318@ 1 4.7K_0402_5% +3VS HDMIDAT 6 1 VGA_DDC_HDMIDAT
2

FUNCTION1 FUNCTION3 R801 2 @

4 FUCNTION2 FUNCTION4 35 1 0_0402_5%
PM@ Q10A

5
R802 2 7318@ 1 4.7K_0402_5% +3VS 2N7002DW-T/R7_SOT363-6
1.2K_0402_1% 1 2 6 R803 2 @ 1 0_0402_5%
7318@ R388 8101@ 430_0402_1% ANALOG1(REXT) HDMICLK VGA_DDC_HDMICLK
3 4
HPD_SOURCE 7
C HPD_SOURCE PM@ Q10B C

<8> HDMIDAT_NB 8 2N7002DW-T/R7_SOT363-6

SDA_SOURCE

<8> HDMICLK_NB 9 SCL_SOURCE

10/16 change symbol from SC1B411D000 to SC1B411D010
10 ANALOG2
C391 @ 0.5P_0402_50V8B
+5VS
R389 @ 68_0402_5% HDMI_CLK+ 13 48 IN_D4+ 1 4 PCIE_MTX_C_GRX_P3 <10,17> 1 R807@ 2
HDMI_CLK- OUT_D4+ IN_D4+ IN_D4- 0_0805_5%
14 OUT_D4- IN_D4- 47 2 3 PCIE_MTX_C_GRX_N3 <10,17>
C392 @ 0.5P_0402_50V8B RP47 GM@ 0_0404_4P2R_5% D18
HDMI_TX2+ 16 45 IN_D3+ 1 4 PCIE_MTX_C_GRX_P0 <10,17> 2 1 +VCC_HDMI 1 2 +5VS_HDMI
R390 @ 68_0402_5% HDMI_TX2- OUT_D3+ IN_D3+ IN_D3- F2
17 OUT_D3- IN_D3- 44 2 3 PCIE_MTX_C_GRX_N0 <10,17>
RP48 GM@ 0_0404_4P2R_5% RB491D_SC59-3 1.1A_6VDC_FUSE 1
C393 @ 0.5P_0402_50V8B HDMI_TX1+ 19 42 IN_D2+ 1 4 C394
OUT_D2+ IN_D2+ PCIE_MTX_C_GRX_P1 <10,17>
HDMI_TX1- 20 41 IN_D2- 2 3
OUT_D2- IN_D2- PCIE_MTX_C_GRX_N1 <10,17>
R391 @ 68_0402_5% RP49 GM@ 0_0404_4P2R_5% 0.1U_0402_16V4Z
HDMI_TX0+ IN_D1+ 2
22 39 1 4
C395

R392
@

@
0.5P_0402_50V8B

68_0402_5%
HDMI_TX0- 23
OUT_D1+
OUT_D1-
IN_D1+
IN_D1- 38 IN_D1- 2
RP50
3
GM@
PCIE_MTX_C_GRX_P2 <10,17>
PCIE_MTX_C_GRX_N2 <10,17>
0_0404_4P2R_5% HDMI Connector JHDMI1
HDMI_HPD 19 HP_DET
1 GND 18 +5V
5 +3VS 17
GND DDC/CEC_GND

1
12 +5VS HDMIDAT 16
GND 1 SDA

1
18 R811 R632 C649 HDMICLK 15
GND R631 GM@ SCL
24 GND 2 14 Reserved
27 C650 PM@ 0_0402_5% 100K_0402_5% 0.1U_0402_16V4Z 13
GND CEC

5
1
2.2K_0402_5% 2 HDMI_CLK-_R
31 12 20

2
GND 0.1U_0402_16V4Z CK- GND
36 11 21

P
OE#

2
GND PM@ 1 HDMI_DETECT HDMI_CLK+_R CK_shield GND
37 GND 2 A Y 4 10 CK+ GND 22
B HDMI_TX0-_R B
43 GND 9 D0- GND 23

G
U35 8
SN74AHCT1G125GW_SOT353-5 HDMI_TX0+_R D0_shield
7

3
PS8101TQFN48G QFN 48P PM@ HDMI_TX1-_R D0+
6 D1-
8101@ 5
HDMI_TX1+_R D1_shield
4 D1+
HDMI_TX2-_R 3 D2-
2 D2_shield
HDMI_TX2+_R 1
Inverting level shift for hot-plug detect D2+
TYCO_1775040-6
+3VS Layout Notice: CONN@
Need short
2

R395
7318@
20K_0402_5%

Cantiga NB Ext VGA R HDMI Conn. <17> VGA_HDMI_CLK+ 1 4 HDMI_CLK+

1

C <17> VGA_HDMI_CLK- 2
RP51
3 HDMI_CLK-
PM@ 0_0404_4P2R_5%
R810 1 8101@ 2 0_0402_5% 1 4 HDMI_TX0+
R <17> VGA_HDMI_TX0+
<17> VGA_HDMI_TX0- 2
RP52
3 HDMI_TX0-
PM@ 0_0404_4P2R_5%
<10> TMDS_B_HPD#
CH7318 <17> VGA_HDMI_TX1+ 1 4 HDMI_TX1+
Q11 2 3 HDMI_TX1-
<17> VGA_HDMI_TX1-
SSM3K7002FU_SC70-3 RP53 PM@ 0_0404_4P2R_5%
1

D 7318@ HDMI_TX2+
<17> VGA_HDMI_TX2+ 1 4
R401 2 HPD_SOURCE 2 3 HDMI_TX2-
<17> VGA_HDMI_TX2-
7318@ G RP54 PM@ 0_0404_4P2R_5%
2

7.5K_0402_1% R406 2 PM@ 1 0_0402_5% HDMI_DETECT

S Near MXM conn. <17> VGA_HDMI_DETECT
3

R405
2

A 7318@ VGA_DDC_HDMIDAT A
<17> VGA_HDMIDAT 1 4
100K_0402_5% <17> VGA_HDMICLK 2 3 VGA_DDC_HDMICLK
RP59 PM@ 0_0404_4P2R_5%
1

Security Classification Compal Secret Data Compal Electronics, Inc.

100K follow DG 0.8 Issued Date 2007/08/18 Deciphered Date 2008/8/18 Title
If there is 5% resister availble,just change CH7318A&HDMI Connector
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JHXXX M/B LA-4241P Schematic
Date: Tuesday, June 03, 2008 Sheet 25 of 49
5 4 3 2 1
 5 4 3 2 1

SD,MMC,MS muti-function pin define

Active High EN MDIO SD/MMC Card MS Card
11/24 Andy PIN Name PIN Name PIN Name
40mil MDIO00 SD1_DAT0 MS1_DAT0
+3VS +VCC_OUT MDIO01 SD1_DAT1 MS1_DAT1
+VCC_3IN1
Use 0805 type and over 20 mils U13 MDIO02 SD1_DAT2 MS1_DAT2
trace width on both side
3 VIN VOUT 1 MDIO03 SD1_DAT3 MS1_DAT3
4 VIN/CE VOUT 5
+VCC_OUT +VCC_3IN1 MDIO04 SD1_CMD MS1_BS

1U_0603_10V4Z
1

2
C397 2 1
GND

C398
@ R410 MDIO05 SD1_CLK MS1_CLK
D 1 2 0.1U_0402_16V4Z RT9701-PB_SOT23-5 D
R409 2 150K_0402_5%
@
2
MDIO06 SD1_WP
0_0805_5% 1 1 @

1
C400 MDIO07
C399
10U_0805_10V4Z 0.1U_0402_16V4Z reserved power circuit MDIO08 MMC_DAT4 MS1_DAT4
2 2
mount JMB suggest MDIO09 MMC_DAT5 MS1_DAT5
MDIO10 MMC_DAT6 MS1_DAT6
+VCC_3IN1
MDIO11 MMC_DAT7 MS1_DAT7
MDIO12
1 2 SDWP#_MMCWP# MDIO13
R411 10K_0402_5% +1.8VS_CR
20mil Refer JMB suggest 11/14 MDIO14
1 2 XD_RB# 0.1U_0402_16V4Z 1 2 +1.8VS_CRR
R412 10K_0402_5% 1 1 1 1 R413 @ 0_0805_5% CR1_LEDN SD1_LED# MS1_LED#
C401 C402 C403 C404 CR1_PCTLN SD1_PCTL# MS1_PCTL#
0.1U_0402_16V4Z
2 2 2 2
CR1_CD0 SD1_CD#
10U_0805_10V4Z 1000P_0402_50V7K
CR1_CD1 MS1_CD#
U14
40 mil
+3VS
1 1 1 1
3 5 C651 C652 C405 C406
<16> CLK_PCIE_CARD# APCLKN APVDD
<16> CLK_PCIE_CARD 4 APCLKP APV18 10
30 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
TAV33 2 2 2 2
<22> PCIE_ITX_C_PRX_N5 9 APRXN
<22> PCIE_ITX_C_PRX_P5 8 APRXP DV33 19
C DV33 20 C
C407 1 2 0.1U_0402_10V7K PCIE_PTX_IRX_N5 11 44
<22> PCIE_PTX_C_IRX_N5 APTXN DV33
C408 1 2 0.1U_0402_10V7K PCIE_PTX_IRX_P5 12 18 +1.8VS_CR
<22> PCIE_PTX_C_IRX_P5 APTXP DV18
R414 1 2 8.2K_0402_5% APREXT 7
DV18 37 12mil 1 1
APREXT SDDATA0_MSDATA0 C409 C410
12mil,length <250 mil MDIO0 48
+3VS 47 SDDATA1_MSDATA1 0.1U_0402_16V4Z
MDIO1 SDDATA2_MSDATA2 2 2
1 2 38 PCIES_EN MDIO2 46
R665 0_0402_5% 39 45 SDDATA3_MSDATA3 0.1U_0402_16V4Z
Refer JMB suggest 11/09
PCIES JMB385 MDIO3
MDIO4 43 SDCMD_MSBS
42 SDCLK_MSCLK R420 1 2 22_0402_5% SDCLK
MDIO5 SDWP#_MMCWP#
MDIO6 41
Change Pin definition for Rev:B 40 XD_CLE R421 1 2 22_0402_5% MSCLK
MDIO7
MDIO8 29
<8,17,20,28,30,40> PLT_RST_BUF# 1 XRSTN MDIO9 28
2 XTEST MDIO10 27 Damping need to close to IC
<22> GPIO18 1 2 MDIO11 26
R673 @ 0_0402_5% 25 XD_RE#
+3VS MDIO12 XD_RB#
@
13
14
D3E_WAKEN MDIO13 23
22 XD_ALE
Strap pin for JMicro
T19 PAD NC MDIO14
34 +3VS
R415 MSCD#_XDCD1 NC
1 2 4.7K_0402_5% 15 CR1_CD1N NC 35
R416 1 2 4.7K_0402_5% SDCD#_XDCD0# 16 36 1 2 XD_CLE
CR1_CD0N NC R417 10K_0402_5%
1 2 6
<22> CR_WAKE#
R642 @ 0_0402_5% +VCC_OUT 17 CR1_PCTLN
APGND
200K_0402_5%
2 1
R418
XD_RE# 3 in 1 Card Reader
40 mil GND 24
31 2 1 XD_ALE
GND 200K_0402_5% R419 JREAD1
21 CR1_LEDN GND 32
GND 33 +VCC_3IN1 6 VDD_SD
SDDATA0_MSDATA0 9
SDDATA1_MSDATA1 DAT0_SD
10 DAT1_SD
SDDATA2_MSDATA2
JMB385-LGEZ0A_LQFP48_7X7
Refer JMB suggest 11/09 SDDATA3_MSDATA3
2
3
DAT2_SD
SDCLK CD/DAT3_SD
B 7 CLK_SD
B
SDWP#_MMCWP# 11
SDCMD_MSBS WP_SD
4 CMD_SD
SDCD#_XDCD0# 1

C701
D66
SDCD#_XDCD0#
Rev :B 5
CD_SD
VSS_SD
3 8 VSS_SD
2 1 1
2 MSCD#_XDCD1
270P_0402_50V7K SDDATA1_MSDATA1 19
@ VCC_MS
DAN202UT106_SC70-3 13 VCC_MS
MSCLK 14
@ MSCD#_XDCD1 SCLK_MS
16 INS_MS
SDDATA0_MSDATA0 18
SDCMD_MSBS SDIO_MS
20 BS_MS
SDDATA3_MSDATA3 15
SDDATA2_MSDATA2 RESERVED_MS
17 RESERVED_MS
21 VSS_MS
12 VSS_MS
22 GND
23 GND
+1.8V
PROCO_MDR019-C0-1202
CONN@

1
C713
@
10/17 add for
1U_0603_10V4Z JMB380
3

2
S
R532 1 2 100K_0402_5% 2
G
@
The circuit need reserve for JMB385?
<41,47> SUSP
@ Q50 SDCLK 1 2 1 2
C714 SI2301BDS_SOT23
@ R633 C412
D
0.1U_0402_16V4Z W=40mils @ 100_0402_5% @ 100P_0402_50V8J
1

A +1.8VS_CRR A

MSCLK 1 2 1 2

R634 C413
@ 100_0402_5% @ 100P_0402_50V8J

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/18 Deciphered Date 2008/8/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
JMB385 CardReader
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JHXXX M/B LA-4241P Schematic
Date: Tuesday, June 03, 2008 Sheet 26 of 49
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/18 Deciphered Date 2008/8/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
3 in 1 Card Reader Conn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. JHXXX M/B LA-4241P Schematic
Date: Friday, April 11, 2008 Sheet 27 of 49
5 4 3 2 1
 5 4 3 2 1

width > 60mil

Max 340mA
SROUT12
Length < 200mil to Pin1 R424 8102E@ 0_0603_5%
AVDD12 FB12
L27 8111C@
AVDD12 0.1U_0402_16V4Z R425 0_0603_5% 1 2
1 1 1 1 1 1 4.7UH_1008HC-472EJFS-A_5%_1008 1
C414 C415 C416 C417 C418 C419 C420
+3VALW VDD33 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z @
8111C@ 8111C@ 0.1U_0402_16V4Z 22U_0805_6.3V6M
Max 541mA R426 width > 40mil
2 2 2 2 2 2
22U_0805_6.3V6M
8111C@
2
0.1U_0402_16V4Z VDD33
D Bead current rating:600mA D
0_0603_5% EVDD12

0.1U_0402_16V4Z
1 1 1 1 1 1 Inductor=4.7uH,600mA
C421 C422 C423 C424 C425 C426 L28 MBK1608121YZF_0603 SHI00004C00
@ EVDD12 1 2
22U_0805_6.3V6M 0.1U_0402_16V4Z 8111C@

D
6 1 1 1
2 2 2 2 2 2 C722 C427 C428
S

4 5
Q12 2 0.1U_0402_16V4Z 8102E@ 8111C@
SI3445ADV-T1-E3_TSOP6 1 0.1U_0402_16V4Z 4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z R427 @ 0_0603_5%
@ AVDD33 2 2 2
G

width > 40mil R428

3

0_0603_5%
@ R429 0_0603_5% AVDD33
R678 1 210K_0402_5% 1 1
8111C@ Max 340mA
EN_WOL# <32>
2 C430 C431
C429 CTRL12
@ 0.1U_0402_16V4Z DVDD12
0.1U_0402_16V4Z 2 2 8111C@
1 0.1U_0402_16V4Z DVDD12 0.1U_0402_16V4Z 0.1U_0402_16V4Z R430 8102E@ 0_0603_5% CTRL12
For soft start
Andy 11/24 1 1 1 1 1 1
C436 C437 C438 C439 C440 C441

0.1U_0402_16V4Z
2 2 2 2 2 2

0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

8111C@

U15

C
<22> PCIE_PTX_C_IRX_P4 2 1 PCIE_PTX_IRX_P4 29 HSOP EEDO 45 EEDO C
C442 0.1U_0402_10V7K 47 EEDI
EEDI/AUX
<22> PCIE_PTX_C_IRX_N4 2 1 PCIE_PTX_IRX_N4 30 HSON EESK 48 EESK
C443 0.1U_0402_10V7K 44 EECS
PCIE_ITX_C_PRX_P4 EECS
<22> PCIE_ITX_C_PRX_P4 23 HSIP
PCIE_ITX_C_PRX_N4 24
<22> PCIE_ITX_C_PRX_N4 HSIN
LED3 54
55 LINK10 R431 1 2 0_0402_5%
LAN_CLKREQ# R432 1 LED2
<16> LAN_CLKREQ# 2 0_0402_5% CKREQB 33 CLKREQB LED1 56 LINKLED#
LINKLED# <29>
57 ACTIVITY#
LED0 ACTIVITY# <29>
CLK_PCIE_LAN 26
<16> CLK_PCIE_LAN REFCLK_P
CLK_PCIE_LAN# 27 3 MDI0+ VDD33
<16> CLK_PCIE_LAN# REFCLK_N MDIP0 MDI0+ <29>
4 MDI0-
MDIN0 MDI0- <29>
PLT_RST_BUF# 20 6 MDI1+
<8,17,20,26,30,40> PLT_RST_BUF# PERSTB MDIP1 MDI1+ <29>

1
7 MDI1-
MDIN1 MDI1- <29> VDD33
width > 60mil 9 MDI2+ R433
MDIP2 MDI2+ <29>
SROUT12 1 10 MDI2- U16
SROUT12 MDIN2 MDI2- <29>
12 MDI3+ 3.6K_0402_5% EECS 1 8
MDIP3 MDI3+ <29> CS VCC
2 1 FB12 5 13 MDI3-
MDI3- <29>
EESK 2 7 1

2
C721 0.01U_0402_16V7K FB12 MDIN3 EEDI SK NC C445
3 DI NC 6
+3VS VDD33 R434 1 2 8111C@ 0_0402_5% ENSR 62 EEDO 4 5 @
R435 1 ENSR DO GND
2 @ 0_0402_5% DVDD12 21 DVDD12 0.1U_0402_16V4Z
R436 2.49K_0402_1% RSET AT93C46-10SI-2.7_SO8 2
64 RSET DVDD12 32
1

38 @
R439 DVDD12
DVDD12 43
1K_0402_5% 49
ICH_PCIE_WAKE# DVDD12
<22,30,31> ICH_PCIE_WAKE# 19 LANWAKEB DVDD12 52
B B
2

ISOLATEB ISOLATEB 36 ISOLATEB EVDD12

EVDD12 22
1

R441 LAN_XTAL_IN 60
EVDD12 28 Pin 11,14,32,38,52,59 are NC pins when use 8102E
CKTAL1
15K_0402_5% LAN_XTAL_OUT 61 16 VDD33
CKTAL2 VDD33
37
2

VDD33
VDD33 46
53 width > 40mil CTRL12
VDD33
65 EXPOSE_PAD
10/09 change to SJ125P0M200 Length < 200mil R443 8111C@ 0_0603_5% VDD33
VDDSR 63
25 EGND
LAN_XTAL_IN 2 AVDD33 1
AVDD33 C446
31 EGND AVDD33 59 1
C447
Y2 8 AVDD12 8111C@ 0.1U_0402_16V4Z
LAN_XTAL_OUT DVDD12 R445 8102E@ 0_0603_5% AVDD12 22U_0805_6.3V6M 2
1 2 15 NC AVDD12 11
2 8111C@
17 NC AVDD12 14
18 58 R448 8111C@ 0_0603_5%
NC AVDD12 R449 8102E@ 0_0603_5% DVDD12
25MHz_20pF_6X25000017 34 NC
1 1 35 NC
39 NC IGPIO 50
C448 C449 40 51 U15
NC OGPIO
27P_0402_50V8J 27P_0402_50V8J 41 NC
2 2
42 NC
RTL8111C-GR_QFN64_9X9
A A
8111C@
8102E
8102E@

Security Classification Compal Secret Data

Issued Date 2007/08/18 Deciphered Date 2008/8/18 Title
LAN-RTL8111C/RTL8102E
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JHXXX M/B LA-4241P Schematic
Date: Tuesday, June 03, 2008 Sheet 28 of 49
5 4 3 2 1
 5 4 3 2 1

D D

T20
C450 1 2 0.01U_0402_16V7K V_DAC 1 24 MCT0 R450 2 1 75_0402_5%
MDI0+ TCT1 MCT1 MDO0+
<28> MDI0+ 2 TD1+ MX1+ 23
MDI0- 3 22 MDO0-
<28> MDI0- TD1- MX1-
C451 1 2 0.01U_0402_16V7K 4 21 MCT1 R451 2 8111C@ 1 75_0402_5%
8111C@ MDI2+ TCT2 MCT2 MDO2+
<28> MDI2+ 5 TD2+ MX2+ 20
MDI2- 6 19 MDO2-
<28> MDI2- TD2- MX2-
C452 1 2 0.01U_0402_16V7K 7 18 MCT2 R452 2 1 75_0402_5%
MDI1+ TCT3 MCT3 MDO1+
<28> MDI1+ 8 TD3+ MX3+ 17
MDI1- 9 16 MDO1-
<28> MDI1- TD3- MX3-
C453 1 2 0.01U_0402_16V7K 10 15 MCT3 R453 2 8111C@ 1 75_0402_5% RJ45_PR
8111C@ MDI3+ TCT4 MCT4 MDO3+
<28> MDI3+ 11 TD4+ MX4+ 14
MDI3- 12 13 MDO3-
<28> MDI3- TD4- MX4-
GSL5009LF
C 8111C@ C

3/4 Change T20 Value from 350uH_GSL5009LF to GSL5009LF

Change T20 P/N fromSP050003T00 to SP050003T10

Lan Conn.
2 1 <EMI> JP23
T21 C454 470P_0402_50V7K 12
VDD33 Amber LED+
MDI0+ 1 16 MDO0+ ACTIVITY# 1 2 LAN_ACT# 11
MDI0- RD+ RX+ MDO0- <28> ACTIVITY# Amber LED-
2 RD- RX- 15 R454 300_0402_5% 10mil 16
V_DAC 3 14 MCT0 MDO3- SHLD2
CT CT 8 PR4-
4 NC NC 13 15
5 12 MDO3+ SHLD1
NC NC 7 PR4+
V_DAC 6 11 MCT2
MDI1+ CT CT MDO1+
7 TD+ TX+ 10 MDO1- 6
B MDI1- 8 9 MDO1- PR2- B
TD- TX-
MDO2- 5 PR3-
NS0013LF MDO2+ 4
8102E@ PR3+
MDO1+ 3 PR2+
Change T21 Value from 350uH_NS0013LF to NS0013LF MDO0- 2 PR1-
SHLD2 14
MDO0+ 1 PR1+
10mil SHLD1 13
LINKLED# 1 2 LAN_LINK# 10
<28> LINKLED# Green LED-
R455 300_0402_5%
VDD33 9 Green LED+
2 1 <EMI>
C455 470P_0402_50V7K TYCO_3-440470-4
CONN@
C456
RJ45_PR 1 2 <EMI> LANGND
1 1
1000P_1206_2KV7K
C457 C458
0.1U_0402_16V4Z 4.7U_0805_10V4Z
2 2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/18 Deciphered Date 2008/8/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LAN CONNECTOR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JHXXX M/B LA-4241P Schematic
Date: Wednesday, May 28, 2008 Sheet 29 of 49
5 4 3 2 1
 A B C D E

NAND mini Card(Robson support) Mini-Express Card for TV Tuner +3VS +1.5VS +3VS

+3VS_ROB +1.5VS_ROB
Use Y topology to place these resisters between JMIN2 and JMIN1 1
C459
1
C460
1
C461
1
C462
1
C463
1
C464
@ @
4.7U_0805_10V4Z 0.1U_0402_16V4Z 4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 2 2 2

1 1 1 1 1 1
C465 C466 C467 C468 C469 C470 1 2 PCIE_PTX_C_IRX_N2_14
<22> PCIE_PTX_C_IRX_N2
@ @ R788 14W@ 0_0402_5%
1 0.01U_0402_16V7K 0.1U_0402_16V4Z 4.7U_0805_10V4Z 4.7U_0805_10V4Z 0.01U_0402_16V7K 0.1U_0402_16V4Z PCIE_PTX_C_IRX_P2_14 1
<22> PCIE_PTX_C_IRX_P2 1 2
2 ROBSON@ 2 ROBSON@ 2 2 2 ROBSON@ 2 ROBSON@ R789 14W@ 0_0402_5% JMIN1
1 2 PCIE_ITX_C_PRX_N2_14 ICH_PCIE_WAKE# 1 2 +3VS
<22> PCIE_ITX_C_PRX_N2 <22,28,31> ICH_PCIE_WAKE# 1 2
R790 14W@ 0_0402_5% WLAN_ACTIVE 3 4
<34> WLAN_ACTIVE 3 4
1 2 PCIE_ITX_C_PRX_P2_14 BT_ACTIVE 5 6 +1.5VS
<22> PCIE_ITX_C_PRX_P2 <34> BT_ACTIVE 5 6
R791 14W@ 0_0402_5% +3VS 1 2 3G_CLKREQ# 7 7 8 8
R456 10K_0402_5% 9 10
<16> 3G_CLKREQ# 9 10
<16> CLK_PCIE_3G# 11 11 12 12
<16> CLK_PCIE_3G 13 13 14 14
15 15 16 16
1 2 PCIE_PTX_C_IRX_N2_15 17 18
+3VS_ROB +1.5VS_ROB <22> PCIE_PTX_C_IRX_N2 17 18
R792 15W@ 0_0402_5% 19 20 MINI2_OFF#
PCIE_PTX_C_IRX_P2_15 19 20 PLT_RST_BUF#
<22> PCIE_PTX_C_IRX_P2 1 2 21 21 22 22
JMIN3 R793 15W@ 0_0402_5% PCIE_PTX_C_IRX_N2_14 23 24 +3VS
PCIE_ITX_C_PRX_N2_15 PCIE_PTX_C_IRX_P2_14 23 24
1 1 2 2 <22> PCIE_ITX_C_PRX_N2 1 2 25 25 26 26
3 4 R794 15W@ 0_0402_5% 27 28
ROBSON@ 3 4 PCIE_ITX_C_PRX_P2_15 27 28 ICH_SMBCLK
5 5 6 6 <22> PCIE_ITX_C_PRX_P2 1 2 29 29 30 30
+3VS_ROB 1 2 ROB_CLKREQ# 7 7 8 8 R795 15W@ 0_0402_5% PCIE_ITX_C_PRX_N2_14 31 31 32 32 ICH_SMBDATA
R457 10K_0402_5% 9 10 PCIE_ITX_C_PRX_P2_14 33 34
9 10 33 34 USB20_R_N8
<16> CLK_PCIE_NAND# 11 11 12 12 35 35 36 36
13 14 37 38 USB20_R_P8
<16> CLK_PCIE_NAND 13 14 37 38
15 15 16 16 39 39 40 40
17 17 18 18 +3VS 41 41 42 42
19 20 43 44 (WWAN_LED#)
19 20 43 44 WLAN_LED# <40>
21 22 PLT_RST_BUF# 45 46
21 22 PLT_RST_BUF# <8,17,20,26,28,40> 45 46
PCIE_PTX_C_IRX_N2_15 23 24 Vcc 3.3V +/- 8% 47 48
PCIE_PTX_C_IRX_P2_15 23 24 47 48
25 25 26 26 49 49 50 50
27 28 Peak Icc 2750mA 51 52
27 28 +3VS 51 52
29 29 30 30 with max supply droop 50mA
PCIE_ITX_C_PRX_N2_15 31 32 53 54
PCIE_ITX_C_PRX_P2_15 31 32 +3VS +3VS_ROB Average Icc 1000mA GND1 GND2
33 33 34 34

1
35 35 36 36
2 R458 FOX_AS0B226-S56N-7F 2
37 37 38 38
+3VS_ROB +3VS_ROB 39 40 ROBSON@ CONN@
39 40 R780 0_0805_5% 10K_0402_5%
41 41 42 42 @
43 44

2
43 44 WCM2012F2SF-121T04_0805
45 45 46 46
47 48 MINI2_OFF# USB20_R_N8 4 USB20_N8
47 48 4 3 3 USB20_N8 <22>
49 49 50 50

1
+1.5VS +1.5VS_ROB D
51 51 52 52
Q13 2 TV_ON# USB20_R_P8 1 2 USB20_P8
TV_ON# <32> 1 2 USB20_P8 <22>
53 54 SSM3K7002FU_SC70-3 G
GND1 GND2 ROBSON@ L51 <EMI> <EMI>
S

3
R781 0_0805_5% 1 2 R666 0_0402_5%
FOX_AS0B226-S56N-7F 1 2 R667 0_0402_5%
ROBCONN@ <EMI>

Mini-Express Card for WLAN

MINI_VCC +1.5VS +3VS
*** L29
JMIN2
<22,28,31> ICH_PCIE_WAKE#
ICH_PCIE_WAKE#
WLAN_ACTIVE
1 1 2 2 MINI_VCC 1 2 Kill SWITCH
<34> WLAN_ACTIVE 3 3 4 4
BT_ACTIVE 5 6 KC FBM-L11-201209-221LMAT_0805
<34> BT_ACTIVE 5 6
WLAN_CLKREQ# 7 8 +3VALW
<16> WLAN_CLKREQ# 7 8
9 9 10 10
CLK_PCIE_WLAN# 11 12
3 <16> CLK_PCIE_WLAN# 11 12 3
CLK_PCIE_WLAN 13 14
<16> CLK_PCIE_WLAN 13 14
15 15 16 16

2
17 17 18 18
19 20 MINI_RF_OFF# +3VS D21 +3VALW
19 20 PLT_RST_BUF# DAN217_SC59
21 21 22 22

2
23 24 MINI_VCC @
<22> PCIE_PTX_C_IRX_N3 23 24
25 26 R461
<22> PCIE_PTX_C_IRX_P3 25 26

1
27 28

1
27 28 ICH_SMBCLK R462 100K_0402_5%
29 29 30 30 ICH_SMBCLK <16,22,31>
31 32 ICH_SMBDATA
<22> PCIE_ITX_C_PRX_N3 ICH_SMBDATA <16,22,31>

1
31 32 10K_0402_5% KILL_SW#
<22> PCIE_ITX_C_PRX_P3 33 33 34 34 KILL_SW# <32>
35 36 USB20_R_N3

2
35 36 USB20_R_P3
37 37 38 38
MINI_VCC 39 40 MINI_RF_OFF#
39 40
41 41 42 42

1
WLAN_LED# D
43 43 44 44 WLAN_LED# <40>

3
45 46 Q14 2 RF_ON#
45 46 RF_ON# <32>
47 48 SSM3K7002FU_SC70-3 G

3
47 48
49 50 S

3
49 50
@ 51 51 52 52 01/22 change sw2 P/N DE100000300
WCM2012F2SF-121T04_0805 R463 SW2
USB20_R_P3 USB20_P3
53 GND1 GND2 54
1BS003-1211L_3P 11/23 Change SW2 to correct symbol (by Andy)
4 4 3 3 USB20_P3 <22> 1 2 +5VS
FOX_AS0B226-S56N-7F 100K_0402_5% +3VS
USB20_R_N3 1 2 USB20_N3 CONN@
1 2 USB20_N3 <22>
L59 <EMI> <EMI> Please place these caps between JMIN1 and JMIN2
1 2 R808 0_0402_5% 1
1 2 R809 0_0402_5% C471
<EMI> ICH_SMBCLK C757 1 2 @ 100P_0402_50V8J
0.1U_0402_16V4Z
4 MINI_VCC +1.5VS 2 ICH_SMBDATA C758 4
1 2 @ 100P_0402_50V8J

1 1 1 1 1 1
C472 C473 C474 C475 C476 C477
@ @
0.01U_0402_16V7K 0.1U_0402_16V4Z 4.7U_0805_10V4Z 0.01U_0402_16V7K 0.1U_0402_16V4Z 4.7U_0805_10V4Z
2 2 2 2 2 2 Security Classification
2007/08/18
Compal Secret Data
2008/8/18 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Mini-Card/Kill SWITCH
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JHXXX M/B LA-4241P Schematic
Date: Wednesday, May 28, 2008 Sheet 30 of 49
A B C D E
 A B C D E

New Card Socket (Left/TOP)

New Card Power Switch +3VS_CARD1

JAQ60
New Card
JEXP1

1 1 1 GND
C695 C696 <22> USB20_N10 2
@ USB_D-
<22> USB20_P10 3 USB_D+
+1.5VS 0.1U_0402_16V4Z 4.7U_0805_10V4Z CP_USB# 4
C694 U18 2 2 CPUSB#
5 RSV
2 1 0.1U_0402_16V4Z 12 1.5Vin 1.5Vout 11 +1.5VS_CARD1 6 RSV
14 1.5Vin 1.5Vout 13 <16,22,30> ICH_SMBCLK 7 SMB_CLK
+3VS 8
1 +1.5VS_CARD1 <16,22,30> ICH_SMBDATA SMB_DATA 1
C689 +1.5VS_CARD1 9 +1.5V
2 1 0.1U_0402_16V4Z 2 3.3Vin 3.3Vout 3 +3VS_CARD1 10 +1.5V
4 3.3Vin 3.3Vout 5 <22,28,30> ICH_PCIE_WAKE# 11 WAKE#
2 1 0.1U_0402_16V4Z 1 1 +3VALW_CARD1 12 +3.3VAUX
+3VALW C693 17 15 +3VALW_CARD1 C697 C698 PERST1# 13
AUX_IN AUX_OUT @ PERST#
+3VS_CARD1 14 +3.3V
PCI_RST# 6 19 0.1U_0402_16V4Z 4.7U_0805_10V4Z 15
<20,32,35> PCI_RST# SYSRST# OC# 2 2 +3.3V
EXP_CLKREQ# 16
<16> EXP_CLKREQ# CLKREQ#
SYSON 20 8 PERST1# CP_PE# 17
<32,41,46> SYSON SHDN# PERST# <22> CP_PE# CPPE#
<16> CLK_PCIE_EXP# 18 REFCLK-
SUSP# 1 16 19
<17,32,41,46,47> SUSP# STBY# NC <16> CLK_PCIE_EXP REFCLK+
20 GND
+3VALW 2 1 CP_PE# 10 7 21
CPPE# GND <22> PCIE_PTX_C_IRX_N1 PERn0
R635 100K_0402_5% 22
+3VALW_CARD1 <22> PCIE_PTX_C_IRX_P1 PERp0
2 1 CP_USB# 9 23
R636 100K_0402_5% CPUSB# GND
<22> PCIE_ITX_C_PRX_N1 24 PETn0
18 RCLKEN <22> PCIE_ITX_C_PRX_P1 25 PETp0
26 GND
R5538D001-TR-F_QFN20_4X4~D 1 1
C699 C700 27 29
internal pull high to 3.3Vaux-in @ 28
GND1
GND2
GND3
GND4 30
0.1U_0402_16V4Z 4.7U_0805_10V4Z
EC need setting at Hi-Z & output Low 2 2 SANTA_130810-1
CONN@

Change to GMT PartNumber

Update FootPrint from
SANTA_13181060-5_26P-T to
2
SANTA_130810-1_26P 2

Update FootPrint from

SANTA_130810-1_26P to
SANTA_130810-1_26P-S

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/18 Deciphered Date 2008/8/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
NEW CARD
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JHXXX M/B LA-4241P Schematic
Date: Wednesday, May 28, 2008 Sheet 31 of 49
A B C D E
 5 4 3 2 1

+3VALW +EC_DVCC +3VALW +3VALW

10/12 Add MB2 ID need check
L30

1
1 2 +EC_AVCC
+3VALW 1 2 FBM-11-160808-601-T_0603 +EC_AVCC
FBM-11-160808-601-T_0603 R469 R470
L31 @
C492
2 1
C493 1 1 1 1 1 1
RC 100K_0402_5%
Rb 47K_0402_5%

0.1U_0402_16V4Z
C494

0.1U_0402_16V4Z
C495

0.1U_0402_16V4Z
C496

0.1U_0402_16V4Z
C497

1000P_0402_50V7K
C498

1000P_0402_50V7K
C499
RB@

2
0.1U_0402_16V4Z 1000P_0402_50V7K MB2_ID MB_ID
1 ECAGND 2
1 2

1
L32 FBM-11-160808-601-T_0603 2 2 2 2 2 2
1 1
C500 R471 C501 R472
@ @ @ @
D
0.1U_0402_16V4Z
Rd 0_0402_5% 0.1U_0402_16V4Z
Ra 0_0402_5%
D

111
125
2 2

22
33
96

67

2
9
U21

VCC
VCC
VCC
VCC
VCC
VCC

AVCC
1 2
R474 0_0402_5%
+5VS
GATEA20 1 21 INVT_PWM
<21> GATEA20 GA20/GPIO00 INVT_PWM/PWM1/GPIO0F INVT_PWM <18>
KB_RST# 2 1 2 23 BEEP# TP_CLK R475 1 2 4.7K_0402_5%
<21> KB_RST# KBRST#/GPIO01 BEEP#/PWM2/GPIO10 BEEP# <36>
D23 @ <22,35,40> SERIRQ SERIRQ 3 26 VGA_THERM#
SERIRQ# FANPWM1/GPIO12 VGA_THERM# <17>
CH751H-40PT_SOD323-2 LPC_FRAME# 4 27 ACOFF TP_DATA R477 1 2 4.7K_0402_5%
<21,35,40> LPC_FRAME# LFRAME# ACOFF/FANPWM2/GPIO13 ACOFF <44>
<21,35,40> LPC_AD3 LPC_AD3 5
C502 LPC_AD2 LAD3 ECAGND +5VALW
<21,35,40> LPC_AD2 7 LAD2 PWM Output 1 2
2 1 2 @ 1 <21,35,40> LPC_AD1 LPC_AD1 8 63 BATT_TEMP C503 0.01U_0402_16V7K
LAD1 BATT_TEMP/AD0/GPIO38 BATT_TEMP <43>
R476 10_0402_5% LPC_AD0 BATT_OVP GPXOA02 R813 1TONTEK@ 2 10K_0402_5%
@ 22P_0402_50V8J
<21,35,40> LPC_AD0 10 LAD0 LPC & MISC BATT_OVP/AD1/GPIO39 64
ADP_I
BATT_OVP <44>
ADP_I/AD2/GPIO3A 65 ADP_I <44>
CLK_PCI_EC 12 AD Input 66
<16> CLK_PCI_EC PCICLK AD3/GPIO3B
PCI_RST# 13 75 MB2_ID +3VALW
<20,31,35> PCI_RST# PCIRST#/GPIO05 AD4/GPIO42
R478 1 2 EC_RST# 37 76 MB_ID
+3VALW ECRST# SELIO2#/AD5/GPIO43
47K_0402_5% EC_SCI# 20
<22> EC_SCI# SCI#/GPIO0E
1 1 @ 2 38 CIR_DET# R731 2 1 10K_0402_5%
<22,40> PM_CLKRUN# CLKRUN#/GPIO1D
C504 R479 0_0402_5% 68 DAC_BRIG
DAC_BRIG/DA0/GPIO3C DAC_BRIG <18>
70 EN_FAN1 P_USB# R485 2 1 10K_0402_5%
EN_DFAN1/DA1/GPIO3D EN_FAN1 <4>
0.1U_0402_16V4Z DA Output 71 IREF
2 IREF/DA2/GPIO3E IREF <44>
KSI0 55 72 CHGVADJ RCIRRX R489 1 2 10K_0402_5%
+3VS KSI0/GPIO30 DA3/GPIO3F CHGVADJ <44>
KSI1 56
KSI2 KSI1/GPIO31 <EMI> SM_KEY# R672 1
57 KSI2/GPIO32 2 10K_0402_5%
1 @ 2 PM_CLKRUN# KSI3 58 83 CLK_GUEST_R L53 1TONTEK@ 2 0_0402_5% CLK_GUEST
KSI3/GPIO33 PSCLK1/GPIO4A CLK_GUEST <33>
R714 8.2K_0402_5% KSI4 59 84 DATA_GUEST_R L54 1TONTEK@ 2 0_0402_5% DATA_GUEST
KSI4/GPIO34 PSDAT1/GPIO4B DATA_GUEST <33>
KSI5 60 85 <EMI> PCI_RST# R256 1 2 100K_0402_5%
KSI6 KSI5/GPIO35 PSCLK2/GPIO4C POWER_USB_LED#
C
61 KSI6/GPIO36 PS2 Interface PSDAT2/GPIO4D 86 POWER_USB_LED# <33> C
KSI7 62 87 TP_CLK KB926 SPI STRAP PIN CLK_GUEST
KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E TP_CLK <34>
KSO0 TP_DATA
+3VALW 2 1 39 KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F 88 TP_DATA <34> No stuff when use KB926C0
R483 10K_0402_5% KSO1 40 1 2 DATA_GUEST
KSO1/GPIO21 KILL_SW# <30>
EC_PME# KSO2 41 R637 1 2 0_0402_5% 1 1
KSO3 KSO2/GPIO22 R488 @ 10K_0402_5% C719 C720
<20> PCI_PME# 1 2 42 KSO3/GPIO23 SDICS#/GPXOA00 97
R487 0_0402_5% KSO4 43 98 EN_WOL# @ @
KSO4/GPIO24 SDICLK/GPXOA01 EN_WOL# <28>
KSO5 GPXOA02 R812 1TONTEK@ 2 0_0402_5% ACK_GUEST 22P_0402_50V8J 22P_0402_50V8J
KSO6
44 KSO5/GPIO25 Int. K/B SDIDO/GPXOA02 99
LID_SW# <EMI> 2 2 <EMI>
45 KSO6/GPIO26 Matrix SDIDI/GPXID0 109 LID_SW# <35>
KSO7 46 SPI Device Interface
KSO[0..15] KSO8 KSO7/GPIO27
<33> KSO[0..15] 47 KSO8/GPIO28
KSO9 48 119 FRD#SPI_SO
+5VALW KSI[0..7] KSO9/GPIO29 SPIDI/RD# FRD#SPI_SO <34>
KSO10 49 120 FWR#SPI_SI EC_RSMRST#
<33> KSI[0..7] KSO10/GPIO2A SPIDO/WR#
KSO11 50 SPI Flash ROM 126 SPI_CLK BEEP#
KSO12 KSO11/GPIO2B SPICLK/GPIO58 FSEL#SPICS# SYSON
51 KSO12/GPIO2C SPICS# 128
<EMI> KSO13 52 EC_SCI#
EC_SMB_CK1 L57 1CYPRESS@ KSO13/GPIO2D
1 2 2 0_0402_5% CLK_GUEST KSO14 53 KSO14/GPIO2E
EC_THERM#
R490 4.7K_0402_5% KSO15 54 73 RCIRRX SERIRQ
KSO15/GPIO2F CIR_RX/GPIO40 RCIRRX <35>

100P_0402_50V8J

100P_0402_50V8J

100P_0402_50V8J

100P_0402_50V8J

100P_0402_50V8J

100P_0402_50V8J
1 2 EC_SMB_DA1 L58 CYPRESS@
1 2 0_0402_5% DATA_GUEST 81 74 MCH_TSATN#_EC
KSO16/GPIO48 CIR_RLC_TX/GPIO41 MCH_TSATN#_EC <8>
R491 4.7K_0402_5% <EMI> 82 89 FSTCHG
KSO17/GPIO49 FSTCHG/SELIO#/GPIO50 FSTCHG <44>
1 2 CLK_GUEST_R 90 CHARGE_LED0#
BATT_CHGI_LED#/GPIO52 CHARGE_LED0# <40>
R711 10K_0402_5% 91 CAPS_LED# 1 1 1 1 1 1
CAPS_LED#/GPIO53 CAPS_LED# <33>
1 2 DATA_GUEST_R <34,43> EC_SMB_CK1 EC_SMB_CK1 77 GPIO 92 CHARGE_LED1#
SCL1/GPIO44 BATT_LOW_LED#/GPIO54 CHARGE_LED1# <40>
R712 10K_0402_5% <34,43> EC_SMB_DA1 EC_SMB_DA1 78 93 PWR_LED#
SDA1/GPIO45 SUSP_LED#/GPIO55 PWR_LED# <33,40>
1 2 ACK_GUEST_R <4,17> EC_SMB_CK2 EC_SMB_CK2 79 SM Bus 95 SYSON
SCL2/GPIO46 SYSON/GPIO56 SYSON <31,41,46> 2 2 2 2 2 2
R713 10K_0402_5% <4,17> EC_SMB_DA2 EC_SMB_DA2 80 121 VR_ON
SDA2/GPIO47 VR_ON/XCLK32K/GPIO57 VR_ON <48>
127 ACIN
AC_IN/GPIO59 ACIN <22,42,44>
C508 C506 C507
+3VS @ C505 @ C509 @ C510
PM_SLP_S3# 6 100 EC_RSMRST# @ @ @
<22>
PM_SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXO03 EC_RSMRST# <22>
1 2 EC_SMB_CK2 PM_SLP_S5# 14 101 EC_LID_OUT# ICH_PWROK
<22>
PM_SLP_S5# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXO04 EC_LID_OUT# <22>
R492 4.7K_0402_5% EC_SMI# 15 102 EC_ON PBTN_OUT#
<22>
EC_SMI# EC_SMI#/GPIO08 EC_ON/GPXO05 EC_ON <35>
B 1 2 EC_SMB_DA2 <EMI> SM_KEY# 16 103 TV_ON# EN_FAN1 B
<33>
SM_KEY# LID_SW#/GPIO0A EC_SWI#/GPXO06 TV_ON# <30>
R493 4.7K_0402_5% 1 1 CLK_GUEST L60 1 ENE@ 2 0_0402_5% ESB_CLK 17 104 ICH_PWROK EC_ON
SUSP#/GPIO0B ICH_PWROK/GPXO06 ICH_PWROK <8,22>
C511 C512 DATA_GUEST L61 1 ENE@ 2 0_0402_5% ESB_DAT 18 GPO 105 BKOFF# ON/OFF#
PBTN_OUT#/GPIO0C BKOFF#/GPXO08 BKOFF# <18>
@ @ <33> P_USB# <EMI> P_USB# 19 GPIO 106 RF_ON# TV_ON#
EC_PME#/GPIO0D WL_OFF#/GPXO09 RF_ON# <30>

100P_0402_50V8J

100P_0402_50V8J

100P_0402_50V8J

100P_0402_50V8J

100P_0402_50V8J

100P_0402_50V8J
100P_0402_50V8J 100P_0402_50V8J USB2_ON# 25 107 BT_ON#
2 2 <35> USB2_ON# EC_THERM#/GPIO11 GPXO10 BT_ON# <34>
FAN_SPEED1 28 108 VGA_AC_DET
<4> FAN_SPEED1 FAN_SPEED1/FANFB1/GPIO14 GPXO11 VGA_AC_DET <17>
ACK_GUEST_R 29
EC_TX_P80_DATA FANFB2/GPIO15
<14,15> EC_TX_P80_DATA 30 EC_TX/GPIO16 1 1 1 1 1 1
EC_RX_P80_CLK 31 110 PM_SLP_S4#
<14,15> EC_RX_P80_CLK EC_RX/GPIO17 PM_SLP_S4#/GPXID1 PM_SLP_S4# <22>
1 2 SUSP# ON/OFF# 32 112 ENBKL
<35> ON/OFF# ON_OFF/GPIO18 ENBKL/GPXID2 ENBKL <18>
C513 @ 100P_0402_50V8J SM_KEY_LED# 34 114 CIR_DET#
<33> SM_KEY_LED# PWR_LED#/GPIO19 GPXID3 CIR_DET# <35> 2 2 2 2 2 2
NUM_LED# 36 GPI 115 EC_THERM#
<33> NUM_LED# NUMLED#/GPIO1A GPXID4 EC_THERM# <22>
116 SUSP#
GPXID5 SUSP# <17,31,41,46,47>
117 PBTN_OUT# C733 C731 C515
GPXID6 PBTN_OUT# <22>
118 EC_PME# C732 C514 @ C516
ACK_GUEST 1CYPRESS@ GPXID7
<33> ACK_GUEST 2 ACK_GUEST_R XCLKI 122 XCLK1
@ @
R814 0_0402_5% XCLKO 123 124 BATT_TEMP C517 1 2 100P_0402_50V8J
XCLK0 V18R
2
AGND

BATT_OVP C519 1 2 100P_0402_50V8J

GND
GND
GND
GND
GND

SPI_CS# 1 2 FSEL#SPICS# C518

<34> SPI_CS#
R494 0_0402_5% R497 4.7U_0805_10V4Z ACIN C520 1 2 100P_0402_50V8J
SPI_CLK_R SPI_CLK XCLKO 1 1
<34> SPI_CLK_R 1 2 @ 2 XCLKI KB926QFA1 LQFP 128P
11
24
35
94
113

69

R495 0_0402_5% 20M_0603_5% VR_ON C521 1 2 @ 100P_0402_50V8J

SPI_SI 1 2 FWR#SPI_SI
<34> SPI_SI
ECAGND

R496 0_0402_5% ENBKL C522 1 2 @ 100P_0402_50V8J

1 1 FSTCHG C734 1 2 100P_0402_50V8J

EC DEBUG PORT Use KB926C0
4

C523 C524 ACK_GUEST C735 1 2 100P_0402_50V8J

15P_0402_50V8J 15P_0402_50V8J
OSC

OSC

JP61 2 2 ADP_I C736 1 2 @ 100P_0402_50V8J

A +3VALW 1 X2 A
EC_TX_P80_DATA 1 EC_SMB_DA1 C743
2 2 1 2 @ 100P_0402_50V8J
EC_RX_P80_CLK
NC

NC

3 3
4 EC_SMB_CK1 C744 1 2 @ 100P_0402_50V8J
4
3

ACES_85205-0400
DBCONN@
32.768KHZ_12.5PF_Q13MC14610002 Compal Secret Data
Security Classification
2007/08/18 2008/8/18 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ENE-KB926
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. JHXXX M/B LA-4241P Schematic
Date: Tuesday, June 03, 2008 Sheet 32 of 49
5 4 3 2 1
 5 4 3 2 1

INT_KBD Conn.
KSI[0..7]
For JHL90 For JHT00 KSO[0..15]
KSI[0..7] <32>

KSO[0..15] <32>
JP43 JP44
KSI1 1 KSI1 1
KSI7 2
1 KSI7 2
1 Delete C525~C548 SE071101J80 (100pF)
KSI6 2 KSI6 2
D
KSO9
3
4
3 KSO9
3
4
3 Add SI102101K80 (CP : 100pF) D
4 4
KSI4
KSI5
5
6
5
KSI4
KSI5
5
6
5 (EMI Recommend)
KSO0 6 KSO0 6
7 7 7 7
KSI2 8 KSI2 8
KSI3 8 KSI3 8
9 9 9 9
KSO5 10 KSO5 10 CP1 <EMI> CP4 <EMI>
KSO1 10 KSO1 10 KSI4 KSO6
11 11 11 11 1 8 1 8
KSI0 12 KSI0 12 KSI5 2 7 KSO3 2 7
KSO2 12 KSO2 12 KSO0 KSO12
13 13 13 13 3 6 3 6
KSO4 14 KSO4 14 KSI2 4 5 KSO13 4 5
KSO7 14 KSO7 14
15 15 15 15
KSO8 16 KSO8 16 100P_1206_8P4C_50V8 100P_1206_8P4C_50V8
KSO6 16 KSO6 16
17 17 17 17
KSO3 18 KSO3 18 CP2 <EMI> CP5 <EMI>
KSO12 18 KSO12 18 KSI1 KSI3
19 19 19 19 1 8 1 8
KSO13 20 KSO13 20 KSI7 2 7 KSO5 2 7
KSO14 20 KSO14 20 KSI6 KSO1
21 21 21 21 3 6 3 6
KSO11 22 KSO11 22 KSO9 4 5 KSI0 4 5
KSO10 22 KSO10 22
23 23 23 23
KSO15 24 KSO15 24 100P_1206_8P4C_50V8 100P_1206_8P4C_50V8
24 24
25 25 25 25
27 27 CP3 <EMI> CP6 <EMI>
GND GND KSO2 KSO14
GND 26 GND 26 1 8 1 8
KSO4 2 7 KSO11 2 7
ACES_88502-2501 ACES_88502-2501 KSO7 3 6 KSO10 3 6
CONN@ CONN@ KSO8 4 5 KSO15 4 5
C 100P_1206_8P4C_50V8 100P_1206_8P4C_50V8 C

Function Board Conn.

Power USB Board Conn.

+3VS R817 2 @ 1 0_0603_5%

+3VALW R816 2 @ 1 0_0603_5%

+5VS R805 2 @ 1 0_0603_5% +5V_SW

+5VALW R806 2 1 0_0603_5%

JP48
1 +5VALW
1
2 2
CLK_GUEST 3 JP62
<32> CLK_GUEST 3
DATA_GUEST 4 1
<32> DATA_GUEST 4 1
ACK_GUEST 5 ON/OFFBTN# 2
<32> ACK_GUEST 5 <35> ON/OFFBTN# 2
SM_KEY# 6 D_P_USB# 3
<32> SM_KEY# 6 3
SM_KEY_LED# 7 PWR_LED# 4
<32> SM_KEY_LED# 7 <32,40> PWR_LED# 4
8 POWER_USB_LED# 5
B 8 <32> POWER_USB_LED# 5 B
CAPS_LED# 9 6
<32> CAPS_LED# 9 6
NUM_LED# 10 7
<32> NUM_LED# 10 GND
11 GND 8 GND
12 GND ACES_85201-06051
ACES_85201-1005N
CONN@

+3VALW
ACK_GUEST C759 1 2 @ 100P_0402_50V8J 1

R659

10K_0402_5%
2

D67
2 P_USB#
P_USB# <32>
D_P_USB# 1
3 51_ON#
51_ON# <35,42>
DAN202UT106_SC70-3

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/18 Deciphered Date 2008/8/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
KB/SW/PW Conn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JHXXX M/B LA-4241P Schematic
Date: Wednesday, May 28, 2008 Sheet 33 of 49
5 4 3 2 1
 +3VALW +5VALW

2 @ 1 EEPROM_VCC
R521 0_0603_5% 8M SPI ROM
2
R522
@ 1
0_0603_5%
16M SPI ROM For iTPM+HDCP
+3VALW
For EC+BIOS+VBIOS
1 20mils
EEPROM_VCC SA00001IT00 C549 U22 @
+3VALW @ 8 4
EEPROM_VCC EEPROM_VCC 16Mbit 12/10 Andy 0.1U_0402_16V4Z VCC VSS
2
3 W
1 @ 2 EC_SMB_CK1 @ 1 20mils

1
R523 4.7K_0402_5% C550 1 2 0.1U_0402_16V4Z C551 U23 7 HOLD
1 @ 2 EC_SMB_DA1 R525 8 VCC VSS 4
R524 4.7K_0402_5% @ 0.1U_0402_16V4Z ICH_SPI_CS0#_R 1
2 <22> ICH_SPI_CS0#_R S
100K_0402_5% 3
U24 @ W ICH_SPI_CLK_R
<22> ICH_SPI_CLK_R 6

2
C
12/28 Add 8 VCC A0 1 7 HOLD ICH_SPI_MOSI_R ICH_SPI_MISO_R @
7 WP A1 2 <22> ICH_SPI_MOSI_R 5 D Q 2 ICH_SPI_MISO <22>
6 3 SPI_CS# 1 R526 15_0402_5%
<32,43> EC_SMB_CK1 SCL A2 <32> SPI_CS# S
<32,43> EC_SMB_DA1 5 4 SST25LF080A_SO8-200mil
SDA GND SPI_CLK_R
<32> SPI_CLK_R 6 C
AT24C16AN-10SU-2-7_SO8
SPI_SI 5 SPI_SO 2
<32> SPI_SI D Q 2 R527
1
0_0402_5%
FRD#SPI_SO <32>

1
SST25LF080A_SO8-200mil
0206 => change PN to SA00001N800 R528 follow CRB Check
@
12/19 change pn to SA00001MP00 ( original part EOL ) 100K_0402_5% SD028150A80

2
12/25 change back to SA024160140 ( Samples can not on time ) 12/15 change from 15 to 0 ohm'

Bluetooth Conn. To TP/B Conn.

Need to check BT pin definition again!
9/20 modified this block JP12
1 1
+5VS SWR# 2
SWL# 2
3 3
<32> TP_DATA TP_DATA 4
TP_CLK 4
<32> TP_CLK 5 5
1

L39 <EMI> 6
R529 +5VS 6
1 1 2 2 7 GND
8 GND
10K_0402_5% +BT_VCC
4 3 ACES_85201-06051
2

4 3 JP42 SWR#
BT_LED# WCM2012F2SF-121T04_0805 1
<40> BT_LED# 1
BT_ACTIVE @ 2 SWL#
<30> BT_ACTIVE 2
<22> USB20_P6 USB20_P6 1 <EMI> 2 USB20_R_P6 3 3
1

3
D R638 1
<22> USB20_N6 USB20_N6 2 0_0402_5% USB20_R_N6 4 4
+5VS
Q18 2 BTON_LED R639 <EMI> 0_0402_5% 5
G WLAN_ACTIVE 5 D25
SSM3K7002FU_SC70-3 <30> WLAN_ACTIVE 6 6
S 7 @ C552
3

7
1

8 PSOT24C_SOT23
8 0.1U_0402_16V4Z
9

1
R530 GND1
10 GND2
10K_0402_5%
MOLEX_53780-0870
2

CONN@ Update Footprint

14W Use 15W Use

SW4 SW5

6
5

6
5
SWL# 2 4 SWL# 2 4
+3VALW
Left Switch 1 3 Left Switch 1 3

SMT1-05_4P SMT1-05_4P
1 14W@ 15W@
C553 C554

0.1U_0402_16V4Z 1U_0603_10V4Z
3

2
S
G
<32> BT_ON# 1 2 2
R531 100K_0402_5% Q19 SW6 SW7

6
5

6
5
SI2301BDS_SOT23
D SWR# 2 4 SWR# 2 4
W=40mils
1

+BT_VCC Right Switch 1 3 Right Switch 1 3

1 SMT1-05_4P SMT1-05_4P
C557 C558 14W@ 15W@
@
4.7U_0805_10V4Z 0.1U_0402_16V4Z
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/18 Deciphered Date 2008/8/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BIOS, TP & BT Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JHXXX M/B LA-4241P Schematic
Date: Wednesday, May 28, 2008 Sheet 34 of 49
 A B C D E

ON/OFF switch
TOP Side
12/4 Change D14 to correct symbols FOR LPC DEBUG PORT FOR LPC SIO DEBUG PORT
2 1
J3 @ JOPEN
2 1 +3VS JP54
J4 @ JOPEN +3VALW 1
1 +5VS
Bottom Side 2 2
3 3 +3VS
4 4

2
5 5
R533 JP57 6
6 CLK_14M_SIO <16>
1 7 LPC_AD0
100K_0402_5% 1 CLK_PCI_DB 7 LPC_AD1
2 2 CLK_PCI_DB <16> 8 8
1 LPC_AD2 1
3 9

1
D26 3 LPC_AD0 9 LPC_AD3
4 4 LPC_AD0 <21,32,40> 10 10
2 ON/OFF# 5 LPC_AD1 11 LPC_FRAME#
ON/OFF# <32> 5 LPC_AD1 <21,32,40> 11
ON/OFFBTN# 1 6 LPC_AD2 12 LPC_DRQ0#
<33> ON/OFFBTN# 6 LPC_AD2 <21,32,40> 12 LPC_DRQ0# <21>
3 51_ON# 51_ON# <33,42> 7 LPC_AD3 13 PCI_RST#
7 LPC_AD3 <21,32,40> 13
8 LPC_FRAME# 14 2 A@ 1
8 LPC_FRAME# <21,32,40> 14
DAN202UT106_SC70-3 9 15 CLK_PCI_DB R534 10K_0402_5%
9 PCI_RST# 15 SERIRQ
10 16
Power Button 10
GND 11
PCI_RST# <20,31,32> 16
17 17
SERIRQ <22,32,40>

GND 12 1 18 18
C562 19
19

1
2 ACES_85201-1005N @ 20
C561 D27 DBCONN@ 0.1U_0402_16V4Z 20
2 ACES_85201-2005
1000P_0402_50V7K RLZ20A_LL34 DBCONN@
1

2
SMT1-05_4P
SW3
A@
1 3ON/OFFBTN#

2 4

1
D
EC_ON 2
<32> EC_ON
6
5

G
2
S

3
R535 Q21
SSM3K7002FU_SC70-3
10K_0402_5%
10/09 add for debug
1

2 2

CIR
+3VALW USB IO Conn.
JP51
1 5 +USB_VCCC
RCIRRX 15
<32> RCIRRX 2 26 6
CIR_DET# 3
<32> CIR_DET# 3
4 JP52
4
ACES_85201-0405 1
15WCONN@ 2
USB20_N0 3
<22> USB20_N0 4
<22> USB20_P0 USB20_P0
5
6
7
USB20_N5 8
<22> USB20_N5 9
<22> USB20_P5 USB20_P5
10
11
12
Change JP51 from 18 pin to 4 pin 150u 13
14
11/09 Andy ESR 0.9 ohm <22> USB20_N11 USB20_N11
USB20_P11 15
<22> USB20_P11 16
Package(L*W*H)7.3*4.3*2.9
3 17 3
Rating 6.3V 18
19
20
ACES_85201-20051
+USB_VCCC
W=80mils
+USB_VCCC
Lid Switch 1
1
1
C768
+ C564 C563
@ 10U_0805_10V4Z
150U_D_6.3VM 470P_0402_50V7K 2
2 2
11/29 change this symbol's footprint as
ADT7421ARMZ-REEL_MSOP8
+5VALW +USB_VCCC +3VALW
copy LM75CIMMX-3_MSOP8
footprint

2
+3VALW 1 2 +VCC_LID R537 1 2 100K_0402_5%
R536 0_0402_5% R468
U26
2

1 8 10K_0402_5%
GND OUT R691 0_0402_5%
2 7
VDD

1
IN OUT
3 IN NC 6 2 1 USB_OC#04 <22>
1 1 4 EN# OC 5 USB_OC#511 <22>
C565 3 C566
OUTPUT LID_SW# <32>
G545A2P8U MSOP 8P
0.1U_0402_16V4Z 2 4.7U_0805_10V4Z 1
GND

2 C567 2 C568
4 4
U25 10P_0402_50V8J 0.1U_0402_16V4Z
1

A3212ELHLT-T_SOT23W-3 1 2 @
<32> USB2_ON#

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/18 Deciphered Date 2008/8/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power OK/Lid/Front,IO,DB Conn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JHXXX M/B LA-4241P Schematic 0.4
Date: Wednesday, May 28, 2008 Sheet 35 of 49
A B C D E
 5 4 3 2 1

+3VS_DVDD

HD Audio Codec 10mil 1 1

L33 1 2
FBMA-L11-160808-800LMT_0603
+3VS
+VDDA

C570 C571

1
@
4.7U_0805_10V4Z R538
2 2 @
0.1U_0402_16V4Z 10K_0402_5%
+AVDD_AC97
10/03 add +1.5VS

2
L34 +1.5VS_DVDD
0.1U_0402_16V4Z 40mil R539 PM@ 0_0603_5% C572 1 2 0.1U_0402_16V4Z
+VDDA +3VS

1
D 0_0603_5% 1 1 1 1 L35 1 2 +1.5VS D
C573 C574 C575 C577 FBMA-L11-160808-800LMT_0603 R540
@ 10mil 1
C580
1
C581 GM@
10U_0805_10V4Z 100P_0402_50V8J @ 0_0402_5%
2 2 2 2 4.7U_0805_10V4Z EC Beep

2
2 2
0.1U_0402_16V4Z 0.1U_0402_16V4Z 1 R541 2 1 R804 2 MONO_IN_1 1 2 MONO_IN
<32> BEEP#
10K_0402_5% 0_0402_5% C582 0.1U_0402_16V4Z

25

38

9
U27

1
C R542 1 @ 2

AVDD1

AVDD2

DVDD_IO
DVDD
<22> SB_SPKR 1 R543 2 2 Q22 2.4K_0402_5%
10K_0402_5% B @
E 2SC2411K_SOT23
PCI Beep

3
14 35 AMP_LEFT
NC LINE_OUT_L AMP_LEFT <37>
Need Update Footprint

1
15 36 AMP_RIGHT
NC LINE_OUT_R AMP_RIGHT <37>
R544 D28
1 2 MIC2_R_L C589 2.2U_0603_6.3V6K MIC2_C_L 16 39 AMP_LEFT_HP @
<38> MIC2_L MIC2_L HP_OUT_L AMP_LEFT_HP <37>
R715 1K_0402_5% 10K_0402_5% CH751H-40PT_SOD323-2
1 2 MIC2_R_R C585 2.2U_0603_6.3V6K MIC2_C_R 17 41 AMP_RIGHT_HP 9/19 Realtek suggest
<38> MIC2_R AMP_RIGHT_HP <37>

2
R716 1K_0402_5% MIC2_R HP_OUT_R
Add bypass schematic.
23 LINE1_L NC 45

24 LINE1_R DMIC_CLK 46

18 CD_L NC 43
2/01 Let them floating
20 CD_R NC 44
C 19 C
CD_GND HDA_BITCLK_AUDIO
1 2 MIC1_R_L C591 2.2U_0603_6.3V6K MIC1_C_L 21
BIT_CLK 6 HDA_BITCLK_AUDIO <21> Sense Pin Impedance Codec Signals Funnction
<37> MIC1_L MIC1_L
R717 1K_0402_5%
MIC1_R_R C592 2.2U_0603_6.3V6K MIC1_C_R SDIN0 39.2K PORT-A (PIN 39, 41)
<37> MIC1_R 1
R718
2
1K_0402_5%
22 MIC1_R SDATA_IN 8 1
R545
2
33_0402_5%
HDA_SDIN0 <21> HP
C594 1 2 100P_0402_50V8J MONO_IN 12 37
@ PCBEEP MONO_OUT
20K PORT-B (PIN 21, 22) MIC
LINE1_VREFO 29 SENSE A / B
<21> HDA_RST_AUDIO# 11 RESET#
GPIO1 31 10K PORT-C (PIN 23, 24) LINE IN
<21> HDA_SYNC_AUDIO 10 SYNC
MIC1_VREFO_L 28 10mil +MIC1_VREFO_L
<21> HDA_SDOUT_AUDIO 5 SDATA_OUT 5.1K PORT-D (PIN 35, 36) LINE OUT
2
MIC1_VREFO_R 32 10mil +MIC1_VREFO_R
GPIO0
SENSE_A
3 GPIO3 MIC2_VREFO 30 10mil +MIC2_VREFO 39.2K PORT-E (PIN 14, 15) HP
SENSE_B
13
34
SENSE A
27 ACZ_VREF 10mil
SENSE B VREF
ACZ_JDREF
20K PORT-F (PIN 16, 17) MIC
<37> EAPD 47 EAPD JDREF 40 SENSE B

1
SPDIFO 10K PORT-G (PIN 43, 44)
<17> SPDIFO 2 1 48 SPDIFO NC 33 1 1 LINE IN
2

R546 PM@ 0_0402_5% R548 C596 C597

R547 4 26
DVSS1 AVSS1 20K_0402_1% 10U_0805_10V4Z 100P_0402_50V8J
10_0402_5%
7 DVSS2 AVSS2 42
2 2 5.1K PORT-H (PIN 45, 46) LINE OUT

2
@ ALC268-GR_LQFP48
1

B
1 B
C598 DGND AGND
15P_0402_50V8J
2 @

SENSE FOR Ext. Mic. HDA_BITCLK_AUDIO

J9 @
Regulator for CODEC
2

1 2
R549
1 2 SENSE_A PAD-OPEN 3x3m
<37> MIC_SENSE
R550 20K_0402_1% 10_0402_5%
@
40mil
1

L36 U28 +VDDA

1 +5VS
60mil +5VS_VDDA 1 IN (Max output = 300 mA)
C599 5
0_0603_5% OUT
2
SENSE FOR Solo Int. Mic. 10P_0402_50V8J
2 @
C600
1 1
C601 GND
1 4.75V
3 4 C602
SHDN BYP
10U_0805_10V4Z 2 2 0.1U_0402_16V4Z G9191-475T1U_SOT23-5 1 4.7U_0805_10V4Z
@ C603 2 @

1 2 SENSE_B 0.01U_0402_16V7K
R551 20K_0402_1% 2
A A

Moat Bridge 10/2 change circuit

SENSE FOR HP U8 change footprint

SENSE_A
Security Classification Compal Secret Data
Title
Compal Electronics, Inc.
<37> HP_SENSE 2 1 1 2 Issued Date 2007/08/18 Deciphered Date 2008/8/18
R554 39.2K_0402_1% R555 0_0805_5% <Title>
1 2
HD Audio Codec ALC268
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
R556 0_0805_5% AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JHXXX M/B LA-4241P Schematic
Date: Wednesday, May 28, 2008 Sheet 36 of 49
5 4 3 2 1
 A B C D E

+MIC1_VREFO_R

APA2057 SPK/HP Amplifier 10/2 U6 APA2057A P/N:SA00001QD00

+MIC1_VREFO_L

10mil 10mil MICROPHONE

1
+5VALW R557 R558
IN JACK
W=40mil 2.2K_0402_5% 2.2K_0402_5%
JP63

2
680P_0402_50V7K

10U_0805_10V4Z
0.1U_0402_16V4Z
1 1 2 MIC_SENSE 5
<36> MIC_SENSE
C604 C605 C606 C607
4 10
+3VALW 1U_0603_10V4Z 9
2 2 1 MIC1_R L47 1
<36> MIC1_R 2 <EMI> MIC1_R_1 3 8
1 KC FBM-L11-160808-121LMT 0603 1
6 7
MIC1_L L48 1 2 <EMI> MIC1_L_1 2
<36> MIC1_L
R560 @ 1.5K_0402_1% KC FBM-L11-160808-121LMT 0603

11

19

20
10
1 1 1

1
fo=1/(2*3.14*R*C)=106Hz 1 2 U29 C610 C611

3
R=1.5K / C= 1uF R562 @ 1.5K_0402_1% <EMI> <EMI> FOX_JA6333L-B3S0-7F~N

CVDD

HVDD

PVDD
PVDD

VDD
1 2 220P_0402_50V7K 220P_0402_50V7K CONN@
2 2
1 2 AMPR
<36> AMP_RIGHT
C609 1U_0603_10V4Z SPKR+
AMPL
3 INR_A ROUT+ 22
SPKR- @ RED
<36> AMP_LEFT 1 2 5 21
Trace width/spacing/other=8/6/50

1
C608 1U_0603_10V4Z INL_A ROUT- D29
R563 1 2 100K_0402_5% AMP_EN# 27 8 SPKL+ PSOT05C-LF-T7 SOT-23-3
/AMP EN LOUT+ SPKL- <EMI>
LOUT- 9
+5VS R564 1 @ 2 100K_0402_5% HP_EN 24 HP EN HP_R
HP_R 17
1 2 AMP_RHPIN 1 2 INR_H 4 18 HP_L
<36> AMP_RIGHT_HP INR_H HP_L
C612 4.7U_0805_10V4Z R565 39K_0402_5% 6
AMP_LHPIN INL_H INL_H
1 2 1 2
<36> AMP_LEFT_HP
C613 4.7U_0805_10V4Z R566 39K_0402_5% 26 /SD
10mil
AMP_SD# 15 CVSS
AMP_BEEP CVSS
1 2 1 2 1 2 28
R569 0_0402_5% C614 0.47U_0603_16V4Z R567 0_0402_5% BEEP
16
HEADPHONE
AMP_CP+ VSS
1 2 AMP_CP-
12
14
CP+
2
OUT JACK
CP- GND

1
C617 1U_0603_10V6K 23 C619
AMP_BIAS PGND 1U_0603_10V6K JP64
25 BIAS PGND 7
C618 2.2U_0603_6.3V6K 13 HP_SENSE 5
<36> HP_SENSE

2
CGND
2 1 GND 29
C620 0.1U_0402_16V4Z 4 10
APA2057A_TSSOP28 9
HP_R L49 1 2 <EMI> HPR 3 8
9/5 If implement AMP BEEP, Swap C641 and R524. KC FBM-L11-160808-121LMT 0603 6 7
2 IN_A Gain = 10dB (Internal Speaker) HP_L L50 1 2 <EMI> HPL 2 2
R524 change from 0 Ohm to 47K KC FBM-L11-160808-121LMT 0603 1
IN_H Gain = 0dB (Headphone)

1
1 1

3
R570 R568 C615 C616 FOX_JA6333L-B3S0-7F~N
@ @ <EMI> <EMI> CONN@
0_0402_5% 0_0402_5%
11/28 Modified to X5R 10P_0402_50V8J2 2 10P_0402_50V8J

2
11/28 Change to SE080105K80 @

1
D30
PSOT05C-LF-T7 SOT-23-3 GREEN
Trace width/spacing=15/9 <EMI>

Add below circuit for APA2057 gain tunning use

+5VALW

1
R571

10K_0402_1%
+3VALW 2

AMP_SD# R572 1 2 10K_0402_5% HP_EN

2

3 R573 3
1
1

1 C622
10K_0402_5% C621 R574
1

D 0.1U_0402_16V4Z
1

22K_0402_1% 2
2
G 0.01U_0402_16V7K 2
2

S
3
1

D
EAPD 2 1 2 Q23
<36> EAPD
R577 0_0402_5% G
Q24 S SSM3K7002FU_SC70-3 1/8 change JSPK1 following JAW91
3

SSM3K7002FU_SC70-3

JSPK1
Gain= 10dB SPKL- R580 1 2 <EMI> 0_0603_5% SPK_L1- 4 4 G2 6
SPKL+ R578 1 2 <EMI> 0_0603_5% SPK_L1+ 3 5
SPKR- R581 <EMI> 0_0603_5% SPK_R1- 3 G1
1 2 2 2
SPKR+ R579 1 2 <EMI> 0_0603_5% SPK_R1+ 1 1

20mil ACES_88266-04001
Gain (dB) Low (V) High (V) Recommended (V) Speaker Conn. CONN@

3
10 3.45 3.51 3.48 D31 D32
@ @
11 3.56 3.62 3.59 PSOT24C_SOT23 PSOT24C_SOT23
<EMI> <EMI>

1
4 4

12 3.68 3.73 3.70

13 3.80 3.85 3.82

+5VALW assume equal 5.1V
10 dB ---> 5.1 x 220 / 320 = 3.5 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/08/18 Deciphered Date 2008/8/18 Title
AMP/VR/Audio Jack
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JHXXX M/B LA-4241P Schematic
Date: Wednesday, May 28, 2008 Sheet 37 of 49
A B C D E
 SINGLE INT MIC/DUAL INT MIC
+3VS

1
R723
10K_0402_5%
@

2
+MIC2_VREFO +MIC2_VREFO 1 2 +MIC2_VREF_R
R725 0_0402_5%

1
1
C723 R724
27K_0402_5%
0.1U_0402_16V4Z @
@ 2

2
2/01 Add D52 for INT MIC use( PN:SCD0T05CA20 )
D52 is a modified symbol
2 R582 1
@ 0_0402_5%

D70 DUAL@
+MIC2_VREF_R 2 1 1 R583 2 DUAL@
2.2K_0402_5%
RLS4148_LL34-2
JMIC1
1 MIC2_L_OUT 1 2 <EMI> MIC2_L
1 MIC2_L <36>
2 2 1 R707 0_0402_5%
2 C623 220P_0402_50V7K
3 <EMI> DUAL@
GND
GND 4
D34

1
ACES_88231-02001 @
DUALCONN@ R585 3
1
0_0402_5% 2
SINGLE@

2
PSOT05C-LF-T7 SOT-23-3

2 R586 1
SINGLE@
0_0402_5%

D71 DUAL@
+MIC2_VREF_R 2 1 1 R587 2
2.2K_0402_5%
RLS4148_LL34-2
JMIC2
1 MIC2_R_OUT 1 2 <EMI> MIC2_R
1 MIC2_R <36>
2 2 1 R708 0_0402_5%
2 C625 220P_0402_50V7K
3 <EMI>
GND
4
GND 12/21 Place these parts close to CODEC (U7)
ACES_88231-02001

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/18 Deciphered Date 2008/8/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MIC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. JHXXX M/B LA-4241P Schematic
Date: Wednesday, May 28, 2008 Sheet 38 of 49
 A B C D E

1 1

11/27 Add screw for layout request

H1 H2 H3 H4 H5 H6 H7 H8 H10 H11 H12 H13 H14

HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA

H_3P0
1

1
H22 H23 H26
HOLEA HOLEA HOLEA
H_3P7
1

2 2

H28 H29 H30 H31

HOLEA HOLEA HOLEA HOLEA
H_4P2
1

2/22 change these from H_3P7 to H_3P8

H9 H21 H24 H25 H27 H32
HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
1

2/22 change these from H_3P2 to H_3P3 FD1 FD2 FD3 FD4 FD5 FD6

H15 H16 H17 H18 H19 H20

3 HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA @ @ @ @ @ @ 3

1
1

M1 M2
HOLEA HOLEA
1

H_5P0X3P2N H_5P0X3P2N

M3 M4 M5
HOLEA HOLEA HOLEA

11/27 Add screw for layout request

1

4 H_5P2X3P2N H_3P1N H_5P0X3P2N 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/18 Deciphered Date 2008/8/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Screw
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS JHXXX M/B LA-4241P Schematic 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 11, 2008 Sheet 39 of 49
A B C D E
 Camera Conn +5VS R590 2 1 0_0603_5%

MDC Conn. +5VALW R591 2 @ 1 0_0603_5%

20mil
1 1
PM@ C627 C628
JMDC1 1 R710 2 0_0402_5% +3VS
GM@ 4.7U_0805_10V4Z 0.1U_0402_16V4Z
+VCC_MDC 2 2
1 GND1 RES0 2 1 R695 2 0_0402_5% +1.5VS
HDA_SDOUT_MDC 3 4 JP3
<21> HDA_SDOUT_MDC IAC_SDATA_OUT RES1
5 6 +3V_MDC 1 R697 2 0_0402_5% +3VS +5V_CAMERA 1
HDA_SYNC_MDC GND2 3.3V USB20_N2 R594 1 USB20_R_N2 1
<21> HDA_SYNC_MDC 7 IAC_SYNC GND3 8 <22> USB20_N2 2 0_0402_5% 2 2
SDIN1_MDC 9 10 <22> USB20_P2 USB20_P2 R595 1 2 0_0402_5% USB20_R_P2 3
HDA_RST_MDC# IAC_SDATA_IN GND4 HDA_BITCLK_MDC 3
<21> HDA_RST_MDC# 11 IAC_RESET# IAC_BITCLK 12 HDA_BITCLK_MDC <21> 4 4
1 5 5
C629 6
@ GND1
7

GND
GND
GND
GND
GND
GND
22P_0402_50V8J WCM2012F2SF-121T04_0805 GND2
2 @ ACES_88266-05001
4 4 3 3
CAMCONN@

13
14
15
16
17
18
1 1 2 2
Connector for MDC Rev1.5
L42
ACES_88018-124G
CONN@
R593
HDA_SDIN1 1 2 SDIN1_MDC 05/26 Change D36 from SC300000X00 to SC300000K00
<21> HDA_SDIN1
33_0402_5% +VCC_MDC +3V_MDC
Finger Print board 1/05 Modified D3 to SCA00000A00 For EMI 2/1 change JP4 pin 6 to +5VS for LTT FP use
Please add these caps close to JMDC1 as close as possible, 0208 Remove D3 , Add D55 (SC300000G00)
HDA_SDOUT_MDC C752 1 2 @ 100P_0402_50V8J
C746
1 1
C745 EMI Request
HDA_SYNC_MDC C753 1 2 @ 100P_0402_50V8J
0.1U_0402_16V4Z 0.1U_0402_16V4Z D36 FP@ @
HDA_RST_MDC# C754 2 2 @ WCM2012F2SF-121T04_0805 +5VS
1 2 @ 100P_0402_50V8J @ 3 I/O I/O 2
4 4 3 3
HDA_SDIN1 C756 1 2 @ 100P_0402_50V8J
4 VCC GND 1
1 1 2 2
PJLCR05 SOT143
L40 JP4
1 1
<22> USB20_P1 USB20_P1 R640 10_0402_5%2USB20_R_P1 2
USB20_N1 2
<22> USB20_N1 1 2USB20_R_N1 3 3
R641 0_0402_5% 4
TPM X76 Information 5
4
5
+3VS 6 6
7 GND
X76 P/N Vendor Location Bom Structure 8 GND
1 1 ACES_85201-06051
X7611630L07 Infineon C717,C718,R698,R702,R703,U32,X3 IN_TPM@ C630 C631 FPCONN@

4.7U_0805_10V4Z 0.1U_0402_16V4Z
X7611630L08 Winbond C724,U32 WB_TPM@ @ 2 2

Let C715 close pin 24 Let C724 close pin 10

+3VS Copy IFT
LED 05/28 Change R660,R596,R597,R598,R599,R600 to 820ohm for 15W@ +3VALW
1 1
C715 C724
05/28 Add R660,R596,R597,R598,R599,R600 to 2kohm for 14W@ TPM 1.2 +3VS WB_TPM@
0.1U_0402_16V4Z 1U_0402_6.3V4Z
TPM@ 2 2
R660 R596 R597 R598 R599 R600
+3VS

24
19
10

1
U32
Base I/O Address R700

VSB
VDD
VDD
VDD
2K_0402_5% 2K_0402_5% 2K_0402_5% 2K_0402_5% 2K_0402_5% 2K_0402_5% 0 = 02Eh 4.7K_0402_5%
14W@ 14W@ 14W@ 14W@ 14W@ 14W@ 1 = 04Eh TPM@
LPC_AD0 SUS_STAT#
*
<21,32,35> LPC_AD0 26 28 SUS_STAT# <22>

2
LPC_AD1 LAD0 LPCPD#
<21,32,35> LPC_AD1 23 LAD1 TESTB1/BADD 9
<21,32,35> LPC_AD2 LPC_AD2 20 8 TPM_TEST1 R703 1 2 0_0402_5%
LAD2 TEST1

1
R660 15W@ <21,32,35> LPC_AD3 LPC_AD3 17 IN_TPM@
820_0402_5% LAD3 TPM_XTALO R701
XTALO 14
+5VS 1 2 2 1 LED4 SATA_LED# <21> XTALI 13 TPM_XTALI 4.7K_0402_5%
TPM @
HT-191NB_BLUE_0603 CLK_PCI_TPM 21 SLB 9635 TT 1.1
<16> CLK_PCI_TPM

2
LPC_FRAME# LCLK
<21,32,35> LPC_FRAME# 22 LFRAME# GPIO2 2
R596 15W@ PLT_RST_BUF# 16 6
<8,17,20,26,28,30> PLT_RST_BUF# LRESET# GPIO
820_0402_5% SERIRQ 27
<22,32,35> SERIRQ SERIRQ
+5VALW 1 2 2 1 LED1 PM_CLKRUN# 15
PWR_LED# <32,33> <22,32> PM_CLKRUN# CLKRUN#
+3VS 1 2 7 PP NC 1
HT-191NB_BLUE_0603 R698 4.7K_0402_5% 3
IN_TPM@ NC C717 IN_TPM@
12

GND
GND
GND
GND
NC 15P_0402_50V8J
TPM_XTALI
R597 15W@ HT-191UD_AMBER_0603 SLB-9635-TT-1.2_TSSOP28

4
11
18
25

10M_0402_5%
820_0402_5% Amber IN_TPM@ X3

1
+5VALW 1 2 2 1 LED6 CHARGE_LED0# <32> 1 IN NC 2

IN_TPM@
CLK_PCI_TPM
R598 15W@ Blue 4 3
OUT NC
2

R702
+5VALW 1 2 2 1 LED7 CHARGE_LED1# <32>
820_0402_5% R699 32.768KHZ_12.5P_1TJS125BJ2A251

2
@ 10_0402_5% U32 IN_TPM@
HT-191NB_BLUE_0603 TPM_XTALO
1

R599 15W@ HT-191UD_AMBER_0603 2 C718 IN_TPM@

820_0402_5% Amber 15P_0402_50V8J
+5VS 1 2 2 1 LED5 WLAN_LED# <30>
C716
@ 15P_0402_50V8J S IC WPCT200AA0WG TSSOP 28P TPM
R600 15W@ 1 WB_TPM@
Blue
+5VS 1 2 2 1 LED3 BT_LED# <34>
820_0402_5%

HT-191NB_BLUE_0603 Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/18 Deciphered Date 2008/8/18 Title

12/7 Modified LED footprint to LED_HT-297UD-CB_4P THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MDC/LED/Camera/FP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B
12/15 Modified to correct LED symbol! DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JHXXX M/B LA-4241P Schematic 0.4
Date: Tuesday, June 03, 2008 Sheet 40 of 49
 A B C D E

+1.5V TO +1.5VS

+5VALW TO +5VS +1.5V

+3VALW TO +3VS J8
+5VALW +5VS PAD-OPEN 3x3m
+3VALW +3VS 1 2
U30 +1.5VS
8 1 U31
1 D S 1
7 2 8 1 U34
D S D S

2
6 D S 3 1 1 7 D S 2 8 D S 1

2
5 4 C632 C633 R601 6 3 1 1 7 2
D G D S C634 C635 R602 D S
5 D G 4 6 D S 3 1 1
AO4468_SO8 10U_0805_10V4Z 470_0603_5% 5 4 C643 C644
@ 2 2
1U_0603_10V4Z @ AO4468_SO8 10U_0805_10V4Z 470_0603_5% D G

6 1
@ 2 2
1U_0603_10V4Z @ AO4468_SO8 10U_0805_10V4Z

3 1
Q51A @ @ 2 2
1U_0603_10V4Z
@ Q51B
@
2 SUSP
+VSB 5VS_GATE 5 SUSP
R604 2N7002DW-T/R7_SOT363-6 +VSB 1 2

1
33K_0402_5% 1 R605 2N7002DW-T/R7_SOT363-6 +VSB 1 2

4
1

D C638 47K_0402_5% R612

1

1
SUSP D C639 47K_0402_5%
2 1

1
G 0.1U_0603_25V7K SUSP @ D C646
2
Q28 2 G 0.1U_0603_25V7K SUSP
S 2
3

SSM3K7002FU_SC70-3 Q29 S 2 G 0.1U_0603_25V7K

3
SSM3K7002FU_SC70-3 Q35 S 2 @

3
SSM3K7002FU_SC70-3
@

+5VALW

+5VALW
2

2 2
R613

2
100K_0402_5%
R621
100K_0402_5%
1

SYSON#

1
SUSP
SUSP <26,47>
1

D
SYSON 2 Q36
<31,32,46> SYSON

1
G D
SSM3K7002FU_SC70-3
S 2 Q43
<17,31,32,46,47> SUSP#
3
1

G SSM3K7002FU_SC70-3
1
R614 S

3
1
C647
10K_0402_5% R622 100P_0402_50V8J
2
2

3/14 Change R16 from 100K to 10K 10K_0402_5%

2
3 3

+1.5VS +1.05VS +0.9VS +1.8V

2

R615 R617 R618 R619

470_0603_5% 470_0603_5% 470_0603_5% 470_0603_5%
@ @ @ @
1

1
3

Q47B Q47A Q48B Q48A

@ @ @ @

5 SUSP 2 SUSP 5 SUSP 2 SYSON#

2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6

4

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/18 Deciphered Date 2008/8/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC Interface
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JHXXX M/B LA-4241P Schematic
Date: Wednesday, May 28, 2008 Sheet 41 of 49
A B C D E
 A B C D

DC301001Y00
PL1 VIN
@ SINGA_2DW-0268-B16 ADPIN HCB4532KF-800T90_1812
1 1 1 2
2 2
3 3

0.022U_0603_50V7K
4 4

2200P_0402_50V7K
0.01U_0402_50V7K

0.01U_0402_50V7K

0.022U_0603_50V7K
PJP1

1
PC142
PC1

PC2

PC3

PC4
1 1

2
PR2 PC5
@ 10K_0402_1% @ 0.01U_0402_25V7K
1 2 1 2
VS
PR3
VIN 1M_0402_1%
1 2

10K_0402_1%
1
84.5K_0402_1%
1

VS

PR5
PR4

PR6

8
10K_0402_1%
1 2 5

P
ACIN <22,32,44>

2
PR7 +
7
2

O
8
22K_0402_1% 6
-

G
1 2 3 P PU2B
+ LM393DG_SO8
1

4
O
1000P_0603_50V7K

20K_0402_1%

2 -
1

10K_0402_1%
0.1U_0402_16V7K

PU2A

RLZ4.3B_LL34
1

1
PR8

LM393DG_SO8
4
PC6

PC7

PR9
2
Vin Detector 2

PD2
2

2
2

PR10

2
10K_0402_1%
2 1
High 18.764 17.901 17.063
RTCVREF
3.3V Low 17.745 16.9 16.03

VIN

2
PD3

RLS4148_LL34-2

1
PD4
2 1
3.3V BATT+

1
68_1206_5%

68_1206_5%
RTCVREF

PR11

PR12
RLS4148_LL34-2
G920AT24U_SOT89-3 VS
PR13
560_0603_5% PR14 PU3 PR15

2
560_0603_5% 200_0805_5%
1 2 1 2 3 2 2 1 CHGRTCP 3 1
OUT IN
0.22U_1206_25V7K
1

PC9

0.1U_0603_25V7K
1U_0805_25V4Z

+CHGRTC
4.7U_0805_10V4Z

3 3
1

GND
100K_0402_1%
PC8

1
PR16

PC10

PC11
2

1
2

2
PR17
2

22K_0402_1%
<33,35> 51_ON# 1 2
PQ1
TP0610K-T1-E3_SOT23-3

PJ1 PAD-OPEN 3x3m

+1.8VP 1 2 +1.8V
PJ14 PAD-OPEN 3x3m
1 2
(8A,320mils ,Via NO.= 16)
PJ2 PJ3
PAD-OPEN 3x3m PAD-OPEN 3x3m PJ4 PAD-OPEN 3x3m
+5VALWP 1 2 +5VALW +0.9VSP 1 2 +0.9VS +1.05VSP 1 2 +1.05VS

(16A,800mils ,Via NO.= 24)

(6A,240mils ,Via NO.= 12) (2A,80mils ,Via NO.= 4)
4 PJ5 PJ7 4

PAD-OPEN 3x3m
1 2 +3VALW PAD-OPEN 3x3m
+3VALWP
+VSBP 1 2 +VSB

(6A,240mils ,Via NO.=12)

(0.3A,40mils ,Via NO.= 2) Security Classification Compal Secret Data Compal Electronics, Inc.
PJ6
PAD-OPEN 3x3m 2005/10/17 2006/10/17 Title
Issued Date Deciphered Date
1 2
+1.5VP +1.5V
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DCIN/DECTOR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
(6A,240mils ,Via NO.=12) DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, June 03, 2008 Sheet 42 of 49
A B C D
 A B C D

BATT++ PJ8
DC040003600 PAD-OPEN 3x3m
1 2 BATT+

PJP2
PH1 under CPU botten side :
BATT++
1 1
2
1 2 +3VALWP CPU thermal protection at 89 degree C
2

1000P_0402_50V7K

1000P_0402_50V7K
CNT1 PR19 @ PR18
3 3 Recovery at 70 degree C

0.01U_0402_50V7K
4 CNT2 1 2 100K_0402_5%
4 +3VALWP

1
1 5 EC_SMCA VS 1
5

1
PC12

PC13

PC14
6 EC_SMDA @ 100K_0402_5%
6 TS_A
7

2
7

2
VL

1K_0402_1%

0.1U_0603_25V7K
8 GND

2
8

2
VL

PR21
9 9

PC15
G1 10

150K_0402_1%
G2 11 PR20

2
10K_0402_1%
1K_0402_1%

2
1

PR23
SUYIN_200275MR009G180ZR

PR22
PR24
1 442K_0603_1%
2

1
2
100_0402_1%
1 PR27

8
100_0402_1%
78.7K_0603_1% PU4A
PD5
PR25

PR26
1 2 3 +

P
0 1 1 2 MAINPWON <21,45>
TM_REF1 2 -

G
100K_0603_1%_TH11-4H104FT
2

2
1SS355TE-17_SOD323-2

1
LM358ADR_SO8

4
<BOM Structure> <BOM Structure>

PH1
1000P_0402_50V7K
EC_SMB_CK1 <32,34>

1U_0603_6.3V6M
2
1

PC16
EC_SMB_DA1 <32,34>

PC17
PR28
2 150K_0402_1%
1 VL

2
1 2 +3VALWP
2 2

150K_0402_1%
PR29

1
1K_0402_1%

6.49K_0402_1%
1

PR31
PR30

2
2

BATT_TEMP <32>

PQ2
TP0610K-T1-E3_SOT23-3

B+ 3 1 +VSBP
0.22U_1206_25V7K

0.1U_0603_25V7K
1

100K_0402_1%

1
PR32

PC18

PC19
2

PR33
2

22K_0402_1%
VL 1 2
3 3
10K_0402_1%
2
PR34

PR35
1

0_0402_5% D
1 2 2 PQ3
<45> SPOK
G SSM3K7002F_SC59-3
0.1U_0402_16V7K

S
3
1

PC20
2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/10/17 Deciphered Date 2006/10/17 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BATTERY CONN. / OTP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, June 03, 2008 Sheet 43 of 49
A B C D
 A B C D

65W, Iadapter=0~3.42A, Current sense=0.015ohm, PR45=110K, CP=3.175A

90W, Iadapter=0~4.74A, Current Sense=0.015ohm, PR45=54.9K, CP=4.303A

AO4407_SO8 B+
PQ5
PQ4
AO4407_SO8
VIN 8 1 1 8 PR36
7 2 2 7 0.015_2512_1% PJ9
6 3 3 6 1 4 2 1 CHG_B+
2 1

1
1 1

5 5

2
10U_1206_25V6M

10U_1206_25V6M
1 2 3 @ JUMP_43X118 PR38

1
PC145 PC21 100K_0402_1%

2
0.01U_0402_25V7K
PR37 2200P_0402_50V7K 0.01U_0402_25V7K

CHGEN#

1
2

100K_0402_1%

PC23

PC24
3.3_1210_5%

2
1
PC22 PC27 PC28

1
2

5
6
7
8

3
2
1
PC26

PR39
0.01U_0603_50V7K 0.1U_0402_16V7K PU5 0.1U_0805_25V7K
2

1
1 2 1 28 CHG_PVCC 1 2 PQ7
CHGEN PVCC AO4407_SO8

1
1

1
PR40 BATDRV# 4

2
PR43 PC29 PC30 2.2_0603_5% PQ6
3.3_1210_5% 0.1U_0603_25V7K @0.1U_0603_25V7K 27 1 2 4 AO4466_SO8

2
BTST

2
PR41
2

340K_0402_1% ACN 2 26 1 PR181 2

ACP ACN HIDRV
3

3
2
1

5
6
7
8
ACP 0_0603_5% PR44

1
1

ACDRV 4 25 PL2 0.02_2512_1%

ACDRV PH
1

PD6 ACDET 5 PD7 10UH_SIL1045RA-100PF_4.5A_30% BATT+

PC31 ACDET
2 1 1 2 1 2 1 4

10U_1206_25V6M
1U_0603_25V6K

<BOM Structure>
RLZ24B_LL34
2

10U_1206_25V6M
RLS4148_LL34-2 PC32

REGN
2 3
2

2
PR45 0.1U_0603_25V7K PR46

5
6
7
8

PC34
PR42 110K_0402_1% 4.7_1206_5%

PC33
54.9K_0402_1% 1 2 ACSET 6
VREF ACSET <BOM Structure>
24 PQ8

2
REGN

1
1

1
PR47 PC36 AO4466_SO8
PC35 100K_0402_1% 1U_0603_10V6K 4

1
@ 0.01U_0402_25V7K

2
2

PC37

2
2
1 2 7 ACOP 680P_0603_50V7K 2

2
PR48 PC38 23

3
2
1
340K_0402_1% 0.47U_0603_16V7K LODRV
Icharge=(Vsrset/Vvdac)*(0.1/PR44)
CP setting
1

PGND 22
Iadapter=(Vacset/Vvdac)*(0.1/PR36) OVPSET 8 PC39
OVPSET 0.1U_0402_16V7K
Input OVP : 22.3V 1 2
9 AGND LEARN 21 ACOFF <32>
2

Input UVP : 17.26V

1
PR49
Fsw : 300KHz 54.9K_0402_1% VREF=3.3V PR50
PC40 PC41
VREF 20 1 2 0.1U_0603_25V7K @0.1U_0603_25V7K

2
CELLS
1

10 VREF 0_0402_5%
VREF VREF PR51
3

1
100K_0402_1% PC42
PR178 1U_0603_10V6K
1

200K_0402_1% 19 SE_CHG+
1

2
SRP
1

PR179 2 11 18 SE_CHG-
100K_0402_1% PQ9 VDAC SRN
17
2

BAT
1

D SI2301BDS-T1-E3_SOT23-3
2

1
2 PC43 VADJ 12
G 0.1U_0603_25V7K VADJ PC44
2

1
1

PC141 D ACSET 0.1U_0603_25V7K

S
3

2
ACOFF 1 2 2 PQ31 29
G RHU002N06_SOT323-3 ACGOOD# TP
S PQ30
13 ACGOOD ICHG setting
3
1

0.1U_0402_16V7K PR53
PR180 RHU002N06_SOT323-3 16 2 1
3
SRSET IREF <32> 3
340K_0402_1% BATDRV# 14 49.9K_0402_1%
BATDRV

1
PR55
2

15 1 2 100K_0402_1% PC45
IADAPT @0.01U_0402_25V7K

2
BQ24751ARHDR_QFN28_5X5 PR54

2
REGN 10_0603_5%

1
1

PC46
PR56 100P_0402_50V8J

2
0_0402_5% <32> ADP_I
IREF Current
PR57
2

OVP voltage : 1 2 VADJ 2.968V 3A VREF

BATT+ <32> CHGVADJ
LI-3S :13.50V--BATT-OVP=1.5V VS
@ 4.3K_0402_5%

2
VREF
BATT-OVP=0.111*BATT+
1

RTCVREF PR58
1

PC140 100K_0402_1%

2
PR59 CHGVADJ Per Cell @1000P_0402_50V7K
2
0.01U_0402_25V7K

340K_0402_1% PR61

1
2

3.3V 4.35V @ 100K_0402_1% CHGEN#

2
1

PC47

PR52

1
D
1

100K_0402_1% 2 PQ10
ACIN <22,32,42> <32> FSTCHG
2

PR62 0V 4V PR60 G RHU002N06_SOT323-3

2

1
499K_0402_1% @ 10K_0402_5% D
S

3
ACGOOD# 2 PQ11
8

4
PR63 PU4B G @ SSM3K7002F_SC59-3 4
2

10K_0402_1% 5 S
P

3
+
<32> BATT_OVP 1 2 7 0
0.01U_0402_25V7K

- 6
G

LM358ADR_SO8
4
1

1
PC48

<BOM Structure> PR64 PC49

105K_0402_1% 0.01U_0402_25V7K
@
Security Classification Compal Secret Data Compal Electronics, Inc.
2

Issued Date 2006/05/18 Deciphered Date 2007/05/18 Title

2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CHARGER
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
CHARGER
Date: Wednesday, May 28, 2008 Sheet 44 of 49
A B C D
 A B C D

ISL6237_B+
ISL6237_B+
B+
PR65
PJ10 PAD-OPEN 3x3m
1 2 1 2

2200P_0402_50V7K

2200P_0402_50V7K
4.7U_1206_25V6K
0_0603_5%

2200P_0402_50V7K

5
6
7
8

4.7U_1206_25V6K

4.7U_1206_25V6K
PQ12

1
PC50

PC51
PQ13

8
7
6
5

1
AO4466_SO8

PC54
PC150
1
VL AO4466_SO8 1

PC52

PC53
2

1U_0603_10V6K

2
2
PC55 4

2
0.1U_0603_25V7K

4.7U_0805_6.3V6K
1
PC56
4

PC57
1
+5VALWP

3
2
1
1
2
3
PL4

7
PL3 PU6 PC58 2 1
1 2 1U_0603_10V6K 4.7UH_SIL104R-4R7PF_5.7A_30%

LDO
VIN

VCC
+3VALWP 4.7UH_SIL104R-4R7PF_5.7A_30% 33 19 1 2
TP PVCC

2.2_1206_5%
1

8
7
6
5

5
6
7
8
2.2_1206_5%
DH3 26 15 DH5
UGATE2 UGATE1

@ PR67

@ PR69
PR66 PR68

0_0402_5%
220U_6.3V_M

2 1 BST3A 24 BOOT2 BOOT1 17 BST5A 2 1

2

1 0_0603_5%

1 2
2

2
PR70

61.9K_0402_1%
PC60 0_0603_5% PC61

2
+

220U_6.3V_M
4 0.1U_0603_25V7K 4

2
PC59

680P_0603_50V8J
0.1U_0603_25V7K

1
1

PC63

@ PR71
680P_0603_50V8J
LX3 25 16 LX5 1
1

2
2 PHASE2 PHASE1

PC62
+

PC64
Rds=18mOHM

1
2
3

3
2
1
DL3 23 18 DL5 @

1
@ LGATE2 LGATE1
PQ15 2
AO4712_SO8 22 PQ14
PGND

2
FB3 AO4712_SO8
2 30 OUT2 Rds=18mOHM 2

0_0402_5%
PR72
10K_0402_1%

OUT1 10
2

VL 32 REFIN2
PR74

1
11 FB5
2VREF_ISL6237 FB1
1

@ 1 2 1 REF VFB=0.7V
PC65 0.22U_0603_10V7K
BYP 9
8 LDOREFIN @ PR75 0_0402_5%
SKIP 29 2 1 VL
Rds(on) = 18m ohm(max) ; Rds(on) = 15m ohm(typical) PR76 0_0402_5%
1 2
PZD1 20 28
RLZ5.1B_LL34 PR77 NC POK2
100K_0402_1%
3.3VALWP VS
1 2 1 2 4 13
SPOK <43>
EN_LDO POK1 PR79
Imax=5.59A
2
200K_0402_5%

330K_0402_1%
2

Ipeak=7.85A
PR78

PC66 14 12 ILM1 2 1
0.22U_0603_25V7K EN1 ILIM1
Iocp=10.133A PR80
1

27 31 ILIM2 2 1

GND
TON
1

EN2 ILIM2

NC
2
3 330K_0402_1% 3

0_0402_5%
PR81 ISL6237IRZ-T_QFN32_5X5

21
@ 0_0402_5%

PR82
1

2VREF_ISL6237
Rds(on) = 18m ohm(max) ; Rds(on) = 15m ohm(typical)
1

1
PR84
0_0402_5%
<21,43> MAINPWON

2
PR85
0_0402_5%
5VALWP

2
2 1 1 2 Imax=4.9A
2

PC139
Ipeak=7A

2VREF_ISL6237
@ PR86 1U_0603_10V6K
47K_0402_1%
Iocp=10.146A
0.047U_0603_16V7K

0.047U_0402_16V7K
1

1
PC67

PC68

1 3
2

@
PQ29
TP0610K-T1-E3_SOT23-3

PD8
1 2

1SS355TE-17_SOD323-2
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/10/17 Deciphered Date 2006/10/17 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+5VALWP/+3VALWP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, May 28, 2008 Sheet 45 of 49
A B C D
 5 4 3 2 1

PC69 PC70

1
1U_0402_6.3V6K 1U_0402_6.3V6K

2.2_0603_1%

2
PR87 PR88

+5VALWP 2 1 1 2 +5VALWP

2.2_0603_1%

D D

1
PC71 PC72
0.1U_0603_25V7K 0.1U_0603_25V7K
PJ11

2
B+ 2 2 1 1 ISL6228_B+
ISL6228_B+ 2 PR89 1 2 PR90 1 ISL6228_B+
JUMP_43X118
1 10_0603_1% 10_0603_1%
PC147
2200P_0402_50V7K
2

+5VALWP

2
PC73 PC74
1000P_0402_50V7K 1000P_0402_50V7K PR92

1
PR91 18.2K_0402_1%
1000P_0402_50V7K 3.3K_0402_5% PR93 22K_0402_1%
PR95 22K_0402_1%

1
PC75 1 PR94 2
2 1 1 2

1
@
PR96 0_0402_5%

1
2 1 FB_1.5
29

PGOOD1

FSET1

VIN1

VCC1

VCC2

VIN2

FSET2
34K_0402_1% GND_T

2
PR98
PR97 PR99 3.3K_0402_5%
1 2 8 28 1 2 +5VALWP 16.5K_0402_1% PR100 1000P_0402_50V7K
FB1 PGOOD2 PC76
8.2K_0402_1% @ 2 1 1 2

1
0_0402_5%
ISL6228_B+ PR101
VO_1.5 9 27 FB_1.8 1 2
C VO1 FB2 C
4.7U_1206_25V6K

4.7U_1206_25V6K

34K_0402_1%
1

1
PC78

PC79

8
7
6
5

PC77 PR102
0.022U_0402_16V7K OCSET_1.5 10 26 VO_1.8 1 2
2

PQ16 OCSET1 VO2

1 2
AO4466_SO8 12.1K_0402_1%
2

PR103 4
8.2K_0402_1% 1.5V_EN 11 25 OCSET_1.8
PR104 EN1 PU7 OCSET2 PR105 ISL6228_B+
SYSON <31,32,41>
DH_1.5-21 2 0_0402_5%
ISL6228HRTZ-T_QFN28_4X4 1 2
1

1
2
3

PL5 0_0603_5%
PC80
+1.5VP 1 2 LX_1.5 12 24 0.022U_0402_16V7K
PHASE1 EN2

5
6
7
8

4.7U_1206_25V6K
1 2

PC81

4.7U_1206_25V6K
PC83

PC82
1 1.8UH_SIL104R-1R8PF_9.5A_30% PC146 @ 0.01U_0402_25V7K 1 2
1

8
7
6
5

@ 1000P_0402_50V7K PQ17

2
+ DH_1.5-113 LX_1.8 AO4466_SO8
DCR 10 mOHM 23

2
UGATE1 PHASE2

2
PC85 4 PR106
2

DH_1.8-2
12.1K_0402_1%
PC84 2 PQ18 0.1U_0402_16V7K
220U_6.3V_M AO4712_SO8 4 PR108
2 1 2 1BST_1.5 14 22 DH_1.8-1 1 2

3
2
1

1
BOOT1 UGATE2 0_0603_5% PL6
LGATE1

LGATE2
PR107
Rds=18mOHM 1 2
PGND1

PGND2

BOOT2
PVCC1

PVCC2
+1.8VP
2.2_0603_5%
1
2
3

5
6
7
8
1.8UH_SIL104R-1R8PF_9.5A_30%
1.5VP
15

16

17

18

19

20

21
PQ19 + PC86
PC88
B
Imax=2.89A AO4712_SO8 DCR 10 mOHM 220U_6.3V_M B
PR109
Ipeak=4.13A +5VALWP BST_1.8 1 2 1 2
2

Iocp=8.2A +5VALWP 4
2

2
2.2_0603_5%
PC89 PC87 0.1U_0402_16V7K
0_0402_5% 1U_0402_6.3V6K 1U_0402_6.3V6K
1

3
2
1
<17,31,32,41,47> SUSP# 1 2 Rds=18mOHM
PR177 DL_1.5 DL_1.8

PR110
@ 0_0402_5%
2 1 1.5V_EN
<31,32,41> SYSON
1.8VP
0.01U_0402_25V7K

VFB=0.6V
1

Imax=6.09A
PC90

Ipeak=8.7A
2

Iocp=12.1A

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/10/17 Deciphered Date 2006/10/17 Title
1.5VP/1.8VP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, May 28, 2008 Sheet 46 of 49
5 4 3 2 1
 5 4 3 2 1

PJ12
2 1 6268_B+ For discrete
B+ 2 1
D @ JUMP_43X118 D
PC97=>220UF/15m,
PHASE_1.05V
PR111 PR119=>11.5K

1
0_0603_5%
PC149 DH_1.05-1 1 2 DH_1.05-2

1
3300P_0402_50V7K PC92 6268_1.05V
PC93

2
PC91 4.7U_1206_25V6K

1
PR112 1 PR113 2 1 2 1.05VSP

2
4.7U_1206_25V6K

1
10K_0402_1% 2.2_0603_5%
+5VS
0.1U_0402_16V7K Imax=14.56A
PR114
0_0603_5% BOOT_1.05V Ipeak=20.4A

5
6
7
8
PR115
Iocp=24.5A

1
0_0603_5% PQ20

2
AO4466_SO8

16

15
8

1
PU500 PR116
4.7_0603_5% 4

PHASE
GND

PGOOD

UG

BOOT

2
PC94 1 2 6268_1.05V

1 2 3 VIN PVCC 14 1 2

3
2
1
@ 0.1U_0603_25V7K PC95 2.2U_0603_6.3V6K

6268_1.05V LG_1.05V PL7

4 VCC LG 13
1.8UH_SIL104R-1R8PF_9.5A_30%
+1.05VSP

1
1 2 +1.05VSP
PC96

1
2.2U_0603_6.3V6K 12 1

2
PGND PR117

5
6
7
8
4.7_1206_5% + PC97
PR118 330U_D2_2.5VY_R15M
C ISEN_1.05V PQ21 C
<17,31,32,41,46> SUSP# 1 2 5 11 1 2

2
EN ISEN AO4712_SO8 2

COMP
0_0402_5% PR119

FSET
1

1
19.1K_0402_1%

VO
4

FB

1
PC99 PR120
0.1U_0402_16V7K PC98 2.37K_0402_1%
2

10
@ @ISL6268CAZ-T_SSOP16 680P_0603_50V7K

2
3
2
1

2
Rds=18mOHM

FB_1.05V
1
PR121
1 49.9K_0402_1%

1
PC100

1
22P_0402_50V8J PR122
2

2
57.6K_0402_1% @PC500
@PC500

1
0.01U_0402_25V7K

2
1
PR123

2
ZZZ 3K_0402_1%

2
PC102
ISL6268CAZ 6800P_0402_25V7K

VFB=0.6V
B B

+1.8V
1

PJ13
1

JUMP_43X118
2 2

PU9
1 VIN VCNTL 6 +3VALWP
2 GND NC 5
1

1
1

PC103 3 7 PC104
10U_0805_6.3V6M VREF NC 1U_0603_6.3V6M
2

PR124 4 VOUT NC 8 2
1K_0402_1%
9
2

TP

PR125 APL5331KAC-TRL_SO8
+0.9VSP
1

0_0402_5% D
1

<26,41> SUSP 1 2 2
1

G
S PC106
3

2
1

10U_0805_6.3V6M
2

A PC107 A
@ 0.1U_0402_16V7K
2

PC105
PQ22 PR126 0.1U_0402_16V7K
SSM3K7002F_SC59-3 1K_0402_1%
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/10/17 Deciphered Date 2006/10/17 Title
1.05VSP/0.9VSP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, May 28, 2008 Sheet 47 of 49
5 4 3 2 1
 5 4 3 2 1

+5VS

2
<5>

<5>

<5>

<5>

<5>

<5>

<5>
CPU_VID6

CPU_VID5

CPU_VID4

CPU_VID3

CPU_VID2

CPU_VID1

CPU_VID0
PR127

<32>
VR_ON
1_0603_5% +CPU_B+ PL8
D
HCB4532KF-800T90_1812 D
1 2 B+

10U_1206_25V6M

10U_1206_25V6M

10U_1206_25V6M
1

220U_25V_M
1

1
PC110

PC111

PC112
+

0.022U_0402_16V7K
PR128 0_0402_5%

1
PC109

PC113
2.2U_0603_6.3V6K
1 2 PC143
<8,22> PM_DPRSLPVR_D

PC108
2200P_0402_50V7K

2
PR129 0_0402_5% 2

2
PR133

PR134

PR135

PR136

PR137

PR138

PR139
PR132
<5,8,21> H_DPRSTP# 1 2

5
PR130 @ 0_0402_5% PQ23
1 2 SI7686DP-T1-E3_SO8
<16> CLK_EN#

1
1

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%
0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%
PR131 0_0402_5%
+3VS 1 2 4
+3VS

1U_0603_6.3V6M

2
2
1.91K_0402_1%
2.2_0603_5% 0.22U_0603_10V7K

1
PC114
PR141 PC115 UGATE_CPU1-2 0.36UH_MPC1040LR36_24A_20%

3
2
1
1
BOOT_CPU1 1 2 1 2 2 1 +CPU_CORE
2

PR140

4.7_1206_5%
PR142

1
10K_0402_1%
3.65K_0805_1%
PL9

AO4456-T1-E3_SO8

PR144

PR145

PR146
499_0402_1% PR147

49

48

47

46

45

44

43

42

41

40

39

38

37
1 2

5
6
7
8

5
6
7
8
<BOM Structure>

1000P_0402_50V7K
2 0_0603_5% 1_0402_5%

PC144
PR143

3V3

CLK_EN#

DPRSTP#

VID6

VID5

VID4

VID3

VID2

VID1

VID0
GND

DPRSLPVR

VR_ON

D
D
D
D

D
D
D
D
1

PQ25

680P_0603_50V8J
1 2

2
1 36 PR148 @ 0_0603_5%
<8,16,22> VGATE

2
PGOOD BOOT1

PC116
@ 1 2

G
S
S
S

S
S
S
2 35 UGATE_CPU1-1 VSUM PC117
<5> H_PSI# PSI# UGATE1
1 2

4
3
2
1

4
3
2
1

2
1 2 3 34 PHASE_CPU1 PQ24 VCC_PRM
PMON PMON PHASE1
PR149 @ 0_0402_5% AO4456-T1-E3_SO8 ISEN1
C 0.22U_0603_10V7K C
1 2 4 RBIAS PGND1 33
@ PR151 0_0402_5% PR150 147K_0402_1%
1 2 VR_TT# 5 32 LGATE_CPU1 +CPU_B+
<4> H_PROCHOT# VR_TT# LGATE1

10U_1206_25V6M

10U_1206_25V6M
PR152 @ 4.22K_0402_1% PH2

1
1 2 1 2 6 NTC PVCC 31

PC119

PC120
PQ26
@ 100K_0603_1%_TH11-4H104FT 7 30 LGATE_CPU2 SI7686DP-T1-E3_SO8

2
SOFT LGATE2
1 2
@ PC118 8 29
0.015U_0402_16V7K 0.022U_0603_50V7K PC121 OCSET ISL6262ACRZ-T_QFN48_7X7 PGND2
4
1 2 9 28 PHASE_CPU2
VW PHASE2 PR154
PR153 13K_0402_1% 10 27 UGATE_CPU2-1 1 2 UGATE_CPU2-2 0.36UH_MPC1040LR36_24A_20%
COMP UGATE2 0_0603_5%
1 2

3
2
1
11 26 BOOT_CPU2
1 2 1 2 2 1
FB BOOT2 PR155 PL10
1 2

1
1000P_0402_50V7K PC122 2.2_0603_5% PC123
DROOP

12 FB2 NC 25

5
6
7
8

5
6
7
8

1
VDIFF

ISEN2

ISEN1
VSUM

10K_0402_1%
VSEN

PR156 6.81K_0402_1% 0.22U_0603_10V7K PR157

GND

VDD
RTN

DFB

1
<BOM Structure>PR160
VIN

PR159
3.65K_0805_1%
4.7_1206_5%
VO

1 2

D
D
D
D

D
D
D
D

PR158
1 2 PU10 PQ27
13

14

15

16

17

18

19

20

21

22

23

24

1 2
<BOM Structure> AO4456-T1-E3_SO8 1_0402_5%

2
G

G
S
S
S

S
S
S
PC124 1000P_0402_50V7K

2
ISEN1 PC125 PR164 @ 0_0603_5%

4
3
2
1

4
3
2
1
ISEN2 680P_0603_50V8J 1 2

2
2

PR161 97.6K_0402_1% PC126 470P_0402_50V7K 1 2 +5VS

1

1 2 2 1 PR162 VSUM PC128

1

@ 0_0402_5% PR163 1_0603_5% 1 2

PR165 PC127
1 2 1U_0402_6.3V6K
1

1K_0402_1% PQ28 0.22U_0603_10V7K

2

B PC129 220P_0402_50V7K AO4456-T1-E3_SO8 VCC_PRM B

PR167 ISEN2
255_0402_1% PC130 1000P_0402_50V7K 10_0603_5%
1 2 1 2 1 2 +CPU_B+
1

PR166 1 2 PC131
0.1U_0603_25V7K
PR168 1K_0402_1%
2

PC132 0.018U_0603_50V7J
<5> VCCSENSE 1 2 1 2
VSUM
1

PR169 0_0402_5%
1

2.61K_0402_1%

PC134 PC133
PR171

+CPU_CORE 1 2 0.018U_0603_50V7J 0.018U_0603_50V7J

2

PR170 20_0402_5% 1 2
PR172 0_0402_5%
<5> VSSSENSE
2
1

11K_0402_1%

PC135 180P_0402_50V8J
PR174

PR173 1 2
2

10KB_0603_5%_ERTJ1VR103J
20_0402_5% 1 2 1 2 PH3
2

PR175 1K_0402_1% PR176 4.02K_0402_1%

PC136 0.1U_0402_16V7K
1

VCC_PRM 1 2

PC138 0.22U_0402_6.3V6K
PC137 2 1 2 1
0.22U_0603_10V7K

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/10/17 Deciphered Date 2006/10/17 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+CPU_CORE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, June 03, 2008 Sheet 48 of 49
5 4 3 2 1
 5 4 3 2 1

page Reason for change Modify list

Add original ACIN detector fun,and del TI fun. ADD PR6, Del PQ11, PR61
Change PC28 to 0.1U for common design PC28
Change PR16,PR32 & PR77 to 1% for common part PR16 & PR32 & PR77
D D

Change PC55 to 0.1U_0603 for common design PC55

Add PC139 for 3/5V 2nd source PC139

Change PQ21 to AO4712 and PL7 to 1.8UH for cost PQ21 & PL7
Change PC12 and PC13 to 0402 for source suggest PC12 & PC13
Change PR176 to 4.02K for load line PR176
Change 1.05V VIN from 5valwp to 5VS. reduse S3 power loss
Del PR83 for extra pull-high R
Add cpu_core boost and sunnber for EMI request Add PR141,PR144,PC116,PR155,PR157 &PC125
Add 1.05VSP boost and sunnber for EMI request Add PR113,PR117 &PC98
Fixed CV mode Add PR56,Del PR57&PR60
C C

Adjust 1.05V to 1.074 for HW request Modify PR120 to 2.37K

Adjust 1.5V to 1.527 for HW request Modify PR93 to 22K

DVT Del PR73 for fix 3V in 2nd source

Add PQ30,PQ31, PR178,PR179,PR180,PC141 Prevent ACOP protection by charger
Modify PQ10 to SOT322 Layout limit
Modify 1.5V to susp# Add PR177, Del PR170
Modify PR36 to 0.015 for rating & change PR45 to 100K
Modify PL9 & PL10 form NEC to TOKO
Modify PR108 to 2.2 for EMI request

B
PVT Fix 5valwp, so del PR71, change PR72 to 0 B

Change PC8 to Y5V type for costdown

Change PU6 & PC101 to PU500 &PC500 for BOM

Add PC142,PC143,PC144,PC145,PC146,PC147,PC149,PC150 for EMI request
Add PR40,PR181,PR107,PR109,PR46,PC37 & Del PR108 for EMI request
Change PQ24,PQ25,PQ27,PQ28 to AO4456 for EOL
PVT-1 Move PC500 & PU500 to X76 group.

Pre-MP Del PC144 & PC146 for EMI request

A A

Title
<Title>

Size Document Number Rev

Custom<Doc> <RevCode>

Date: Wednesday, May 28, 2008 Sheet 49 of 49

5 4 3 2 1