SystemC

Aleksandar Milenkovic
The University of Alabama in Huntsville
Email: milenka@ece.uah.edu
 Outline

n Introduction
n Data Types
n Modeling Combinational Logic
n Modeling Synchronous Logic
n Misc

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 Introduction

n What is SystemC?
n Why SystemC?
n Design Methodology
n Capabilities
n SystemC RTL

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 What is SystemC
An extension of C++
enabling modeling of hardware descriptions
n SystemC adds a class library to C++
n The class library provides constructs necessary for hardware
design
n Mechanisms to model system architecture
n Concurrency – multiple processes executed concurrently
n Timed events
n Reactive behavior
n Constructs to describe hardware
n Signals
n Modules
n Ports
n Processes
n Simulation kernel

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 What is SystemC
n Provides methodology for describing
n System level design
n Software algorithms
n Hardware architecture
n Design Flow
n Create a system level model
n Explore various algorithms
n Simulate to validate model and optimize design

n Create executable specifications

n Hardware team and software team use the

same specification

Test input files

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 C++/SystemC Development
Environment

Compiler
Linker SystemC
Class Library and
Debugger
Simulation Kernel

Source files in
Make
SystemC
(design + testbenches)

Simulator
executable

Run
Test input files Test, log output files

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 Why SystemC?
n Designs become
n Bigger in size
n Faster in speed
n Larger in complexity
n Design description on higher levels of abstraction
enables
n Faster simulation
Fastest
n Hardware/software co-simulation
n Architectural Exploration System
Iteration
RTL Time

Chip
Slowest

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 Why SystemC?

SystemC describes overall system

n System level design
n Describing hardware architectures
n Describing software algorithms
n Verification
n IP exchange

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 Non-SystemC Design Methodology
System Designer RTL Designer
Hand-over
Write conceptual Understand
C/C++ model specification

Verify against Partition design

specification

Write each block

Write testbench in HDL

Write testbenches Reverify

Synthesize

To implementation

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 SystemC Design Methodology
System Designer RTL Designer
Hand-over
Write conceptual Understand
C/C++ model specification

Verify against Partition design

specification

Refine SystemC
Write testbench model to RTL

Reverify
Reuse testbench

Synthesize

To implementation

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 System Level Design Process
- Not synthesizable
System Level model
- Event driven
Explore algorithms
Verify against specifications - Abstract data types
- Abstract communication
Refine
- Untimed
Timed model
Explore architectures - Event driven
Do performance analysis
Partition
hardware / software - Synthesizable

Software Hardware - Algorithmic description

Behavioral - I/O cycle accurate

RTOS
model - Clocked
Refine
- Synthesizable
Target code RTL model - FSM
- Clocked

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 SystemC Capabilities
n Modules n Event-base simulation
n SC_MODULE class n Multiple abstraction levels
n Processes n Communication protocols
n SC_METHOD,
SC_THREAD n Debugging support
n Ports: input, output, inout n Waveform tracing
n Signals n VCD: Value Change Dump
n resolved, unresolved (IEEE Std. 1364)
n updates after a delta delay n WIF: Waveform Interch. F.
n Rich set of data types n ISDB: Integrated Signal
n 2-value, 4-value logic Data Base
n fixed, arbitrary size n RTL synthesis flow
n Clocks n System and RTL modeling
n built-in notion of clocks n Software and Hardware

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 Getting Started with SystemC

We will learn how to

n Describe a module
n Declare ports and their types
n Describe module behavior
n Write testbenches

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 SystemC Half Adder

// File half_adder.h // File half_adder.cpp

#include “systemc.h” #include “half_adder.h”

SC_MODULE(half_adder) { void
sc_in<bool> a, b; half_adder::prc_half_adder() {
sc_out<bool> sum, carry; sum = a ^ b;
carry = a & b;
void prc_half_adder(); }

SC_CTOR(half_adder) {
SC_METHOD(prc_half_adder);
sensitive << a << b;
}
};

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 Hierarchy: Building a Full Adder
// File full_adder.h // a destructor
#include “half_adder.h” // no impact on synthesis
~full_adder() {
SC_MODULE(full_adder) { delete ha1_ptr;
sc_in<bool> a,b,carry_in; delete ha2_ptr;
sc_out<bool> sum,carry_out; }
sc_signal<bool> c1, s1, c2; };
void prc_or();
half_adder *ha1_ptr, *ha2_ptr; // File: full_adder.cpp
#include “full_adder.h”
SC_CTOR(full_adder) {
ha1_ptr = new half_adder(“ha1”); void full_adder::prc_or(){
ha1_ptr->a(a); ha1_ptr->b(b); carry_out = c1 | c2;
ha1_ptr->sum(s1); }
ha1_ptr->carry(c1);
ha2_ptr = new half_adder(“ha2”);
Named Association
(*ha2_ptr)(s1, carry_in,sum,c2);
SC_METHOD(prc_or);
sensitive << c1 << c2; Positional Association
}

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 Verifying the Functionality: Driver
// File driver.h // File: driver.cpp
#include “systemc.h” #include “driver.h”

SC_MODULE(driver) { void driver::prc_driver(){

sc_out<bool> d_a,d_b,d_cin; sc_uint<3> pattern;
pattern=0;
void prc_driver();
while(1) {
SC_CTOR(driver) { d_a=pattern[0];
SC_THREAD(prc_driver); d_b=pattern[1];
} d_cin=pattern[2];
}; wait(5, SC_NS);
pattern++;
}
}

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 Verifying the Functionality: Monitor

// File monitor.h // File: monitor.cpp

#include “systemc.h” #include “monitor.h”

SC_MODULE(monitor) { void monitor::prc_monitor(){

sc_in<bool> m_a,m_b,m_cin,
m_sum, m_cout;
void prc_monitor();
SC_CTOR(monitor) {
SC_METHOD(prc_monitor);
sensitive << m_a,m_b,m_cin,
m_sum, m_cout;
cout << “At time “ <<
sc_time_stamp() << “::”;
cout <<“(a,b,carry_in): ”;
cout << m_a << m_b << m_cin;
cout << “ (sum,carry_out): ”;
cout << m_sum << m_cout << endl;
}

}
};

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 Verifying the Functionality: Main
// File full_adder_main.cpp
#include “driver.h”
#include “monitor.h”
#include “full_adder.h”

int sc_main(int argc, char * argv[]) {

sc_signal<bool> t_a, t_b, t_cin, t_sum, t_cout;

full_adder f1(“FullAdderWithHalfAdders”);
f1 << t_a << t_b << t_cin << t_sum << t_cout;

driver d1(“GenWaveforms”);
d1.d_a(t_a);
d1.d_b(t_b);
d1.d_cin(t_cin);

monitor m1(“MonitorWaveforms”);
m1 << t_a << t_b << t_cin << t_sum << t_cout;

sc_start(100, SC_NS);
return(0);
}

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 Running an Example in MSVC60
n To create a new design, first create a new project by using the `New‘
menu item under the `File' menu. Select the Projects tab on the dialog
box that appears and select a Win32 Console Application. Create an
empty project.
n For your own SystemC applications, make sure that the Run Time Type
Information switch is on by using the `Settings...' menu item under the
`Project' menu. Select the C/C++ tab, and select the `C++ Language'
category. Make sure that the `Enable Run Time Type Information
(RTTI)' checkbox is checked.
n Also make sure that the SystemC header files are included by selecting
the C/C++ tab, selecting the `Preprocessor' category, and typing the
path to the SystemC `src' directory in the text entry field labeled
`Additional include directories'. The examples use e.g. `../../../src'.
n Next add the source files to the project by using the `Add To
Project>Files...' menu item under the `Project' menu. Make sure that
the files are added to the new project directory just created. Do the
same for the `systemc.lib' library before building your SystemC
application.

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 Output for full_adder_main.cpp
At time 0 s::(a,b,carry_in): 000 (sum,carry_out): 00 At time 65 ns::(a,b,carry_in): 101 (sum,carry_out): 10
At time 5 ns::(a,b,carry_in): 100 (sum,carry_out): 00 At time 65 ns::(a,b,carry_in): 101 (sum,carry_out): 00
At time 5 ns::(a,b,carry_in): 100 (sum,carry_out): 10 At time 65 ns::(a,b,carry_in): 101 (sum,carry_out): 01
At time 10 ns::(a,b,carry_in): 010 (sum,carry_out): 10 At time 70 ns::(a,b,carry_in): 011 (sum,carry_out): 01
At time 15 ns::(a,b,carry_in): 110 (sum,carry_out): 10
At time 75 ns::(a,b,carry_in): 111 (sum,carry_out): 01
At time 15 ns::(a,b,carry_in): 110 (sum,carry_out): 01
At time 75 ns::(a,b,carry_in): 111 (sum,carry_out): 11
At time 20 ns::(a,b,carry_in): 001 (sum,carry_out): 01
At time 20 ns::(a,b,carry_in): 001 (sum,carry_out): 11 At time 80 ns::(a,b,carry_in): 000 (sum,carry_out): 11
At time 20 ns::(a,b,carry_in): 001 (sum,carry_out): 10 At time 80 ns::(a,b,carry_in): 000 (sum,carry_out): 01
At time 25 ns::(a,b,carry_in): 101 (sum,carry_out): 10 At time 80 ns::(a,b,carry_in): 000 (sum,carry_out): 00
At time 25 ns::(a,b,carry_in): 101 (sum,carry_out): 00 At time 85 ns::(a,b,carry_in): 100 (sum,carry_out): 00
At time 25 ns::(a,b,carry_in): 101 (sum,carry_out): 01 At time 85 ns::(a,b,carry_in): 100 (sum,carry_out): 10
At time 30 ns::(a,b,carry_in): 011 (sum,carry_out): 01 At time 90 ns::(a,b,carry_in): 010 (sum,carry_out): 10
At time 35 ns::(a,b,carry_in): 111 (sum,carry_out): 01 At time 95 ns::(a,b,carry_in): 110 (sum,carry_out): 10
At time 35 ns::(a,b,carry_in): 111 (sum,carry_out): 11 At time 95 ns::(a,b,carry_in): 110 (sum,carry_out): 01
At time 40 ns::(a,b,carry_in): 000 (sum,carry_out): 11
At time 40 ns::(a,b,carry_in): 000 (sum,carry_out): 01
At time 40 ns::(a,b,carry_in): 000 (sum,carry_out): 00
At time 45 ns::(a,b,carry_in): 100 (sum,carry_out): 00
At time 45 ns::(a,b,carry_in): 100 (sum,carry_out): 10
At time 50 ns::(a,b,carry_in): 010 (sum,carry_out): 10
At time 55 ns::(a,b,carry_in): 110 (sum,carry_out): 10
At time 55 ns::(a,b,carry_in): 110 (sum,carry_out): 01
At time 60 ns::(a,b,carry_in): 001 (sum,carry_out): 01
At time 60 ns::(a,b,carry_in): 001 (sum,carry_out): 11
At time 60 ns::(a,b,carry_in): 001 (sum,carry_out): 10

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