8085 - Study Material PDF

An Introduction to Microprocessor
Architecture
using intel 8085 as a classic processor.
By:
Mayank Dev
Astt.. Prof. ET Deptt.
Astt Deptt.
(Advance microprocessros TEC- 504,
Prepared by: Mayank Dev) 1
Intel 8085 (Source:
Source: Intel Corp)
Fig-2:8085 Signals and I/O Pins
(Source:
Source: Intel Corp )
(Advance microprocessros TEC- 504, Prepared by: Mayank Dev) 4 4
Fig: Architecture-
Architecture-8085A
Source: Intel Corp (Advance microprocessros TEC- 504,
Prepared by: Mayank Dev) 5 5
The 8085 and Its Buses
 The 8085 is an 8-bit general purpose microprocessor that
can address 64K Byte of memory.
 It has 40 pins and uses +5V for power. It can run at a
maximum frequency of 3 MHz.
◦ The pins on the chip can be grouped into 6 groups:
 Address Bus.
 Data Bus.
 Control and Status Signals.
 Power supply and frequency.
 Externally Initiated Signals.
 Serial I/O ports.
(Advance microprocessros TEC- 504, Prepared by: Mayank Dev) 6
The Address and Data Bus Systems
 The address bus has 8 signal lines A8 – A15 which are
unidirectional.
 The other 8 address bits are multiplexed (time shared)
with the 8 data bits.
◦ So, the bits AD0 – AD7 are bi-directional and serve as
A0 – A7 and D0 – D7 at the same time.
 During the execution of the instruction, these lines
carry the address bits during the early part, then
during the late parts of the execution, they carry the
8 data bits.
◦ In order to separate the address from the data, we can
use a latch to save the value before the function of the
bits changes. (Advance microprocessros TEC- 504, Prepared by: Mayank Dev) 7
ALE used to demultiplex address/data bus
(Advance microprocessros
8 TEC- 504, Prepared by: Mayank Dev)
The Control and Status Signals
 There are 4 main control and status signals.These are:
 ALE: Address Latch Enable. This signal is a pulse that
become 1 when the AD0 – AD7 lines have an address
on them. It becomes 0 after that. This signal can be
used to enable a latch to save the address bits from
the AD lines.
 RD: Read.Active low.
 WR:Write.Active low.
 IO/M: This signal specifies whether the operation is a
memory operation (IO/M=0) or an I/O operation
(IO/M=1).
 S1 and S0 : Status signals to specify the kind of
operation being performed. Usually not used in small
systems. (Advance microprocessros TEC- 504,
Frequency Control Signals
 There are 3 important pins in the frequency control
group.
◦ X0 and X1 are the inputs from the crystal or clock
generating circuit.
 The frequency is internally divided by 2.
 So, to run the microprocessor at 3 MHz, a clock
running at 6 MHz should be connected to the X0
and X1 pins.
◦ CLK (OUT): An output clock pin to drive the clock of

the rest of the system.
 We will discuss the rest of the control signals as we get to
them.
A closer look at the 8085
Architecture
 Now, let’s look at some of its features with

more details.

The ALU
 In addition to the arithmetic & logic circuits, the ALU
includes an accumulator, which is a part of every
arithmetic & logic operation.
 Also, the ALU includes a temporary register used for

holding data temporarily during the execution of the
operation. This temporary register is not accessible by the
programmer.

Programming
model of 8085:
Accumulator (8-bit)
Flag Register (8-bit)
Register(s)
B(8-bit),C(8-bit),
D(8-bit),E(8-bit),
H(8-bit),L(8-bit)
B-C, D-E, H-L

can be used
collectively in the
Fig: Programming model – Intel 8085A source Intel Corp. form of register
pairs (16-bit)

The Flag register
◦ There is also a flag register whose bits are affected by the arithmetic & logic
operations.
 S-sign flag
 The sign flag is set if bit D7 of the accumulator is set after an arithmetic
or logic operation.
 Z-zero flag
 Set if the result of the ALU operation is 0. Otherwise is reset. This flag is
affected by operations on the accumulator as well as other registers.
(DCR B).
 AC-Auxiliary Carry
 This flag is set when a carry is generated from bit D3 and passed to D4 .
This flag is used only internally for BCD operations.
 P-Parity flag
 After an ALU operation, if the result has an even # of 1s, the p-flag is set.
Otherwise it is cleared. So, the flag can be used to indicate even parity.
 CY-carry flag
 This flag is set when a carry is generated from bit D7 after an unsigned
operation.
 OV-Overflow flag
 This flag is set when an overflow occurs after a signed operation.

 Now, Let us see how the different units
and bus systems stay connected:
Chip Selection
A15- A10 Circuit
8085
CS
A15-A8
ALE
A9- A0 1K Byte
AD7-AD0 Latch Memory
A7- A0 Chip
WR RD IO/M D7- D0
RD WR

More on the 8085 machine cycles
 The 8085 executes several types of instructions with

each requiring a different number of operations of
different types. However, the operations can be
grouped into a small set.
 The three main types are:
 Memory Read and Write.
 I/O Read and Write.
 Request Acknowledge.
 These can be further divided into various smaller
operations (machine cycles).
Opcode Fetch Machine Cycle
 The first step of executing any instruction is the Opcode fetch cycle.
◦ In this cycle, the microprocessor brings in the instruction’s Opcode
from memory.
 To differentiate this machine cycle from the very similar
“memory read” cycle, the control & status signals are set as
follows:
 IO/M=0, s0 and s1 are both 1.
◦ This machine cycle has four T-states.
 The 8085 uses the first 3 T-states to fetch the opcode.
 T4 is used to decode and execute it.
◦ It is also possible for an instruction to have 6 T-states in an opcode
fetch machine cycle.

Memory Read Machine Cycle
 The memory read machine cycle is exactly
the same as the opcode fetch except:
◦ It only has 3 T-states
◦ The s0 signal is set to 0 instead.

The Memory Read Machine Cycle
◦ To understand the memory read machine cycle, 2000H
let’s
3E
study the
execution of the following instruction:
2001H 32
 MVI A, 32
◦ In memory, this instruction looks like:
 The first byte 3EH represents the opcode for loading a
byte into the accumulator (MVI A), the second byte is the
data to be loaded.
◦ The 8085 needs to read these two bytes from memory before
it can execute the instruction.Therefore, it will need at least
two machine cycles.
 The first machine cycle is the opcode fetch discussed
earlier.
 The second machine cycle is the Memory Read Cycle.
Machine Cycles vs. Number of bytes
in the instruction
 Machine cycles and instruction length, do not have a direct
relationship.
◦ To illustrate, let’s look at the machine cycles needed to execute
the following instruction.
 STA 2065H 32H 2010H
 This is a 3-byte instruction requiring 4 machine 65H 2011H
cycles and 13 T-states. 20H 2012H
 The machine code will be stored

in memory as shown to the right
 This instruction requires the following 4 machine cycles:
 A ‘Opcode fetch’ to fetch the opcode (32H) from location 2010H, ‘decode’ it and
determine that 2 more bytes are needed (4 T-states).
 A ‘Memory read’ to read the low order byte of the address (65H) (3 T-states).
 A ‘Memory read’ to read the high order byte of the address (20H) (3 T-states).
 A ‘memory write’ to write the contents of the accumulator into the memory
location. (Advance microprocessros TEC- 504,
The Memory Write Operation
 In a memory write operation:
◦ The 8085 places the address (2065H) on the address
bus
◦ Identifies the operation as a ‘memory write’ (IO/M=0,
s1=0, s0=1).
◦ Places the contents of the accumulator on the data bus
and asserts the signal WR.
◦ During the last T-state, the contents of the data bus are
saved into the memory location.

Memory interfacing
 There needs to be a lot of interaction between the
microprocessor and the memory for the exchange of
information during program execution.
◦ Memory has its requirements on control signals and
their timing.
◦ The microprocessor has its requirements as well.
 The interfacing operation is simply the matching of these

requirements.

Memory structure & its requirements
Data Lines
ROM
RAM
Input Buffer WR
Address CS
Lines
Address CS
Lines
Output Buffer RD
Output Buffer RD
Date
Lines
Data Lines
 The way of interfacing the above two chips to the

microprocessor is the same.
◦ However, the ROM does not have a WR signal.
Interfacing Memory
◦ Accessing memory can be summarized into the following three steps:
 Select the chip.
 Identify the memory register.
 Enable the appropriate buffer.
◦ Translating this to microprocessor domain:

 The microprocessor places a 16-bit address on the address bus.
 Part of the address bus will select the chip and the other part
will go through the address decoder to select the register.
 The signals IO/M and RD combined indicate that a memory read
operation is in progress. The MEMR signal can be used to enable
the RD line on the memory chip.

Address decoding
 The result of ‘address decoding’ is the identification of
a register for a given address.
◦ A large part of the address bus is usually connected
directly to the address inputs of the memory chip.
◦ This portion is decoded internally within the chip.
◦ What concerns us is the other part that must be
decoded externally to select the chip.
◦ This can be done either using logic gates or a
decoder.

Putting all of the concepts together:

Back to the Overall Picture
Chip Selection
A15- A10 Circuit
8085
CS
A15-A8
ALE
A9- A0 1K Byte
AD7-AD0 Latch Memory
A7- A0 Chip
WR RD IO/M D7- D0
RD WR

Control and Status Signals.
(Advance microprocessros TEC-

28 504, Prepared by: Mayank Dev)
Interrupt Signals
 8085 μp has several interrupt signals as shown in the following
table.

Interrupt signals
 An interrupt is a hardware-initiated subroutine CALL.

 When interrupt pin is activated, an ISR will be called,
interrupting the program that is currently executing.
Pin Subroutine Location

TRAP 0024
RST 5.5 002C
RST 6.5 0034
RST 7.5 003C
INTR *
Note: * the address of the ISR is determined by the external hardware.
Interrupt signals
 INTR input is enabled when EI instruction is

executed.
 The status of the RST 7.5, RST 6.5 and RST
5.5 pins are determined by both EI
instruction and the condition of the mask
bits in the interrupt mask register.

Interrupt
Vectors

32Prepared by: Mayank Dev)
A circuit that causes an RST4 instruction (E7) to be
executed in response to INTR.
 When INTR is
asserted, 8085
response with
INTA pulse.
 During INTA
pulse, 8085
expect to see
an instruction
applied to its
data bus.

RESET signal
 Following are the two kind of RESET signals:

◦ RESET IN: an active low input signal, Program
Counter (PC) will be set to 0 and thus MPU will
reset.
◦ RESET OUT: an output reset signal to indicate that
the μp was reset (i.e. RESET IN=0). It also used to
reset external devices.

34 Prepared by: Mayank Dev)
RESET signal
(Advance microprocessros TEC-

35 504, Prepared by: Mayank Dev)
Direct Memory Access (DMA)
 DMA is an IO technique where external IO device requests
the use of the MPU buses.
 Allows external IO devices to gain high speed access to the
memory.
◦ Example of IO devices that use DMA: disk memory system.
 HOLD and HLDA are used for DMA.
 If HOLD=1, 8085 will place it address, data and control pins
at their high-impedance.
 A DMA acknowledgement is signaled by HLDA=1.

MPU Communication and Bus Timing
Figure 3: Moving data form memory to MPU using instruction MOV C, A

(code machine 4FH = 0100 1111) (Advance
37 microprocessros TEC- 504, Prepared by: Mayank Dev)
 The Fetch Execute Sequence :

1. The μp placed a 16 bit memory address from PC
(program counter) to address bus.
– Figure 4: at T1
– The high order address, 20H, is placed at A15 – A8.
– the low order address, 05H, is placed at AD7 - AD0 and ALE is
active high.
– Synchronously the IO/M is in active low condition to show it is a
memory operation.
2. At T2 the active low control signal, RD, is activated
so as to activate read operation; it is to indicate that
the MPU is in fetch mode operation.
Figure 4: 8085 timing diagram for Opcode fetch cycle for MOV C, A .
3. T3: The active low RD signal enabled the

byte instruction, 4FH, to be placed on AD7
– AD0 and transferred to the MPU. While
RD high, the data bus will be in high
impedance mode.
4. T4: The machine code, 4FH, will then be
decoded in instruction decoder. The
content of accumulator (A) will then copied
into C register at time state, T4.
40 Prepared by: Mayank Dev)
Addressing Modes – 8085 µP

Addressing Modes of 8085
The microprocessor has different ways of
specifying the data or operand for the
instruction.
The various formats of specifying operands
are called addressing modes
The 8085 has Five addressing modes:
1) Register Addressing mode: This type of
addressing mode specifies register or register
pair that contains data.
Example: ADD B, MOV B, A
2) Immediate Addressing Mode:
In this type of addressing mode, immediate

data byte is provided with the
instruction.
Example: MVI A, 47H, LXIH, 4100H etc.

Memory Addressing
One of the operands is a memory location
Depending on how address of memory
location is specified, memory addressing is
of two types
◦ Direct addressing
◦ Indirect addressing
3) Direct Addressing Mode: In this type of
addressing mode, the 16bit memory
address is directly provided with the
instruction.
Example: LDA C500H , STA 3050H etc
 4) Indirect Addressing Mode: In this type of
addressing mode, the 16bit memory address is
indirectly provided with the instruction using a
register pair
 Example: LXI H, 2050H
 (Load the contents of accumulator to the
memory location whose address is stored in
the register pair HL)
 MOV M, A ;copy register A to memory location whose
address is stored in register pair HL
H L
A 30H 20H 50H 2050H 30H
(Advance microprocessros TEC- 504, Prepared by: Mayank Dev)
45
5) IMPLICIT/Implied Addressing mode: In
this type of addressing mode, No operand
(register or data) is specified in the
instruction.
The operand is inborn to the instruction.
Example: CMA (Complement Accumulator) ,
(Advance microprocessros TEC- 504, Prepared by: Mayank Dev)

46
Counters & Time Delays
 Counters
 A loop counter is set up by loading a
register with a certain value.
 Then using the DCR (to decrement) and
INR (to increment) the contents of the
register are updated.
 A loop is set up with a conditional jump
 instruction that loops back or not
depending on whether the count has
reached the termination count.
Counters
• The operation of a loop counter can be
described using the following flowchart.
Initialize
Body of loop
Update the
count
No Is this
Final
Count
?
Yes

Sample ALP for implementing a
loop Using DCR instruction
MVI C, 15H
LOOP: DCR C
JNZ LOOP

Using a Register Pair as a Loop
Counter
• Using a single register, one can repeat a loop for
a maximum count of 255 times.
• It is possible to increase this count by using a

register pair for the loop counter instead of the
single register.
– A minor problem arises in how to test for the final
count since DCX and INX do not modify the flags.
– However, if the loop is looking for when the count
becomes zero, we can use a small trick by ORing the
two registers in the pair and then checking the zero
flag.

Using a Register Pair as a
Loop Counter
• The following is an example of a loop
set up with a register pair as the loop
counter.
LXI B,1000H
LOOP: DCX B
MOV A, C
ORA B
JNZ LOOP

Delays
• It was shown that each instruction passes through different
combinations of Fetch, Memory Read, and Memory Write
cycles.
• Knowing the combinations of cycles, one can calculate
how long such an instruction would require to complete.
– B for Number of Bytes
– M for Number of Machine Cycles
– T for Number of T-State.

Delays
• Knowing how many T-States an instruction requires, and
keeping in mind that a T-State is one clock cycle long, we
can calculate the time using the following formula:
Delay = No. of T-States / Frequency
• For example a “MVI” instruction uses 7 T-States. Therefore,

if the Microprocessor is running at 2 MHz, the instruction
would require 3.5 Seconds to complete.

Delay loops
• We can use a loop to produce a certain amount of time
delay in a program.
• The following is an example of a delay loop:
MVI C, FFH 7 T-States

LOOP: DCR C 4 T-States
JNZ LOOP 10/7 T-States
• The first instruction initializes the loop counter and is executed

only once requiring only 7 T-States.
• The following two instructions form a loop that requires 14
T-States to execute and is repeated 255 times until C
becomes 0.

Delay Loops (Contd
Contd…
…)
 We need to keep in mind though that in the last
iteration of the loop, the JNZ instruction will fail
and require only 7 T-States rather than the 10.
 Therefore, we must deduct 3 T-States from the
total delay to get an accurate delay calculation.
 To calculate the delay, we use the following
formula:
– Tdelay = total delay
 Tdelay = TO + TL
– TO = delay outside the loop
– TL = delay of the loop
• TO is the sum of all delays outside the

loop.
Delay Loops (Contd
Contd…
…)
• Using these formulas, we can calculate

the time delay for the previous example:
• TO = 7 T-States
– Delay of the MVI instruction
• TL = (14 X 255) - 3 = 3567 T-States

– 14 T-States for the 2 instructions repeated 255
times (FF16 = 25510) reduced by the 3 T-States for
the final JNZ.

Loop Counter
• Using a single register, one can repeat a loop for
a maximum count of 255 times.
• It is possible to increase this count by using a

register pair for the loop counter instead of the
single register.
– A minor problem arises in how to test for the final
count since DCX and INX do not modify the flags.
– However, if the loop is looking for when the count
becomes zero, we can use a small trick by ORing the
two registers in the pair and then checking the zero
flag.

Loop Counter
• The following is an example of a delay
loop set up with a register pair as the loop
counter.
LXI B, 1000H 10 T-States

LOOP: DCX B 6 T-States
MOV A, C 4 T-States
ORA B 4 T-States
JNZ LOOP 10/7 T-States

Loop Counter
• Using the same formula from before, we
can calculate:
• TO = 10 T-States
– The delay for the LXI instruction
• TL = (24 X 4096) - 3 = 98301 T- States

– 24 T-States for the 4 instructions in the loop
repeated 4096 times (100016 = 409610) reduced by
the 3 T- States for the JNZ in the last iteration.

Nested Initialize loop 2
Loops Body of loop 2
• Nested loops can be Initialize loop 1
easily setup in Body of loop 1
Assembly language Update the

by using two count1
registers for the two N

o
Is this
Final
loop counters and Count
?
updating the right Ye
Update thescount
register in the right 2
loop. N
o
Is this
Final
– In the figure, the body Count
?
of loop2 can be before Ye
s
or after loop1.

Nested Loops for Delay
• Instead (or in conjunction with) Register

Pairs, a nested loop structure can be used to
increase the total delay produced.
MVI B, 10H 7 T-States

LOOP2: MVI C, FFH 7 T-States
LOOP1: DCR C 4 T-States
JNZ LOOP1 10 T-States
DCR B 4 T-States
JNZ LOOP2 10 T-States

Delay Calculation of
Nested Loops
• The calculation remains the same
except that it the formula must be
applied recursively to each loop.
– Start with the inner loop, then plug that delay
in the calculation of the outer loop.
• Delay of inner loop

– TO1 = 7 T-States
• MVI C, FFH instruction
– TL1 = (255 X 14) - 3 = 3567 T-States
• 14 T-States for the DCR C and JNZ instructions repeated
255 times (FF16 = 25510) minus 3 for the final JNZ

Delay Calculation of
Nested Loops
• Delay of outer loop
– TO2 = 7 T-States
• MVI B, 10H instruction
– TL1 = (16 X (14 + 3574)) - 3 = 57405 T-States
• 14 T-States for the DCR B and JNZ instructions and 3574
T-States for loop1 repeated 16 times (1016 = 1610) minus 3 for
the final JNZ.
– TDelay = 7 + 57405 = 57412 T-States
• Total Delay
– TDelay = 57412 X 0.5 Sec = 28.706 mSec

Increasing the delay
• The delay can be further increased by
using register pairs for each of the loop
counters in the nested loops setup.
• It can also be increased by adding
dummy instructions (like NOP) in the
body of the loop.

Instruction Cycle
Each instruction in 8085 microprocessor consists of two part- operation code (opcode) and operand.
The opcode is a command such as ADD and the operand is an object to be operated on, such as a byte
or the content of a register.
Instruction Cycle: The time taken by the processor to complete the execution of an instruction. An
instruction cycle consists of one to six machine cycles.
Machine Cycle: The time required to complete one operation; accessing either the memory or I/O
device. A machine cycle consists of three to six T-states.
T-State: Time corresponding to one clock period. It is the basic unit to calculate execution of
instructions or programs in a processor.
To execute a program, 8085 performs various operations as:

• Opcode fetch (4 T-State)
• Operand fetch (3 T-State)
• Memory read/write (3 T-State)
• I/O read/write (3 T-State)
External communication functions are:

• Memory read/write
• I/O read/write
• Interrupt request acknowledge

Opcode Fetch Machine Cycle:
It is the first step in the execution of any instruction. The timing diagram of this cycle is given in
next Figure. The following points explain the various operations that take place and the signals
that are changed during the execution of opcode fetch machine cycle:
T1 clock cycle
i.The content of PC is placed in the address bus; AD0 - AD7 lines contains lower bit address and A8
– A15 contains higher bitaddress.
ii.IO/Msignal is low indicating that a memory location is being accessed. S1 and S0 also changed
to the levels as indicated in Table 1.
iii. ALE is high, indicates that multiplexed AD0 – AD7 act as lower order bus.
T2 clock cycle
i.Multiplexed address bus is now changed to data bus.
ii.The RD signal is made low by the processor. This signal makes the memory device load the data
bus with the contents of the location addressed by the processor.

T3 clock cycle
i.The opcode available on the data bus

is read by the processor and moved to
the instruction register.
ii.The RD signal is deactivated by

making it logic 1.
T4 clock cycle
i. The processor decode the instruction

in the instruction register and generate
the necessary control signals to execute
the instruction. Based on the instruction
further operations such as fetching,
writing into memory etc takesplace.
Fig. Opcode fetch machine cycle

Memory Read Machine Cycle:
The memory read cycle is executed by the processor to read a data byte from memory.
The machine cycle is exactly same to opcode fetch except: a) It has three T-states b) The
S0 signal is set to 0. The timing diagram of this cycle is given in the following Figure.

Memory Write Machine Cycle:
The memory write cycle is executed by the processor to write a data byte in a memory
location. The processor takes three T-states and WR signal is made low. The timing diagram
of this cycle is given in the following Figure.

Summary: Instruction Cycle
A processor have to execute the program. A program is just a set of instructions written in a sequence. Multiple machine cycles are
required to execute an instruction. The processor fetches an instruction from memory, Decodes it and then executes it. This fetching,
decoding and executing an instruction makes an instructiion cycle. Basically we have an equation for instruction cycle....
IC = FC + EC
where IC is instruction cycle, FC is fetch cycle and EC is the execution cycle. Every instruction will have a fetch machine cycle. Mainly
a processor have three machine cycles: (i) Fetch, (ii) Read, (iii) Write.
Fetch Machine cycle: Fetch machine cycle is made up of two parts, First read an instruction from memory, Second Decode the
instruction code. It requires 4 t-states in case of Intel 8085 MP.
T1: Address to memory with contents of PC register. T2: Initiate

the memory read process.
T3: Complete the memory read.
T4: Decode the instruction.
Some of the instruction that dont require any memory or I/O operation will be over in the same machine cycle, others may require
some read or write machine cycles.
Read Machine cycle: This requires 3 T-states. In this microprocessor will read the contents of memory or I/O device.
T1: Address to memory.

T2: Initiate the memory read process. T3: Complete
the memory read.
Write Machine Cycle: In this the microprocessor will write the contents on memory or I/O devce. It again requires 3 T-States.
T1: Address to memory.

T2: Initiate the memory write process. T3: Complete
the memory write.

Timing Diagram
Representation of Various Control signals generated during Execution of an Instruction
Following Buses and Control Signals must be shown in a Timing Diagram:
•Higher Order Address It is one of the best way to understand to

process of micro-processor/controller.
Bus.
With the help of timing diagram we can
•Lower Address/Data bus understand the working of any system, step
by step working of each instruction and its
•ALE execution, etc.
•RD It is the graphical representation of process in
steps with respect to time.
•WR The timing diagram represents the clock cycle
and duration, delay, content of address bus and
•IO/M data bus, type of operation ie. Read/write/status
signals.

Timing Diagram
Instruction
: A000h MOVA,B
Corresponding
Coding: A000h 78

Timing Diagram
Instruction:
A000h MOV
A,B
Corresponding
Coding: A000h 78
OFC
8085 Memory

Timing Diagram
Instruction: T1 T2 T3 T4
A000h MOV A0h
A,B A15- A8 (Higher OrderAddress bus)

00h 78h
Corresponding
Coding: A000h 78
ALE
RD
OFC WR
IO/M
8085 Memory
Op-code fetch
Cycle

Timing Diagram
Instruction:
A000h MVIA,45h
Corresponding Coding:
A000h 3E
A001h 45

Timing Diagram
Instruction:
A000h MVIA,45h
OFC
A000h 3E
MEMR
A001h 45
8085 Memory

Timing Diagram
T1 T2 T3 T4 T5 T6 T7
A0h A0h
A15- A8 (Higher OrderAddress bus)
00h 3Eh 01h 45h
DA7-DA0 (Lower order address/data
Instruction: Bus)
A000h MVI A,45h

ALE
Corresponding
Coding: RD
A000h 3E
A001h 45 WR
IO/M
Op-Code Fetch Memory Read

Cycle Cycle

Timing Diagram
Instruction:
A000h LXI A,FO45h
A000h 21
A001h 45
A002h F0

Timing Diagram
Instruction:
A000h LXI A,FO45h
Corresponding Coding: OFC
A000h 21 MEMR
MEMR
A001h 45
A002h F0 808 Memor
5 y

Timing Diagram
Op-Code Fetch Memory Read Memory Read Cycle

Cycle Cycle
T1 T2 T3 T4 T5 T6 T7 T8 T9 T10
A0h A0h A0h

A15- A8 (Higher OrderAddress bus)
00h 21h 01h 45h 02h F0h
DA7-DA0 (Lower order address/data
Bus)
ALE
RD
WR
IO/M

Timing Diagram
Instruction:
A000h MOVA,M
A000h 7E

Timing Diagram
Instruction:
A000h MOV
A,M OFC
Corresponding MEMR
Coding: A000h 7E
808 Memor
5 y

Timing Diagram
T1 T2 T3 T4 T5 T6
T
A0h 7
A15- A8 (Higher OrderAddress bus) Content Of Reg H
00h 7Eh LReg Content Of M

Instruction: DA7-DA0 (Lower order address/data
Bus)
A000h MOVA,M
Corresponding
ALE
Coding: A000h 7E
RD
WR
IO/M
Op-Code Fetch Memory Read

Cycle Cycle
Timing Diagram
Instruction:
A000h MOV M,A
Corresponding Coding: A000h 77

Timing Diagram
Instruction:
A000h MOV
M,A OFC
Corresponding MEMW
Coding: A000h 77
8085 Memory

Timing Diagram
T1 T2 T3 T4 T5 T6
T
A0h 7
A15- A8 (Higher OrderAddress bus) Content Of Reg H
00h 7Eh LReg Content of RegA

Instruction: DA7-DA0 (Lower order address/data
Bus)
A000h MOV M,A
Corresponding
ALE
Coding: A000h 77
RD
WR
IO/M
Op-Code Fetch Memory Write

Cycle Cycle

8085 - Study Material PDF

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An Introduction to Microprocessor

◦ CLK (OUT): An output clock pin to drive the clock of

 Now, let’s look at some of its features with

(Advance microprocessros TEC- 504,

 Also, the ALU includes a temporary register used for

(Advance microprocessros TEC- 504, Prepared by: Mayank Dev) 12

B-C, D-E, H-L

(Advance microprocessros TEC- 504,

(Advance microprocessros TEC- 504,

(Advance microprocessros TEC- 504, Prepared by: Mayank Dev) 16

 The 8085 executes several types of instructions with

(Advance microprocessros TEC- 504, Prepared by: Mayank Dev) 18

(Advance microprocessros TEC- 504, Prepared by: Mayank Dev) 19

 This is a 3-byte instruction requiring 4 machine 65H 2011H

cycles and 13 T-states. 20H 2012H

 The machine code will be stored

(Advance microprocessros TEC- 504, Prepared by: Mayank Dev) 22

 The interfacing operation is simply the matching of these

(Advance microprocessros TEC- 504,

 The way of interfacing the above two chips to the

◦ Translating this to microprocessor domain:

(Advance microprocessros TEC- 504,

(Advance microprocessros TEC- 504, Prepared by: Mayank Dev) 26

(Advance microprocessros TEC- 504, Prepared by: Mayank Dev) 27

(Advance microprocessros TEC-

(Advance microprocessros TEC- 504,

 An interrupt is a hardware-initiated subroutine CALL.

Pin Subroutine Location

 INTR input is enabled when EI instruction is

(Advance microprocessros TEC- 504, Prepared by: Mayank Dev) 31

(Advance microprocessros TEC- 504,

(Advance microprocessros TEC- 504, Prepared by: Mayank Dev) 33

 Following are the two kind of RESET signals:

(Advance microprocessros TEC- 504,

(Advance microprocessros TEC-

(Advance microprocessros TEC- 504, Prepared by: Mayank Dev) 36

Figure 3: Moving data form memory to MPU using instruction MOV C, A

 The Fetch Execute Sequence :

3. T3: The active low RD signal enabled the

(Advance microprocessros TEC- 504, Prepared by: Mayank Dev) 41

2) Immediate Addressing Mode:

In this type of addressing mode, immediate

Example: MVI A, 47H, LXIH, 4100H etc.

(Advance microprocessros TEC- 504, Prepared by: Mayank Dev) 43

The operand is inborn to the instruction.

Example: CMA (Complement Accumulator) ,

(Advance microprocessros TEC- 504, Prepared by: Mayank Dev)

(Advance microprocessros TEC- 504, Prepared by: Mayank Dev) 48

(Advance microprocessros TEC- 504, Prepared by: Mayank Dev) 49

• It is possible to increase this count by using a

(Advance microprocessros TEC- 504,

(Advance microprocessros TEC- 504, Prepared by: Mayank Dev) 51

(Advance microprocessros TEC- 504,

Delay = No. of T-States / Frequency

• For example a “MVI” instruction uses 7 T-States. Therefore,

(Advance microprocessros TEC- 504, Prepared by: Mayank Dev) 53

MVI C, FFH 7 T-States

• The first instruction initializes the loop counter and is executed

(Advance microprocessros TEC- 504, Prepared by: Mayank Dev) 54

• TO is the sum of all delays outside the

• Using these formulas, we can calculate

• TL = (14 X 255) - 3 = 3567 T-States

(Advance microprocessros TEC- 504,