Main 2

Chapter-1
Introduction
Power consumption is one of the top concerns of Very Large Scale

Integration (VLSI) circuit design, for which Complementary Metal Oxide
Semiconductor (CMOS) is the primary technology. Today’s focus on low
power is not only because of the recent growing demands of mobile
applications. Even before the mobile era, power consumption has been a
fundamental problem. To solve the power dissipation problem, many
researchers have proposed different ideas from the device level to the
architectural level and above. However, there is no universal way to avoid
tradeoffs between power, delay and area, and thus designers are required to
choose appropriate techniques that satisfy application and product needs.
Power consumption of CMOS consists of dynamic and static components.

Dynamic power is consumed when transistors are switching, and static
power is consumed regardless of transistor switching. Dynamic power
consumption was previously (at 0.18μ technology and above) the single
largest concern for low-power chip designers since dynamic power
accounted for 90% (Fig-1) or more of the total chip power. Therefore, many
previously proposed techniques, such as voltage and frequency scaling,
focused on dynamic power reduction. However, as the feature size shrinks,
e.g., to 0.09μ and 0.065μ, static power has become a great challenge for
current and future technologies. Based on the International Technology
Roadmap for Semiconductors (ITRS) report the sub-threshold leakage power
dissipation of a chip may exceed dynamic power dissipation at the 65nm
feature size.
SLEEPY STACK A LOW POWER VLSI DESIGN

One of the main reasons causing the leakage power increase is increase of
sub-threshold leakage power. When technology feature size scales down,
supply voltage and threshold voltage also scale down. Sub-threshold leakage
power increases exponentially as threshold voltage decreases. Furthermore,
the structure of the short channel device lowers the threshold voltage even
lower. In addition to sub-threshold leakage, another contributor to leakage
power is gate-oxide leakage power due to the tunneling current through the
gate-oxide insulator. Since gate-oxide thickness will be reduced as the
technology decreases, in nanoscale technology, gate-oxide leakage power
may be comparable to sub-threshold leakage power if not handled properly.
Figure 1
In this dissertation, we provide novel circuit structure named “sleepy stack”

as a new remedy for designers in terms of static power. The sleepy stack has
a novel structure that combines the advantages of two major prior
approaches, the sleep transistor technique and the forced stack technique.
However, unlike the sleep transistor technique, the sleepy stack technique
retains the original state; furthermore, unlike the forced stack technique, the
sleepy stack technique can utilize high-Vth to achieve more than two orders

of magnitude leakage power reduction compared to the forced stack.
Unfortunately, the sleepy stack technique comes with delay and area
overheads. Therefore, the sleepy stack technique provides new Pareto points
to designers who require ultra-low leakage power consumption and are
willing to pay some area and delay cost. In this thesis, we explore the basic
structure of the sleepy stack. Also, we study various sleepy stack circuits
including generic logic circuits and memory.
Purpose of Low Power VLSI Design
Digital integrated circuits are found everywhere in modern life and many of
them are embedded in mobile devices where limited power resource is
available (e.g. mobile phones, watches, mobile computers, personal
assistants, ...). To permit an usable battery runtime, such devices must be
designed to consume the lowest possible power. Furthermore, low power is
also very important for non-portable devices, too. Indeed,a reduced power
consumption can highly decrease the packaging costs and highly increase
the circuit reliability, which is tightly related to the circuit working
temperature.

Table 1
Table-1 shows the technology scaling of the components and the estimated
power consumption. The number of transistors per circuit will continue to
increase as predicted by Moore’s law, whereas the transistor sizes will
continue to shrink. Despite a decreased supply voltage, the total power will
continue to increase.
The reduction of the supply voltage is dictated by the need to maintain

the electric field constant on the ever shrinking gate oxide. Unfortunately, to
keep transistor speed (proportional to the transistor “on” current)
acceptable, the threshold voltage must be reduced too, which results in an
exponential increase of the “off” transistor current, i.e. the current
constantly flowing through the transistor even when it should be “non-
conducting”.

Chapter-2
Sources of Dissipation in CMOS Transistors
Circuits designed before 1980 were mainly implemented in NMOS

technology. Such devices presented the major inconvenient of a large
current constantly flowing through the circuit even when no transitions
occurred. To solve this issue, CMOS (Complementary Metal Oxide
Semiconductor) technology was introduced. This seemed to be an ultimate
solution for avoiding static power consumption. Thus, the only remaining
sources of dissipation were the switched capacitance power (due to the
charging/discharging of capacitance nodes) and the shortcut power (due to
the current flowing from supply voltage (V dd) to the ground (V ss) when
switching), both only present during node transitions.

Unfortunately, the constant dimension reduction driven by Moore’s law and
the corresponding reduction of the supply voltage (needed to maintain the
electric field on the transistor gates constant) yielded a huge increase of the
static power consumption, taking it back to a non negligible source of
consumption. The reasons why this occurred are mainly two. The former is
the reduction of the threshold voltage imposed by the Vdd reduction in order
to maintain the speed acceptable, and the latter is the new electrical effects
originated by the reduction of the transistors geometrical dimensions, known
under the name of short channel effects.
Starting from 0.13μm technology node (i.e. a technology with a minimal

transistor size of 0.13μm), the static power consumption cannot be
neglected anymore and must be added to the dynamic power to correctly
estimate the total power consumption.
2.1 Dynamic consumption

Dynamic consumption is considered as the dissipation that occurs only when
the circuit is active (i.e. internal circuit nodes are switching).
Two distinct contributions exist. The first is the so called switching energy
and corresponds to the energy required to charge (and discharge) the node
capacitances during transitions. The second is the energy dissipated during
transitions due to the conductive path existing, for a short period of time,
between the supply voltage and the ground. This effect is known as shortcut
or short-circuit.
2.1.1 Switching energy

The energy consumed to charge (and then discharge) a capacitance C to a
voltage V is given by
This type of consumption can easily be reduced from a technology

node to the other by reducing capacitance C and supply voltage V . Both
reductions are effectively obtained in a new scaled technology; in fact, the
supply voltage has to be reduced in order to avoid high electric fields on the
transistor gates and the reduction of the transistor physical dimensions
automatically results in reduced capacitances. This type of dissipation was
the primary source of consumption in active mode for circuit implemented in
technology larger than 0.13μm
2.1.2 Shortcut energy
The second source of dynamic consumption arises from shortcut paths.

Consider a CMOS inverter (Fig. 2.1) with the input node at zero. In this
condition the NMOS transistor is off and the PMOS transistor is conducting.
Now, if the input node potential increases from 0 to Vdd, the NMOS will start
to conduct for Vin > Vth_nmos while the PMOS is still on, which result in a current
flowing from Vdd to Vss. Then, when V in acquires the potential Vdd − Vth_pmos,
the PMOS stops to conduct and the shortcut current vanishes too. Clearly,
this type of conduction only exists if the supply voltage Vdd is greater than
the sum of the NMOS/PMOS sub-threshold voltages (Vth nmos + Vth_pmos).

With V dd the supply voltage, Vth_nmos and Vth pmos the threshold voltages for
NMOS and PMOS, respectively and _ is the transition time, i.e. the period of
time needed to sweep the input voltage from 0 to Vdd.
Figure-2.1
For well designed cells (i.e. with balanced rising and falling edges), the
shortcut energy is in general much smaller than the switching energy.
Moreover, for very low supply voltage designs, the value Vdd − Vth nmos − Vth
pmos can be very small. Additionally, the case where Vdd < Vth nmos + Vth pmos will
not present shortcut dissipation at all. For these reasons, in modern designs,
shortcut power is often not considered or is simply included in the switching
consumption by increasing the switching capacitance to an equivalent
capacitance which incorporates the shortcut effect.
2.2 Static consumption

Contrary to the dynamic consumption, static power is defined as the
consumption originated from currents constantly flowing from V dd to
ground. This means that even when the circuit is in idle mode (no transition
occurs), power continues to be dissipated. For long channel transistors with
high threshold voltage, this type of dissipation was completely negligible.
Unfortunately, present and future technologies will suffer from high static
power, which could even exceed the dynamic contribution in active mode.
Hence, it is of uttermost importance to consider this type of dissipation in
present and future design methodologies. To understand the main sources of
static dissipation, let us look at the structure of a transistor in CMOS
technology. Fig. 2.2 shows 5 different leakage mechanisms that can be
observed in a CMOS transistor
.
These mechanisms are:
(a) Sub-threshold current;
(b) Gate leakage current;
(c) Reverse-bias p-n junction current and band to band tunneling;
(d) Gate-Induced Drain Leakage (GIDL) current;
(e) Punchthrough current.

Figure-2.2
2.2.1 Sub-threshold current
The most important leakage current is the sub-threshold one originated by

the diffusion of minority carriers in a non conducting transistor (Vgate − Vsource
< Vth). Under this condition, the transistor is operating in weak inversion. The
potential applied between drain and source creates a flow of the minority
carriers on the surface of the channel. The equation describing this
mechanism is
With Io the reference static current, V th the threshold voltage, n the sub-
threshold slope, Ut (=kbT/q) the thermal potential and Vds the Drain-Source
voltage. The sbove equation shows an exponential dependency of the sub-
threshold current on the threshold voltage Vth. This is the reason why the low
Vth characterizing recent technologies leads to large sub-threshold currents.
10

Moreover, in typical digital designs, Vds is much larger than nUt, which leads
to the approximation
The value of Vth is not fixed for a given technology; in fact, it can be
modulated through different effects like:
• Drain Induced Barrier Lowering (DIBL) effect: In short channel

transistors, the potential on the drain contact modulates the threshold
voltage by lowering the energy barrier at the surface of the channel. A
schematic representation of this effect is illustrated in Fig. 2.3. For long
channel transistors (L1), the potential in the channel is independent on the
drain voltage (V d1 and V d2 show the same potential profile), whereas for
short channels (L2), an increase of the drain voltage also reduces the barrier
energy level in the channel, which can be modeled by a reduction of the
threshold voltage. Ideally, the DIBL effect doesn’t change the sub-threshold
slope n. DIBL can be reduced by using high surface and channel doping and
shallow source/drain junction depths.
11

Figure-2.3
• Body effect: The body effect appears when a potential difference is

present between body (bulk) and source. This happens because bulk and
source operate as a reverse biased p-n junction. By increasing the body
potential in a NMOS or by decreasing it in a PMOS (forward biasing), the
junction depletion reduces the channel potential and the sub-threshold
leakage current increases. Similarly, a reduction of the body potential (lower
than Vss for NMOS and higher than Vdd for PMOS, called reverse biasing)
increases the channel potential, leading to a reduced sub-threshold leakage.
It should be noted that for body-source potentials (Vbs) higher than 0.5 V the
p-n junction starts to conduct as forward biased diode, drawing very large
current, which has to be avoided at all costs. Body effect is more pronounced
for high bulk doping levels and decreases as substrate reverse bias
increases. At V bs = 0, the body effect sensitivity is equal to (n − 1), with n
the sub-threshold slope. The body effect can be modeled as a modification of
the threshold voltage Vth.
12

By considering the effects of DIBL and body bias, the threshold voltage can
be expressed by
With Vth0 the reference threshold voltage for Vds = Vbs = 0, η (eta) the DIBL
effect coefficient and γ (gamma, equal to n-1 for Vbs = 0) the linearized body
effect coefficient.
By considering the described effects, the sub-threshold current can be

expressed
as:
2.2.2 Gate leakage current
The transistor gate potential influences the charges in the channel by

electrostatic effect: an accumulation of holes in the gate produces an
accumulation of electrons at the surface of the channel, obtaining exactly
the behavior of a capacitance with gate and channel as poles and the silicon
oxide as dielectric. Ideally, no current should occur across the gate oxide,
but practically some electrons are able to pass through the oxide, generating
a gate current. The mechanisms behind this effect can be divided into two
categories: oxide tunneling and hot carrier injection.
Oxide tunneling current
13

Tunneling through the gate oxide is primarily due to direct tunneling across
very thin oxide layers (less than 3-4 nm). An efficient way to reduce this
source of leakage in future technologies is to use other insulators with a
higher dielectric constant, resulting in a higher effective oxide thickness (i.e.
the thickness of the silicon oxide that would show the same behavior as this
high dielectric insulator). In this way, it should be possible to maintain the
gate tunneling current to acceptable (i.e. negligible) levels.
Hot carrier injection
Due to the high electric field in the interface Si−SiO2 (channel-oxide),

electrons and holes can gain sufficient energy to enter into the gate oxide.
Because the effective mass of the electrons, as well as their barrier height, is
lower than the corresponding ones for holes, electrons injection is much
more probable. A reduction of the supply voltage will reduce the electric field
on the gate, also reducing in this way the hot carrier injection.
2.2.3 Reverse bias p-n junction leakage and band to band

Tunneling
In the normal transistor operation mode, the drain/source to well junctions

are reverse biased. Under this condition, a small current exists due to the
drift of carriers originated by the thermal electron-hole generation.
Nevertheless, in advanced short channel MOS (where heavily doped and
shallow junctions are used), such effects are masked by the dominating
band-to-band tunneling.
Band to band tunneling happens on junctions with high electric field (> 10 6
V/cm) and is due to the direct tunneling of electrons from the band of
valence of the p region to the band of conduction in the n region.
14

2.2.4 Gate-Induced Drain Leakage (GIDL)
In the overlapping zone between gate and drain, a high electric field can
exist, leading to the generation of currents from drain to substrate. Consider
a NMOS transistor; when a low gate potential is applied (V g near zero volts
or below), holes accumulate at the surface and create a region which is more
heavily p doped than the substrate. If this happens while the drain is
connected to a high potential (let say V dd), the depletion layer near the
drain becomes narrower. If this is important enough to invert the polarity of
the n+ drain region under the gate, high field effects like band-to-band
tunneling, avalanche multiplication and traps-assisted tunneling take place.
As a consequence minority carriers are emitted in the drain region
underneath the gate and pushed to the substrate due to the vertical electric
field. All these effects are increased by a reduction of the gate oxide
thickness.
This type of leakage is especially important for “relatively high” supply

voltage circuits (V dd > 1.1 V). Low power digital designs, with very low
supply voltage (i.e. V dd around 0.5V), are not heavily concerned by this type
of leakage.
The equivalent of the GIDL effect for a “high” source potential is called GISL
(Gate-Induced Source Leakage). This effect is generally not considered
because, in normal transistor operations, the source will show a low or zero
potential compared to the bulk.
2.2.5 Punchthrough
15

With the physical dimensions reduction, the depletion layers of source and
drain become nearer and nearer until they touch each other, originating
punchthourgh currents.
In submicron MOS transistors, implants at the substrate surface aiming Vth

adjustment are used, forcing the punchthrough to occur deeper in the
substrate. The size of the depletions directly depends on the V ds potential.
Hence, low voltage design can prevent the generation of punchthrough
currents
2.3 Switching power and delay tradeoffs
CMOS power consumption of a particular CMOS gate under consideration can

be represented by the following switching power (Pswitching) equation for 0.18μ
and above
where CL, Vdd, and f denote the load capacitance of a CMOS gate, the supply
voltage and the clock frequency, respectively. Notation pt denotes the
switching ratio of a gate output; this switching ratio represents the number
of times the particular gate’s output changes from Gnd to Vdd per second –
please note that when output capacitance discharges from Vdd to Gnd,
switching power is not consumed because power from Vdd is not used (e.g.,
discharging to Gnd does not consume battery power). The switching ratio
varies according to the input vectors and benchmark programs, and thus an
average value of each benchmark may be used as a switching ratio.
16

The above equation shows that lowering Vdd decreases CMOS switching
power consumption quadratically. However, this power reduction
unfortunately entails an increase in the gate delay in a CMOS circuit as
shown in following approximated equation:
where Td, Vth, and α denote the gate delay in a CMOS circuit, the threshold
voltage and velocity saturation index of a transistor, respectively.
In this project we estimate leakage power consumption by measuring static

power when transistors are not switching. Furthermore, we estimate active
power consumption by measuring power when transistors are switching. This
active power include dynamic power consumption and leakage power
consumption.
Chapter-3
17

Leakage Reduction Techniques
Modern DSM technologies are suffering from a dramatic increase in
leakage current. Constant scaling dictates that the supply voltage has
to be reduced when downsizing the technology feature size. Low
threshold voltage devices are used to maintain the required current
drive and to satisfy performance specifications. Low threshold devices
have caused a dramatic increase in leakage current. A direct and live
solution for that is to utilize low threshold devices in the critical path
and high threshold devices elsewhere. The threshold voltage can be
controlled utilizing the well bias of the device in the so called Variable
Threshold CMOS (VTCMOS)
Dual threshold technology is another way to address the increasing active

and leakage power problem. The technology is a CMOS process with two
types of devices, low threshold and high threshold device. Performance is
enhanced by placing the low threshold devices on the critical path to
increase performance and place the high threshold devices on the non-
critical paths to decrease leakage. Several mechanisms have been
developed to optimize the process of placing the low/high threshold devices
on the gate level or on the transistor level . This method is referred to as
Multi-Threshold CMOS (MTCMOS).
Multi-Threshold CMOS (MTCMOS)
The leakage current can be dynamically controlled using multi-

threshold devices as was proposed and is shown in Figure 3.1 In this
scheme, low VTH logic is used for faster evaluation while a high VTH
NMOS device, Sleep device, is used to disconnect the logic from the
18

supply during standby. A Sleep control signal is line is much larger
than that of the real ground resulting in a ground bounce. This bounce
adversely affects both noise margin and delay. A methodology for
properly sizing the Sleep device to minimize the delay based on mutual
exclusive used to turn the high VTH NMOS device ON and OFF
depending upon the mode of operation. A clear drawback of this
technique is the impact of the Sleep device sizing on performance.
Increasing the Sleep transistor size more than necessary would add to
the circuit capacitance and power dissipation while sizing it too small
would result in a supply current limitation and speed degradation.
Another potential problem in the MTCMOS scheme is the bounce of
virtual ground line bouncing. In fact, the capacitance of the virtual
ground discharge patterns was proposed than zero The advantage of
low leakage during standby mode is stressed by back biasing the sleep
transistors to more than VDD [26] [27]. By reverse biasing the body of
the sleep transistor, threshold voltage is increased and leakage current
is decreased. Therefore, a low threshold voltage device can be used
without an increase in leakage current during standby. The low
threshold sleep device limits voltage drop during the active mode and
provides more current drive. Improving the current drive during the
active mode is highly desirable in order to achieve more speed. By
increasing the voltage swing of the gate of the sleep transistor, the
gate-to-source voltage becomes greater and boosts the current drive
Variable-Threshold CMOS (VTCMOS)
19

VTCMOS technique uses all low threshold devices . However, the
threshold voltage is controlled using the well bias of the devices in a
triple-well CMOS process. During the ON state, the well bias is VDD +
0:5V for the p-well and ¡0:5V for the n-well allowing for low threshold
voltage realization as shown in Figure 3.1(b). During standby, the
source- body junction is strongly reverse biased to increase the
threshold voltage and to reduce leakage current. The p-well bias is set
to VDD +3:3V while the n-well bias is set to ¡3:3V .Consequently, VTH
is adjusted to be 0.77V during the active mode and greater than 0.5V
during the standby mode. One potential problem with this approach is
that the threshold voltage varies as the square root of the body-source
voltages. Therefore, the body-source voltage has to significantly
increase to change the threshold voltage to a relatively higher value.
VTCMOS is even more efficient in leakage current suppression for
series connected transistors due to the increased body- VTCMOS
scheme depends on a high body-effect to control the threshold
voltage. With technology scaling, the body-effect is reduced from one
technology generation to the next. The body effect is primarily reduced
due to the short channel effect. Techniques such as well doping can be
applied to enhance the short channel effect. However, well doping
causes the doping levels in the vicinity of source-body and drain-body
junctions to increase signifcantly. As the doping limit approaches the
tunneling limit, the junction current increases exponentially, and
becomes the dominant leakage component. Therefore, body- effect is
reduced and limits the effectiveness of the VTCMOS scheme SOI
technology can also be used in the implementation of VTCMOS. In a
silicon- on-insulator-with-active-substrate (SOIAS) was used to
20

dynamically control the threshold voltage. The dynamic threshold MOS
(DTMOS) scheme is another mean to provide low threshold during the
ON state and high threshold during the OFF state A summary of the
different features of the MTCMOS and VTCMOS techniques is presented
in Table Moving towards smaller feature size, the MTCMOS technique
seems to be a better choice. However, VTCMOS is more effective in
reducing process variations which are increasing with technology
scaling. Therefore, the choice between MTCMOS and VTCMOS is
application dependent.
Figure 3.1
Static Power Reduction VLSI Research

In this section, we discuss previous low-power techniques that primarily
target reducing leakage power consumption of CMOS circuits. Techniques for
leakage power reduction can be grouped into two categories: (i) state-saving
techniques where circuit state (present value) is retained and (ii) state-
destructive techniques where the current Boolean output value of the circuit
21

might be lost A state-saving technique has an advantage over a state-
destructive technique in that with a state-saving technique the circuitry can
immediately resume operation at a point much later in time without having
to somehow regenerate state.
3.1 “SLEEP” Technique

State-destructive techniques cut off transistor (pull-up or pull-down or both)
networks from supply voltage or ground using sleep transistors (Fig-3.2). This
technique is Multi-Threshold- Voltage CMOS (MTCMOS), which adds high-Vth
sleep transistors between pull-up networks and Vdd and between pull-down
networks and ground while logic circuits use low-Vth transistors in order to
maintain fast logic switching speeds. By isolating the logic networks using
sleep transistors, the sleep transistor technique dramatically reduces
leakage power during sleep mode. However, the additional sleep
Figure 3.2
transistors increase area and delay. Furthermore, the pull-up and pull-down
networks will have floating values and thus will lose state during sleep mode.
22

These floating values significantly impact the wakeup time and energy of the
sleep technique due to the requirement to recharge transistors which lost
state during sleep
3.2 Forced Stack Technique
For the stack approach, every transistor in the base case network is
duplicated with both original and duplicate bearing half the original transistor
width (Fig 3.3). Duplicated transistors cause a slight reverse bias between
the gate and source when both transistors are turned off. Because sub
threshold current is exponentially dependent on gate bias, a substantial
current reduction is obtained. Since all transistors are placed in-between two
parallel rows of continuous VDD and GND, stack approach design forces an
increase in row length because of an increase in the number of transistors
and decrease in transistor width.
Figure-3.3
3.3 “SLEEPY STACK” Technique
23

The sleepy stack structure has a combined structure of the forced stack and
the sleep transistor techniques. The sleepy stack technique has a structure
merging the forced stack technique and the sleep transistor technique. Fig
3.3 shows a sleepy stack inverter. The sleepy stack technique divides
existing transistors into two transistors each typically with the same width
W1 half the size of the original single transistor’s width W0 (i.e., W1 = W0/2),
thus maintaining equivalent input capacitance. The sleepy stack inverter in
uses W/L = 3 for the pull-up transistors and W/L = 1.5 for the pull-down
transistors, while a conventional inverter with the same input capacitance
would use W/L = 6 for the pull-up
Figure-3.3
transistor and W/L = 3 for the pull-down transistor (assuming μn = 2μp). Then
sleep transistors are added in parallel to one of the transistors in each set of
two stacked transistors. We use half size transistor width of the original
transistor (i.e., we use W0/2) for the sleep transistor width of the sleepy
stack. Although we use W0/2 for the width of the sleep transistor, changing
24

the sleep transistor width may provide additional tradeoffs between delay,
power and area.
3.4 Sleepy stack operation

Now we explain how the sleepy stack works during active mode and during
sleep mode. Also, we explain leakage power saving using the sleepy stack
structure. The sleep transistors of the sleepy stack operate similar to the
sleep transistors used in the sleep transistor technique in which sleep
transistors are turned on during active mode and turned off during sleep
mode. Figure 3.3 depicts the sleepy stack operation using a sleepy stack
inverter. During active mode (Fig 3.3(a)) S = 0 and S` = 1 are asserted, and
thus all sleep transistors are turned on. This sleepy stack structure can
potentially reduce circuit delay in two ways. First, since the sleep transistors
are always on during active mode, the sleepy stack structure achieves faster
switching time than the forced stack structure; specifically, in Figure 3.3(a),
at each sleep transistor drain, the voltage value connected to the sleep
transistor source is always ready and available at the sleep transistor drain,
and thus current flow is immediately available to the low-Vth transistors
connected to the gate output regardless of the status of each transistor in
parallel to the sleep transistors. Furthermore, we can use high-Vth transistors
(which are slow but 1000X or so less leaky), for the sleep transistors and the
transistors parallel to the sleep transistors without incurring large delay
increase. During sleep mode (Fig-3.3(b)), S = 1 and S` = 0 are asserted, and
so both of the sleep transistors are turned off. Although the sleep transistors
are turned off, the sleepy stack structure maintains exact logic state. The
leakage reduction of the sleepy stack structure occurs in two ways. First,
leakage power is suppressed by high-Vth transistors, which are applied to the
sleep transistors and the transistors parallel to the sleep transistors. Second,
25

two stacked and turned off transistors induce the stack effect, which also
suppresses leakage power consumption. By combining these two effects, the
sleepy stack structure achieves ultra-low leakage power consumption during
sleep mode while retaining exact logic state. The price for this, however, is
increased area.
Chapter-4
Experimental Methodology
26

We will draw the layouts using Microwind tools and calculate the area from it
Using the Tanner tools we will drae the schematics and then we will extract
the Netlist from it
Then by SPICE tools and the required technology files we will simulate the
netlist
From the output waveforms we can observe the delay and power
1-Bit Full adder Logic Diagram
27

Truth Table
A B C Cout Sum
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
Logic Equation
1-Bit Full Adder Schematic
28

Tanner Schematic
Sleepy Stack Approach 1 Bit Full Adder
29

30

Layout Base Case (90nm)
31

Layout Sleepy Stack (90nm)
32

Layout Base Case (120nm)
33

Layout Sleepy Stack (120nm)
34

Chapter 5
35

Output Waveforms
Base Case (90nm Layout)
Sleepy Stack Case (90nm Layout)
Base Case (120nm Layout)
36

Sleepy Stack (120nm Layout)
Base Case
37

A=0 B=0 C=0
Power Results
vdd gnd from time 0 to 1e-007
Average power consumed -> 2.178864e-002 watts
Max power 4.357727e-009 at time 0
Min power 4.357727e-009 at time 0
Sleepy Stack
38

A=0 B=0 C=0
Power Results
Base Case
39

A=0 B=0 C=1
Power Results
Sleepy Stack
40

A=0 B=0 C=1
Power Results
Base Case
41

A=0 B=1 C=0
Power Results
Sleepy Stack
42

A=0 B=1 C=0
Power Results
Base Case
43

A=0 B=1 C=1
Power Results
Sleepy Stack
44

A=0 B=1 C=1
Power Results
Base Case
45

A=1 B=0 C=0
Power Results
Sleepy Stack
A=1 B=0 C=0
46

Power Results
Base Case
A=1 B=0 C=1
47

Power Results
Sleepy Stack
A=1 B=0 C=1
48

Power Results
Base Case
A=1 B=1 C=0
49

Power Results
Sleepy Stack
A=1 B=1 C=0
50

Power Results
Base Case
A=1 B=1 C=1
51

Power Results
Sleepy Stack
A=1 B=1 C=1
52

Power Results
Dynamic Waveforms
Base Case
53

Sleepy Stack Dynamic
54

RESULT
Table for 180nm Spice Program
55

Static Power (Watts) at
a b c 180nm
Single Dual
Base Vth Vth
2.18E- 1.12E- 1.09E-
0 0 0 02 02 02
3.78E- 1.95E- 1.94E-
Graph 0 0 1 02 02 02
4.00E- 2.07E- 2.08E-
0 1 0 02 02 02
5.35E- 1.95E- 1.95E-
0 1 1 02 02 02
4.47E- 2.00E- 2.00E-
1 0 0 02 02 02
3.47E- 1.77E- 1.77E-
1 0 1 02 02 02
4.61E- 4.19E- 7.21E-
1 1 0 02 02 02
5.18E- 2.63E- 2.68E-
1 1 1 02 02 02
56

Conclusion
Hence by using the sleepy stack method we can reduce

the leakage power drastically which will help in better
utilization of the power. This technique is useful for the
systems in which delay and area is not an important
criteria when compared to the power requirements of the
system.
57

Bibliography
[1] J. C. Park and V. J. Mooney, “Pareto Points in SRAM Design Using the Sleepy Stack
Approach,” IFIP International Conference on Very Large Scale Integration (IFIP VLSI-
SOC’05), October 2005.
[2] J. C. Park, V. J. Mooney and P. Pfeiffenberger, “Sleepy Stack Reduction in Leakage

Power,” Proceedings of the International Workshop on Power and Timing Modeling,
Optimization and Simulation (PATMOS’04), pp.148-158, September 2004.
[3] P. Pfeiffenberger, J. C. Park and V. J. Mooney, “Some Layouts Using the Sleepy Stack
Approach,” Technical Report GIT-CC-04-05, Georgia Institute of Technology, June 2004,
[Online] Available http://www.cc.gatech.edu/tech reports/index.04.html.
58

[4] A. Balasundaram, A. Pereira, J. C. Park and V. J. Mooney, “Golay and Wavelet Error
Control Codes in VLSI,” Proceedings of the Asia and South Pacific Design Automation
Conference (ASPDAC’04), pp. 563-564, January 2004.
[5] A. Balasundaram, A. Pereira, J. C. Park and V. J. Mooney, “Golay and Wavelet Error
Control Codes in VLSI,” Technical Report GIT-CC-03-33, Georgia Institute of Technology,
December 2003,
[Online] Available http://www.cc.gatech.edu/tech reports/index.03.html
[6] J. C. Park, V. J. Mooney and S. K. Srinivasan, “Combining Data Remapping and

Voltage/Frequency Scaling of Second Level Memory for Energy Reduction in Embedded
Systems,”Microelectronics Journal, 34(11), pp. 1019-1024, November 2003.
[7] J. C. Park, V. J. Mooney, K. Palem and K. W. Choi, “Energy Minimization of a Pipelined

Processor using a Low Voltage Pipelined Cache,” Conference Record of the 36th Asilomar
Conference on Signals, Systems and Computers (ASILOMAR’02), pp. 67-73, November 2002.
[8] K. Puttaswamy, K.W. Choi, J. C. Park, V. J.Mooney, A. Chatterjee and P. Ellervee,
“System Level Power-Performance Trade-Offs in Embedded Systems Using Voltage and

Frequency Scaling of Off-Chip Buses and Memory,” Proceedings of the nternational
Symposium on System Synthesis (ISSS’02), pp. 225-230, October 2002.
[9] S. K. Srinivasan, J. C. Park and V. J. Mooney, “‘Combining Data Remapping and

Voltage/Frequency Scaling of Second Level Memory for Energy Reduction in Embedded
Systems,” Proceedings of the International Workshop on Embedded System Codesign
(ESCODES’02), pp. 57-62, September 2002.
[10] K. Puttaswamy, L. N. Chakrapani, K. W. Choi, Y. S. Dhillon, U. Diril, P. Korkmaz, K. K.

Lee, J. C. Park, A. Chatterjee, P. Ellervee, V. J. Mooney, K. Palem and W. F. Wong, “Power-
Performance Trade-Offs in Second Level Memory Used by an ARM-Like RISC Architecture,”
59

in the book Power Aware Computing, edited by RamiMelhem, University of Pittsburgh, PA,
USA and Robert Graybill, DARPA/ITO, Arlington, VA, USA, published by Kluwer
Academic/Plenum Publishers, pp. 211- 224, May 2002.
Appendix-A
Netlist Programs
Base Case (180nm)
* SPICE netlist written by S-Edit Win32 7.00
* Written on Mar 20, 2010 at 16:05:29
* Waveform probing commands
.probe
.options probefilename="BaseAdder180.dat"
60

+ probesdbfile="D:\Documents and Settings\Gamers\My
Documents\BaseAdder180.sdb"
+ probetopmodule="Module0"
* Main circuit: Module0
M1 N7 a N2 Gnd NMOS L=.18u W=.54u
M2 N2 b Gnd Gnd NMOS L=.18u W=.54u
M3 N10 c N7 Gnd NMOS L=.18u W=.54u
M4 Ca N7 Gnd Gnd NMOS L=.18u W=.54u
M5 N4 N7 N20 Gnd NMOS L=.18u W=.54u
M6 Gnd b N10 Gnd NMOS L=.18u W=.54u
M7 N20 a Gnd Gnd NMOS L=.18u W=.54u
M9 N20 c Gnd Gnd NMOS L=.18u W=.54u
M12 N5 b N8 Gnd NMOS L=.18u W=.81u
M14 Sum N4 Gnd Gnd NMOS L=.18u W=.81u
M15 N6 a Vdd Vdd PMOS L=.18u W=1.62u
M16 Vdd b N6 Vdd PMOS L=.18u W=1.62u
M17 N7 c N6 Vdd PMOS L=.18u W=.81u
M18 N6 a N1 Vdd PMOS L=.18u W=1.62u
61

M19 N1 b N7 Vdd PMOS L=.18u W=1.62u
M20 Ca N7 Vdd Vdd PMOS L=.18u W=1.08u
M21 N4 N7 N16 Vdd PMOS L=.18u W=.72u
M23 N16 b Vdd Vdd PMOS L=.18u W=2.16u
M24 N16 c Vdd Vdd PMOS L=.18u W=2.16u
M25 Vdd a N11 Vdd PMOS L=.18u W=2.16u
M26 N9 c N4 Vdd PMOS L=.18u W=2.16u
M27 Sum N4 Vdd Vdd PMOS L=.18u W=1.08u
V29 a Gnd bit({00001111} pw=100n on=5.0 off=0.0 rt=1n ft=1n

delay=0 lt=10n ht=10n)
V30 b Gnd bit({00110011} pw=100n on=5.0 off=0.0 rt=1n ft=1n

V31 c Gnd bit({01010101} pw=100n on=5.0 off=0.0 rt=1n ft=1n

v32 Vdd Gnd 1.8
* End of main circuit: Module0
.model NMOS NMOS
+Level = 49
+Lint = 4.e-08 Tox = 4.e-09
+Vth0 = 0.3999 Rdsw = 250
62

+lmin=1.8e-7 lmax=1.8e-7 wmin=1.8e-7 wmax=1.0e-4 Tref=27.0
version =3.1
+Xj= 6.0000000E-08 Nch= 5.9500000E+17
+lln= 1.0000000 lwn= 1.0000000 wln= 0.00
+wwn= 0.00 ll= 0.00
+lw= 0.00 lwl= 0.00 wint= 0.00
+wl= 0.00 ww= 0.00 wwl= 0.00
+Mobmod= 1 binunit= 2 xl= 0
+xw= 0 binflag= 0
+Dwg= 0.00 Dwb= 0.00
+K1= 0.5613000 K2= 1.0000000E-02
+K3= 0.00 Dvt0= 8.0000000 Dvt1= 0.7500000
+Dvt2= 8.0000000E-03 Dvt0w= 0.00 Dvt1w= 0.00
+Dvt2w= 0.00 Nlx= 1.6500000E-07 W0= 0.00
+K3b= 0.00 Ngate= 5.0000000E+20
+Vsat= 1.3800000E+05 Ua= -7.0000000E-10 Ub=

3.5000000E-18
+Uc= -5.2500000E-11 Prwb= 0.00
+Prwg= 0.00 Wr= 1.0000000 U0= 3.5000000E-02
+A0= 1.1000000 Keta= 4.0000000E-02 A1= 0.00
63

+A2= 1.0000000 Ags= -1.0000000E-02 B0= 0.00
+B1= 0.00
+Voff= -0.12350000 NFactor= 0.9000000 Cit= 0.00
+Cdsc= 0.00 Cdscb= 0.00 Cdscd= 0.00
+Eta0= 0.2200000 Etab= 0.00 Dsub= 0.8000000
+Pclm= 5.0000000E-02 Pdiblc1= 1.2000000E-02 Pdiblc2=

7.5000000E-03
+Pdiblcb= -1.3500000E-02 Drout= 1.7999999E-02 Pscbe1=

8.6600000E+08
+Pscbe2= 1.0000000E-20 Pvag= -0.2800000 Delta=

1.0000000E-02
+Alpha0= 0.00 Beta0= 30.0000000
+kt1= -0.3700000 kt2= -4.0000000E-02 At=

5.5000000E+04
+Ute= -1.4800000 Ua1= 9.5829000E-10 Ub1=

-3.3473000E-19
+Uc1= 0.00 Kt1l= 4.0000000E-09 Prt= 0.00
+Cj= 0.00365 Mj= 0.54 Pb= 0.982
+Cjsw= 7.9E-10 Mjsw= 0.31 Php= 0.841
+Cta= 0 Ctp= 0 Pta= 0
+Ptp= 0 JS=1.50E-08 JSW=2.50E-13
64

+N=1.0 Xti=3.0 Cgdo=2.786E-10
+Cgso=2.786E-10 Cgbo=0.0E+00 Capmod= 2
+NQSMOD= 0 Elm= 5 Xpart= 1
+Cgsl= 1.6E-10 Cgdl= 1.6E-10 Ckappa= 2.886
+Cf= 1.069e-10 Clc= 0.0000001 Cle= 0.6
+Dlc= 4E-08 Dwc= 0 Vfbcv= -1
* Predictive Technology Model Beta Version
* 0.18um PMOS SPICE Parametersv (normal one)
.model PMOS PMOS
+Level = 49
+Lint = 3.e-08 Tox = 4.2e-09
+Vth0 = -0.42 Rdsw = 450

version =3.1
+Xj= 7.0000000E-08 Nch= 5.9200000E+17
+lln= 1.0000000 lwn= 1.0000000 wln= 0.00
+wwn= 0.00 ll= 0.00
65

+lw= 0.00 lwl= 0.00 wint= 0.00
+wl= 0.00 ww= 0.00 wwl= 0.00
+Mobmod= 1 binunit= 2 xl= 0.00
+xw= 0.00
+binflag= 0 Dwg= 0.00 Dwb= 0.00
+ACM= 0 ldif=0.00 hdif=0.00
+rsh= 0 rd= 0 rs= 0
+rsc= 0 rdc= 0
+K1= 0.5560000 K2= 0.00
+K3= 0.00 Dvt0= 11.2000000 Dvt1= 0.7200000
+Dvt2= -1.0000000E-02 Dvt0w= 0.00 Dvt1w= 0.00
+Dvt2w= 0.00 Nlx= 9.5000000E-08 W0= 0.00
+K3b= 0.00 Ngate= 5.0000000E+20
+Vsat= 1.0500000E+05 Ua= -1.2000000E-10 Ub=

1.0000000E-18
+Uc= -2.9999999E-11 Prwb= 0.00
+Prwg= 0.00 Wr= 1.0000000 U0= 8.0000000E-03
+A0= 2.1199999 Keta= 2.9999999E-02 A1= 0.00
+A2= 0.4000000 Ags= -0.1000000 B0= 0.00
+B1= 0.00
66

+Voff= -6.40000000E-02 NFactor= 1.4000000 Cit= 0.00
+Eta0= 8.5000000 Etab= 0.00 Dsub= 2.8000000
+Pclm= 2.0000000 Pdiblc1= 0.1200000 Pdiblc2=

8.0000000E-05
+Pdiblcb= 0.1450000 Drout= 5.0000000E-02 Pscbe1=

1.0000000E-20
+Pscbe2= 1.0000000E-20 Pvag= -6.0000000E-02 Delta=

1.0000000E-02
+Alpha0= 0.00 Beta0= 30.0000000
+kt1= -0.3700000 kt2= -4.0000000E-02 At=

5.5000000E+04
+Ute= -1.4800000 Ua1= 9.5829000E-10 Ub1=

-3.3473000E-19
+Uc1= 0.00 Kt1l= 4.0000000E-09 Prt= 0.00
+Cj= 0.00138 Mj= 1.05 Pb= 1.24
+Cjsw= 1.44E-09 Mjsw= 0.43 Php= 0.841
+Cta= 0.00093 Ctp= 0 Pta= 0.00153
+Ptp= 0 JS=1.50E-08 JSW=2.50E-13
+N=1.0 Xti=3.0 Cgdo=2.786E-10
67

+Cf= 1.058e-10 Clc= 0.0000001 Cle= 0.6
.tran 10n 100n
.plot V(a) V(b) V(c) V(Sum) V(Ca)
.power vdd gnd
Sleepy Stack Case (180nm)
* SPICE netlist written by S-Edit Win32 7.00
* Written on Mar 20, 2010 at 15:33:20
* Waveform probing commands
.probe
.options probefilename="stackadder180.dat"
68

+ probesdbfile="D:\Documents and Settings\Gamers\My
Documents\stackadder180.sdb"
+ probetopmodule="Module0"
* Main circuit: Module0
M5 Gnd b N13 Gnd NMOS L=.18u W=.27u
M11 N12 S` Gnd Gnd NMOS L=.18u W=.27u
M12 N15 S` N14 Gnd NMOS L=.18u W=.27u
M13 Gnd S` N13 Gnd NMOS L=.18u W=.27u
M16 Ca N21 N22 Gnd NMOS L=.18u W=.27u
M17 N22 N21 Gnd Gnd NMOS L=.18u W=.27u
M18 N22 S` Gnd N24 NMOS L=.18u W=.27u
69

70

M41 N16 N34 Gnd Gnd NMOS L=.18u W=.27u
M42 Sum N34 N16 Gnd NMOS L=.18u W=.27u
M43 N8 a Vdd Vdd PMOS L=.18u W=.81u
M44 Vdd b N6 Vdd PMOS L=.18u W=.81u
M45 N8 S Vdd Vdd PMOS L=.18u W=.81u
M46 Vdd S N6 N51 PMOS L=.18u W=.81u
M47 N1 a N8 Vdd PMOS L=.18u W=.81u
M48 N6 b N1 Vdd PMOS L=.18u W=.81u
M51 N2 S N1 Vdd PMOS L=.18u W=.405u
M59 N19 N21 Vdd Vdd PMOS L=.18u W=.54u
M60 Ca N21 N19 Vdd PMOS L=.18u W=.54u
M61 N52 S Vdd Vdd PMOS L=.18u W=1.08u
71

M64 N53 b Vdd Vdd PMOS L=.18u W=1.08u
M66 N55 c Vdd Vdd PMOS L=.18u W=1.08u
M71 N62 N21 N28 N57 PMOS L=.18u W=.36u
M72 N34 N21 N62 N57 PMOS L=.18u W=.36u
M74 Vdd a N43 Vdd PMOS L=.18u W=1.08u
M75 Vdd S N43 Vdd PMOS L=.18u W=1.08u
M80 N42 S N41 Vdd PMOS L=.18u W=1.08u
M81 N40 S N39 Vdd PMOS L=.18u W=1.08u
M82 Sum N34 N17 Vdd PMOS L=.18u W=.54u
M83 N17 N34 Vdd Vdd PMOS L=.18u W=.54u
72

V85 a Gnd bit({00001111} pw=100n on=5.0 off=0.0 rt=1n ft=1n
V86 b Gnd bit({00110011} pw=100n on=5.0 off=0.0 rt=1n ft=1n

V87 c Gnd bit({01010101} pw=100n on=5.0 off=0.0 rt=1n ft=1n

v88 S Gnd 0.0
v89 Vdd Gnd 1.8
v90 S` Gnd 1.8
* End of main circuit: Module0
.model NMOS NMOS
+Level = 49
+Lint = 4.e-08 Tox = 4.e-09
+Vth0 = 0.3999 Rdsw = 250

version =3.1
+Xj= 6.0000000E-08 Nch= 5.9500000E+17
+lln= 1.0000000 lwn= 1.0000000 wln= 0.00
+wwn= 0.00 ll= 0.00
+lw= 0.00 lwl= 0.00 wint= 0.00
+wl= 0.00 ww= 0.00 wwl= 0.00
73

+Mobmod= 1 binunit= 2 xl= 0
+xw= 0 binflag= 0
+Dwg= 0.00 Dwb= 0.00
+K1= 0.5613000 K2= 1.0000000E-02
+K3= 0.00 Dvt0= 8.0000000 Dvt1= 0.7500000
+Dvt2= 8.0000000E-03 Dvt0w= 0.00 Dvt1w= 0.00
+Dvt2w= 0.00 Nlx= 1.6500000E-07 W0= 0.00
+K3b= 0.00 Ngate= 5.0000000E+20
+Vsat= 1.3800000E+05 Ua= -7.0000000E-10 Ub=

3.5000000E-18
+Uc= -5.2500000E-11 Prwb= 0.00
+Prwg= 0.00 Wr= 1.0000000 U0= 3.5000000E-02
+A0= 1.1000000 Keta= 4.0000000E-02 A1= 0.00
+A2= 1.0000000 Ags= -1.0000000E-02 B0= 0.00
+B1= 0.00
+Voff= -0.12350000 NFactor= 0.9000000 Cit= 0.00
+Eta0= 0.2200000 Etab= 0.00 Dsub= 0.8000000
74

+Pclm= 5.0000000E-02 Pdiblc1= 1.2000000E-02 Pdiblc2=
7.5000000E-03
+Pdiblcb= -1.3500000E-02 Drout= 1.7999999E-02 Pscbe1=

8.6600000E+08
+Pscbe2= 1.0000000E-20 Pvag= -0.2800000 Delta=

1.0000000E-02
+Alpha0= 0.00 Beta0= 30.0000000
+kt1= -0.3700000 kt2= -4.0000000E-02 At=

5.5000000E+04
+Ute= -1.4800000 Ua1= 9.5829000E-10 Ub1=

-3.3473000E-19
+Uc1= 0.00 Kt1l= 4.0000000E-09 Prt= 0.00
+Cj= 0.00365 Mj= 0.54 Pb= 0.982
+Cjsw= 7.9E-10 Mjsw= 0.31 Php= 0.841
+Cta= 0 Ctp= 0 Pta= 0
+Ptp= 0 JS=1.50E-08 JSW=2.50E-13
+N=1.0 Xti=3.0 Cgdo=2.786E-10
+Cf= 1.069e-10 Clc= 0.0000001 Cle= 0.6
75

* Predictive Technology Model Beta Version
* 0.18um PMOS SPICE Parametersv (normal one)
.model PMOS PMOS
+Level = 49
+Lint = 3.e-08 Tox = 4.2e-09
+Vth0 = -0.42 Rdsw = 450

version =3.1
+Xj= 7.0000000E-08 Nch= 5.9200000E+17
+lln= 1.0000000 lwn= 1.0000000 wln= 0.00
+wwn= 0.00 ll= 0.00
+lw= 0.00 lwl= 0.00 wint= 0.00
+wl= 0.00 ww= 0.00 wwl= 0.00
+Mobmod= 1 binunit= 2 xl= 0.00
+xw= 0.00
+binflag= 0 Dwg= 0.00 Dwb= 0.00
+ACM= 0 ldif=0.00 hdif=0.00
76

+rsh= 0 rd= 0 rs= 0
+rsc= 0 rdc= 0
+K1= 0.5560000 K2= 0.00
+K3= 0.00 Dvt0= 11.2000000 Dvt1= 0.7200000
+Dvt2= -1.0000000E-02 Dvt0w= 0.00 Dvt1w= 0.00
+Dvt2w= 0.00 Nlx= 9.5000000E-08 W0= 0.00
+K3b= 0.00 Ngate= 5.0000000E+20
+Vsat= 1.0500000E+05 Ua= -1.2000000E-10 Ub=

1.0000000E-18
+Uc= -2.9999999E-11 Prwb= 0.00
+Prwg= 0.00 Wr= 1.0000000 U0= 8.0000000E-03
+A0= 2.1199999 Keta= 2.9999999E-02 A1= 0.00
+A2= 0.4000000 Ags= -0.1000000 B0= 0.00
+B1= 0.00
+Voff= -6.40000000E-02 NFactor= 1.4000000 Cit= 0.00
+Eta0= 8.5000000 Etab= 0.00 Dsub= 2.8000000
+Pclm= 2.0000000 Pdiblc1= 0.1200000 Pdiblc2=

8.0000000E-05
77

+Pdiblcb= 0.1450000 Drout= 5.0000000E-02 Pscbe1=
1.0000000E-20
+Pscbe2= 1.0000000E-20 Pvag= -6.0000000E-02 Delta=

1.0000000E-02
+Alpha0= 0.00 Beta0= 30.0000000
+kt1= -0.3700000 kt2= -4.0000000E-02 At=

5.5000000E+04
+Ute= -1.4800000 Ua1= 9.5829000E-10 Ub1=

-3.3473000E-19
+Uc1= 0.00 Kt1l= 4.0000000E-09 Prt= 0.00
+Cj= 0.00138 Mj= 1.05 Pb= 1.24
+Cjsw= 1.44E-09 Mjsw= 0.43 Php= 0.841
+Cta= 0.00093 Ctp= 0 Pta= 0.00153
+Ptp= 0 JS=1.50E-08 JSW=2.50E-13
+N=1.0 Xti=3.0 Cgdo=2.786E-10
+Cf= 1.058e-10 Clc= 0.0000001 Cle= 0.6
.tran 10n 100n
78

.plot V(a) V(b) V(c) V(Ca) V(Sum)
.power vdd gnd
APPENDIX-B
79

Software Tools
S-EDIT V 8.0
MICROWIND
T-SPICE
W-EDIT
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Chapter-1

Power consumption is one of the top concerns of Very Large Scale

Power consumption of CMOS consists of dynamic and static components.

SLEEPY STACK A LOW POWER VLSI DESIGN

In this dissertation, we provide novel circuit structure named “sleepy stack”

SLEEPY STACK A LOW POWER VLSI DESIGN

Purpose of Low Power VLSI Design

SLEEPY STACK A LOW POWER VLSI DESIGN

The reduction of the supply voltage is dictated by the need to maintain

SLEEPY STACK A LOW POWER VLSI DESIGN

Sources of Dissipation in CMOS Transistors

Circuits designed before 1980 were mainly implemented in NMOS

SLEEPY STACK A LOW POWER VLSI DESIGN

Starting from 0.13μm technology node (i.e. a technology with a minimal

2.1 Dynamic consumption

2.1.1 Switching energy

SLEEPY STACK A LOW POWER VLSI DESIGN

This type of consumption can easily be reduced from a technology

2.1.2 Shortcut energy

The second source of dynamic consumption arises from shortcut paths.

SLEEPY STACK A LOW POWER VLSI DESIGN

2.2 Static consumption

SLEEPY STACK A LOW POWER VLSI DESIGN

(a) Sub-threshold current;

(b) Gate leakage current;

(c) Reverse-bias p-n junction current and band to band tunneling;

(d) Gate-Induced Drain Leakage (GIDL) current;

(e) Punchthrough current.

SLEEPY STACK A LOW POWER VLSI DESIGN

2.2.1 Sub-threshold current

The most important leakage current is the sub-threshold one originated by

SLEEPY STACK A LOW POWER VLSI DESIGN

• Drain Induced Barrier Lowering (DIBL) effect: In short channel

SLEEPY STACK A LOW POWER VLSI DESIGN

• Body effect: The body effect appears when a potential difference is

SLEEPY STACK A LOW POWER VLSI DESIGN

By considering the described effects, the sub-threshold current can be

2.2.2 Gate leakage current

The transistor gate potential influences the charges in the channel by

Oxide tunneling current

SLEEPY STACK A LOW POWER VLSI DESIGN

Hot carrier injection

Due to the high electric field in the interface Si−SiO2 (channel-oxide),

2.2.3 Reverse bias p-n junction leakage and band to band

In the normal transistor operation mode, the drain/source to well junctions

SLEEPY STACK A LOW POWER VLSI DESIGN

This type of leakage is especially important for “relatively high” supply

SLEEPY STACK A LOW POWER VLSI DESIGN

In submicron MOS transistors, implants at the substrate surface aiming Vth

2.3 Switching power and delay tradeoffs

CMOS power consumption of a particular CMOS gate under consideration can

SLEEPY STACK A LOW POWER VLSI DESIGN

In this project we estimate leakage power consumption by measuring static

SLEEPY STACK A LOW POWER VLSI DESIGN

Dual threshold technology is another way to address the increasing active

Multi-Threshold CMOS (MTCMOS)

The leakage current can be dynamically controlled using multi-

SLEEPY STACK A LOW POWER VLSI DESIGN

Variable-Threshold CMOS (VTCMOS)

SLEEPY STACK A LOW POWER VLSI DESIGN

SLEEPY STACK A LOW POWER VLSI DESIGN

Static Power Reduction VLSI Research

SLEEPY STACK A LOW POWER VLSI DESIGN