TN 423: VLSI CIRCUITS

Lecture 5

CMOS CIRCUITS

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 Outline
1. CMOS Gate Design
2. Combinational Circuits
3. Sequential Circuits

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 CMOS Gate Design…
Conduction Complement
Ωtransistors that appear in series in the PDN must
appear in parallel in the PUN.
ΩTransistors that appear in parallel in the PDN
must appear in series in the PUN.
ΩRule of Conduction Complements
✓ PUN is complement of PDN
✓ Parallel -> series, series -> parallel

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 Combinational Circuits…
Conduction Complement
ΩComplementary CMOS gates always produce 0
or 1
ΩEx: NAND gate
✓ Series nMOS: Y=0 when both inputs are 1
✓ Thus Y=1 when either input is 0
✓ Requires parallel pMOS Y
A
B

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 CMOS Gate Design…
Signal Strength
Ω The strength of a signal is measured by how
closely it approximates an ideal voltage source.
Ω VDD and GND rails are strongest 1 and 0
respectively
Ω nMOS transistor passes strong 0 but degraded
or weak 1
Ω pMOS transistor passes strong 1
✓ But degraded or weak 0
Ω Thus nMOS are best for pull-down network
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CMOS Gate Design…

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 Combinational Circuits
Ω A combinational system (device) is a digital
system in which the value of the output at any
instant depends only on the value of the input at
that same instant (and not on previous values)
Ω Block diagram of a combinational logic circuit

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 Combinational Circuits…
Ω Some of the characteristics of combinational
circuits are following.
✓ The output of combinational circuit at any
instant of time, depends only on the levels
present at input terminals.
✓ The combinational circuits do not use any
memory. The previous state of input does not
have any effect on the present state of the
circuit.
✓ A combinational circuit can have a n number
of inputs and m number of outputs.
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 Combinational Circuits…
Ω Examples include:
✓ Inverter (NOT gates)
✓ AND/NAND gates
✓ OR/NOR Gates
✓ XOR/NOR
✓ Compound Gates
✓ Pass Transistors
✓ Transmission gates
✓ Tristates

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 Combinational Circuits…
CMOS Inverter

A Y

VDD OFF
ON
0
1

A Y ON
OFF
A Y
0 1
1 0
GND
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 Combinational Circuits…
CMOS NAND Gate
follow this video:
OFF
ON
OFF
ON OFF
ON

1
0 A B Y ON
OFF
Y 0 0 1
0
1
1
0 OFF
ON
ON
OFF
A 0 1 1
1 0 1
B
1 1 0

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 Combinational Circuits…
CMOS NOR Gate

A B Y
A
0 0 1
B 0 1 0
Y
1 0 0
1 1 0

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 Combinational Circuits…
Compound Gates follow this video:
ΩCompound gates are formed by using a
combination of series and parallel switch
structures and can do any inverting function
ΩEx:

ΩThis function is sometimes called AND-OR-

INVERT-22, or AOI22 because it performs the
NOR of a pair of 2-input ANDs.
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 Combinational Circuits…
Compound Gates
ΩFor the pMOS pull-up network, we must compute the
complementary expression using switches that turn ON
with inverted polarity
✓ interchange AND and OR operations (De Morgan’s
law)
ΩIn the pull-up network, the parallel combination of A and B
is placed in series with the parallel combination of C and D.
ΩThis progression is evident in Figure (a) and Figure (b).

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 Combinational Circuits…
Compound Gates
ΩFor the nMOS PDN, take the uninverted expression ((A ·
B) + (C · D)) indicating when the output should be pulled to
‘0.’
✓ The AND expressions (A · B) and (C · D) may be
implemented by series connections of switches, as
shown in Figure (c).
✓ Now ORing the result requires the parallel
connection of these two structures, which is shown
in Figure (d).

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 Combinational Circuits…
Compound Gates
Ω Putting the networks together yields the full
schematic as is shown in Figure (e).

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 Combinational Circuits…
Compound Gates
Ω The symbol is shown in Figure (f ).

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 Combinational Circuits…
Activity 1
Ω Sketch a CMOS gate structure for:

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 Combinational Circuits…
Activity 2
ΩSketch a CMOS gate structure for:

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 Combinational Circuits…
Activity 3:
Ω Sketch a static CMOS gate computing (O3AI)

A
B
C D
Y
D
A B C

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 Combinational Circuits…
Pass Transistors
Ω When an nMOS or pMOS is used alone as an
imperfect switch, it is called a pass transistor
nMOS Pass Transistor

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 Combinational Circuits…
Pass Transistors pMOS

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 Combinational Circuits…
Transmission Gates
ΩBy combining an nMOS and a pMOS transistor
in parallel (figure below), we obtain a switch that
turns on when a 1 is applied to gate (Figure (b) in
which 0s and 1s are both passed in an acceptable
fashion (Figure (c)).
ΩTransmission gates pass both 0 and 1 well

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Combinational Circuits…

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 Combinational Circuits…
Tristate Buffers
ΩA digital buffer is an electronic circuit that is used to
isolate the input from the output, preventing the impedance
of one circuit to alter the impedance of another (with Q=A).
ΩWhen the enable input EN is 1, the output Q equals the
input A, just as in an ordinary buffer.
ΩWhen the enable is 0, Q is left floating (a ‘Z’ value).

EN
EN A Q
A Y
0 0 Z
EN 0 1 Z
A Y 1 0 0

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1 1 1
EN
 Combinational Circuits…
Nonrestoring Tristate
Ω Transmission gate acts as a tristate buffer
✓ Only two transistors
✓ But nonrestoring
Ω If the input is noisy or otherwise degraded, the
output will receive the same noise.
EN

A Y

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 Combinational Circuits…
Tristate Inverter
Ω Tristate inverter produces restored output
✓ Violates conduction complement rule
✓ Because we want a Z output
Ω When EN is 0 (Figure (b)), both enable transistors are
OFF, leaving the output floating.
Ω When EN is 1 (Figure (c)), both enable transistors are
ON.
Ω They are conceptually removed from the circuit, leaving
a simple inverter.
Ω Figure (d) shows symbols for the tristate inverter.

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 Combinational Circuits…
Tristate Inverter…

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 Sequential Circuits
Ω A sequential logic circuit contains storage
elements in addition to logic gates
Ω The memory elements are devices, capable of
storing binary information within them.
Ω The block diagram is shown.

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 Sequential Circuits…
Ω It consists of a combinational circuit to which
storage elements are connected to form a feed
back path.
Ω The binary information stored in these
elements at any given time defines the state of
the sequential circuit at that time.
Ω Sequential circuits are classified in two main
categories depending on timing of their signals.
1. Synchronous or clocked sequential circuits
2. Asynchronous or un-clocked sequential
circuits.
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 Sequential Circuits…
Ω Examples include:
✓ Flip-flop (latches) (S-R, J-K, T and D)
✓ Registers (Shift, SISO,SIPO, PISO, PIPO)
✓ Counters (binary, Johnson, Synchronous)
✓ Multiplexors/Demux
✓ Encoder/Decoder

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Activity: to design Multiplexors, Flip
Flops

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 Multiplexers
Ω A multiplexer chooses the output from among several
inputs based on a select signal.
Ω A 2-input, or 2:1 multiplexer, chooses
✓ input D0 when the select is 0 and
✓ input D1 when the select is 1.
Ω For the logic function Y = S · D0 + S · D1,
✓ The truth table is given below
S S D1 D0 Y
0 X 0 0
D0 0
Y 0 X 1 1
D1 1 1 0 X 0
1 1 X 1
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 Multiplexers
Ω Two transmission gates can be tied together to
form a compact 2-input multiplexer, as shown in
Figure below.
Ω The select and its complement enable exactly
one of the two transmission gates at any given
time

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 Gate-Level Mux Design
Ω
Y  SD1  SD0 (too many transistors)
Ω How many transistors are needed? 20

D1
S Y
D0

D1 4 2
S 4 2 Y
D0 4 2
2

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 Transmission Gate Mux
Ω Nonrestoring mux uses two transmission gates
✓ Only 4 transistors
S

D0
S Y
D1

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 Inverting Mux
Ω Inverting multiplexer
✓ Use compound AOI22
✓ Or pair of tristate inverters
✓ Essentially the same thing
Ω Noninverting multiplexer adds an inverter
D0 S D0 D1 S
S D1 S S
Y Y D0 0
S S S S Y
D1 1

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 4:1 Multiplexer
Ω 4:1 mux chooses one of 4 inputs using two
selects
✓ Two levels of 2:1 muxes S1S0 S1S0 S1S0 S1S0
✓ Or four tristates
D0
S0 S1

D0 0
D1
D1 1
0
Y Y
1
D2 0 D2
D3 1

D3

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 D Latch
Ω When CLK = 1, latch is transparent
✓ D flows through to Q like a buffer
Ω When CLK = 0, the latch is opaque
✓ Q holds its old value independent of D
Ω a.k.a. transparent latch or level-sensitive latch
CLK CLK

D
Latch

D Q
Q

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 D Latch Design
Ω Multiplexer chooses D or old Q

CLK
CLK
D Q Q
1
Q D Q
0
CLK CLK

CLK

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 D Latch Operation
Q Q
D Q D Q

CLK = 1 CLK = 0

CLK

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 D Flip-flop
Ω When CLK rises, D is copied to Q
Ω At all other times, Q holds its value
Ω a.k.a. positive edge-triggered flip-flop, master-
slave flip-flop

CLK
CLK
D
Flop

D Q
Q

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 D Flip-flop Design
Ω Built from master and slave D latches

CLK CLK
CLK QM
D Q
CLK CLK CLK CLK
CLK
Latch

Latch

QM
D Q
CLK CLK

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 D Flip-flop Operation
QM Q
D

CLK = 0

QM
D Q

CLK = 1

CLK

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 Gate Layout
Ω Layout can be very time consuming
✓ Design gates to fit together nicely
✓ Build a library of standard cells
Ω Standard cell design methodology
✓ VDD and GND should abut (standard height)
✓ Adjacent gates should satisfy design rules
✓ nMOS at bottom and pMOS at top
✓ All gates include well and substrate contacts

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