TN 423: VLSI CIRCUITS

Lecture 7b

MOS TRANSISTOR ANALYSIS

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 Outline
1. Introduction
2. Terminal Voltage
3. Drain Current equation
4. MOS Capacitor
5. nMOS I-V Characteristics
6. pMOS I-V Characteristics
7. Gate and Diffusion Capacitance
8. CMOS Bias
9. CMOS Band Diagrams

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 Introduction
Ω MOS is a four-terminal device: gate (G), source (S), drain (D) and
body (B).
Ω The device size (channel region) is specified by channel width (W)
and channel length (L).
Ω Two kinds of MOS: n-channel (NMOS) and p-channel (PMOS)
devices
Ω The device structure is basically symmetric in terms of drain and
source.
Ω Source and drain terminals are specified by the operation voltage

Ngeze, LV VLSI Circuits 3

 Terminal Voltages
nMOS is used to explain the concept Vg
ΩMode of operation depends on Vg, Vd, Vs + +
Vgs Vgd
 Vgs = Vg – Vs - -
 Vgd = Vg – Vd Vs Vd
- +
Vds
 Vds = Vd – Vs = Vgs - Vgd
ΩSource and drain are symmetric diffusion terminals
 By convention, source is terminal at lower voltage
 Hence Vds  0
ΩFor nMOS, body is grounded.
ΩThree regions of operation
 Cutoff
 Linear
 Saturation

Slide 4
 Terminal Voltages
When Gate Voltage is Zero (VGS=0)
ΩThe MOS structure forms a parallel-plate plate
capacitor with gate oxide layer in the middle.
ΩTwo pn junctions (S-B and D-B) are connected
as back to back diodes.
ΩThe source and drain terminals are isolated by
two depletion region without conducting current.
ΩThe operating principles will be introduced by
using the n-channel MOSFET as an example

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 Terminal Voltages
Small Voltage at the gate (Vg)
ΩPositive charges accumulate in gate.
ΩElectric field is formed
ΩThe electric field forms a depletion region by pushing
holes in p-type substrate away from the surface.

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 Terminal Voltages
When gate voltage exceeds Vtn
ΩElectrons start to accumulate on the substrate
surface
ΩThe induced n region thus forms a channel for
current flow from drain to source
ΩThe channel is created by inverting the substrate
surface from p-type to n-type inversion layer.
ΩThe channel is controlled by the effective voltage
or overdrive voltage VOV=VGS-Vt

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8
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 Terminal Voltages
Applying a small Drain Voltage VDS
ΩElectrons travel from source to drain through the induced
n-channel
ΩThe resulting current iD flows from drain to source
ΩThe current is proportional to the number of carriers in the
induced channel.
ΩThe electron charge in the channel due to the overdrive
voltage:
|Q| = CoxWLVOV
 Gate oxide capacitance Cox is defined as capacitance per unit
area.

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Terminal Voltages

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 Terminal Voltages
As VDS is increased
ΩThe voltage along the channel increases from 0 to VDS, and the
voltage between the gate and the points along the channel decreases
from VGS at the source end to (VGS-VDS) at the drain end.
ΩIncreasing VDS will result in a narrowed channel.
ΩThe resistance increases due to narrowed channel and the iD-VDS
curve does not continue as a straight line.
ΩAt the point VDSsat= VGS - Vt, the channel is pinched off at the drain
side.
ΩIncreasing VDS beyond this value has little effect on the channel
shape and iD saturates at this value.
ΩTriode region: VDS< VDSsat
ΩSaturation region: VDS>=VDSsat

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Terminal Voltages

Ngeze, LV VLSI Circuits 13

Terminal Voltages

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 make sure you know it...!!

Derivation of Drain Current

Ngeze, LV VLSI Circuits 15

Derivation of Drain Current

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 Channel Charge
Ω MOS structure looks like parallel plate capacitor
while operating in inversion
 Gate – oxide – channel
Ω Qchannel =

gate
Vg
polysilicon + +
gate source Vgs Cg Vgd drain
W
Vs - - Vd
tox
channel
n+ - + n+
SiO2 gate oxide
Vds
L
n+ n+ (good insulator, ox = 3.9) p-type body
p-type body

Slide 17
 Channel Charge
Ω MOS structure looks like parallel plate capacitor
while operating in inversion
 Gate – oxide – channel
Ω Qchannel = CV
Ω C=

gate
Vg
polysilicon + +
gate source Vgs Cg Vgd drain
W
Vs - - Vd
tox
channel
n+ - + n+
SiO2 gate oxide
Vds
L
n+ n+ (good insulator, ox = 3.9) p-type body
p-type body

Slide 18
 Channel Charge
Ω MOS structure looks like parallel plate capacitor
while operating in inversion
 Gate – oxide – channel
Ω Qchannel = CV
Ω C = Cg = oxWL/tox = CoxWL Cox = ox / tox

Ω V=
gate
Vg
polysilicon + +
gate source Vgs Cg Vgd drain
W
Vs - - Vd
tox
channel
n+ - + n+
SiO2 gate oxide
Vds
L
n+ n+ (good insulator, ox = 3.9) p-type body
p-type body

Slide 19
 Channel Charge
Ω MOS structure looks like parallel plate capacitor
while operating in inversion
 Gate – oxide – channel
Ω Qchannel = CV
Where C = Cg = oxWL/tox = CoxWL as Cox = ox / tox

V = Vgc – Vt = (Vgs – Vds/2) – Vt

gate
Vg
polysilicon + +
gate source Vgs Cg Vgd drain
W
Vs - - Vd
tox
channel
n+ - + n+
SiO2 gate oxide
Vds
L
n+ n+ (good insulator, ox = 3.9) p-type body
p-type body

Slide 20
 Carrier velocity
Ω Charge is carried by e-
Ω Carrier velocity v proportional to lateral E-field
between source and drain
Ω v=

Slide 21
 Carrier velocity
Ω Charge is carried by e-
Ω Carrier velocity v proportional to lateral E-field
between source and drain
Ω v = mE m called mobility
Ω E=

Slide 22
 Carrier velocity
Ω Charge is carried by e-
Ω Carrier velocity v proportional to lateral E-field
between source and drain
Ω v = mE m called mobility
Ω E = Vds/L
Ω Time for carrier to cross channel:
 t=

Slide 23
 Carrier velocity
Ω Charge is carried by e-
Ω Carrier velocity v proportional to lateral E-field
between source and drain
Ω v = mE m called mobility
Ω E = Vds/L
Ω Time for carrier to cross channel:
 t=L/v

Slide 24
 nMOS Linear I-V
Ω Now we know
 How much charge Qchannel is in the channel
 How much time t each carrier takes to cross

I ds 

Slide 25
 nMOS Linear I-V
Ω Now we know
 How much charge Qchannel is in the channel
 How much time t each carrier takes to cross

Qchannel
I ds 
t


Slide 26
 nMOS Linear I-V
Ω Now we know
 How much charge Qchannel is in the channel
 How much time t each carrier takes to cross

Qchannel
I ds 
t
 mCox
W V  V  Vds V
 gs t 2  ds
L
  Vgs  Vt  ds Vds
V
 2 W
 = mCox
L
Slide 27
 nMOS Saturation I-V
Ω If Vgd < Vt, channel pinches off near drain
 When Vds > Vdsat = Vgs – Vt
Ω Now drain voltage no longer increases current

I ds 

Slide 28
 nMOS Saturation I-V
Ω If Vgd < Vt, channel pinches off near drain
 When Vds > Vdsat = Vgs – Vt
Ω Now drain voltage no longer increases current

I ds   Vgs  Vt  dsat V
V
 dsat
 2 

Slide 29
 nMOS Saturation I-V
Ω If Vgd < Vt, channel pinches off near drain
 When Vds > Vdsat = Vgs – Vt
Ω Now drain voltage no longer increases current

I ds   Vgs  Vt  dsat V
V
 dsat
 2 

  Vt 
2
 Vgs
2

Slide 30
 Drain-Current Equations-pMOS
pMOS Characteristics

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 Drain-Current Equations-pMOS
Ω Transconductance parameter
Ω The values of VGS, VDS, Vt, and for p-channel
MOSFET are all NEGATIVE
Ω Drain current iD is still defined as a positive
current

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 Drain-Current Equations-pMOS
Ω I-V Characteristics of pMOS

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 Capacitance
Ω Any two conductors separated by an insulator
have capacitance
Ω Gate to channel capacitor is very important
 Creates channel charge necessary for operation
Ω Source and drain have capacitance to body
 Across reverse-biased diodes
 Called diffusion capacitance because it is associated
with source/drain diffusion

Slide 34
 Gate Capacitance
Ω Approximate channel as connected to source
Ω Cgs = oxWL/tox = CoxWL = CpermicronW
Ω Cpermicron is typically about 2 fF/mm

polysilicon
gate
W
tox
L SiO2 gate oxide
n+ n+ (good insulator, ox = 3.90)
p-type body

Slide 35
 Bias Conditions
Ω Bias condition at the transition between
saturation and non-saturation states as
VGS = VDS +Vtn
For nMOS
Ω The non-saturated condition is given by
VGS > VDS +Vt
Ω Saturated bias condition is given by
VGS < VDS + Vt

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 Bias Conditions
Question1: Determine the bias state condition of the
nMOS transistor if Vtn = 0.4 V.

Soln
First identify the correct terminals.
VGS = 1.9 V,
VDS = 2.5 V,
Vtn = 0.4 V,
=> VGS = 1.9 V < 2.5 V + 0.4 V =2.9 V.
The transistor is in the saturated state

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 Bias Conditions
Question2: Determine the bias state conditions
if Vtn = 0.4 V.

VGS = VG – VS = 2.2 V – (– 2.3 V) = 4.5 V.

VDS = VD – VS = 0.5 V – ( –2.3) = 2.8 V.
=> VGS = 4.5 V > 2.8 V + 0.4 V = 3.2 V.
The transistor is in non-saturation.

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 Bias Conditions
Ω Determine the bias state conditions
if Vtn = 0.4 V.

VGS = VG – VS = 0.9 V – (– 2.5 V) = 3.4 V.

VDS = VD – VS = 0.5 V – (– 2.5 V) = 3 V.
VGS = 3.4 V = VDS + Vtn = 3 V + 0.4 V = 3.4 V,
The transistor is at the boundary of the saturated and non-saturated
regions.

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 Questions
Ω Calculate ID in an nMOS transistor for VGS=2V,
VD=0.1V. The device parameters are W=8μm,
L=1μm, Vt=1V and μnCOX=25μA/V2

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 Bias Conditions
Question
Ω Determine the bias state for the three circuit
conditions if Vtn = 0.4 V.

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 CMOS Energy Band Diagrams
Ω Let n = mobile carrier concentration of electrons
p = mobile carrier concentration of holes
Ω From the law of mass action
Where ni = intrinsic concentration

Ω Taking the substrate concentration to be

Ω The equilibrium concentration of holes is given
by:

Ω Likewise,

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 CMOS Energy Band Diagrams
Ω Fermi level: The energy level of an atom in a solid at a
given temperature for which there is a 50 percent
probability of occupation of any available state of that
energy by an electron
Ω Intrinsic Fermi level: Fermi level in an intrinsic
semiconductor; located not exactly in the center of the
energy gap because of the different effective mass of
electron and hole.
Ω The value of the Fermi level at absolute zero (−273.15
°C) is called the Fermi energy and is a constant for
each solid.
Ω The Fermi level changes as the solid is warmed and as
electrons are added to or withdrawn from the solid.
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 CMOS Energy Band Diagrams
Ω Energy band diagram of a MOS device

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 CMOS Energy Band Diagrams
Ω Work function It is the energy required for an electron to
move from the Fermi level into free space (vacuum
level)
 It is denoted by

Ω Electron affinity is the potential difference between the

conduction band and the vacuum level
 It is denoted by
Ω The potential difference between and is called
Fermi potential or flat band condition.
 It is denoted by:
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 CMOS Energy Band Diagrams
Ω Energy band diagram of a n-type substrate

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 CMOS Energy Band Diagrams
Ω Consider an n-type s/c.
Ω At zero applied voltage, energy difference
between the metal work function and the
s/c work function is zero.
Ω It is given by:
for p-type

for n-type

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 CMOS Energy Band Diagrams
Ω Fermi level is given as:

for p-type

for n-type
Ω ND = Donor ion concentration
Ω NA = Acceptor ion concentration
Ω k = Boltzman constant
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 CMOS Energy Band Diagrams
Ω Energy band diagram of a p-type substrate

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