Control Unit

Module 3
 Classifications of Instructions
• Data Transfer
• Arithmetic
• Logical
• Branching
• Machine Control

Prof. Shanmugasundaram | SENSE | VIT 2

 Data Transfer
• Useful to move a data from one place(Source) to
another place(Destination)
• The following addressing modes are used mostly
a)Immediate
b)Register
Caution:
1. Sizes of source and destination must match
2. The destination can not be an imm/.data
3. Even after move the source not get modified

Prof. Shanmugasundaram | SENSE | VIT 3

 Arithmetic Instructions
• Most of the processors uses a special
register(accumulator) for arithmetic operations.
• For complex mathematical operations, if needed, a
separate math processor is used along with the main
processor
• The status of the operation is reflected on the flag
register(PSW)
• Some processors allows bit wise operations also..

Prof. Shanmugasundaram | SENSE | VIT 4

 Logical Instructions
• Most of the processors uses a special
register(accumulator) for arithmetic operations.
• The status of the operation is reflected on the flag
register(PSW)
• Some processors allows bit wise operations also..

Prof. Shanmugasundaram | SENSE | VIT 5

Branching(un conditional and
conditional)

Prof. Shanmugasundaram | SENSE | VIT 6

 Machine Control

• Examples are,
• NOP
• END

Prof. Shanmugasundaram | SENSE | VIT 7

 Control Unit
• Control unit: configures the datapath
operations Processor
– Sequence of desired operations Control unit Datapath
(“instructions”) stored in memory –
“program” ALU
Controller Control
• Instruction cycle – broken into several /Status
sub-operations, each one clock cycle,
e.g.: Registers
– Fetch: Get next instruction into IR
– Decode: Determine what the
instruction means
– Fetch operands: Move data from PC IR R0 R1
memory to datapath register
– Execute: Move data through the ALU
– Store results: Write data from register I/O
...
to memory 100 load R0, M[500] Memory
500 10
104 inc R1, R0
108 store M[501], R1
501 ...

Prof. Shanmugasundaram | SENSE | VIT 8

 Microprogramming
• Execution of instruction  execution of sequence of sub steps
 cycles.
• Each cycle  made of sequence of more fundamental
operations (micro-operations performed by micro-instruction).
• A single micro-operations involves transfer of data
– Between register
– Between register and external bus
– ALU operation
• Stored in (i) ROM (ii) Control memory located in Control Unit.
• Micro program consists of micro instruction which are bit level
representation of control signals.

Prof. Shanmugasundaram | SENSE | VIT 10

 Microprogramming
• For a given time certain operations are performed and others idle
the control variable at any given time can be represented by 0’s
and 1’s and it is called as control word.
• Each micro instructions generates micro-operation to fetch the
instruction from main memory, evaluate effective address to
execute the operation specified by the instruction and to return
the control to the fetch.

Prof. Shanmugasundaram | SENSE | VIT 11

 Micro operations
• Execution of program  consists of sequence of instruction
cycle.
• Sequence of instruction not necessary to follow written
sequence.  branch instruction.
• Instruction cycle  combination of number of smaller units.
– Fetch, Indirect, Execute, Interrupt
• Further more division of these instruction cycle  micro
operation.
– Functional
– Atomic
– Involved with registers
– Operations of processor.

Prof. Shanmugasundaram | SENSE | VIT 12

Program Execution(constituent Elements)

 Performance of each sub cycle involves one or more shorter operations, that
is, micro – operations.
Micro – operations are the functional, or atomic, operations of a processor.

Prof. Shanmugasundaram | SENSE | VIT 13

Fetch Cycle

Prof. Shanmugasundaram | SENSE | VIT 14

Micro operation of Fetch Cycle

Prof. Shanmugasundaram | SENSE | VIT 15

 Micro operation of Indirect Cycle
Consider the instruction SUB R1, M [X], which subtracts the
contents of location X from the contents of register R1, and places
the result in R1.
t1: MAR ← (IR(address))
t2: MBR ← Memory
t3: MBR ← Complement(MBR)
t4: MBR ← Increment(MBR)
t5: R1 ← (R1) + (MBR)

Prof. Shanmugasundaram | SENSE | VIT 16

Micro operation of Interrupt cycle

Prof. Shanmugasundaram | SENSE | VIT 17

 The Instruction Cycle
• To complete the picture, we need to tie sequences of micro-
operations together.
• We assume a new 2-bit register called the instruction cycle code
(ICC).
• The ICC designates the state of the processor in terms of which portion
of the cycle it is in:
00: Fetch
01: Indirect
10: Execute
11: Interrupt

Prof. Shanmugasundaram | SENSE | VIT 18

Prof. Shanmugasundaram | SENSE | VIT 19
• How we are going to implement these micro-operations
 Control Unit Design
• Control Unit Design
– By Hardware  Hardwired
– By Software  micro-programmed

Prof. Shanmugasundaram | SENSE | VIT 20

 Characterization of Control Unit
1. Define the basic elements of processor.
2. Describe the micro-operation that processor performs.
3. Determine the functions that the control unit must perform to
cause the micro operations to be performed.

Prof. Shanmugasundaram | SENSE | VIT 21

 What Control Unit is doing?
• Sequencing: The control unit causes the processor to step
through the series of micro-operations in the proper sequence ,
based on the program being executed.
• Execution: The control unit causes each micro-operations to be
performed.

Prof. Shanmugasundaram | SENSE | VIT 22

Control Unit Model

Prof. Shanmugasundaram | SENSE | VIT 23

 Example

Prof. Shanmugasundaram | SENSE | VIT 24

Prof. Shanmugasundaram | SENSE | VIT 25
 Hard wired control Unit
• In this, for each control signal a Boolean expression is
derived as a function of input of that signal
• Let P &Q are two signal defined as
00 – Fetch cycle
01 - Indirect cycle
10 - Execute cycle
11 – Interrupt cycle
Then Boolean expression for a Control signal C5(for
example) then from the previous table

Prof. Shanmugasundaram | SENSE | VIT 26

Then Boolean expression for a Control signal C5(for example) then from the
previous table

𝐶5 = 𝑃. 𝑄. 𝑇2 + 𝑃 . 𝑄 . 𝑇2

P Q Cycle
0 0 Fetch
0 1 Indirect
1 0 Execute
1 1 Interrupt

Prof. Shanmugasundaram | SENSE | VIT 27

• LOAD AC:
t1: MAR ← (IR(address))
t2: MBR ← Memory
t3: AC ← (MBR)
• STORE AC
t1: MAR ← (IR(address))
t2: MBR ← (AC)
t3: Memory ← (MBR)
• ADD AC
t1: MAR ← (IR(address))
t2: MBR ← Memory
t3: AC ← (AC) + (MBR)

Prof. Shanmugasundaram | SENSE | VIT 28

• LOAD AC:
t1: MAR ← (IR(address))
t2: MBR ← Memory
t3: AC ← (MBR)
• STORE AC
t1: MAR ← (IR(address))
t2: MBR ← (AC)
t3: Memory ← (MBR)
• ADD AC
t1: MAR ← (IR(address))
t2: MBR ← Memory
t3: AC ← (AC) + (MBR)

Prof. Shanmugasundaram | SENSE | VIT 29

• LOAD AC:
t1: MAR ← (IR(address))
t2: MBR ← Memory
t3: AC ← (MBR)
• STORE AC
t1: MAR ← (IR(address))
t2: MBR ← (AC)
t3: Memory ← (MBR)
• ADD AC
t1: MAR ← (IR(address))
t2: MBR ← Memory
t3: AC ← (AC) + (MBR)

Prof. Shanmugasundaram | SENSE | VIT 30

• LOAD AC:
t1: MAR ← (IR(address))
t2: MBR ← Memory
t3: AC ← (MBR)
• STORE AC
t1: MAR ← (IR(address))
t2: MBR ← (AC)
t3: Memory ← (MBR)
• ADD AC
t1: MAR ← (IR(address))
t2: MBR ← Memory
t3: AC ← (AC) + (MBR)

Prof. Shanmugasundaram | SENSE | VIT 31

• LOAD AC:
t1: MAR ← (IR(address)) C8
t2: MBR ← Memory C5,CR
t3: AC ← (MBR) C10
• STORE AC
t1: MAR ← (IR(address))
t2: MBR ← (AC)
t3: Memory ← (MBR)
• ADD AC
t1: MAR ← (IR(address))
t2: MBR ← Memory
t3: AC ← (AC) + (MBR)

Prof. Shanmugasundaram | SENSE | VIT 32

• LOAD AC:
t1: MAR ← (IR(address)) C8
t2: MBR ← Memory C5,CR
t3: AC ← (MBR) C10
• STORE AC
t1: MAR ← (IR(address)) C8
t2: MBR ← (AC) C11
t3: Memory ← (MBR) C12,CW
• ADD AC
t1: MAR ← (IR(address)) C8
t2: MBR ← Memory C5,CR
t3: AC ← (AC) + (MBR) CALU,C7,C9

Prof. Shanmugasundaram | SENSE | VIT 33

• LOAD AC:
t1: MAR ← (IR(address)) C8
t2: MBR ← Memory C5,CR
t3: AC ← (MBR) C10
• STORE AC
t1: MAR ← (IR(address)) C8
t2: MBR ← (AC) C11
t3: Memory ← (MBR) C12,CW
• ADD AC
t1: MAR ← (IR(address)) C8
t2: MBR ← Memory C5,CR
t3: AC ← (AC) + (MBR) CALU,C7,C9

Prof. Shanmugasundaram | SENSE | VIT 34

 Problems with Hardwired Control Unit
• Sequencing & micro-operation logic gets complex
• Difficult to design, prototype, and test
• Resultant design is inflexible, and difficult to build upon
(Pipeline, multiple computation units, etc.)
• Adding new instructions requires major design and adds
complexity quickly

Prof. Shanmugasundaram | SENSE | VIT 36

 Hard wired and Micro programmed
Control Units
• In H/wired, control signals are generated by a micro instructions
are used cause register transfers and ALU operations.
• In Micro programmed control unit, the control unit is specified
by a micro program

Prof. Shanmugasundaram | SENSE | VIT 37

 Basic Idea
• For each micro operation control unit has to generate set of
control signals and each control line is either ON or OFF
• We can assume each control line by a binary digit.
• A Control word is then formed by these bits.
• Control word  sequence of control signals / control variables
at any given time  micro instructions.

Prof. Shanmugasundaram | SENSE | VIT 38

 Basic Idea
• All these micro-operations are converted in the form of control
signals and they are stored in control memory as a program 
micro-program.
• Micro-programs are written for every operations like FETCH,
DECODE & EXECUTE and these are called are ROUTINE.
• Routines are stored in control memory (which is inside the
Control Unit)

Prof. Shanmugasundaram | SENSE | VIT 39

• Hardware controls address sequence must be capable of
branching not only within the routine but also other routines.

Prof. Shanmugasundaram | SENSE | VIT 41

Address Sequence Logic

Register

Prof. Shanmugasundaram | SENSE | VIT 42

 Address Sequence Logic
• Steps:
– When the computer is on, the initial address is loaded on control
address register.
• This address is the address of first instruction , which activates the
instruction in fetch routine.
• Each micro instruction may sequence the next address in fetch routine.
• At the end of each routine the instruction is loaded in the IR.
– An MI may have the bits that specify the effective address of the
operand. In this EA can be reached through branching in MI.
– After completing the EA computing the add of the operand is
available in the MAR
– Based on the opcode bits of the MI, the execute routine will be
executed.
– When the execution is completed , control must return to fetch
instruction.

Prof. Shanmugasundaram | SENSE | VIT 44

 Horizontal Micro instruction

ADDRESS
F1 (3) F2 (3) F3 (3) CD (2) BR (2)
(7)

Micro operation Field

Prof. Shanmugasundaram | SENSE | VIT 45
Prof. Shanmugasundaram | SENSE | VIT 47
• F1, F2, F3  micro-operation field. The binary values vary
according to the instruction.

F1 F2 F3
ADD 001 000 000
SUB 000 001 000
XOR 000 000 001

• F1, F2, F3  totally 9 bits  29 combinations are possible.

ADDRE
F1 (3) F2 (3) F3 (3) CD (2) BR (2)
SS (7)

Prof. Shanmugasundaram | SENSE | VIT 48

 ADDRE
F1 (3) F2 (3) F3 (3) CD (2) BR (2)
SS (7)

• CD  Condition for Branching

– 00  unconditional
– 01  Indirect Address Field.
– 10  sign bit of AC
– 11  Zero value of AC
• BR  Branch Field
– 00  jump
– 01  CALL
– 10  RET
– 11  Not Use
• ADDRESS field  points the address to which
branching is taking place.
Prof. Shanmugasundaram | SENSE | VIT 49
Control Unit Micro architecture

Prof. Shanmugasundaram | SENSE | VIT 50

Block diagram of micro programmed
control unit

Prof. Shanmugasundaram | SENSE | VIT 51

Microinstruction sequencing techniques
• Based on the current micro instruction, condition flags, and
contents of instruction register a control memory address is
generated for next instruction.
• Based on the format of the address information in the micro
instruction it is classified in to
– Two address field
– Single address field and
– Variable format

Prof. Shanmugasundaram | SENSE | VIT 52

Two address field

Prof. Shanmugasundaram | SENSE | VIT 53

Single address field

Prof. Shanmugasundaram | SENSE | VIT 54

Variable format

Prof. Shanmugasundaram | SENSE | VIT 55