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-- Company:
-- Engineer:
--
-- Create Date: 22:29:15 05/20/2019
-- Design Name:
-- Module Name: DP - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity CU is
Port ( clk : in STD_LOGIC;
aGEb : in STD_LOGIC;
go : in STD_LOGIC;
rst : in STD_LOGIC;
CW : out STD_LOGIC_VECTOR (4 downto 0);
inFlag : out STD_LOGIC_VECTOR (1 downto 0);
done : out STD_LOGIC);
end CU;

architecture Behavioral of CU is
SIGNAL sreg : std_logic_vector (2 DOWNTO 0);

CONSTANT S0 : std_logic_vector (2 DOWNTO 0) :="000";

CONSTANT S1 : std_logic_vector (2 DOWNTO 0) :="001";
CONSTANT S2 : std_logic_vector (2 DOWNTO 0) :="010";
CONSTANT S3 : std_logic_vector (2 DOWNTO 0) :="011";
CONSTANT S4 : std_logic_vector (2 DOWNTO 0) :="100";
CONSTANT S5 : std_logic_vector (2 DOWNTO 0) :="101";
CONSTANT S6 : std_logic_vector (2 DOWNTO 0) :="110";

--SIGNAL CW : std_logic_vector (4 DOWNTO 0);

--SIGNAL inFlag : std_logic_vector (1 DOWNTO 0);
begin

fsm_transitions:process(clk,rst)
begin
if rst ='1' then
sreg<=s0;
elsif rising_edge(clk) then
case sreg is
 when S0 =>
if go='1' then
sreg<= S1;
else
sreg<=S0;
end if;
when S1=>
if go='1' then
sreg<= S2;
else
sreg<=S1;
end if;
when S2=>
if ( aGEb='1' ) then
sreg<=S3;
end if;
if ( aGEb='0' ) then
sreg<=S4;
end if;
when S3 =>
sreg<=S5;
when S4 =>
sreg<=S5;
when S5 =>
sreg<=S6;
when S6 =>
sreg<=S6;
when others =>
end case;
end if;
end process;

fsm_ouputs:process(sreg)
begin
CW<=std_logic_vector'("00000");
inFlag<=std_logic_vector'("00");
done <= '0';

case sreg is
when S0=>
CW<=std_logic_vector'("00001");
inFlag<=std_logic_vector'("01");
done <= '0';
when S1=>
CW<=std_logic_vector'("00010");
inFlag<=std_logic_vector'("10");
done <= '0';
when S2=>
CW<=std_logic_vector'("00000");
inFlag<=std_logic_vector'("00");
done <= '0';
when S3=>
CW<=std_logic_vector'("00100");
inFlag<=std_logic_vector'("00");
done <= '0';
when S4=>
CW<=std_logic_vector'("10100");
inFlag<=std_logic_vector'("00");
done <= '0';
 when S5=>
CW<=std_logic_vector'("00000");
inFlag<=std_logic_vector'("00");
done <= '0';
when S6=>
CW<=std_logic_vector'("01000");
inFlag<=std_logic_vector'("00");
done <= '1';
when others =>NULL;
end case;
end process;

end Behavioral;