BSS138

BSS138
N-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description Features
These N-Channel enhancement mode field
effect transistors are produced using ON • 0.22 A, 50 V. RDS(ON) = 3.5Ω @ VGS = 10 V
Semicondcutor’s proprietary, high cell density, DMOS
technology. These products have been designed to RDS(ON) = 6.0Ω @ VGS = 4.5 V
minimize on-state resistance while provide rugged, • High density cell design for extremely low RDS(ON)
reliable, and fast switching performance.These
products are particularly suited for low voltage, low • Rugged and Reliable
current applications such as small servo motor • Compact industry standard SOT-23 surface mount
control, power MOSFET gate drivers, and other package
switching applications.

D D

S
G S

SOT-23
G

Absolute Maximum Ratings TA=25oC unless otherwise noted

Symbol Parameter Ratings Units

VDSS Drain-Source Voltage 50 V
VGSS Gate-Source Voltage ±20 V
ID Drain Current – Continuous (Note 1) 0.22 A
– Pulsed 0.88
PD Maximum Power Dissipation (Note 1) 0.36 W
Derate Above 25°C 2.8 mW/°C
TJ, TSTG Operating and Storage Junction Temperature Range −55 to +150 °C
Maximum Lead Temperature for Soldering
TL 300 °C
Purposes, 1/16” from Case for 10 Seconds

Thermal Characteristics
RθJA Thermal Resistance, Junction-to-Ambient (Note 1) 350 °C/W

Package Marking and Ordering Information

Device Marking Device Reel Size Tape width Quantity
SS BSS138 7’’ 8mm 3000 units

2005 Semiconductor Components Industries, LLC. Publication Order Number:

September-2017, Rev. 3 BSS138/D
 BSS138
Electrical Characteristics TA = 25°C unless otherwise noted

Symbol Parameter Test Conditions Min Typ Max Units

Off Characteristics
BVDSS Drain–Source Breakdown Voltage VGS = 0 V, ID = 250 µA 50 V
∆BVDSS Breakdown Voltage Temperature ID = 250 µA,Referenced to 25°C mV/°C
72
∆TJ Coefficient
IDSS Zero Gate Voltage Drain Current VDS = 50 V, VGS = 0 V 0.5 µA
VDS = 50 V, VGS = 0 V TJ = 125°C 5 µA
VDS = 30 V, VGS = 0 V 100 nA
IGSS Gate–Body Leakage. VGS = ±20 V, VDS = 0 V ±100 nA

On Characteristics (Note 2)
VGS(th) Gate Threshold Voltage VDS = VGS, ID = 1 mA 0.8 1.3 1.5 V
∆VGS(th) Gate Threshold Voltage ID = 1 mA,Referenced to 25°C –2 mV/°C
∆TJ Temperature Coefficient
RDS(on) Static Drain–Source VGS = 10 V, ID = 0.22 A 0.7 3.5 Ω
On–Resistance VGS = 4.5 V, ID = 0.22 A 1.0 6.0
VGS = 10 V, ID = 0.22 A, TJ = 125°C 1.1 5.8
ID(on) On–State Drain Current VGS = 10 V, VDS = 5 V 0.2 A
gFS Forward Transconductance VDS = 10V, ID = 0.22 A 0.12 0.5 S

Dynamic Characteristics
Ciss Input Capacitance VDS = 25 V, V GS = 0 V, 27 pF
Coss Output Capacitance f = 1.0 MHz 13 pF
Crss Reverse Transfer Capacitance 6 pF
RG Gate Resistance VGS = 15 mV, f = 1.0 MHz 9 Ω

Switching Characteristics (Note 2)

td(on) Turn–On Delay Time VDD = 30 V, ID = 0.29 A, 2.5 5 ns
tr Turn–On Rise Time VGS = 10 V, RGEN = 6 Ω 9 18 ns
td(off) Turn–Off Delay Time 20 36 ns
tf Turn–Off Fall Time 7 14 ns
Qg Total Gate Charge VDS = 25 V, ID = 0.22 A, 1.7 2.4 nC
Qgs Gate–Source Charge VGS = 10 V 0.1 nC
Qgd Gate–Drain Charge 0.4 nC

Drain–Source Diode Characteristics and Maximum Ratings

IS Maximum Continuous Drain–Source Diode Forward Current 0.22 A
VSD Drain–Source Diode Forward VGS = 0 V, IS = 0.44 A(Note 2) 0.8 1.4 V
Voltage
Notes:
1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of
the drain pins. RθJC is guaranteed by design while RθCA is determined by the user's board design.

a) 350°C/W when mounted on a

minimum pad..

Scale 1 : 1 on letter size paper

2. Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2.0%

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 BSS138
Typical Characteristics

1 3.4
VGS = 10V 6.0V 4.5V
3.5V

DRAIN-SOURCE ON-RESISTANCE
3
0.8 3.0V VGS = 2.5V
ID, DRAIN CURRENT (A)

RDS(ON), NORMALIZED
2.6

0.6
2.2
3.0V
2.5V
1.8 3.5V
0.4
4.0V
4.5V
1.4
6.0V
0.2 2.0V
1 10V

0.6
0
0 0.2 0.4 0.6 0.8 1
0 0.5 1 1.5 2 2.5 3
ID, DRAIN CURRENT (A)
VDS, DRAIN TO SOURCE VOLTAGE (V)

Figure 1. On-Region Characteristics. Figure 2. On-Resistance Variation with

Drain Current and Gate Voltage.

2 4.1
ID = 110mA
DRAIN-SOURCE ON-RESISTANCE

ID = 220mA
RDS(ON), ON-RESISTANCE (OHM)

1.8
VGS = 10V 3.5
RDS(ON), NORMALIZED

1.6
2.9
1.4 TA = 125oC
2.3
1.2
1.7
1
TA = 25oC

0.8 1.1

0.6 0.5
-50 -25 0 25 50 75 100 125 150 0 2 4 6 8 10
o VGS, GATE TO SOURCE VOLTAGE (V)
TJ, JUNCTION TEMPERATURE ( C)

Figure 3. On-Resistance Variation with Figure 4. On-Resistance Variation with

Temperature. Gate-to-Source Voltage.

0.6 1
VDS = 10V VGS = 0V
IS, REVERSE DRAIN CURRENT (A)

o o
TA = -55 C 25 C
0.5
ID, DRAIN CURRENT (A)

125oC 0.1
TA = 125oC
0.4
25oC
0.3 0.01
-55oC
0.2
0.001
0.1

0 0.0001
0.5 1 1.5 2 2.5 3 3.5 0 0.2 0.4 0.6 0.8 1 1.2
VGS, GATE TO SOURCE VOLTAGE (V) VSD, BODY DIODE FORWARD VOLTAGE (V)

Figure 5. Transfer Characteristics. Figure 6. Body Diode Forward Voltage Variation

with Source Current and Temperature.

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 BSS138
Typical Characteristics

10 100
f = 1 MHz
ID = 220mA VDS = 8V
VGS, GATE-SOURCE VOLTAGE (V)

25V VGS = 0 V
8 80
30V

CAPACITANCE (pF)
6 60

CISS
4 40

COSS
2 20

CRSS
0 0
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 0 10 20 30 40 50

Qg, GATE CHARGE (nC) VDS, DRAIN TO SOURCE VOLTAGE (V)

Figure 7. Gate Charge Characteristics. Figure 8. Capacitance Characteristics.

10 5
P(pk), PEAK TRANSIENT POWER (W) SINGLE PULSE
RθJA = 350°C/W
100µs 4 TA = 25°C
ID, DRAIN CURRENT (A)

1
1ms
RDS(ON) LIMIT
10ms
3
100ms
0.1 1s
DC 2
VGS = 10V
0.01 SINGLE PULSE
RθJA = 350oC/W 1
TA = 25oC

0.001 0
0.1 1 10 100 0.001 0.01 0.1 1 10 100 1000
VDS, DRAIN-SOURCE VOLTAGE (V) t1, TIME (sec)

Figure 9. Maximum Safe Operating Area. Figure 10. Single Pulse Maximum
Power Dissipation.

1
r(t), NORMALIZED EFFECTIVE TRANSIENT

D = 0.5
RθJA(t) = r(t) * RθJA
o
THERMAL RESISTANCE

0.2 RθJA = 350 C/W

0.1 0.1

0.05 P(pk)
0.02 t1
0.01
0.01 t2
TJ - TA = P * RθJA(t)
SINGLE PULSE Duty Cycle, D = t1 / t2

0.001
0.0001 0.001 0.01 0.1 1 10 100 1000
t1, TIME (sec)

Figure 11. Transient Thermal Response Curve.

Thermal characterization performed using the conditions described in Note 1a.
Transient thermal response will change depending on the circuit board design.

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