YMCA UNIVERSITY OF SCIENCE & TECHNOLOGY, FARIDABAD

M.TECH IIIrd Sem. CBS EXAMINATION, DEC-2012

SUBJECT - VLSI Architecture (E-705(A)- V)

Time: 3Hrs M.Marks: 60

Note: (1) Attempt any five question.
(2) All questions carry equal marks.
(3) In Case of numerical problems, assume data wherever not provided.
(4) Be precise in your answer.

Q. No. 1 Distinguish between computer terminologies in each of the following groups.

(a) Parallel processing at the job level, the task level, the inter instruction level and the intra
instruction level.
(b) Uniprocessor system versus multiprocessor system 6× 2 = 12

Q. No. 2 Explain which is a superior technique.

(a) Parallelism versus VLIW
(b) Serial processing versus parallel processing
6× 2 = 12

Q. No. 3 6× 2 = 12
(a) For a computer network distinguish between static & Dynamics interconnection networks.
(b) Compare the features of RISC & CISC processors.

Q. No. 4 6× 2 = 12
Define Pipelining concept. Explain the pipeline mechanism in CPU. Define the parameters
for measuring efficiency of pipelined system.
(a) Look at this code sequence:
SW R3, 512(R0) ;M[512] ← R3 (cache index 0)
LW R1, 1024(R0) ;R1 ← M[1024] (cache index 0)
LW R2, 512(R0) ;R2 ← M[512] (cache index 0)

Assume a direct-mapped, write-through cache that maps 512 and 1024 to the same block,
and a four- word write buffer that is not checked on a read miss. Will the value in R2 always be
equal to the value in R3?

Q. No. 5 (12)
Assume we have a computer where the clock per instruction (CPI) is 1.0 when all memory
accesses hit in the cache. The only data accesses are loads and stores, and these total 50% of
the instructions. If the miss penalty is 25 clock cycles and the miss rate is 2%, how much
faster would the computer be if all instructions were cache hits?

Q. No. 6 Write short note on any two parts: 6 × 2 = 12

(a) Differentiate between symmetric & distributed shared memory architecture
(b) Alpha 364 & HT protocol
(c) MSI, MESI, MOESI