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1636 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO. 7, JULY 2011

A 5 Mb/s UWB-IR Transceiver Front-End for

Wireless Sensor Networks in 0.13 m CMOS
Silvia Soldà, Member, IEEE, Michele Caruso, Andrea Bevilacqua, Member, IEEE,
Andrea Gerosa, Senior Member, IEEE, Daniele Vogrig, Member, IEEE, and Andrea Neviani, Member, IEEE

Abstract—This paper presents a fully integrated UWB-IR trans-
ceiver front-end operating in the 7.25–8.5 GHz band designed for
high overall transmission and detection energy efficiency and ro-
bustness to interferers. The transceiver front-end features a pulsed
transmitter that wakes up when triggered by a digital signal, gener-
ates a pulse, and automatically switches-off in less than 2 ns. The re-
ceiver includes an LNA, a VGA, a squarer, a windowed integrator,
and a comparator to perform PPM demodulation of the data. A
prototype of the transceiver front-end was integrated in a 0.13 m
CMOS technology. The transmitter delivers 13 pJ/pulse to the an-
tenna consuming about 190 pJ/b, with an efficiency , well
in excess of comparable designs. Using pulse polarity scrambling, it
complies with the FCC spectral emission limits up to a pulse repeti-
tion frequency (PRF) of 5 MHz. The receiver achieves a sensitivity
of 87 dBm at a PRF of 100 kHz, and of 70 dBm at a PRF of
5 MHz, while consuming 4.2 mW. It can tolerate interferers up to
12 dBm at 5.4 GHz.
Index Terms—CMOS, impulse radio, ultra-wideband, wireless
sensor networks.
I. INTRODUCTION
advantage of extreme duty cycling, at the price of an inefficient
spectral occupation. On the contrary, conventional radios are
always consuming power when communicating. Despite their
power consumption can be traded for lower noise performance
at the receiver, or a lower output power at the transmitter, lever-
aging a reduced data rate, the need of a frequency synthesizer
sets a floor to the minimum possible current constantly drained
from the supply.
In this work, we propose an approach where the transmitter
is designed to generate pulses with the maximum energy (at the
desired pulse rate) allowed by the power spectral density regu-
lations, with the twofold advantage of improving significantly
its efficiency with regards to existing transmitter designs and
of relaxing the sensitivity requirements of the receiver. Addi-
tionally, to reduce the risk of blocking by in-band interferers,
we chose the 7.25–8.5 GHz frequency range, in the UWB high
band, which is far from any other commonly used communica-
tion channel, and is the only common range where UWB radios
can operate in Europe, USA and Japan with similar regulations
[7]. We thus obtained a system which is robust to interferers,

W IRELESS sensor networks (WSN) mark the confluence

of the technological trends in sensing, computation,
and wireless communications towards smaller size, lower
and efficient in terms of total energy spent to transmit and re-
ceive a bit over a given range. We implemented prototypes of
the transceiver front-end in a 0.13 m CMOS technology. Some
power and lower cost electronics [1], [2]. They can be used
digital control and calibration loops have been left out, as they
for a plethora of applications: from the elimination of the
are beyond the scope of this research work.
wiring cost for light switches, thermostats, fire alarm, chemical
The paper is organized as follows: the main issues and trade-
sensors, etc., to inventory monitoring, location of boxes and
offs of UWB impulse radios are illustrated in Section II, where
pallets in warehouses, inertial sensing in some entertainment
a link budget is derived as well as the specifications for both
applications, wearable or implanted medical devices.
the transmitter and the receiver. In Section III, the design of
The preferred solution to realize a radio link for such net-
the building blocks of the transceiver front-end is discussed,
works must feature an ultra-low-power consumption (0.1–10
with particular regards to the optimization of the transmitter ef-
mW) while conveying a relatively low data rate (0.01–10 Mb/s)
ficiency, and to the bias current reuse in the receiver. Results of
over a short-range (0.1–10 m). Ultra-wideband Impulse-Radio
experiments carried out on implemented prototypes of the pro-
(UWB-IR) is becoming one of the preferred solutions to realize
posed transceiver front-end are reported in Section IV, while
such a wireless link [3]–[6]. UWB-IR can be a very low energy
a discussion on the possibilities to extend the communication
solution since it can be implemented with relatively simple
range of the proposed wireless link beyond the original 3 m
transceiver architectures. On the other hand, this simplicity
target is carried out in Section V. Eventually, Section VI wraps
often implies a low transmitter efficiency and a relatively high
up the paper.
sensitivity of non-coherent receivers to in-band interferers.
Compared to classic narrowband radios, UWB-IR can take II. SYSTEM-LEVEL CONSIDERATIONS
There is a sharp difference between conventional narrowband
radios and impulse radios, despite the basic idea of digital com-
Manuscript received November 12, 2010; revised January 31, 2011; accepted
February 07, 2011. Date of publication May 27, 2011; date of current version
munications is always there. In both cases, a digital symbol is
June 24, 2011. This paper was approved by Guest Editor Domine Leenaerts. associated to a continuous-time pulse to enable transmission
This work was supported by the Cariparo Foundation, Italy, under Project over the wireless medium. However, while in conventional ra-
WISE-WAI.
The authors are with Dipartimento di Ingegneria dell’Informazione, Univer-
dios the pulse duration and the symbol period are approximately
sità di Padova, 35131 Padova, Italy (e-mail: andrea.bevilacqua@dei.unipd.it). equal, in impulse radios the pulse occupies a tiny fraction of
Digital Object Identifier 10.1109/JSSC.2011.2144070 the symbol period. This means that in impulse radios the data

0018-9200/$26.00 © 2011 IEEE

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SOLDÀ et al.: A 5 Mb/s UWB-IR TRANSCEIVER FRONT-END FOR WIRELESS SENSOR NETWORKS IN 0.13 m CMOS
rate and the bandwidth of the transmitted signal are inde-
pendent to each other.1 Moreover, while typically in conven-
tional radios the transmission power is set by the regulatory
limits, in impulse radios it is the maximum transmitted pulse
energy to be controlled. These differences have a strong impact
on the link budget of the radios. To gain insight, let us con-
sider the simple case of a communication system employing a 1
bit-per-symbol modulation scheme, while transmitting 1 pulse
per bit. The pulse energy at the receiver input is related to
the average received power by
(1)
where is the transmitted power, is the transmitted
pulse energy, and is the path loss. For a given receiver noise
performance, the communication link will show a target bit error
rate (BER) if a large enough is accumulated at the receiver.
In a conventional radio, where is fixed, we can use the
same receiver and expand the communication range for a given
BER trading a longer range for a lower data rate. On the con-
trary, in an impulse radio, since is fixed, the communica-
tion range is independent on the data rate for a given receiver
noise performance. However, in this case the received power
changes as is varied, for a given path loss. As such,
the concept of receiver sensitivity, as given in terms of received
power, becomes quite slippery in impulse radios, since it does
not convey complete information if not associated to the data
rate. In the following, we will see how these basic considera-
tions translate into a link budget and guide the choices on the
system architecture for minimum energy consumption.
A. Link Budget
In the foregoing discussion, we have observed that the
starting point in building a link budget for an impulse radio is
the limit on the maximum transmitted pulse energy set by the
regulatory bodies. The FCC, for example, limits the maximum
power spectral density (PSD), , to 41.3 dBm/MHz in
the 3.1-to-10.6 GHz band, which translates to the following
constraint:
(2)
From (2), it is clear that to maximize the communication range
one should maximize the pulse bandwidth and reduce the data
rate, a scenario highly compatible with the wireless sensor net-
works. However, hardware limitations come also into play when
designing the system. Having a large calls for circuits with
a large passband fractional bandwidth, which are not straight-
forward to implement at low power. Moreover, wide pulse
bandwidths may make the system more susceptible to interferers.
Last, but not least, pulses with large energies may be difficult to
implement with the ultra-scaled CMOS technologies because
of the limited available supply voltage. Such technologies are
anyway necessary to keep the energy consumption and cost low,
while enjoying good radio frequency circuit performance.
The key point in the system-level design is thus the choice
of the combination of transmitted pulse energy, modulation
scheme and receiver noise performance to achieve a given
1Of course we have . of a simple pulse position modulation (PPM) scheme. Such
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1637
communication range. This choice is not unique and has an
impact on the overall energy consumption of the transceiver.
There are several examples [4]–[6], [8]–[12] in which the
adopted strategy is that of minimizing the total energy spent
by the transmitter to generate a pulse, , regardless of
the actual energy of the pulse delivered at the antenna, .
These designs show almost consistently a TX efficiency
of a few percent at most, and implicitly
demand an extremely sensitive receiver in order to cover
a significant communication range. Since sensitivity costs
power, this explains why the energy-per-bit figure of UWB-IR
receivers published in the literature is normally significantly
larger than that of transmitters [4], [6], [8], [9].
One goal of this work is to achieve minimum overall energy
consumption for the transmission and reception of one bit of in-
formation for the desired communication range, i.e., for a fixed
path loss . The main design variables at the system level are
then the energy of the transmitted pulse and the link mod-
ulation scheme. is related to the transmitter energy con-
sumption through the efficiency , and determines the
pulse energy at the receiver input, , through (1). The choice of
the modulation sets the receiver noise specification and thus the
achievable energy consumption per bit at the receiver, .
The exploration of the design space led to the conclusion that
the approach promising better results was to maximize
and , to enable the choice of a modulation scheme such that
the receiver architecture is mostly simplified. In addition, in this
way the system does not need an ultra low noise receiver to
accommodate the desired communication range, which allows
to reduce the energy consumption.
It should not be surprising that this approach yields an im-
provement over the state-of-the-art given the significant margin
between the energy-per-bit figure of receivers and transmitters
mentioned before, while it is reasonable to expect the minimum
overall energy consumption to be reached when .
The transceiver is designed for a generic wireless sensor net-
work, with specifications on communication range and data rate
loosely set as a few meters and a few Mb/s. The selected pulse
bandwidth is GHz, from 7.25 to 8.5 GHz, which is the
only common range where UWB radios can operate in Europe,
USA and Japan with similar regulations [7]. Additionally, this
choice reduces the risk of blocking by in-band interferers, since
this portion of the spectrum is far from any other commonly
used communication channel, in particular WLANs at 2.4 GHz
and 5.4 GHz.
Given the emission regulations in the selected band [7],
the choice of a maximum data rate Mb/s makes
the system compliant to the average power density limit
( 41.3 dBm/MHz) if the pulse energy is pJ.
If the envelope of the pulse is Gaussian, then the transmitter
should be capable of delivering a peak-to-peak voltage swing
of about 3 V at the antenna input to meet the pJ
specification. The circuit-level design of the transmitter and of
the matching network required to deliver a 3 V pulse to the
antenna with a supply voltage are discussed in
Section III-A.
The relatively large value of allows the adoption
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TABLE I
LINK BUDGET OF THE PROPOSED SYSTEM
Fig. 1. Structure of the data packet of the proposed wireless sensor network
communication link.
a modulation format gives the opportunity of implementing
a non-coherent receiver architecture, that does not need any
power hungry local oscillator or high resolution ADC. In fact,
the receiver just needs a voltage comparator, as described in
Section III-B. To guarantee an uncoded BER , the
PPM modulation requires dB, where is
the receiver input referred noise PSD [13]. Assuming antennas
with dB gain, and recalling that the path loss can be
estimated to be about dB at 8 GHz [14], the receiver
noise figure can be as high as 20 dB for the com-
munication range to be in excess of 3 m. This is convenient,
as non-coherent receivers tend to be more noisy than their
coherent counterpart due to the non-linear nature of the energy
detector (see details in the Appendix).
The link budget of the proposed system is summarized in
Table I, where is the link margin. It is worthwhile to un-
derline again that once the pulse energy, on the transmitter side,
and the noise figure, on the receiver side, are set, the communi-
cation range does not change as a function of the data rate.
B. Synchronization
In order to maintain the low complexity nature of the trans-
ceiver, a simple and effective synchronization algorithm is
required. We developed an algorithm similar to the one de-
scribed in [10]. It is based on a preamble with 19 repetitions of
a Gold code, sent at the pulse repetition frequency
of MHz, followed by an inverted Gold code
sequence used to indicate the end of the synchronization phase.
With this choice, all the data rates up to 5 Mb/s for the payload
transmission can be accommodated without exceeding the FCC
mask limits. The structure of each data packet is reported in
Fig. 1.
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO. 7, JULY 2011
Fig. 2. Simulated probability of detection as a function of the received pulse
energy.
The PPM-modulated data is received by energy detection:
the square of the input signal is integrated over two consecu-
tive time windows; the collected energies are then compared to
identify the position of the transmitted pulse and thus recover
the data. During the synchronization phase, a 31-bit word is re-
ceived and correlated to all the possible time-shifted versions
of the Gold code to identify the position of the transmitter time
reference. This operation can fail, as the received pulse is inte-
grated over a time window, , which is much shorter than the
pulse repetition period (1/PRF), such that the transmitter and re-
ceiver operation could possibly have no overlap in time. If this
occurs, the receiver time reference is delayed by ns,
and the synchronization procedure is repeated. This process is
iterated up to 14 times, until the entire pulse repetition period
is explored. The number of repetitions of the Gold code in the
preamble is thus explained: 15 words is the minimum required
to implement the algorithm, while four repetitions are taken as
a margin in case the transmission begins ahead of the receiver
wake-up. Once one correlator flags the correct acquisition of the
Gold code, the receiver aligns itself to the transmitter clock and
looks for the inverted Gold code sequence. When the latter is
eventually found, the reception of the payload begins.
The drawback of such a simplicity is that the synchronization
time resolution is equal to . This is usually not an issue, as
the pulse duration is much shorter than . However, it may
happen that the received pulse partly lies outside the integra-
tion window. This would impair the detection capability of the
receiver because some of the signal energy is not accounted
for in the integration. The only way to preserve the receiver
performance is to make the probability of these events negli-
gible, making larger. On the other hand, a larger integra-
tion window worsens the receiver performance because it in-
creases [13]. Following these considerations, we singled
out ns as a good design compromise.
The performance of the synchronization algorithm in terms
of probability of detection , i.e the probability that synchro-
nization is correctly declared, has been assessed by using a be-
havioral model of the system similar to the one reported in [13].
The position of the received pulse within an integration window
is modeled as a uniformly distributed random time shift. The
simulation result is reported in Fig. 2 as a function of . It can
be observed that at the sensitivity level, i.e., aJ, the
probability of detection is larger than 0.9, usually considered a
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SOLDÀ et al.: A 5 Mb/s UWB-IR TRANSCEIVER FRONT-END FOR WIRELESS SENSOR NETWORKS IN 0.13 m CMOS
Fig. 3. Block diagram of the UWB-IR transmitter.
Fig. 4. Block diagram of the non-coherent UWB-IR receiver front-end.
threshold for the correct operation of the system [15]. Such a
result shows that the chosen 15 ns integration window makes
the exact position of the received pulse within an irrelevant
parameter.
III. CIRCUIT-LEVEL DESIGN
As discussed in Section II-A, the choice of the transceiver
architecture was driven by the objective of minimizing the en-
ergy budget required to transmit and receive a bit of informa-
tion. The appropriate strategy devised to achieve this goal was
then to increase the energy of the transmitted pulse as much as
allowed by the regulations and consequently relax the receiver
specifications. Together with the options enabled by the wide-
band, pulsed nature of the UWB-IR communication scheme,
this strategy has a major impact on the circuit-level design of
both the transmitter and the receiver, whose block diagrams are
shown in Fig. 3 and Fig. 4, respectively. In general, it should be
pointed out that both the pulsed TX and the non-coherent, en-
ergy-detection RX, do not require precise frequency references,
that are notoriously among the most power-demanding building
blocks in coherent radio front-ends. Moreover when an impulse
radio is used, its inherent duty cycled nature can be exploited
to further reduce the average power consumption by switching
the RX and TX circuits off between the generation/detection of
successive pulses. As described below, the TX proposed in this
work is designed to minimize its duty cycle.
A. Transmitter
The transmitter, depicted in Fig. 3, consists of a digitally-
controlled LC oscillator (DCO), which generates the carrier fre-
quency roughly centered in the middle of the 7.25–8.5 GHz
frequency range, a frequency divider by 16 (prescaler),2 a
simple triangular pulse generator, and a combined mixer and
power amplifier (MXR-PA). The MXR-PA mixes the DCO
signal and the triangular pulse producing a Gaussian pulse
with central frequency and bandwidth GHz. The
duty-cycled operation is realized with the activation of the
transmitter by a trigger signal (which allows a straightforward
implementation of PPM and OOK modulation) and then shut
off by a control signal generated by the frequency divider.
Then, for each transmitted pulse, the circuit draws power for
16 times the carrier period , plus an additional delay
2The ratio between the pulse duration and the carrier frequency period
is approximately equal to 16.
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1639
Fig. 5. Circuit schematic of the DCO.
which depends on the duration of the DCO start-up transient.
In order to reduce the energy consumption of the transmitter, it
is then important to minimize the oscillator start-up delay.
Since the choice of non-coherent detection in the RX brings
the benefit of relaxed requirements on the accuracy of the carrier
phase and frequency, then the DCO has been implemented using
an LC-tank differential oscillator whose start-up delay is kept
low by designing a tank with a moderately low quality factor
and by adding switches that force the initial transient, as
explained below. A solution based on a digital multi-loop ring
oscillator was also considered, [16], but the propagation delay
through the ring is much more dependent on process spread with
respect to the LC-product in the tank of the realized DCO.
The DCO schematic is shown in Fig. 5. Transistors
act as switches that help the start-up transient by unbalancing
one of the oscillator output nodes towards ground and the other
toward . The digital control signals of the switches, ,
with , 6, 7, 8, are activated for a short time interval by
the same trigger signal that enables the transmission of a pulse.
Depending on the value of an external binary control signal
SCR, either the pair and , or the pair and , is
activated in order to switch on the corresponding transistors
and or and , thus forcing the sign of the initial voltage
unbalance of the oscillator differential output. This feature allows
to implement scrambling of the pulse polarity simply by driving
the control signal SCR with a pseudo noise sequence. Scrambling
suppresses the spectral lines that would otherwise be present in
the output PSD due to the periodicity of the TX output signal. The
suppression of the spectral lines increases the maximum pulse
energy value compliant with the emission regulation for a given
PRF. Frequency tuning of the DCO is provided by means of a
binary-weighted 5-bit capacitor bank realized with varactors,
which are digitally controlled. Because of the employed non-co-
herent demodulation scheme, a precise frequency control for the
DCO is not required. Yet some coarse frequency tuning/calibra-
tion is to be performed at the start-up by means of, e.g., a FLL,
which is then turned off once the calibration is completed. Such a
calibration loop has not been implemented in the reported design,
although the most critical block, namely the prescaler, is there,
as it is the divider used to control the duration of the transmitted
pulse. In the measurements reported in Section IV the DCO has
been manually tuned. The prescaler is realized by cascading four
dynamic T-flip-flops. The T-flip-flop is built as a ring of three
static CMOS inverters, with the loop broken by two pass-gates,
one between the first and the second inverter, the other between
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1640
Fig. 6. Circuit schematic of MXR-PA.
the second and the third inverter. The pass-gates are driven by
opposite phases of the digital input signal, that is either the
output of the previous flip-flop or, for the first flip-flop in the
cascade, the buffered output of the DCO.
The MXR-PA, whose schematic is shown in Fig. 6, generates
a Gaussian pulse by multiplying a triangular pulse and the car-
rier coming from the DCO. The triangular pulse is generated by
means of two inverters in cascade designed with slow rising and
falling edges and driven by the prescaler output. Consequently
the pulse completes a rising and a falling transition in 16 DCO
oscillations, featuring a full swing between ground and . The parallel capacitor
The pulse drives the gate of , while transistors act
as switches driven by a buffered replica of the DCO output sig-
nals and . In order to reduce the power consump-
tion of the DCO buffers, a 900 pH inductor is connected in
parallel to the MXR-PA input capacitance to resonate it at the
transmitter central frequency. As a result, the buffer power con-
sumption is just the 1% of the total power dissipated by the TX.
It is worth to notice how, at the end of the triangular pulse, the
MXR-PA turns off and stays off until a new triangular pulse and
carrier signal are produced by the divider and the DCO. As this
happens only when a new pulse trigger is delivered to the TX,
the MXR-PA, as the DCO and the divider, draws power only for
the duration of each pulse, thus taking maximum advantage of
the duty-cycled nature of the UWB-IR.
The MXR-PA must deliver the Gaussian pulses to a 50
single-ended antenna with the maximum efficiency and the de-
sired pulse energy. As discussed in Section II-A, the transmitted
pulse energy we target is around 18.5 pJ, corresponding to a
peak-to-peak voltage swing of about 3 V at 50 antenna ter-
minal. On the other hand, the maximum peak-to-peak voltage
at the MXR-PA differential output is about 1.6 V with a supply
voltage , which implies that a 1: impedance trans-
formation with is required, together with a differential to
single-ended conversion. Both goals can be achieved with a res-
onant matching network based on a monolithic transformer with
a parallel capacitor on the primary coil and a capacitor in
series with the secondary coil, as shown in Fig. 6. In Fig. 7, an
equivalent model of the network is reported: is the magnetic
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO. 7, JULY 2011
Fig. 7. Equivalent model of the MXR-PA integrated matching network.
coupling factor, the turn ratio between primary and secondary
coils, is the load resistance, while and model
the losses of the primary and secondary coil, respectively. These
losses may significantly degrade the output power and the trans-
mitter efficiency, so a careful design of the matching network is
required. It can be shown [17] that the value of resulting in
the highest possible matching network efficiency is given by
(3)
where is chosen such that , and and
are the quality factor of the primary and secondary coil,
respectively. The transformer was designed with a concentric
spiral winding layout [18] in the thick top metal, using itera-
tively (3) to size the components, starting from an initial con-
servative estimate of and with the constraint
on the transformer ratio . The parameters of the
resulting design, further adjusted to compensate the effect of
parasitics and of the bond wire inductance, are ,
nH and fF, , and , that cor-
respond to a theoretical matching network efficiency of 65%.
was sized to resonate the primary coil
inductance at , resulting into a value of 4.25 pF, of which
roughly 2.45 pF contributed by the parasitic capacitance of the
MXR-PA output nodes, and the remaining 1.8 pF realized using
MIM capacitors. An electrical lumped model of the transformer
[19] to be used in circuit simulations has been derived from the
physical layout with the aid of a 2.5D electromagnetic simulator.
B. Receiver
The main specifications of the receiver have been derived
in Section II-A: a noise figure of 20 dB, PPM demodulation
capability, bandwidth from 7.25 to 8.5 GHz, input matching
to a single-ended, 50 antenna. On top of that, to enhance
the robustness of the receiver to substrate and supply noise, a
fully-differential topology for the gain stages has been speci-
fied. The design target is to minimize power consumption. The
specifications are affordable for a non-coherent receiver, whose
block diagram is shown in Fig. 4. The core of the receiver is
the energy detector, composed by a block, from now on called
squarer, whose output current is proportional to the square of the
differential voltage at its input, by a windowed integrator, and
by a voltage comparator. A low-noise amplifier (LNA) and a
variable-gain amplifier (VGA) have been included ahead of the
energy detector to relax its noise requirements and to increase
the dynamic range of the receiver.
The LNA, shown on the left side of Fig. 8, features a differen-
tial topology with inductive source degeneration and LC reso-
nant load. The single-ended-to-differential signal conversion at
the LNA input is realized by an integrated transformer. The flux
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SOLDÀ et al.: A 5 Mb/s UWB-IR TRANSCEIVER FRONT-END FOR WIRELESS SENSOR NETWORKS IN 0.13 m CMOS
Fig. 8. Circuit schematic of the LNA and VGA.
Fig. 9. Circuit schematic of the energy detector (squarer and integrator).
leakage inductances of the transformer are used together with
the LNA RLC-series input impedance and the additional capac-
itor in parallel with the transformer primary coil to realize a
wideband input matching network with a ladder topology [20].
The VGA, illustrated on the right side of Fig. 8, is realized as
the cascade of two differential common-source stages with an
LC resonant load. The two stages are stacked so that they reuse
the same bias current. Gain programmability is implemented in
the second stage by adding the two transistors and in
parallel with the stage drivers and . and can
be independently turned on by two digital control signals
and connected directly to their gates, thus subtracting bias
current to the drivers and, consequently, reducing the stage gain.
The resulting combined gain of the LNA and VGA cascade can
then be set to 30, 27, 23, or 21 dB.
In order to save area, the VGA inductors layout has
been realized using stacked coils, as opposed to the inductors
and in the LNA, and the input transformer T, that feature
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1641
a concentric spiral winding layout in the thick top metal in order
to minimize the parasitic resistance that would be critical for
noise. The simulated noise figure for the LNA and VGA cascade
is around 7 dB and is almost insensitive to the VGA gain setting.
The nominal current consumption of the LNA and VGA is 1.25
mA, plus an additional 0.25 mA for biasing.
The circuit schematic of the squarer is reported on the left side
of Fig. 9 [13], [21]. Although a passive mixer is sometimes pro-
posed to realize this block [3], in this case an active circuit has
been preferred in order to introduce some conversion gain. As-
suming for simplicity an ideal long-channel current to voltage
characteristic, the differential input voltage can
be expressed as
(4)
where , and are the electron mobility
and gate capacitance, respectively, is the form factor of
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1642 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO. 7, JULY 2011

transistors and . Since the drain current of M3 can be

expressed as , (4) transforms in

(5)

Hence the drain current of M1 can be expressed as

(6)

Applying a similar analysis to transistors M2–M4, one obtains

(7)

Combining (6) and (7), the sum of the two drain currents be- Fig. 10. Micrograph of the chip. Die area is mm including the pads.
comes proportional to the square of the input signal, as reported
in (8):
these trade-offs, and a bias current budget lower than 1.5 mA,
(8) we set , and m m,
which approximately corresponds to .
Although (8) does not highlight any dependence on the bias cur- The current has to be integrated in order to detect the
rent , once an optimal current density for the transistors has energy received in a given time span. This operation is per-
been singled out, the squarer conversion gain results to be formed with the integrator shown on the right side of Fig. 9: it
proportional to the bias current , posing a design trade-off is composed of a cascode common-source amplifier acting as a
between gain and power consumption. Another critical issue transimpedance amplifier, with a capacitive feedback. During
from the perspective of power efficiency is the size of transis- the reset phase (signal is high), the integrating capacitors
tors and , which must be times larger than and are discharged and the amplifier sets its bias point. During
, consuming an times larger current. These transistors act phase , the current from the squarer flows through capacitor
as voltage followers: has to shift the source of and hence it is integrated over a time window of duration
by , hence the drain current of is proportional to ns; similarly, during phase the current is inte-
, squared. Notice that without the use of and grated on . Therefore the voltage difference stored on
the squarer topology would have to be a pseudo differential one, the capacitors is proportional to the differential energy received
making the circuit sensitive to common-mode disturbances at in the two time spans:
its input. Moreover, the drain current of each half circuit would
now be proportional to squared, with an overall decrease
by a factor 1/4 of the conversion gain for a given coefficient
in (8).
As discussed in more detail in [13], the transfer function from (10)
the gate of to its source is
where and are the received energy allocated in the time
window corresponding to a transmitted 1 and 0 respectively.
(9) Therefore a simple comparator driven by and can de-
tect which between and is largest and hence perform the
PPM demodulation. It is worth considering that after the squarer
the desired signal has been downconverted, therefore the band-
where is the total width specification for the integrator is less demanding than for
capacitance at the output node (source of ) and the other blocks in the front-end. Thus, a bias current as low as
. The pole in (9) must be at a higher frequency with 175 is enough.
respect to the upper limit of the signal bandwidth (i.e., 8.5 GHz),
in order to avoid an equivalent filtering effect on . Consid-
ering that, at fixed current density, , the larger IV. MEASUREMENT RESULTS
, the more the DC gain in (9) approximates unity, although A prototype of the transceiver was realized in a 0.13 m
this comes at the price of higher consumption. On the con- CMOS technology with 8 metal layers and thick top metal for
trary, the bandwidth is basically insensitive to , because both high-Q inductors. A micrograph of the chip is shown in Fig. 10.
and contain terms proportional to that Measurements on test structures revealed a transistor threshold
become dominant for values of greater than 3. Considering 22% higher than predicted by the foundry models in the worst
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SOLDÀ et al.: A 5 Mb/s UWB-IR TRANSCEIVER FRONT-END FOR WIRELESS SENSOR NETWORKS IN 0.13 m CMOS
Fig. 11. Pulse waveform measured at the TX output.
Fig. 12. Measured PSD of a transmitted pulse train at MHz (dashed
line) and MHz (solid line); in the latter case the PSD is reported
without (gray) or with (black) the scrambling operation enabled.
case corner. As a consequence, the chip performance was as-
sessed at a voltage supply , that is 10% higher
than the nominal.
A TX pulse waveform is reported in Fig. 11. The corre-
sponding pulse energy is pJ, just 1.5 dB lower
than the target specification discussed in Section II-A, while
the total energy dissipated by the TX to generate the pulse
is pJ/pulse. Thus the transmitter features an
efficiency . the transmitted pulse energy was derived based on the reported
The spectrum of a pulse train measured at MHz
(dashed line) and MHz (solid line) is reported in
Fig. 12. The expected PSD scaling with the PRF is clearly ob-
served. The spectrum measured at PRF=5 MHz is shown both in
the case the scrambling of the pulse polarity with a pseudo-noise
sequence is disabled (solid grey trace) and when it is enabled
(solid black trace). In the latter case, the spectral lines typical of
a periodic waveform disappear, and the PSD of the transmitted
signal is compliant to the FCC mask limits with some margin. In
a typical WSN, the data rate may be somewhere between 1 kb/s
and 1 Mb/s. For such rates (or lower rates), the TX spectrum
is safely within the FCC mask. For higher rates, some form of
power control loop could be required to enhance the robustness
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Fig. 13. Measured DCO tuning range and corresponding TX continuous-wave
power.
of the TX. In our case, such a control has not been implemented:
a careful design supported by corner and Monte Carlo simula-
tions turned out to be sufficient, as shown by Fig. 12.
For testing purposes, the TX can be configured to generate
a continuous-wave output by locking the gate of in Fig. 6
to . This configuration allows to measure the tuning range
of the DCO and the continuous-wave power generated by the
TX. The result of the measurements is reported in Fig. 13: the
TX is able to output as much as 11.4 dBm over a 3-dB band-
width larger than 2 GHz; the carrier frequency can span from
6.6 to 9 GHz in 80 MHz steps, showing a 31% tuning range for
the DCO.
A performance comparison with other recent UWB-IR trans-
mitter designs is reported in Table II. A meaningful compar-
ison with other UWB-IR transmitters must include the pulse
energy at the antenna, , since it is the parameter that sets
the communication range for a given noise performance of the
receiver, as discussed in Section II. Unfortunately, most of the
papers on UWB-IR transmitters do not report the transmitted
pulse energy, and rather focus on the energy consumed to gen-
erate a pulse, . It is important to stress that, given two
transmitters with the same energy consumption, but different
efficiency , the one characterized by the largest can
cover a given communication range with a less sensitive, and
thus less power hungry, receiver. In order to include in the
comparison of UWB-IR transmitters, had to be estimated
from the experimental data available in the papers. For [4]–[6],
time domain pulse measurements. In [9]–[12], the PSD of the
transmitted spectrum is shown. Thus, in this case, the pulse en-
ergy was obtained by integrating the PSD over the pulse band-
width, divided by the PRF at which the spectrum was mea-
sured. Table II shows that the presented design outperforms
state-of-the-art UWB-IR transmitters by a factor greater than 2
in terms of efficiency.
The RX input matching is shown in Fig. 14. The input re-
flection coefficient is dB roughly between 7.1 and
8 GHz. Compared to simulations, the passband of the LNA
turned out to be shifted towards lower frequencies by about
400 MHz. Consequently, the TX was also manually tuned down
by 400 MHz during the tests.
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1644
TABLE II
PERFORMANCE SUMMARY OF UWB-IR TRANSMITTERS
Fig. 14. Measured receiver input matching .
Fig. 15. Measured receiver conversion gain.
Since the RX operation is based on energy detection, the
most useful figure to characterize its conversion gain is the ratio
between the voltage sampled at the integrator output and the
energy, measured at the RX input, of the pulse that generated
the RX voltage response. This figure was measured at different
pulse energies for two values of the current drawn by the LNA
and VGA, the nominal value (1.25 mA) and an increased value
(1.5 mA): The results are reported in Fig. 15. The conversion
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO. 7, JULY 2011
gain can be decreased by 8, 18 or 21 dB by reducing the VGA
gain.3
The RX sensitivity has been assessed by measuring the link
BER. The data rate has been initially set to kb/s as
suggested in [3] to measure the normalized sensitivity4 .
Fig. 16 shows the BER versus the receiver input power is this
testing scenario. The measured sensitivity for a BER is
dBm. The RX sensitivity has also been assessed
at Mb/s. The result, reported in Fig. 16, shows that, as
expected, the sensitivity scales to 70 dBm, proportionally to
the increase in the data rate. The receiver robustness towards
the interferers has been checked: it takes a 12 dBm blocker at
5.4 GHz to increase the BER from to , while blockers
at 2.4 GHz cause no decrease in the system performance.
The measured RX power consumption is 4.2 mW. The mea-
sured leakage current is as low as 350 nA when the bias cur-
rents of the LNA, VGA, squarer and integrator are turned off.
The maximum rate at which the RX can operate is higher than
5 Mb/s, the limit set by the TX compliance to the FCC mask. The
maximum data rate at which the RX operation could be assessed
is 27.8 Mb/s. At this data rate the RX is always on and the cor-
responding energy consumption is 150 pJ/b. At lower data rates
the receiver is intended to be duty-cycled, a feature that would
make the energy consumption independent on the data rate, but
that has not been implemented in the reported receiver. Simu-
lations show that the wideband LNA, VGA and squarer can be
quickly turned on and off and that the above energy/bit figure
should not be difficult to attain. The RX energy consumption at
5 Mb/s is 840 pJ/b without duty-cycling, a result in line with the
state-of-the-art.
The RX performance has been compared to that of a few re-
cent designs in Table III. Clearly, the choice of relaxing the re-
ceiver noise performance pays off in terms of power and energy
consumption. Nonetheless, the proposed receiver shows a sen-
sitivity comparable to the state-of-the-art.
3Recall that because of the squarer operation a variation of 1 dB in the VGA
gain corresponds to a variation of 2 dB in the conversion gain of the receiver.
4As discussed in Section II, in an IR the sensitivity defined as the average
input power for a given BER scales proportionally to the data rate, thus
two RX exhibiting a sensitivity of 80 dBm at 1 Mb/s and 70 dBm at 10
Mb/s, respectively, are actually featuring the same perfomance in terms of com-
munication range. The normalized sensitivity defined as
where is the data rate at which was measured, is then the right figure
to compare the performance of different receivers.
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SOLDÀ et al.: A 5 Mb/s UWB-IR TRANSCEIVER FRONT-END FOR WIRELESS SENSOR NETWORKS IN 0.13 m CMOS 1645

TABLE III
PERFORMANCE SUMMARY AND COMPARISON OF UWB-IR RX

Fig. 16. Measured BER at kb/s and at Mb/s. Fig. 17. Calculated receiver noise figure as a function of additional VGA gain
.

The measured receiver sensitivity dBm at
kb/s implies a minimum energy of each received pulse
aJ, in excellent agreement with the circuit-level simulations
of the receiver. Given that the measured energy of the trans-
mitted pulse is pJ and that the antenna gain consid-
ered in the link budget calculations (see Table I) is dB,
then a line-of-sight link of 3 m can be attained with a margin
of dB. As already mentioned, the communication
range is independent of the actual data rate up to the maximum
Mb/s allowed by the spectral regulations.
V. FURTHER EXTENDING THE COMMUNICATION RANGE
As discussed in Section II and experimentally confirmed in
Section IV, the proposed transceiver is tailored to cover a com-
munication range of 3 m. It is interesting, however, to investi-
gate ways to expand its operation range, e.g., to 10 m.
One possibility of achieving this goal is to make use of some
processing gain, that is to transmit multiple pulses per bit
at the expense of a reduced data rate. If the received pulses are
summed coherently before the demodulation is performed, a
processing gain as large as is achieved. However,
since in our receiver the ADC is substituted by a simple 1-bit
comparator, such an operation cannot be performed. A simple by
majority decision rule can instead be applied to the demodulated
pulses, yielding a reduced processing gain of . 2.2 V peak-to-peak amplitude, and 1.25 GHz bandwidth,
Thus, in our case would be needed to expand the
communication range to 10 m, with a strong decrease of the
maximum attainable data rate. Worse than that, the energy spent
by the link per bit would be 100 times higher. In general, the ap-
proach of transmitting more pulses per bit does not seem to be
an efficient one in terms of energy consumption, as this example
illustrates.
To improve the communication range, a better approach
would be to decrease the receiver noise figure . As de-
tailed in the Appendix, the energy detector has a strong impact
on , despite the LNA and VGA provide as much as
30 dB gain. Assuming to add another amplifier stage just after
the VGA without impairing the noise figure of the amplifier
cascade, (13) and (14) can be used to find out the additional
gain required to lower the receiver noise figure by a given
amount. The result is shown in Fig. 17: with dB the
receiver noise figure is lowered by more than 10 dB, which is
the requirement for the communication range to be in excess of
10 m. The penalty in the receiver energy consumption due to
this additional block is estimated to be about 25%, which would
not sensibly impair the energy consumption performance of the
proposed transceiver.
VI. CONCLUSION
A fully integrated UWB-IR CMOS transceiver front-end
is presented. The transmitter outputs Gaussian pulses with
corresponding to a transmitted energy of 13 pJ/pulse. The link
supports data rates up to 5 Mb/s covering ranges in excess
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1646
Fig. 18. Equivalent model for the calculation of the receiver noise figure.
to 3 m, despite the non-coherent receiver shows a relatively
high 20 dB noise figure. The choice of the 7.25–8.5 GHz band
for the communication results in a high robustness towards
narrowband interferers, thus compensating the disadvantage
of a higher path loss. The energy efficiency achieved by the
transmitter, i.e. 186 pJ/b to transmit one bit of information, and
the limited power consumption of the receiver, i.e. 4.2 mW,
demonstrate that the approach of demanding more energy per
pulse at the transmitter to relax the receiver noise performance
is effective. Despite some digital control and calibration loops
are still missing in the presented design, the reported results
give favorable indications about the feasibility of a sub-nJ/b
short-range radio link.
APPENDIX
The proposed system is based on the energy detection, which
makes the front-end non-linear. As a consequence, the compu-
tation of the receiver noise figure is not straightforward, and the
classic Friis formula does not apply.
To derive the noise figure of the receiver, we make use of the
equivalent model shown in Fig. 18. Since the comparator takes
its decision on a sample of the signal output by the integrator, it
is possible to work with signals sampled at the PRF as follows:
in Fig. 18 is the sample of the output desired signal, while
is the sample of the output noise. The sample of the noise
due to all the circuits after the squarer is represented by , X. Liu, Y.-S. Wang, X.-J. Yuan, and C. H. Heng, “A 0.92/5.3 nJ/b
while and are the noise of the channel and of the LNA
plus VGA, respectively. The input desired signal is . The
receiver can thus be simply described by an ideal squarer with
conversion gain , defined as in Section IV.
The input signal-to-noise ratio , where
is the expected value, is
(11)
being the PSD of the noise of the channel, i.e.,
dBm/Hz. The output signal-to-noise ratio
, instead, results
(12)
where , and is the noise factor of the LNA
plus VGA cascade. For the receiver to show a target BER, we
need a certain . Assuming that the latter is such that
, we solve (12) for the receiver sensitivity:
(13)
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO. 7, JULY 2011
The receiver noise figure is eventually calculated as
(14)
where is given by (13).
There are two important things to notice: First, even if the re-
ceiver is totally noiseless the signal-to-noise ratio degrades by
6 dB as the input signal is demodulated. This is due to the non-
linearity of the energy detector. As shown in (14), we prefer to
define the receiver noise factor keeping this 6 dB degrada-
tion out. As a consequence, the parameter reported in
Section II-A is related to as , while, ob-
viously, . Second, unlikely the common linear
case, the noise figure of the receiver does not depend only on the
gain and the noise of the receiver building blocks, but it depends
also on the BER performance (i.e ) at which it is calculated,
as clearly shown by (13) and (14).
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Silvia Soldà (S’06–M’10) received the Laurea
degree (summa cum laude) and the Ph.D. degree in
electronic and telecommunication engineering from
the University of Padova, Italy, in 1999 and 2009,
respectively.
In 2000, she joined ST Microelectronics, Milan,
Italy, as an analog design engineer within the
Memory Product Division, where she was involved
in the design of Flash memories for telecom appli-
cations. In 2001, she moved to ST Microelectronics
Wireline Division, where she worked at the design
and testing of BiCMOS and CMOS circuits for signal processing in cooperation
with Tioga Technology, Israel, and the University of Ghent, Belgium. In 2004,
she joined the Automotive Power Division of Infineon Technologies Italia,
Padova, where she has been responsible of the development of high-voltage
ICs for automotive applications.
She is currently with the University of Padova as a Post-Doc research fellow.
She is mainly interested in the design of analog and mixed-signal CMOS circuits
for analog signal processing. In particular, her work focuses on the analog imple-
mentation of error-control decoders and on RF circuits for UWB applications.
Michele Caruso received the B.Eng. and M.Eng. de-
grees in electronic engineering from the University of
Padova, Italy, in 2005 and 2007, respectively. From
2009 to 2010, he worked on low-power RF trans-
ceivers at the University of Padova as a collaborator.
He is currently working towards the Ph.D. degree at
the University of Padova.
His main research focuses on the design of
RF transceiver front-ends and ultra-wideband mi-
crowave radars.
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1647
Andrea Bevilacqua (S’02–M’05) received the
Laurea and Ph.D. degrees in electronics engineering
from the University of Padova, Italy, in 2000 and
2004, respectively.
From 1999 to 2000, he was an intern with Infi-
neon Technologies, Munich, Germany. In 2001, he
visited the Microelectronics Laboratory of the Uni-
versity of Pavia, Italy. From 2002 to 2003, he was
a Visiting Scholar with the University of California,
Berkeley. Presently, he is an Assistant Professor with
the Department of Information Engineering, Univer-
sity of Padova, Italy. His current research interests include the design of RF/mi-
crowave integrated circuits and the analysis of radars and wireless communica-
tion systems.
Dr. Bevilacqua serves as a member of the Technical Program Committee of
the IEEE European Solid-State Circuits Conference and of the IEEE Interna-
tional Conference on Ultra-Wideband. He is an Associate Editor of the IEEE
TRANSACTIONS ON CIRCUITS AND SYSTEMS II.
Andrea Gerosa (M’99–SM’07) received the M.S.
and Ph.D. degrees in electrical engineering in 1995
and 1998, respectively, from the University of
Padova, Italy, where he is now Associate Professor.
Dr. Gerosa is a senior member of the IEEE and
has published more than 70 papers in international
journals or conference proceedings. His performed
research activities are within the area of analog
and mixed integrated circuits, for high-frequency,
low-noise and low-power applications. Currently he
is working on UWB transceivers and radars.
Daniele Vogrig (M’02) was born in Cividale del
Friuli (Udine), Italy, in 1976. He received the
Laurea degree in electronics engineering and the
Ph.D. degree in electronics and telecommunication
engineering from the University of Padova, Padova,
Italy, in 2001 and 2005, respectively.
He is currently an Assistant Professor with the Uni-
versity of Padova. His research interests mainly cover
the design of CMOS integrated circuits for analog
and digital signal processing. He is also involved in
the design of some FPGA projects for various types
of applications.
Andrea Neviani (M’05) received the Laurea degree
(cum laude) in physics from the University of
Modena, Italy, in 1989, and the Ph.D. degree in
electronics and telecommunication engineering from
the University of Padova, Italy, in 1994. He was an
EAP graduate student at the University of California,
Santa Barbara, in 1994.
From 1994 to 1998, he was a Research Associate
at the University of Padova, where, since November
1998, he holds an Associate Professor position. From
November 1998 to November 1999, he was a vis-
iting engineer at Rutherford Appleton Laboratory, Oxfordshire, UK. In his early
career, he worked on numerical simulation, modelling and characterization of
compound semiconductor devices for high frequency applications, and on the
study of methods for the statistical simulation of VLSI circuits. At present, his
main interest is the design of RF integrated circuits for communication and radar
applications, and mixed-signal circuits for biomedical applications. In his ca-
reer, he has been co-author of about 100 journal articles and conference papers.
Dr. Neviani serves as an Associate Editor of the IEEE TRANSACTIONS ON
CIRCUITS AND SYSTEMS I.