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Technology options to reduce contact resistance in nanoscale III-V MOSFETs

Article  in  ECS Transactions · April 2015

DOI: 10.1149/06604.0125ecst

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 ECS Transactions, 66 (4) 125-134 (2015)
10.1149/06604.0125ecst ©The Electrochemical Society

Technology Options to Reduce Contact Resistance in Nanoscale III-V MOSFETs

Rinus T.P. Lee, W.-Y. Loh, R. Tieckelmann, T. Orzali, C. Huffman, A. Vert

G. Huanga, M. Kelmana, Z. Karima, C. Hobbs, RJ.W. Hill, S.S. Papa Rao

SEMATECH, 257 Fuller Road, Suite 2200, Albany, NY 12205, USA

a
AIXTRON Inc, 1139 Karlstad Dr, Sunnyvale, CA 94089, USA

III-V semiconductors have emerged as the leading candidate to

replace Si as the n-FET channel material for future low power
logic applications. However, to realize the full performance
benefits of III-V channels, it is crucial that external parasitic
resistance (Rext) be minimized. Among the different components of
Rext, contact resistance (RC), between metal and source/drain (S/D)
junctions, has become the critical focus. Historically, multi-layered
Au-based contacts (e.g. Au/Ge/III-V) are used in III-V processing
to lower RC. However, the renewed interest in III-V
semiconductors has attracted an increasing interest in developing
Au-free contacts to III-V with low RC. In addition, a “silicide-like”
metal contact process for III-V was recently developed by reacting
Ni with InGaAs to form Ni-InGaAs. This is significant as it
enables self-alignment and offers the option of using a common
S/D contact metal in a hetero-integrated device flow (e.g. Ge/III-
V). In this paper, we will review these RC reduction options and
present some of our recent results on contact/junction engineering
to lower RC in III-V MOSFETs.

Introduction

Compound semiconductors (III-V) are projected to extend Moore’s law beyond the
scaling limits of silicon technology (1 – 3). However, III-V device research has
historically been based on HEMT and MOS-HEMT architectures (4, 5). These are
excellent test vehicles to assess the performance limits of III-V transistors but are not
compatible with CMOS technology. Recent developments in III-V devices and processes
for CMOS have focused extensively on the MOSFET architecture (6 – 8). This has led to
significant improvements in drive current and device density (9 – 11). Further
improvement in device drive current will be limited by the increasing contribution of
external parasitic resistance to device resistance. The resistance of a device can be
expressed as
Rdev = Rch + Rext [1]

where Rdev is the device on-resistance, Rch is the channel resistance and Rext is the
external parasitic resistance. With the aggressive downscaling of gate lengths and the
introduction of various strain engineering techniques, Rch has been reduced dramatically
to the point where Rext begins to dominate Rdev (12). Likewise, the use of III-V
semiconductors will reduce Rch further and performance could ultimately be limited by
Rext.

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 ECS Transactions, 66 (4) 125-134 (2015)

1
2500 10

External Parasitic Resistance, Rext (Ω.µ m)

Surface Channel MOSFETs (a) (b)
0
Buried Channel MOSFETs 10

Contact Resistivity ρ co (Ω-cm )

2
2000 (7) 10
-1
SBH=0.6 eV
-2
10
1500 -3
10
(14) -4
10
1000 -5 SBH=0.4 eV
10
-6
(16) (9) 10
500
(8) (18) -7 SBH=0.2 eV
(8) (19) (20) 10
(15)
(17) (19) (21) -8
0 10
ITRS requirement for Rext in 2022
-9
10 18 19 20
2010 2011 2012 2013 2014 10 10 10
-3
Year Active Doping Concentration, ND (cm )

Figure 1. (a) Rext values for both surface and buried channel III-V MOSFETs as function of year
shows a significant reduction in Rext. (b) Plot of theoretically calculated contact resistivity values
versus active doping concentration for In0.53Ga0.47As as a function of different Schottky-Barrier
Heights (13).

There is an increasing effort to develop solutions to address the issue of escalating

Rext in III-V MOSFETs (14 – 21). This has led to a significant reduction in Rext for III-V
MOSFETs as shown in Figure 1(a). However, Rext values are beginning to saturate at ~
200 Ω⋅µm (19 – 21). This indicates that we are approaching the lower limits of Rext
scaling with current solutions. It is crucial to develop new solutions to reduce Rext further
and realize the full performance benefits of introducing III-V semiconductors into CMOS
technology. To reduce Rext, it is critical to lower resistances at the contact-to-
semiconductor interface (RC) of the source/drain (S/D) regions. RC is given by

ρ co RSheet
RC = [2]
L 
WC × tan  C 
 LT 

where ρco is the contact resistivity, RSheet is the S/D sheet resistance, WC and LC are the
width and length of the contact hole, respectively and LT is the transfer length. To lower
RC, we can reduce ρco according to equation [2]. This is accomplished either by reducing
the metal Schottky-Barrier Height (SBH) and/or increasing the semiconductor active
doping concentration (ND) as shown in Figure 1(b). Hence, there is a strong motivation to
develop solutions to reduce SBH and/or increase ND to boost III-V MOSFET
performance.
In this paper, technology options for reducing RC will be discussed. We will also
discuss the development of a novel interlayer process to enhance the thermal stability of
Ni-InGaAs contacts to In0.53Ga0.47As. This extends the compatibility of Ni-InGaAs
contacts on III-V to typical BEOL processing temperatures. TCAD simulations were also
performed to understand the impact of contact design (i.e. use of self-aligned and non-
self-aligned contacts) on III-V MOSFET performance.

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 ECS Transactions, 66 (4) 125-134 (2015)

0.8
S: Pinning Factor
0.7 S = 1 (No Pinning)

Electron Barrier Height, Φ e (eV)

S = 0 (Severe Pinning)
0.6 S=1

0.5 Pt, Ref. [33]

Ti, Ref. [32]
0.4 Au, Ref. [34]
Pd, Ref. [35]
Ag, Ref. [33]
0.3

0.2 S = 0.078

0.1 Ni-InGaAs, Ref. [36]

Mo, SEMATECH
0.0
4.2 4.5 4.8 5.1 5.4 5.7
Metal Workfunction, Φ M (eV)

Figure 2. Experimentally measured electron barrier heights (Φe) on In0.53Ga0.47As for

different metal workfunctions (ΦM). The solid line show the linear fit to the experimental
data. The dotted line represents the Schottky-Mott limit with S = 1.

Technology Options to Reduce Contact Resistance (RC)

(A) Effect of Schottky-Barrier Height (SBH) on RC

The two main approaches to reduce SBH in III-V are metal work function (ΦM)
selection (22 – 26) and Fermi level depinning (27 – 29). For N-channel devices, it is
critical that ΦM be low, so that SBH for electrons (i.e. electron barrier height) is small.
According to the Schottky-Mott model (30), the electron barrier height (Φe) is given by
the difference between ΦM and the electron affinity of the semiconductor (χS). However,
experimentally, this relationship is generally not observed due to charge transfer at the
metal-semiconductor interface. This reduces Φe to

Φ e = S (Φ M − Φ CNL ) + (Φ CNL − χ S ) [3]

where S is the pinning factor and ΦCNL is the charge neutrality level (31). The solid line in
Figure 2 represents the linear fitting of experimental data (32 – 36) reported in the
literature and gives Φe = 0.078ΦM - 0.12 eV. From this, we obtain a value of S = 0.078
and ΦCNL = 4.751 eV. The charge neutrality level measured from the bottom of the
conduction band is given by ΦO = ΦCNL - χS. By assuming χS = 4.5 eV, we obtain a value
of 0.251 eV for ΦO. The extracted S value of 0.078 is close to the Bardeen limit (i.e. S =
0). This implies that most metals on In0.53Ga0.47As will exhibit an Φe = ~ 0.2 eV due to
Fermi level (FL) pinning. Hence, the effectiveness of ΦM selection to reduce SBH for RC
scaling is compromised.
It was reported that the insertion of a thin dielectric between metal and III-V (i.e.
metal-insulator-semiconductor contacts) reduces/eliminates FL pinning (27 – 29). Two
hypotheses based on the origin of the FL pining (i.e. FL models) have been proposed.
The metal-induced-gap state model (37, 38) states that when a metal and semiconductor
are in contact, the metal electron wave function penetrates into the semiconductor

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 ECS Transactions, 66 (4) 125-134 (2015)

bandgap. This charges the semiconductor’s intrinsic interface states and subsequently
moves the Fermi level at the interface towards the charge neutrality level of the gap states.
By inserting a thin insulator at the metal-semiconductor interface, the metal wave
function is attenuated in the dielectric and does not penetrate into the semiconductor. This
reduces the charges available to drive the Fermi level towards the charge neutrality level.
On the other hand, the bond polarization model (39) suggests that the interaction of the
metal and semiconductor wave functions forms an interface having both metal and
semiconductor-like electronic states. This results in the formation of an interface dipole
that pins the Fermi level. According to this model, when a thin insulator is inserted, an
additional dipole is formed between the insulator and the semiconductor native oxide.
This induces a SBH shift to offset the pinned Φe. These reported results suggest that MIS
contacts could help to reduce SBH for further RC scaling.

(B) Effect of Active Doping Concentration on RC

As shown earlier, ρco is strongly dependent on both SBH and ND. To elucidate the
dependence of ρco on ND, we compared the ρco for Mo contacts on silicon (Si) doped
In0.53Ga0.47As as shown in Figure 3. Si was used as it is a widely studied n-type dopant in
III-V due to its low diffusivity. Doping in this work was realized with either in situ
doping or ion implantation. Mo was selected as contact metal for its excellent thermal
stability on III-V.
Figure 3(a) plots total resistance versus contact spacing for Mo/Si in situ doped (I/D)
fins and Mo/Si ion implanted (I/I) fins. Sheet resistance (RS) is 75 ohms/sq for I/D fins
and 410 ohms/sq for I/I fins. Qualitatively, this indicates that ND in I/D fins are higher
than I/I fins. Figure 3(b) also shows statistically that ρco for I/D fins are significantly
lower than I/I fins, with an average ρco of 1.59×10-8 Ω⋅cm2. A significant percentage
(25%) of the extracted ρco are within 6.0×10-9 Ω⋅cm2. This suggests that Mo/Si I/D fins
will meet ITRS ρco requirements for N5 with further optimization. The degradation of ND
and poor ρco values obtained for I/I fins are attributed to the incomplete recrystallization
of implant damaged III-V fins (24). Our data clearly shows that Si implant at room
temperature is not suitable for III-V fin doping.

-3
1500 o
10 o
Mo/Si implanted at 25 C, (I/I) (a) Mo/Si Implanted at 25 C, (I/I) (b)
Mo/Si insitu doped, (I/D) Mo/Si Insitu Doped, (I/D)
-4
Contact Resistivity, ρ co (Ω -cm )

10
2

o
1200 Mo/Si Implanted at 25 C
Number of FINS = 20
Total Resistance (Ω)

WFIN = 35 nm -5
10
900
Slope = 215.71
-6
Rs = 410 Ω/sq 10
600
-7 Mo/Si Insitu Doped
10
Slope = 39.70
300 Rs = 75 Ω/sq -8
10
ITRS ρco requirement for N5
-9
0 10
1 2 3 4
Contact Spacing (µm)

Figure 3. (a) Plot of total resistance as a function of fin TLM contact spacing for III-V
fins with Si in situ doping and Si ion implantation. (b) Box plots showing the statistical
distribution in ρco for III-V fins doped with Si via in situ doping and ion implantation.

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 ECS Transactions, 66 (4) 125-134 (2015)

RS: ohms/sq 100

150 (a) (b) In0.53Ga0.47As = 100 nm
280.0 250.0
280.0
295.0

Sheet Resistance, RS (ohms/sq)

325.0 265.0
100 310.0 280.0 80
325.0
295.0 295.0
325.0 340.0
50 310.0
Y-axis (mm)

325.0
295.0
355.0 340.0
60 Silicon
0 310.0 355.0
295.0280.0 Average RS = 77 ohms/sq

-50 310.0
310.0
310.0 40
-100
280.0
265.0
265.0 280.0 265.0
-150 Tellurium
20 Average RS = 9.56 ohms/sq
-150 -100 -50 0 50 100 150
X-axis (mm)

Figure 4. (a) Sheet resistance map of a 300 mm In0.53Ga0.47As on Si wafer doped with
sulfur by monolayer-doping. (b) Plot of sheet resistances for 100 nm thick In0.53Ga0.47As
doped with silicon and tellurium via in situ doping during epitaxial growth.

To overcome the limitation of ion implantation for III-V fin doping, we developed a
damage free sulfur-monolayer doping (S-MLD) process for III-V doping (40 – 42). New
sulfate-based S-MLD chemistries with lower Hazardous Materials Identification System
(HMIS) profiles were also developed (43). This addresses the environmental, safety and
health concerns of using sulfide-based S-MLD chemistries (40 – 42) for high volume
manufacturing (HVM). In this work, 300 mm In0.53Ga0.47As on Si wafers were doped
using S-MLD via a 300 mm wet station. Figure 4(a) shows the RS map for a sulfate-
doped In0.53Ga0.47As on Si wafer. An average RS value of 303 ohms/sq with a standard
deviation of 8% was achieved. ND is estimated to be ~1×1019 cm-3 from Hall and SIMS
measurements. This compares well with values achieved with Si I/I. ND values for S-
MLD are expected to increase with optimization as S is not an amphoteric dopant in III-V.
On the other hand, Si is an amphoteric dopant in III-V; it can behave either as a donor
or acceptor depending on the lattice site it occupies. This amphoteric nature results in
self-compensation (44, 45) and leads to low ND values for Si doped In0.53Ga0.47As.
Typical ND values reported for Si doped In0.53Ga0.47As via implantation are limited to ~
1×1019 cm-3 (46). To eliminate self-compensation, we evaluated the effectiveness of non-
amphoteric dopants such tellurium (Te). Te doped In0.53Ga0.47As on Si was grown on an
AIXTRON CRIUS-R 300 mm MOCVD system using 300 mm Si (100) substrates. Pd-
purified hydrogen was used as the carrier gas; Trimethylgallium (TMGa),
Trimethylindium (TMIn), and Diethyltelluride (DETe) were used as precursors. Figure
4(b) shows that Te in situ doped In0.53Ga0.47As exhibit lower sheet resistances (RS) than
Si in situ doped In0.53Ga0.47As. This implies that Te is able to achieve higher ND values
compared to Si due to the elimination of the self-compensation mechanism. Our data
show that both Te and S are promising n-type dopants to achieve high ND in III-V to
reduce Rext.

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 ECS Transactions, 66 (4) 125-134 (2015)

Contact Design Options to Reduce External Parasitic Resistance (Rext)

(A) Self-Aligned Ni-InGaAs Contacts with Enhanced Thermal Stability

Conventionally, self-aligned contacts are used in Si CMOS for S/D contact
metallization. This is realized with self-aligned silicide technology, which minimizes the
contact-to-gate distance and reduces Rext. Until recently, an equivalent of the self-aligned
“silicide-like” approach for III-V MOSFETs did not exist. The development of NiGeSi
contacts for III-V (46) sparked a renewed interest in developing “silicide-like” contact
processes for S/D metallization. This led to the development of Ni-InGaAs contacts (47 –
49). The ability to use Ni as a common S/D contact metal is highly desirable as it reduces
process complexity in a hetero-integrated CMOS flow (i.e. Ge/III-V MOSFETs on Si).
However, Ni-InGaAs interfacial roughness increases with temperature and this could lead
to degraded MOSFET off-state leakage characteristics (50). Additionally, Ni-InGaAs has
been shown to phase segregate and/or agglomerate at temperatures as low as 400 oC (51).
As a result, Ni-InGaAs is incompatible with temperatures used in back-end-of-line
(BEOL) processes. This could limit the use of Ni-InGaAs in future Ge/III-V MOSFETs.
To increase the thermal stability of Ni-InGaAs, we developed a new interlayer (IL)
process (52) for Ni-InGaAs metallization (i.e. Ni/IL/ In0.53Ga0.47As). Figure 5(a) shows
that RS values for Ni-InGaAs remain stable even at 500 oC when formed with an IL.
Additionally, the interfacial morphology of Ni-InGaAs formed with an IL is superior to
that of Ni-InGaAs without an IL as shown in Figure 5(b) and (c). HRTEM reveals that an
excellent crystalline Ni-InGaAs/InGaAs interface is maintained at 400 oC when an IL is
used.

500
(a) Ni-InGaAs (0 nm Interlayer)
5 nm Interlayer (IL)
Sheet Resistance, RS (ohms/sq)

10 nm Interlayer (IL)
400

300

200

100

250 300 350 400 450 500

o
Temperature ( C)

Figure 5. (a) Sheet resistance values of Ni-InGaAs films formed with 0, 5 and 10 nm
interlayers as a function of temperatures from 250 – 500 oC. (b) – (c) TEM micrographs
of the Ni-InGaAs/InGaAs interface; (b) without an interlayer, (c) with a 5 nm interlayer.

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 ECS Transactions, 66 (4) 125-134 (2015)

Figure 6. Structure of the III-V MOSFET used in the simulation of drive current (IDsat) as
a function of LGap (i.e. distance from gate-spacer to S/D contact) and contact resistivity
(ρco) for (I) devices with non-self-aligned Mo contacts and (II) self-aligned Ni-InGaAs
contacts.

1000 3500
(a) 2 % for L = 10 nm (b) 4 % for L = 10 nm
Gap Gap
8 % for L = 20 nm 3000 19 % for L = 20 nm
Gap Gap
800
Drive Current, IDsat (µ A/um)

Drive Current, IDsat (µ A/um)

2500

600
2000

1500 LG = 15 nm
400 LG = 100 nm
Mo, LGap = 0 nm 1000 Mo, LGap = 0 nm
200 Mo, LGap = 10 nm Mo, LGap = 10 nm
Mo, LGap = 20 nm 500 Mo, LGap = 20 nm
Ni-InGaAs Ni-InGaAs
0 -10 -9 -8 -7 -6 -5
0 -10 -9 -8 -7 -6 -5
10 10 10 10 10 10 10 10 10 10 10 10
2 2
Contact Resistivity, ρco (Ω
cm ) Contact Resistivity, ρco (Ω
cm )

Figure 7. Plot of simulated drive current (IDsat) as function of ρco with different LGap for
devices with (a) LG = 100 nm and (b) LG = 15 nm.

(B) Impact of Self-Aligned and Non-Self-Aligned Contacts on III-V MOSFET

Device pitch scaling and improvements in lithography has led to the development of
non-self-aligned contact processes for S/D metallization (e.g. silicide-last processing with
self-aligned contact vias). This negates the benefits of using self-aligned contacts for Rext
scaling. TCAD simulations with device geometries based on N7 specifications were
performed to understand the impact of contact schemes on III-V MOSFET drive current
(IDsat) performance. Mo and Ni-InGaAs were selected as contact metals for the non-self-
aligned and self-aligned contact schemes, respectively. Figure 6 shows the device
structure and contacts used in this simulation. We defined the distance from gate-spacer
to S/D contact as the gap length (LGap) and set it to be 0, 10 and 20 nm. Fig. 7(a) and 7(b)
plots IDsat as a function of ρco and LGap for devices with LG = 100nm and 15nm,

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 ECS Transactions, 66 (4) 125-134 (2015)

respectively. We assumed that ρco is similar for all metals at a given ND as SBH for most
metals are pinned near to 0.2 eV as shown earlier. Comparing IDsat enhancement at ρco =
5×10-9Ω⋅cm2 for LGap = 10 and 20nm shows that the self-aligned Ni-InGaAs approach
remains beneficial for IDsat performance even at LG = 15 nm. By evaluating the ∆IDsat
enhancement between devices with LG = 15 and 100 nm, reveals that the self-aligned
approach has a larger impact on IDsat enhancement as LG scales. Conversely, when LGap =
0 nm, there is no difference in IDsat between the devices. This is because the non-self-
aligned Mo approach becomes equivalent to that of a self-aligned Ni-InGaAs approach
when LGap = 0. This implies that self-alignment either through self-aligned metallization
(i.e. Ni-InGaAs) or self-aligned contact vias (e.g. Mo, Ti, etc) is critical for enhanced
device performance. Nevertheless, a Ni-based contact scheme is preferred for integration
due to its added benefit of reduced process complexity in a Ge/III-V CMOS flow.

Summary

This paper broadly reviews various approaches (i.e. SBH, ND and Contact Schemes)
to reduce RC. We show that most metals on In0.53Ga0.47As exhibit an Φe of ~ 0.2 eV due
to Fermi level pinning. This implies that RC scaling based on SBH reduction with ΦM
selection would be limited. On the other hand, S and Te were found to be promising n-
type dopants in III-V with S-MLD and in situ doping, respectively. This solves the issues
of low ND with Si doping and implant damage with I/I for III-V doping. TCAD
simulations were performed to understand the impact of contact schemes (i.e. use of self-
aligned Mo or non-self-aligned Ni-InGaAs contacts) on III-V MOSFET. In addition, a
novel interlayer process was developed to enhance the thermal stability of Ni-InGaAs.

Acknowledgments

The authors thank Michael Abraham and Prof. Suzanne Mohney for technical discussions
We would also like to thank Eugene Kong for TCAD simulations and Prof. Yeo Yee-
Chia for discussion on contact resistance scaling in III-V devices. We acknowledge the
valuable assistance of L. Walsh, C. Weiland and J.C. Woicik with HAXPS and XAS
measurements at the National Synchrotron Light Source, Brookhaven National Lab.

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