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Product Highlights
EcoSmart™- Energy Efficient
• Multi-mode control maximizes efficiency over full load range
• No-load consumption below 30 mW at 230 VAC (LNK67xx)
• >75% efficiency with 1 W input at 230 VAC
• >50% efficiency with 0.1 W input at 230 VAC
BYPASS DRAIN
(BP) (D)
LATCH/HYSTERETIC 5.75 V
REGULATOR
THERMAL
SHUTDOWN
FAULT FILTER +
-
BYPASS 5.75 V
PROGRAM 4.9 V
MULTI-CYCLE
COMPENSATION MODE CONTROL
(CP)
MCM
OV
AUTO-
RESTART
SOFT-
2V START HIGH GAIN
REFERENCE + OUTPUT
OVERVOLTAGE TRANS-
VOLTAGE CONDUCTANCE
AUTO-RESTART
AMPLIFIER
FEEDBACK + ERROR
VOLTAGE GATE
(FB) AMP DRIVER
S/H
CLOCK S Q
LINE OVERVOLTAGE/ LUV
UNDERVOLTAGE LOV OSC
DETECTION DCMAX LEB
R Q
OSCILLATOR +
LINE
COMP
LINE CUSTOM
COMPENSATION SHUTDOWN CURRENT LIMIT
PROGRAM/ DELAY COMPARATOR
DELAY
(PD) PROGRAM CURRENT
ILIM LIMIT
SETTING PI-6565-072012 SOURCE
(S)
40% ~ 100%
LNK 6 X X X E/V/K
TMCM(OFF)2 BVDSS1
Part Number Series 6 = 0.5 ms 6 = 650 V Power Packages
7 = 4.0 ms 7 = 725 V
LNK6663E/V/K 0.5 ms 650 V eSIP-7C (E), eDIP-12B (V), eSOP-12B (K)
LNK6664E/V/K 0.5 ms 650 V eSIP-7C (E), eDIP-12B (V), eSOP-12B (K)
LNK6665E/V/K 0.5 ms 650 V eSIP-7C (E), eDIP-12B (V), eSOP-12B (K)
LNK6666E/V/K 0.5 ms 650 V eSIP-7C (E), eDIP-12B (V), eSOP-12B (K)
LNK6667E/V/K 0.5 ms 650 V eSIP-7C (E), eDIP-12B (V), eSOP-12B (K)
LNK6763E/V/K 4.0 ms 650 V eSIP-7C (E), eDIP-12B (V), eSOP-12B (K)
LNK6764E/V/K 4.0 ms 650 V eSIP-7C (E), eDIP-12B (V), eSOP-12B (K)
Device
LNK6765E/V/K 6 4.0 ms 650 V eSIP-7C (E), eDIP-12B (V), eSOP-12B (K)
Size
LNK6766E/V/K 4.0 ms 650 V eSIP-7C (E), eDIP-12B (V), eSOP-12B (K)
LNK6767E/V/K 4.0 ms 650 V eSIP-7C (E), eDIP-12B (V), eSOP-12B (K)
LNK6773E/V/K 4.0 ms 725 V eSIP-7C (E), eDIP-12B (V), eSOP-12B (K)
LNK6774E/V/K 4.0 ms 725 V eSIP-7C (E), eDIP-12B (V), eSOP-12B (K)
LNK6775E/V/K 4.0 ms 725 V eSIP-7C (E), eDIP-12B (V), eSOP-12B (K)
LNK6776E/V/K 4.0 ms 725 V eSIP-7C (E), eDIP-12B (V), eSOP-12B (K)
LNK6777E/V/K 4.0 ms 725 V eSIP-7C (E), eDIP-12B (V), eSOP-12B (K)
Table 2. Device Part Numbers and Options.
Notes:
1. Minimum breakdown voltage at TJ = +25 °C.
2. TMCM(OFF) = 0.5 ms for fastest transient response, TMCM(OFF) = 4 ms for <30 mW no-load input power.
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Rev. C 03/14 www.powerint.com
LinkSwitch-HP
Pin Functional Description internal circuit decodes the current limit based on resistor
loaded on the PROGRAM pin. Please see Table 4. It can also
BYPASS (BP) Pin: be used for optionally extending shutdown delay time by
An external bypass capacitor is connected to this pin for the changing the capacitance on the pin. See Figure 6.
internally generated 5.75 V supply. Based on the connected
capacitance determined at start-up, it will provide either SOURCE (S) Pin:
auto-restart or latching shutdown option dependant on the fault This pin is the power MOSFET source connection. It is also the
condition. Please see Table 3. ground reference for the BYPASS, FEEDBACK, PROGRAM and
COMPENSATION pins.
COMPENSATION (CP) Pin:
This pin is the output of transconductance amplifier. An RC Functional Description
compensation network on this pin provides control loop
compensation. A LinkSwitch-HP device monolithically integrates a controller
and high-voltage power MOSFET into one package. It has a
DRAIN (D) Pin: newly developed analogue control scheme, which enables
This pin is the high-voltage power MOSFET drain connection. It continuous conduction mode (CCM), primary side regulated
also provides internal operating current for start-up until output (PSR) power supplies up to 90 W without the efficiency
is in regulation. limitation of DCM or audible noise. It uses an enhanced peak
current mode PWM control scheme with multi-mode operation.
FEEDBACK (FB) Pin: The multi-mode control engine uses the error amplifier output
The FEEDBACK pin is used to sense output and input voltage signal voltage at the COMPENSATION pin to set the operating
by sensing the auxiliary winding voltage. During MOSFET peak current and switching frequency to maintain the output
on-time, the current out of the FEEDBACK pin is sensed to voltage in regulation as shown in Figure 5. For COMPENSATION
detect the line voltage. During the secondary rectifier pin voltages lower than VC(MCM) (typ. 1.25 V) the device enters
conduction time, the feedback voltage is proportional to the multi-cycle modulation (MCM) with a fixed peak current of 25%
output voltage via the turns ratio between the bias and of the programmed current limit. Several innovative improvements
secondary windings. have been added to the peak current mode control to allow
primary side regulated CCM operation with no instability. The
PROGRAM (PD) Pin: device meets less than 30 mW input power with no-load at
This MULTI-FUNCTIONAL pin sets device current limit and high-line (LNK67xx families).
optional shutdown delay time extension. During start-up, the
It also offers extensive built-in features:
• External current limit selection.
E Package • Optional programmable shutdown delay time extension.
(eSIP-7C) • Optional remote On/Off.
Exposed Pad • Optional fast AC reset.
(Hidden) • Primary-side sensed output overvoltage protection (OVP) .
Internally Exposed Pad Internally
Connected to Connected to SOURCE Pin • Lost regulation protection during output overload or
SOURCE Pin
V Package short-circuit (auto-restart).
(eDIP-12B) • Internal current limit over line compensation for constant
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LinkSwitch-HP
Voltage (∝ POUT)
time increases monotonically from 1.2 ms at no or light load to
100% 2.5 ms at full load. Sampled voltage is held until the next clock
cycle. The output of S/H is fed to the error amplifier, once in
50%
regulation the sampled voltage is 2 V.
above 142 °C, the power MOSFET is disabled and remains Programmable Shutdown Delay
disabled until the die temperature falls by 75 °C, at which point The default auto-restart shutdown delay time tSD(AR) (typ. 35 ms)
the device is re-enabled. The large hysteresis maintain the can optionally be extended by connecting a capacitor to the
average temperature below the temperature rating of low cost PROGRAM pin. Once a lost regulation fault is detected the
CEM type PCB material in most cases. PROGRAM pin voltage is cycled 128 times between VPD(DL) (typ.
0.5 V) and VPD(DU) (typ. 1.2 V) as shown in Figure 10. Figure 6
Safe Operating Area (SOA) Protection
depicts the relationship between extended shutdown delay
The device features a safe operating area (SOA) protection
time, added PROGRAM pin capacitor and current limit
mode which disables MOSFET switching for 4 consecutive
programming resistor.
cycles in the event the peak switching current reaches the
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LinkSwitch-HP
Remote On/Off and Fast AC Reset At power-up the current out of the FEEDBACK pin has to
The PROGRAM pin can be used to turn on/off the device exceed the line undervoltage turn-on threshold (brown-in)
remotely. If the voltage on the pin is set to 1.35 V externally, the current IFB(UVREF) = -250 µA (typ.) before switching is enabled.
device stops switching. After releasing the PROGRAM pin the During normal operation switching is disabled if the FEEDBACK
PROGRAM pin device commences switching when the voltage pin current falls below the line undervoltage turn-off threshold
drops below 0.535 V. (brown-out) current IFB(UVOFF) = -100 µA (typ.) for at least 8
consecutive switching cycles. After switching has ended, the
device enters auto-restart. The applicable auto-restart off-
Auto-Restart On-Time Extension (ms)
500
PI-6646-040412
PROGRAM Pin Resistor Value period t AR(OFF) 1 = 150 ms (typ.).
450
124 kΩ
400 78.7 kΩ
52.3 kΩ
350 34.8 kΩ
VSEC D
23.2 kΩ VBUS
15.0 kΩ
300
10.0 kΩ NP NS CO VO
250
200
150
VAUX
100 NA
D BP RFB1
50 T1
CONTROL
0 U1 FB
1 10 100
S PD CP
PROGRAM Pin Capacitor Value (nF)
RFB2
VFB
Figure 6. Optional Shutdown Time Extension Programming.
The PROGRAM pin can also be used to reset the device latch PI-6837-120312
after a latching OVP or OTP event. If the voltage on the pin is
set to 3.4 V externally, the device latch is reset. Once the Figure 8. Indirect High-Voltage Bus Sensing.
voltage drops below 0.535 V, device will start switching.
Switching is also stopped if the FEEDBACK pin current exceeds
110 the line overvoltage threshold current IFB(OV) = -1.15 mA (typ.) for
PI-6721-040412
Normalized Set Current Limit (%)
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LinkSwitch-HP
1. Startup
26. Pause 150 ms
(Auto-Restart Off
Period (tAR(OFF))
No
No Yes
6. Brown-Out?
(IFB < -100 µA
Yes for 8 Cycles)
No
11. AC 27. Pause 150 ms
No
Present? (Auto-Restart Off
(IFB > -250 µA) Period tAR(OFF)1)
7. Regulation No
Lost? (VFB < 1.85 V
Yes for 35 ms)
Yes
No 9. Latch Reset?
(VPD > 3.4 V)
16. Regulation No
21. Line OV? Lost? (VFB < 1.85 V
(IFB > 1.15 mA for 35 ms)
Yes for 2 Cycles)
Yes
Yes
No
10. Reset Latch
22. Brown-Out?
(IFB < -100 µA
Yes for 8 Cycles) PI-6838-101812
17. Stop Switching
No
Yes
Yes
25. Pause 1500 ms
(Auto-Restart Off
Period tAR(OFF)2)
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LinkSwitch-HP
SW
VFB
Fast AC Reset
VPDTHACR 3.40 V
tPD Programmable
VPDI Shutdown Delay
ID ILIMIT Remote On/Off
VPDTHRM 1.35 V
VPDTHPDH 1.25 V
tPDST
VPDTHPDL 0.535 V
t1 t2 t3 t4 t5 t6 t7 t8 t9 t10
PI-6692-101713
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LinkSwitch-HP
D8 J3
STPS30100ST
R3
3 kΩ C12 R28 C22
C3 1000 µF 27 kΩ 10 µF
10 nF 16 V 16 V
630 V
VR1 FL2
RTN
BR2 BZG03C130
DF206ST-G 130 V J4
600 V 7
D2
BAV21WS- C6
R2 7-F 22 µF
100 Ω 16 V
1/2 W
6 8 R9
T1 4.3 kΩ
L4 D1 RM8 1%
10 mH DL4937 1/8 W
C2
68 µF R19
C14 41.2 kΩ
150 nF 400 V
1%
275 VAC
R29 R30 D BP
3.3 MΩ 3.3 MΩ
F1 LinkSwitch-HP CONTROL
2A U1 FB
LNK6766E
90 - 265
VAC S PD CP C5
J1 J2 C23 470 nF
10 pF 50 V
C20 R7 50 V R20
4.7 nF 100 kΩ 10.2 kΩ
50 V 1/8 W C8 1%
100 pF
R8 C7 50 V
23.2 kΩ 100 nF
1% 25 V
1/8 W PI-6844-120312
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LinkSwitch-HP
The transient load response is dependent on the loop gain and BYPASS pin to provide external bias. The external bias current
minimum switching frequency. The values of R7 and C7 shown should set via R9 to be at least 500 mA to guarantee the internal
here typically give good transient response for most designs. current source of LinkSwitch-HP is turned off as this will allow
When the supply is at no-load, the minimum switching frequency the supply to operate more efficiently, especially at light load.
at no-load will create a delay to respond to any step load event For best no-load performance the external supply voltage
during the off-time. In the case above, the minimum frequency across C6 should be minimized (typically 8-9 V) and the current
is 250 Hz so there is a potential 4 ms delay to response. If a into the BYPASS pin set by R9 should be as low as possible.
faster response is desired from no-load initial condition there is Input overvoltage protection is done through sensing the
the option to use the LNK666x which has a minimum frequency negative forward pulse of feedback winding. When the negative
of 2 kHz. There is a trade-off in using this family as no-load forward voltage is sufficiently high to produce more than 1.15 mA
input power will be slightly higher and a smaller pre-load resistor current into the FEEDBACK pin, for 2 consecutive on-cycles the
will be required. device will stop switching for auto-restart delay period.
In order to have good efficiency, regulation performance and Output overvoltage protection is achieved by sensing the flyback
stability, the transformer leakage inductance should be minimized. pulse through the FEEDBACK pin. When the FEEDBACK pin
Low leakage will minimize ringing on the sense winding which sees 2.5 V or greater for 16 consecutive cycles, the supply will
can create an error in the feedback sampling. The example latch off. If non-latching OVP is desired then changing C5 from
above uses split primary winding technique to lower leakage 0.47 mF to 4.7 mF will change fault mode accordingly (see Table
inductance. Leakage inductance should not be greater than 3 for details).
2% of nominal primary inductance and 1% is typically the
desirable target value. OCP protection is accomplished by sensing when the output
drops below 0.925 of nominal regulation value for a duration
Resistor R28 serves as a pre-load resistor to minimize output greater than specified delay time. In the example above, the
voltage rising in no-load condition. The pre-load resistor should total delay time is about 50 ms. Capacitor C20 extends the
be no smaller than is necessary to maintain output within default internal delay time of 35 ms (see Figure 6 for details).
specification limits to minimize added dissipation. In this example, The latching shut-off option is used in the design above.
the added pre-load dissipation is only 4.8 mW.
The primary current limit of LinkSwitch-HP can be adjusted by
LinkSwitch-HP provides an internal current source to bias the selecting the value for R8 (see Table 4 for details). For this
BYPASS pin which is necessary for start-up. When the supply design 60% of maximum current limit was chosen. A lower
is operating and in regulation an external bias is provided from current limit setting is typical for an adapter where lower RDS(ON)
the rectified flyback voltage from the bias winding (D2 and C6). is desirable for higher efficiency and also lower thermal rise of
Resistor R9 is sourced from the bias voltage across C6 into the LinkSwitch-HP.
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LinkSwitch-HP
Layout Considerations for eSIP-7C Package be tied to the positive terminal of the bulk capacitor C2 in order
to route the potential of high currents away from the more
Figure 12 is the layout for a 30 W adapter shown in the schematic sensitive primary return traces.
Figure 11. An eSIP-7C package is used as indicated by the
suffix in LNK6766E which allows the use of a stand-up heat Because of the tight layout common to adapter applications,
sink. The mounting pin for the heat sink should be electrically this design uses triple insulated wire and flying leads for output
isolated. It can be seen that the primary return trace wraps winding termination to avoid secondary arcing to core during
around the LinkSwitch-HP device which acts as a shield around ESD events.
the critical external control related components of LinkSwitch-HP.
These components include R7, R8, R19, R20 and C5, C8, C20. The trace connecting the drain to transformer should be very
Of particular importance is placing the bypass capacitor C5 and short and the primary clamp circuitry should be grouped
COMPENSATION pin noise filter capacitor C8 as close as possible together and away from the more sensitive components. The
to SOURCE pin with very short trace lengths to COMPENSATION bias winding return and return of bias capacitor C6 should be
and BYPASS pins as shown. If an electrolytic capacitor is routed separately to the negative terminal of the input capacitor
selected as the bypass capacitor (C5) then an additional 100 nF C2 away from SOURCE pin.
(C5) ceramic must also be fitted. The ground trace wrap, tight
layout and single point grounding to SOURCE pin of these The secondary rectifying loop that includes the secondary
components avoids having noise related issues during peak winding, the output diode D8, and the first output capacitor C13
loads or during line transient such as surge or ESD events. should be as tight as possible to minimize adding series
inductance which can reduce high load efficiency and degrade
Another consideration for ESD and line surge is the primary- the quality of regulation.
side termination of the Y capacitor. The Y capacitor C18 should
Figure 12. Layout for 30 W Adapter Using a eSIP-7C Package (View From Bottom Copper Layer).
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LinkSwitch-HP
The schematic extract in Figure 13 is an example of LinkSwitch-HP All LinkSwitch-HP designs should be verified on the bench
used in a dual output LCD monitor supply using eDIP-12B particularly for specified worst-case stress conditions. The
package. In this design the exposed metal tab on the topside following set of tests are strongly recommended:
R10
C9 10 Ω C10
of package is left open (no heat sink). The SOURCE pins of 1 nF 1% 470 pF
250 VAC 1/8 W 200 V
LinkSwitch-HP provide heat sinking through connection to the 1. Maximum drain voltage – Verify that VDS does not exceed
source copper pad of PCB. This technique is adequate for 675 V for LNK677X series6 and12600 V for LNK6X6X series.
device dissipation up to 0.85 W (1/2 square inch of copper area This gives a 50 V margin for design variations. D3
R2 R3 30BQ100PBF
required). The layout guidelines described for eSIP-7C are the 2. Under
R1
3 kΩ all
100 conditions,
Ω 100 Ω the maximum Drain current
R12 should be C11
1% 1% 10 Ω C15 220 µ
same for eDIP-12B with an added consideration about sensitive below the specified absolute maximum ratings. 1% 470 pF 35 V
1/8 W 200 V L2
component layout. The return referenced components C4, C8, 3. Thermal
VR1
check – At rated maximum output power, minimum Ferrite Bead
C3 (3.5 × 4.45 mm)
C16, R9, R7 must be placed directly under the LinkSwitch-HP
BR1 input voltage 10
P6KE130A
130 V
andnF maximum ambient temperature, verify that
7,8
DF06M 630 V
package as shown in Figure 14. This requires that these 600 V the maximum allowed temperature is not exceeded D4
B340LB-13-F
for any C13
820 µF
particular components be SMD type as this allows an ideal component in the design. Of particular importance is 6.3 V
noise-immune layout. checking the 20 R4
temperature
Ω rise of the major power conversion
9,10
1% C14
components such as transformer,
3
outputD2diodes, input 820 µ
6.3 V
Output Power Table Assumptions BAV21WS- C6
bridge, primaryD1clamp circuit and LinkSwitch-HP.7-F 22 µF Under the
L1 R5
25 V
10 mH
C2 stated conditions above, LinkSwitch-HP tab temperature
DL4937
6.98 kΩ
• 12 V output. 47 µF
450 V should not exceed 110 °C. T1 5 1 1%
1/8 W
C1
• Schottky rectification. 100 nF EF25 R8
46.4 kΩ
310 VAC
• 82% efficiency. 1%
1/16 W
• VOR = 135 V.
• KP = 0.4 for 85-265 VAC input and KP = 0.6
F1 for 195-265
2A
RT1
5Ω tVAC
O D BP
LinkSwitch-HP CONTROL
input. U1 FB
• VMIN = 100 V for 85-265 VAC input and VMIN = 250 VACV for
90 - 265 LNK6774V
C5
195-265 VAC input. J1-3 J1-1 S PD CP
C16
4.7 µF
10 V
R7 R9
• 0.85 W device dissipation for open frame designs with PCB 100 kΩ 10 pF
50 V
10.5 kΩ
1% 1%
heat sink. R6
23.2 kΩ 1/16 W
C8
1/16 W
C4* 1% C7 100 pF
1/16 W 100 nF 50 V
25 V
PI-6860-120312
*Optional PI-6860-120312
Figure 14. Layout for LCD Monitor Supply Using eDIP-12B Package.
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LinkSwitch-HP
Thermal Resistance
Thermal Resistance: E Package Notes:
(qJA)........................................... 105 °C/W(1) 1. Free standing with no heat sink.
(qJC)............................................... 2 °C/W(2) 2. Measured at the back surface of tab.
K Package 3. Soldered (including exposed pad for K package) to typical
(qJA) ...........................45 °C/W(3), 38 °C/W(4) application PCB with a heat sinking area of 0.36 sq. in.
(qJC)............................................... 2 °C/W(2) (232 mm2), 2 oz. (610 g/m2) copper clad.
V Package 4. Soldered (including exposed pad for K package) to typical
(qJA) ............................74 °C/W(3), 63 °C/W(4) application PCB with a heat sinking area of 1 sq. in. (645 mm2),
(qJC)............................................... 2 °C/W(2) 2 oz. (610 g/m2) copper clad.
Conditions
Parameter Symbol SOURCE = 0 V; TJ = -40 to 125 °C Min Typ Max Units
(Unless Otherwise Specified)
Control Functions
Switching Frequency fOSC Average value, TJ = +25 °C, 120 132 136 kHz
Switching Frequency
ΔfOSC 0 °C ≤ TJ ≤ +100 °C, See Note A ±10 %
Temperature Variation
Frequency Jitter
Δf fOSC = 128 kHz ±5 kHz
Deviation
Frequency Jitter
fM 250 Hz
Modulation Rate
Auto-Restart Shut-
tSD(AR) TJ = +25 °C 35 ms
Down Default Delay
tAR(ON) TJ = +25 °C, tSOFT + tSD(AR) 50
Auto-Restart TAR(OFF)1 First switch off-period 150 ms
TAR(OFF)2 Subsequent switch off-periods 1500
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LinkSwitch-HP
Conditions
Parameter Symbol SOURCE = 0 V; TJ = -40 to 125 °C Min Typ Max Units
(Unless Otherwise Specified)
Transconductance
Amplifier Max Output IGM TJ = +25 °C 10.0 12.5 15.0 μA
Current
COMPENSATION Pin
ZCP See Note A 30 MW
Input Impedance
Bypass (BP) Input
0.47
OVP/UVP/OTP
TJ = +25 °C
Programming CBP 4.7 mF
See Table 3 for programming
Capacitor Value
47
BYPASS Pin Voltage VBP 5.46 5.75 6.04 V
BYPASS Pin
VBPH 0.85 0.95 1.1 V
Voltage Hysteresis
LNK6xx3 -6.8 -4.8 -2.0
VBP = 0 V
ICH1 TJ = +25 °C LNK6xx4-5 -9.2 -6.6 -2.8 mA
VDS ≥ 50 V
BYPASS Pin LNK6xx6-7 -12.0 -8.3 -4.3
Charge Current LNK6xx3 -4.7 -2.7 -1.5
VBP = 5 V
ICH2 TJ = +25 °C LNK6xx4-5 -7.0 -4.0 -2.2 mA
VDS ≥ 50 V
LNK6xx6-7 -8.8 -5.2 -2.9
BYPASS Pin Shutdown
IBPSD TJ = +25 °C 5.7 8.2 10.7 mA
Threshold Current
BYPASS Pin Switching
TJ = +25 °C 8
Shutdown Delay Cycles
BYPASS Pin VBP = 6 V
IBPSC -0.5 mA
Source Current TJ = +25 °C
BYPASS Pin Charge
Current Temperature ΔIBPSC See Note A 0.5 %/°C
Variation
BYPASS Pin
VBP(SHUNT) IBP = 2 mA 6.1 6.4 6.7 V
Shunt Voltage
IBPS1 TJ = +25 °C, See Note B 525 mA
LNKxxx3 0.9 1.2
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LinkSwitch-HP
Conditions
Parameter Symbol SOURCE = 0 V; TJ = -40 to 125 °C Min Typ Max Units
(Unless Otherwise Specified)
Current Limit
Reduction Onset IFB(LIM) TON = 220 ns, TJ = +25 °C -210 mA
Threshold Current
Missing Feedback
Voltage Protection TMFVP TJ = +25 °C 0.8 ms
Sense Delay Time
Missing Feedback
Switching
Voltage Protection 4
Cycles
Delay
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LinkSwitch-HP
Conditions
Parameter Symbol SOURCE = 0 V; TJ = -40 to 125 °C Min Typ Max Units
(Unless Otherwise Specified)
PROGRAM/DELAY
Pin Time Upper VPD(DU) TJ = +25 °C 1.20 1.25 1.30 V
Voltage Threshold
Fast AC Reset
VPDTHACR 3.06 3.4 3.74 V
Threshold
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LinkSwitch-HP
Conditions
Parameter Symbol SOURCE = 0 V; TJ = -40 to 125 °C Min Typ Max Units
(Unless Otherwise Specified)
Output
NOTES:
A. Parameter not tested over specified temperature range. Guaranteed by design and characterization.
B. Average device switching frequency below 1 kHz.
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LinkSwitch-HP
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LinkSwitch-HP
1.1 1.05
PI-2213-012301
PI-6787-053112
Standard Current Limit
1.00
(Normalized to 25 ° C)
(Normalized to 25 °C)
Breakdown Voltage
95
1.0
90
85
0.9 80
-50 -25 0 25 50 75 100 125 150 -40 -20 0 20 40 60 80 100 120
Junction Temperature (° C) Temperature (C)
Figure 16. Breakdown vs. Temperature. Figure 17. Standard Current Limit vs. Temperature.
1200 1000
PI-6851-071912
PI-6850-071912
Scaling Factors:
1000 LNK6xx3 1
LNK6xx4 1.5 Drain Capacitance (pF) Scaling Factors:
Drain Current (mA)
LNK6xx5 2 LNK6xx3 1
800 LNK6xx6 3 100 LNK6xx4 1.5
LNK6xx7 4 LNK6xx5 2
LNK6xx6 3
600 LNK6xx7 4
400 10
TCASE=25 °C
200 TCASE=100 °C
0 1
0 2 4 6 8 10 0 100 200 300 400 500 600
DRAIN Voltage (V) Drain Voltage (V)
Figure 18. Output Characteristic. Figure 19. COSS vs. Drain Voltage.
LNK6xx3 1
Output Frequency
120
LNK6xx4 1.5
LNK6xx5 2 0.8
Power (mW)
LNK6xx6 3
LNK6xx7 4
80 0.6
0.4
40
0.2
0 0
0 100 200 300 400 500 600 -50 -25 0 25 50 75 100 125 150
Drain Voltage (V) Junction Temperature (°C)
Figure 20. Drain Capacitance Power. Figure 21. Frequency vs. Temperature.
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Rev. C 03/14 www.powerint.com
LinkSwitch-HP
1.2 1.2
PI-6854-071812
PI-4761-061407
Undervoltage Threshold
1.0 1.0
Overvoltage Threshold
(Normalized to 25 °C)
(Normalized to 25 °C)
0.8 0.8
0.6 0.6
0.4 0.4
0.2 0.2
0 0
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150
1.2 1.2
PI-6856-071812
Undervoltage Turn-On Threshold
PI-6855-071812
1.0 1.0
(Normalized to 25 °C)
(Normalized to 25 °C)
0.8 0.8
0.6 0.6
0.4 0.4
0.2 0.2
0 0
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150
1.2 1.2
PI-6010-060410
PI-6731-040212
1 1
DRAIN Current
DRAIN Current
0.8 0.8
0.6 0.6
0.4 0.4
0.2 0.2
0 0
0 100 200 300 400 500 600 700 800 0 100 200 300 400 500 600 700
DRAIN Voltage (V) DRAIN Voltage (V)
Figure 26. Maximum Allowable Drain Current vs. Drain Voltage Figure 27. Maximum Allowable Drain Current vs. Drain Voltage
(LNK6773-6777). (LNK6763-6767/LNK6663-6667).
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www.powerint.com Rev. C 03/14
LinkSwitch-HP
eSIP-7C (E Package)
C
2
0.403 (10.24) 0.081 (2.06) 0.264 (6.70)
A
0.397 (10.08) 0.077 (1.96) Ref.
B
Detail A
2
0.325 (8.25) 0.290 (7.37)
Ref. 0.198 (5.04) Ref.
0.320 (8.13)
0.519 (13.18)
Ref.
PI-4917-061510
20
Rev. C 03/14 www.powerint.com
LinkSwitch-HP
eSOP-12B (K Package)
0.010 [0.25]
0.356 [9.04] Ref.
Ref. 0.055 [1.40] Ref.
2 0.004 [0.10] C A 2X
0.400 [10.16] 0.325 [8.26]
Pin #1 I.D. H
(Laser Marked) Max. 7 0.010 [0.25]
2X 7 12
0.004 [0.10] C B Gauge Plane
Seating Plane
0.059 [1.50]
0°- 8°
C
Ref, Typ 2 0.034 [0.85]
0.460 [11.68] 0.350 [8.89] 0.225 [5.72] 0.026 [0.65]
Max. 7
0.059 [1.50]
Ref, Typ
DETAIL A (Scale = 9X)
3 4 6 B 6 1 0.049 [1.23]
0.008 [0.20] C 1 2
3 4 0.028 [0.71] 0.046 [1.16]
2X, 5/6 Lead Tips 0.023 [0.58] 0.120 [3.05] Ref
11× Ref.
0.018 [0.46]
0.070 [1.78]
0.010 (0.25) M C A B
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www.powerint.com Rev. C 03/14
LinkSwitch-HP
eDIP-12B (V Package)
0.004 [0.10] C A
2
0.325 [8.26] Seating Plane C 0.400 [10.16]
Pin #1 I.D. Max. 0.016 [0.41]
11× A
(Laser Marked) 10 0.011 [0.28]
0.120 [3.05] 0.010 [0.25] Ref. 0.059 [1.50]
2X 1 2 3 4 6 Ref. 6 1 Ref, typ.
0.004 [0.10] C B
0.412 [10.46] 7
2
Ref. 0.400 [10.16]
0.350 [8.89] 0.225 [5.72] 8
0.306 [7.77]
Max. 0.436 [11.08] 0.059 [1.50]
10 Ref.
0.406 [10.32] Ref, typ.
B 12 11 10 9 8 7 7 12
3 4
Detail A 0.023 [0.58]
5 °± 4° 0.018 [0.46]
11×
TOP VIEW 0.104 [2.65] Ref.
0.010 [0.25] M C A B
0.192 [4.87]
H Ref.
0.031 [0.80] 0.020 [0.51]
0.028 [0.72] Ref.
0.070 [1.78] 0.028 [0.71]
Ref.
22
Rev. C 03/14 www.powerint.com
LinkSwitch-HP
23
www.powerint.com Rev. C 03/14
Revision Notes Date
A Initial Release. 08/12
A Updated Table 2. 08/23/12
A Updated page 5. 10/24/12
B Formatting changes. KPS Min value updated. 12/04/12
B Fixed Table references. 02/26/13
C Released K package parts. Updated ΔVFB(th) Typ value on page 14. 03/14
Patent Information
The products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered
by one or more U.S. and foreign patents, or potentially by pending U.S. and foreign patent applications assigned to Power Integrations. A
complete list of Power Integrations patents may be found at www.powerint.com. Power Integrations grants its customers a license under
certain patent rights as set forth at http://www.powerint.com/ip.htm.
1. A Life support device or system is one which, (i) is intended for surgical implant into the body, or (ii) supports or sustains life, and (iii)
whose failure to perform, when properly used in accordance with instructions for use, can be reasonably expected to result in significant
injury or death to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause
the failure of the life support device or system, or to affect its safety or effectiveness.
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