Power Supply Design
with Fast Transient
Abstract
Today’s power supply design faces new
challenges to support high-performance
microprocessors such as Pentium II from
Intel Corp. These power supplies require
step-down DC-DC voltage conversation
with fast transient response and high ef-
ficiency at stringent cost restriction. Re-
cently a novel control scheme called V2
control has been developed and widely
embraced by the power supply and
mother board OEMs. One of the unique
features of the V2 control is its fast tran-
sient speed and simple compensation de-
sign. This paper presents an overview of
this new technology and associated de-
sign techniques. The small signal analy-
sis provides an insightful tool for fur-
ther revealing the power of the V2 con-
trol. Finally, an reference design is pro-
vided and test data is presented. The
measured frequency response resembles
closely to that predicted by the small sig-
nal model.
Introduction
As IC designers push to create more com-
plex circuit running at escalated speed,
power consumption becomes critical.
One of the first remedies for limiting
power drain is to lower the supply volt-
age. That changes provided one of the
greatest benefits, since power consump-
tion is directly proportional to the square
of the supply voltage. The first major step
in this direction was taken several years
ago when designers started moving to
3.3V supply levels from the decades old
5V standard. Currently designers are low-
ering the bar again, decreasing the sup-
ply voltage from 3.3V to the next stan-
dard, 2.5V. Similarly, using smaller fea-
ture sizes to fabricate more complex chips
Response Using V2
Control Scheme
Mike Wang
Applications Engineer
Cherry Semiconductor
also demands lower voltages. With fea-
ture sizes dropping below 0.2µm, design-
ers must reduce the high electrical-field
stresses that arise due to the thin oxide lay-
ers and shallow junctions used to build the
high-speed transistors. As a result in a dis-
tributed power system, one or multiple step
down DC-DC converters are required to
derive the IC supply voltage from a higher
bus voltage, which could be 5V, 12V or
more recently emerged 48V.
As the IC designs keep lowering the
supply voltage, the current rating is ramp-
ing up due to the increased complexity
and clock speed. Consequently, the cur-
rent slew rate also elevates to a higher
level when ICs frequently switch among
various power modes. To ensure the
proper functions, the supply voltage is
required to stay within a narrow window
area during load transient and steady-state
operation. For example, the next genera-
tion Intel processors adopt a core voltage
of 2.0V at 16A maximum current. The
dynamic current slew rate can be as high
as 20A/µs, while the core voltage devia-
tion during load transition can not exceed
over +/- 200mV.
This high current slew rate requires
the power supply to possess extreme fast
response time. The conventional voltage-
mode and current-mode control often fail
to deliver the desired performance mainly
due to their relying on the error amplifier
speed to react to the load transition. The
recently developed V2 control scheme [1]
maximizes the transient speed by super-
imposing the ramp signal on the output
voltage. Therefore, the PWM (pulse
width modulation) control experiences no
delay during the load variation. It is also
revealed in the paper that frequency com-
pensation for a V2 controlled circuit is
International IC ‘99 • Conference Proceedings
greatly simplified which often means
lower cost and less development effort.
V2 Control scheme
A typical synchronous Buck DC-DC con-
verter is shown in Fig.1(a). A synchro-
nous Buck is differentiated from a con-
ventional Buck converter by replacing the
low side diode with an active switch Q2.
This eliminates the power loss associated
with diode forward voltage, which can be
a significant part of total loss in a low
voltage application. In this particular to-
pology, the PWM controller modulates
the on/off action of the high side switch
Q1 to regulate the output voltage. A
complementary switching action governs
the low side Q2. As illustrated in Fig.1(b),
on the beginning of each switching cycle
t1, the gate signal turns on the Q1 and
turns off the Q2. Therefore, a voltage of
Vg-Vo is applied across the inductor to
make its current linearly increase. The
ramp signal also rises during this period
and eventually reaches the error ampli-
fier output voltage on t2. This immedi-
ately opens the Q1 and closes the Q2.
Now the voltage across the inductor is
equal to -Vo and the inductor current lin-
early declines. This switching pattern re-
peats itself at the commence of the next
switching cycle. The switching period is
often controlled by a central oscillator
signal, although constant off-time control
is not uncommon in a current-mode and
V2 control. A non-overlapping time is al-
ways inserted between the turn-on signal
of the Q1 and Q2 to prevent the cross
conduction. To ensure the continuation of
the inductor current, the body diode of
the Q2 will temporarily conduct when
both switches are turned off.
189
 Figure 1. (a) A synchronous Buck converter with PWM control.
The major difference among voltage
mode, current mode and V2 control relies
on the source of the ramp signal. As shown
in Fig.1(b), in voltage mode control the
ramp is a fixed signal, typically generated
by the oscillator. Therefore, The speed for
the duty cycle to adapt to any transient
conditions, such as load and line variation,
is solely dependent on the speed of the
error amplifier. This poses great challenge
for designing the error amplifier and fre-
quency compensation. Extra die areas and
engineering efforts will inevitably add cost
to the power solutions.
In current mode control, the ramp sig-
nal is generated from the switching cur-
rent. This current can be sensed through
a current transformer or a resistor. The
current mode control has the advantage
of reacting promptly to the line variation,
because the current slope can immedi-
ately vary the duty cycle even when the
error amplifier fails to response. However,
during the load transient, the DC of the
error amplifier output has to move accord-
ingly to allow for current changes. There-
fore, the error amplifier again becomes
critical to the system performance. To
satisfy the harsh load step required by
today’s microprocessors, optimizing load
transient response occupies significant
part of development time.
The V2 control relieves the burden
from the error amplifier by using the out-
put ripple as the ramp signal. Since the
output ripple is superimposed on the out-
put DC voltage, any deviation on the out-
put voltage will immediately change the
duty cycle and therefore get corrected
through the feedback loop. Having the
output voltage directly connected to the
PWM comparator provides most effec-
tive feedback path. As a result, in V2 con-
trol the error amplifier is often used only
to provide DC accuracy.
In a Buck converter, the output ripple
is caused by the ESR (equivalent series
190 International IC ‘99 • Conference Proceedings
resistor) associated
with the output ca-
pacitors. The ripple Figure 1. (b) Typical waveforms show the pulse by
voltage can be cal- pulse operation and the differences among voltage
2
culated as the ESR mode, current mode and V control.
times the AC cur-
rent through the capacitors.
Variation on the line voltage
changes the inductor current
ramp immediately, which in turn
changes the ripple voltage and
duty cycle just like in current
mode control. Therefore, V2 pro-
vides the mechanism for fast re-
action to both line and load varia-
tions. The PWM comparator
slew rate and Q1/Q2 switching
time are the only limit to the tran-
sient response time.
V2 small signal model Figure 2. The small signal modeling of a Buck converter with
Small signal analysis is a power- feedback path
ful tool to assist understanding and optimiz-
The small signal models for various
ing a close loop system. For a power sup-
PWM topologies are well established by
ply, the key criterion such as DC accuracy,
Cuk and Middlebrook [2] using state
transient response and system stability can
space average technique. The state space
all be well interpreted using frequency do-
average method averages circuit variables
main measurements. While Fig.1 shows a
( such as output voltage and inductor cur-
system using time domain variables, Fig-
rent) within each switch cycle and lin-
ure 2 describes the same system using the
earize their relationships in a small sig-
small signal variables to reveal their rela-
nal sense. For the buck converter operat-
tionships in frequency domain. The total
ing in continuous conduction mode
loop gain, as shown in Fig.2, can be de-
(CCM), the duty cycle (d) to output volt-
rived from power stage (duty cycle to out-
put voltage) transfer function and control age transfer function has a form of
path (feedback voltage to duty cycle) trans-
fer function. The power stage frequency re- 1.
sponse is solely determined by specific con-
verter topology, and thus is independent of
the various control schemes. Similarly, each
control scheme manipulates the frequency
domain variables in its unique way, which
can be separated from the power stage on
which it applies. The main scope of this
paper is to reveal the small signal behavior
of the V2 control which is vastly different
from the current and voltage control.
where the Rs is the series resistor of the
LC resonant loop, which can be the sum
of the MOSFET on resistance, inductor
resistance and ESR.
In accordance with Fig.2, the feed-
back path can be described by the fol-
lowing equations
2.
When a transconductance error ampli-
fier is used, a typical compensation design
for V2 control only requires a capacitor
Ccomp between the error amplifier output
and ground. The gain expression of the
error amplifier can then be determined by
3.
where G = error amplifier
transconductance
Ro = error amplifier output re-
sistance
To obtain the expression for Fm1,
vcomp is fixed at a constant value while
AC perturbation is applied to the vo, as
illustrated in Fig.3.
6.
The derivative of (6) over vo provides
the expression for Fm1 which takes form of
7.
where Vg and Vo represent DC operating
point. The approximation is made that the
change of the slope due to vo has rela-
tively minor effect on the duty cycle.
The similar method can be practiced to
derive the expression of Fm2. This exer-
cise is not covered in this paper to avoid the
redundancy. However, it can be proven that
Fm2 bears the same form as (7) except for
the positive polarity. Therefore, variable Fm
is defined as following to represent both
Fm1 and Fm2.
8.
Combining (2) and (8) generates the com-
plete model for the V2 control,
9.
and when
becomes negligible and FFB carries all
the feedback signals.
It is also worthy noticing that the
PWM comparator gain Fm in V2 control
is significantly greater than the one in cur-
rent and voltage mode controls It is the
result of the small ramp signal (in hun-
dreds milivolt range) used in V2 control.
At low frequency range, Fm along with
Figure 4. A zero is generated in the feedback path
at frequency of fcoa
Av provides tremendous gain for DC ac-
curacy. Fm is maintained at high frequency
range to ensure the strong feedback for
fast transient response.
As Fig.4 indicated, the feedback path
possesses a zero at the frequency of fcoa.
The frequency of this zero is critical for
providing adequate phase margin to en-
sure the loop stability.
The total loop gain can be derived from
(1), (7) and (9) as
11.

fcoa is the cross-over frequency

of Av and can be calculated
from
10. Experimental result
A power supply design using V2 control
is implemented to demonstrate the per-
formance and prove the small signal
V2 control, as its name indi-
cated, has two voltage feedback model. This design uses Cherry
Figure 3. The output voltage vo is perturbed with a small ac paths. The so-called Fast Feed- Semiconductor’s CS51313 V2 controller,
signal to obtain the expression for Fm1.
b a c k
The switch turn on time ton can be Path (FFB) con-
identified as the time interval associated nects the feed-
with the ripple’s rising edge. Therefore, back voltage di-
ton can be derived from rectly to the
PWM comparator
4. and has a gain of
Fm1. The Slow
Feedback Path
where vo is the state space averaged vari- (SFB) passes
able for the output voltage. The variable through the error
sr is the slope of the rising edge which is amplifier and has
in turn determined by the ESR and in- a gain of -Fm2Av.
ductor current ripple, It is shown in (9)
that at frequency
5. below fcoa the SFB
dominates FFB,
Figure 5. A synchronous buck converter using V2 control method.
After substituting the sr in (4) by (5) providing great
and considering d=ton/Ts (assuming fixed gain for DC accu-
frequency operation), the following equa- racy. However at frequency range above which incorporates 5 bit supply voltage
tion is derived fcoa,, the contribution of error amplifier control and Power Good function. As
shown in Fig.5, the synchronous buck

International IC ‘99 • Conference Proceedings 191

 regulator converts the 5V input from a 7(b) zooms in on the rising edge of the
standard ATX computer power supply to current step and shows that the regulator
+2V/16A. immediately enters into 100% duty cycle
R8 serves multiple functions in this to allow the current to ramp up in less
design. First of all, R8 serves as a “Droop than 25us.
Resistor” for Adaptive Voltage Position- To calculate the loop gain in the small
ing to improve AC response [3]. CS- signal model, the component values and
51313 also relies on R8 for sensing the circuit parameters are extracted from the
current so that the circuit will “hiccup” schematic shown in Fig.5, which are then
during the over-current condition. In CS- listed as
51313, VFB (pin 7) is the input to both
FFB and SFB. The 5Bit DAC programs V g =5V, V o =2V, T s =5us, L=1.0uH,
the reference voltage which is connected C=4800uF, G=5m, RL=0.25 Ω, Rs=10m
to the non-inverting input of the error am- Ω, ESR=7mΩ, Ro=1MΩ.
plifier. The output of the error amplifier
is connected to the COMP pin (pin16) and It is worthy noticing that at 8A load cur-
C28 is the compensation capacitor. rent, the inductor is considered to loss
Figure 6 captures the steady state op- 20% of the inductance due to the nature
eration of the regulation. The output of the power iron core. Also the value of
ripple voltage displayed in Ch3 is the Rs has included the ESR. The variables
ramp signal used in V2 control, which is in (10) are calculated using (1), (3), (7)
generated by the current ripple measured and (11)
in Ch4. Figure 7(a) demonstrates that the
regulator quickly responses to a harsh Fm=22.9, DC Gain =
20.5A load step and settles down to steady Vg*Fm*G*Ro=475000(113.5dB),
state operation in less than 100us. Figure ωo=2.1KHz, ξ=0.7, and fesr =4.7K,
Three values of Ccomp
are selected to reveal
its effect on the loop’s
frequency response.
The frequencies of fea
and fcoa, which are
the functions of Ccomp,
are calculated,
Ccomp = 4.7µF:
fea = 0.034Hz and
fcoa =170Hz;
Ccomp = 1.0µF:
fea =0.160Hz and
fcoa =799Hz;
Figure 6. The DC Operation oof the Buck Regulator
Ch 1 = GATEH Ccomp = 0.1µF:
Ch 2 = GATEL fea =1.600Hz and
Ch 3 = Output Voltage Ripple
fcoa =7.99KHz.
Ch 4 = Inductor Ripple Current (5A/10m V/div)
Figure 7. (a) The output voltage reacts to 20.5A load step. (b) The rising edge of the current step
Ch 3 = Output voltage
Ch 4 = Inductor current (5A/10mV/div)
192 International IC ‘99 • Conference Proceedings
In Fig.8, the frequency response of the
loop is measured by a Veneable Fre-
quency Analyzer, and compared with the
results derived from the small signal
model. During the measurement the loop
is broken at the connection between L1
and R8. A 100Ωz resistor is inserted be-
tween the node and R7. A floating AC
source, coupled through a transformer
from the analyzer, is applied across the
resistor. With the frequency of the AC sig-
nal sweeping across the interested range,
the AC voltage on each end of this resis-
tor is used as the input and output signals
to generate the bode plot. In Fig.8(b) and
Fig.8(c), the curves at the low frequency
range are truncated because the high gain
makes measurement extremely difficult.
The input signal is simply too small to be
identified among the noises. However, the
bode plots are reliably recorded in the
vicinity of the cross-over frequency,
where the shape of the curves is most
critical to the system performance. The
phase is not included in the Figure.8 be-
cause the attempt has failed due to the
inconclusive measurement results caused
by the low signal-to-noise-ratio.
As it is shown in Fig.8, the result from
the small signal model agrees very well
with the bench measurements on all three
compensation designs. The model has
accurately predicted the shape of the bode
plot by revealing the inherent zero at er-
ror amplifier’s cross-over frequency. The
model also provides a way to quantify the
loop gain in which PWM comparator gain
is the key for accurate calculation . The
model shows a slightly higher gain (about
5dB) across the frequency. This may be
caused by the approximation made on
amplifier’s transconductance and output
impedance. A lower L1 inductance at DC
current bias can also contribute the dis-
parity.
The frequency domain measurement
provides an insightful tool for design op-
timization. As it is
shown in Fig.8, a
large compensation
capacitor ensures the
system stability. It is
doing so by lowering
fcoa to gain enough
phase margin, which
on the other side may
tamper the transient
response. It is espe-
cially true when
“Adaptive Voltage
Positioning” is used
in which output DC
voltage varies with
the load. This re-
quires error amplifier
to charge/discharge
the compensation cap during the load
transient. A large cap will apparently in-
(a) Ccomp = 4.7µF
(b) Ccomp = 1.0µF
(c) Ccomp = 0.1µF
crease the charge/discharge time, and con-
sequently increase the load transient time.
A capacitor smaller than the optimum value
may jeopardize the system stability, which
is case shown in Fig.8(c ). As rule of thumb,
the loop shall cross over 0dB line at -20dB/
dec slope to safeguard the system stability.
When a small compensation capacitor is
used, fcoa is moved to a higher frequency.
When it is getting close to or beyond the
system cross-over frequency, system will
surfer from inadequate phase margin . As
shown in Fig.8, for this particular design,
using compensation capacitor of 1.0µF
achieves the best performance. This opti-
mum capacitor value is all it takes to com-
pensate a power supply with V2 control.
Conclusion and discussion
The paper has introduced a novel control
scheme, V2 control, which is designed to
achieve fast transient response with mini-
mum design effort. The V2 is compared
with the conventional voltage mode and
current mode control. It is revealed in the
paper that the major difference relies on
the source of the ramp signal. V2 uses the
output voltage and its ripple as the ramp
signal. Therefore, the V2 control can take
advantage of the instant feedback of the
output voltage during the load transient
and delay of the error amplifier is elimi-
nated. A small signal model is developed
to assist the designing and optimizing of
the power supply circuit with V2 control.
An inherent zero is revealed in the feed-
back path at the cross-over frequency of
the error amplifier. The frequency re-
sponse predicted by the small signal
model matches closely with the bench
measurement.
In V2 control signal, slope compensa-
tion technique is frequently used to im-
prove the signal-to-noise ratio and also
eliminate the subharmonic oscillation as-
sociated with the V2 control during fixed
frequency operation. Slope compensation
generates an artificial ramp when the high
side switch is turned on. This ramp can
be added to the output ripple or subtract
from the error amplifier output. As to the
system frequency response, the slope
compensation will reduce the gain by a
certain amount across the whole fre-
quency range. The higher the artificial
slope, the more reduction on the gain. A
quantitative analysis and measurement
remain for future studies.
Acknowledgement
Great thanks to George Lakkas and Ja-
son Solecki to let me use their demo cir-
cuit and test results.
References
[1] Dimitry Goder and William
R.Pelletier, V2 Architecture Provides
Ultra Fast Transient Response in
Switch Mode Power Supplies,
HFPC, 1996.
[2] R.D.Middlebrook and Slobodan
Cuk, A General Unified Approach
To Modeling Switching-Converter
Power Stages, Advance in Switch-
Mode Power Conversion, Volumes
I&II.
[3] Frank DiJoseph, Fault Tolerant
Power Supply System Uses the
Droop Method of Current Sharing,
PCIM Online, 6/18/97
Authors’ contact detail
Mike Wang
Applications Engineer
Cherry Semiconductor Co.
2000 South County Trail
East Greenwich, RI 02818
Email:mwg@cherry-semi.com
Phone: 401-541-3606
Fax: 401-886-3336
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