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February 2007
FDS6690A tm
These devices are well suited for low voltage and • Low gate charge
battery powered applications where low in-line power
loss and fast switching are required. • High performance trench technology for extremely
low RDS(ON)
DD 5 4
DD
DD 6 3
DD
7 2
SO-8 G
SS G 8 1
S
Pin 1 SO-8 SS S
Thermal Characteristics
RθJA Thermal Resistance, Junction-to-Ambient (Note 1a) 50 °C/W
RθJA Thermal Resistance, Junction-to-Ambient (Note 1b) 125
RθJC Thermal Resistance, Junction-to-Case (Note 1) 25
On Characteristics (Note 2)
Notes:
1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of
the drain pins. RθJC is guaranteed by design while RθCA is determined by the user's board design.
50 3
VGS = 10V 4.0V VGS = 3.0V
DRAIN-SOURCE ON-RESISTANCE
40 2.5
6.0V 4.5V 3.5.V
ID, DRAIN CURRENT (A)
RDS(ON), NORMALIZED
30 2
3.5V
20 1.5
4.0V
4.5V
6.0V
3.0V 10V
10 1
0 0.5
0 0.5 1 1.5 2 0 10 20 30 40 50
VDS, DRAIN-SOURCE VOLTAGE (V) ID, DRAIN CURRENT (A)
1.8 0.05
DRAIN-SOURCE ON-RESISTANCE
ID = 11.0A ID = 5.5A
1.6 VGS = 10V
RDS(ON), ON-RESISTANCE (OHM)
0.04
RDS(ON), NORMALIZED
1.4
0.03
1.2 o
TA = 125 C
0.02
1
o
TA = 25 C
0.8 0.01
0.6 0
-50 -25 0 25 50 75 100 125 150 175 2 4 6 8 10
TJ, JUNCTION TEMPERATURE (oC) VGS, GATE TO SOURCE VOLTAGE (V)
50 100
VGS = 0V
VDS = 5V
IS, REVERSE DRAIN CURRENT (A)
10
40
o
TA = 125 C
ID, DRAIN CURRENT (A)
1
30
o
0.1 25 C
20
o 0.01 o
-55 C
TA = 125 C o
25 C
10 0.001
o
-55 C
0 0.0001
1 1.5 2 2.5 3 3.5 4 0 0.2 0.4 0.6 0.8 1 1.2
VGS, GATE TO SOURCE VOLTAGE (V) VSD, BODY DIODE FORWARD VOLTAGE (V)
10 1600
ID = 11.0A VDS = 10V f = 1MHz
VGS, GATE-SOURCE VOLTAGE (V)
15V VGS = 0 V
8
1200
CAPACITANCE (pF)
20V Ciss
6
800
4
Coss
400
2
Crss
0 0
0 5 10 15 20 25 0 5 10 15 20 25 30
Qg, GATE CHARGE (nC) VDS, DRAIN TO SOURCE VOLTAGE (V)
100
100
100
1ms
RDS(ON) LIMIT IAS, AVALANCHE CURRENT (A)
ID, DRAIN CURRENT (A)
10 10ms
100ms
1s
10s
1 10
DC
Tj=25
VGS = 10V
SINGLE PULSE
0.1 o
RθJA = 125 C/W
Tj=125
o
TA = 25 C
0.01 1
0.01 0.1 1 10 100 0.01 0.1 1 10 100
VDS, DRAIN-SOURCE VOLTAGE (V) tAV, TIME IN AVALANCHE (mS)
Figure 9. Maximum Safe Operating Area. Figure 10. Unclamped Inductive Switching
Capability Figure
50
P(pk), PEAK TRANSIENT POWER (W)
SINGLE PULSE
40 R θJA = 125°C/W
TA = 25°C
30
20
10
0
0.001 0.01 0.1 1 10 100
t 1 , TIME (sec)
1
r(t), NORMALIZED EFFECTIVE TRANSIENT
D = 0.5
R θJA (t) = r(t) * R θJA
0.2
THERMAL RESISTANCE
0.05
P(pk)
0.02
0.01
t1
0.01 t2
T J - T A = P * R θJA (t)
SINGLE PULSE Duty Cycle, D = t 1 / t 2
0.001
0.0001 0.001 0.01 0.1 1 10 100 1000
t1, TIME (sec)
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intended to be an exhaustive list of all such trademarks.
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E2CMOS™ ISOPLANAR™ PowerSaver™ SyncFET™
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FACT® MICROCOUPLER™ QFET® TinyBoost™
FAST® MicroFET™ QS™ TinyBuck™
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FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS
HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE
APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS
PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S
WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS.
No Identification Needed Full Production This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Rev. I22