Academic Course Description

SRM University
Faculty of Engineering and Technology
Department of Electronics and Communication Engineering
EC1108 Computer Architecture and organization
Fourth Semester, 2014-15 (Even Semester)

COURSE (CATALOG) DESCRIPTION

This course discuss the basic structure of a digital computer and used for understanding the
organization of various units such as control unit, Arithmetic and Logical unit and Memory unit and I/O unit
in a digital computer.

Compulsory/Elective course: Department Elective for ECE students

Credit hours: 3 credits

Course coordinator(s): Mr. S. Manikandaswamy, Assistant Professor (O.G), Department of ECE

INSTRUCTOR(S)

Office Email Consultations

Name of the instructor
location @ktr.srmuniv.ac.in (Day 1 to Day 5)

Dr. Ruhan Bevi

TP1214 ruhan.b (12:50 - 1:30) PM

Dr. Rahimunnisa TP1306A rahimunnisa.k (12:50 - 1:30) PM

Mr. S. Manikandaswamy
TP1208 manikandaswamy.s (12:50 - 1:30) PM

Mr. Prithiviraj
TP1015 prithiviraj.r (12:50 - 1:30) PM

Relationship to other courses

Pre-requisites : Nil

Assumed knowledge : Basic knowledge in Digital systems

Following courses : Nil

Page1 of 12
Syllabus Content

UNIT I-INTRODUCTION (9 hours)

Evolution of Computers, VLSI Era, System Design- Register Level,Processor Level, CPU
Organization, Data Representation, Fixed –Point Numbers, Floating Point Numbers, Instruction
Formats, InstructionTypes. Addressing modes.

UNIT II-DATA PATH DESIGN (9 hours)

Fixed Point Arithmetic, Addition, Subtraction, Multiplication and Division,Combinational and
Sequential ALUs, Carry look ahead adder, RobertsonAlgorithm, Booth’s algorithm, non-restoring
division algorithm, FloatingPoint Arithmetic, Coprocessor, Pipeline Processing, Modified booth’s
algorithm

UNIT III-CONTROL DESIGN (9 hours)

Hardwired Control, Micro programmed Control, Multiplier Control Unit,CPU Control Unit, Pipeline
Control, Instruction Pipelines, PipelinePerformance, Superscalar Processing, Nano Programming.

UNIT IV-MEMORY ORGANIZATION (9 hours)

Random Access Memories, Serial - Access Memories, RAM Interfaces,Magnetic Surface Recording,
Optical Memories, multilevel memories, Cache& Virtual Memory, Memory Allocation, Associative
Memory.

UNIT V-SYSTEM ORGANIZATION (9 hours)

Communication methods, Buses, Bus Control, Bus Interfacing, Bus arbitration, IO and system control,
IO interface circuits, Handshaking, DMA and interrupts, vectored interrupts, PCI interrupts, pipeline
interrupts, IOP organization, multiprocessors, RISC and CISC processors, Superscalar and vector
processor.

TEXT BOOKS

1. John P.Hayes, “Computer architecture and Organisation”, Tata McGraw-Hill, Third dition, 2012.

2. V.Carl Hamacher, Zvonko G.Varanesic and Safat G.Zaky, “Computer Organisation“, V Edition,
Reprint 2012,Tata McGraw-Hill Inc.

Page1 of 12
REFERENCES

1. Morris Mano, “Computer System Architecture”, Third Edition,Prentice-Hall of India, 2000.

2. Paraami, “Computer Architecture”, E i g h t h impression, 2 0 1 1 , Oxford Press.

3. P.Pal Chaudhuri, , “Computer organization and design”, 2nd Edition., Prentice Hall of India, 2007.

Class schedule : Three 50 minutes lecture sessions per week, for 14-15 weeks

Section Schedule
Batch 1 14 – 15 weeks
Batch 2 14 – 15 weeks

Professional component
General - 0%
Basic Sciences - 0%
Engineering sciences & Technical arts - 0%
Professional subject - 100%
Broad area : Communication | Signal Processing | Electronics | VLSI | Embedded
Course objectives
Correlates to
The objectives of this course is to Program
Objective
1. To have a thorough understanding of the basic 2,3
structure and operation of a digital computer.
2. To discuss in detail the operation of the arithmetic
unit including the algorithms &implementation of fixed-
3,4
point and floating-point addition, subtraction,
multiplication &division.
3. To study in detail the different types of control and 2,3
the concept of pipelining.

4. To study the hierarchical memory system including 2,3,4

cache memories and virtual memory.
5. To study the different ways of communicating with 2,3
I/O devices and standard I/O interfaces.

Page1 of 12
Course Learning Outcome

This course provides the foundation education in the Correlates to

basics of a digital computer and make understanding program outcome
the organization of various units such as Control unit,
Arithmetic and Logical unit, Memory unit and I/O unit
H M L
in a digital computer.

1. To have a thorough understanding of the basic structure and a, k d b

operation of a digital computer.

2. To discuss in detail the operation of the arithmetic unit including b a k

the algorithms &implementation of fixed-point and floating-point
addition, subtraction, multiplication &division.

3. To study in detail the different types of control and the concept of d b k

pipelining.

4. To study the hierarchical memory system including cache d b k

memories and virtual memory.

5. To study the different ways of communicating with I/O devices d, k a, b

and standard I/O interfaces.

H: high correlation, M: medium correlation, L: low correlation

Teaching plan:

Problem Correlates to
Week Topics solving program Text/Page.No
(Yes/No) outcomes
1,2,3
UNIT I-INTRODUCTION
Evolution of Computers, VLSI Era No a T1/35 - 50
System Design No b, k T1/64 - 83
No b, k T1/83 – 97, 114 -
Register Level, Processor Level 118
CPU Organization No T1/ 137 - 147
Data Representation, Fixed –Point No a, b T1/160 - 178
Numbers, Floating Point Numbers
No a, b, k T1/178 - 184
Instruction Formats

Page1 of 12
 No a, b, k T1/ 191 - 202
Instruction Types
No a, b, k T1/ 191
Addressing modes
4,5,6 UNIT II-DATA PATH DESIGN
No a, b, k T1/ 223 - 251
Fixed Point Arithmetic, Addition,
Subtraction, Multiplication and
Division,
No b T1/ 252 – 254,
Combinational and Sequential ALUs 254 - 265
No b T1/228 - 231
Carry look ahead adder,

RobertsonAlgorithm, Booth’s No a, b, d T1/238 - 242

algorithm,
non-restoring division algorithm, No a, b, d T1/249 – 250,
FloatingPoint Arithmetic, 266 - 270
Coprocessor, Pipeline Processing, No d, k T1/272 -292
Modified booth’s algorithm No d, k T1/
7,8,9 UNIT III-CONTROL DESIGN
Hardwired Control, No b, d T1/308 - 315

Micro programmed Control No b, d T1/332 -340

.
Multiplier Control Unit, No b, d T1/344 - 353

CPU Control Unit, T1/ 354 -361

Pipeline Control, Instruction Pipelines No b, d, k T1/364 – 371,

Pipeline No a, k T1/371 - 383

Performance,
Superscalar Processing, Nano No d, k T1/384 – 389,
Programming 361 - 364

10,11,12 UNIT IV-MEMORY ORGANIZATION

Memory device characteristics, No d, k T1/400 – 402,
Random Access Memories 407 - 411

Serial - Access Memories, RAM No d, k T1/418 - 420

Interfaces,

Magnetic Surface Recording No d, k T1/ 420 - 424

Page1 of 12
 Optical Memories No d, k T1/ 424 - 425

Multilevel memories, Cache No b, d, k T1/ 426 - 428

& Virtual Memory
Memory Allocation, No a, d T1/443 - 447
Associative Memory. No a, d T1/458 - 459
13,14,15 UNIT V-SYSTEM ORGANIZATION
Communication methods No a, d T1/480 - 490

Buses, Bus Control, Bus Interfacing No d T1/491-495

Bus arbitration No d T1/ 498 - 501

IO and system control, IO interface No b, d T1/ 504 - 509

circuits,

Handshaking, No b, d T1/513 - 517

DMA and interrupts,

Vectored interrupts, PCI interrupts, No d T1/517 - 520

pipeline interrupts,IOP organization No d T1/522 - 526

multiprocessors, RISC and CISC No a, d, k R1/ 284

processors,

Superscalar Processor No a, d, k R1/ 327 - 329

.
vector processor No a, d, k R1/ 321 - 324

Evaluation methods
Cycle Test – I - 10%
Cycle Test – II - 10%
Model Test - 20%
Surprise Test - 5%
Attendance - 5%
Final exam - 50%

Prepared by:, Mr. S. Manikandaswamy, Assistant Professor (O.G), Department of ECE

Page1 of 12
 th
Dated: 07 January 2015
Revision No.: 00 Date of revision: NA Revised by: NA

Addendum

ABET Outcomes expected of graduates of B.Tech / ECE / program by the time that they graduate:
a. Graduates will demonstrate knowledge of mathematics, science and engineering.
b. Graduates will demonstrate the ability to identify, formulate and solve engineering problems.
c. Graduate will demonstrate the ability to design and conduct experiments, analyze and interpret data.
d. Graduates will demonstrate the ability to design a system, component or process as per needs and
specifications.
e. Graduates will demonstrate the ability to visualize and work on laboratory and multi-disciplinary
tasks.
f. Graduate will demonstrate the skills to use modern engineering tools, software’s and equipment to
analyze problems.
g. Graduates will demonstrate the knowledge of professional and ethical responsibilities.
h. Graduate will be able to communicate effectively in both verbal and written form.
i. Graduate will show the understanding of impact of engineering solutions on the society and also
will be aware of contemporary issues.
j. Graduate will develop confidence for self education and ability for life-long learning.
k. Graduate will show the ability to participate and try to succeed in competitive examinations.

Program Educational Objectives

1. To prepare students to compete for a successful career in Electronics and Communication
Engineering profession through global education standards.
2. To enable the students to aptly apply their acquired knowledge in basic sciences and mathematics in
solving Electronics and Communication Engineering problems.
3. To produce skillful graduates to analyze, design and develop a system/component/ process for the
required needs under the realistic constraints.
4. To train the students to approach ethically any multidisciplinary engineering challenges with
economic, environmental and social contexts
5. To create awareness among the students about the need for life long learning to succeed in their
professional career as Electronics and Communication Engineers.

Page1 of 12
 Class handling Name of the instructor
Signature

Batch 1 Dr. Ruhan Bevi

Batch 1
Dr. Rahimunnisa

Batch 1
Mr. S. Manikandaswamy

Batch 1
Mr. Prithiviraj

Course Coordinator Academic Coordinator Professor In charge

(Mr. S. Manikandaswamy) ( Mr. U Hari / Mrs. Manohari) ( Dr.Shanthi Prince)

Page1 of 12