EC1115 ASIC Design

Academic Course Description

SRM University
Faculty of Engineering and Technology
Department of Electronics and Communication Engineering

EC1115 ASIC Design

Seventh Semester, 2016-17 (Odd Semester)

Course (catalog) description

An application-specific integrated circuit (ASIC) is an integrated circuit customized for a particular
use, rather than intended for general-purpose use. In this course, the reader is introduced to various ASIC
architectures, ASIC design flow, issues in ASIC design and testing of ASICs.
Compulsory/Elective course: Elective Course for ECE students

Credit hours: 3 credits

Course coordinator(s): Mrs.K.Ferents Koni Jiavana, Assistant Professor (O.G), Department of ECE

Course Instructor(s):
Office Office Email (domain:
Name of the Instructor Class
location phone @ktr.srmuniv.ac.in)
Mrs. K. Ferents Koni
Y2 TP1010 2070 ferentskoni.k
Jiavana
Mr. B. Srinath Y4 TP1106A 2063 srinath.b

Relationship to other courses

Pre-requisites : EC1012 Electronic Circuits
Following courses : Nil

Text books, References

1) Smith.M.J.S, “Application Specific Integrated Circuits”, Addison Wesley Longman Inc., 1996. (Pearson
Education Reprint 2006).
2) Sarafzadeh.M. and Wong.C.K, “An Introduction to VLSI Physical Design”, McGraw Hill, 2nd Edition, 1996.
3) Wolf Wayne, “FPGA based system design”,Pearson Education, 2005.
4) Design manuals of Altera, Xilinx and Actel.
5) Jan M. Rabaey. Anantha Chandrakasan, Borivoje Nikolic, “Digital Integrated Circuits”, Prentice-Hall
Publication, 2nd Edition, 2002.

Computer usage: Nil

Class schedule: Three 50 minutes lecture sessions per week for 15 weeks
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 EC1115 ASIC Design
Professional component
General - 0%
Basic Sciences - 0%
Engineering sciences & Technical arts - 0%
Professional subject - 100%

Broad area : Communication | Signal Processing | Electronics | VLSI | Embedded

Course objectives
Correlates to
The goals of the course is to ensure that the learners become familiar Program Objective
H M L
1. To give basic knowledge of ASIC internals. a d j
2. To impart knowledge on ASIC types and tools used in the design. a c,j i
3. To give basic understanding of tools used. c d i

H: high correlation, M: medium correlation, L: low correlation

Teaching Plan

Correlation of
Session Problem
Topic Text / Chapter Topics with
# Solving
IOs
1 Introduction to ASICs - - -
UNIT I : INTRODUCTION TO ASICS
2 Full-custom and Semi -custom ASIC [1] Chapter-1 N 1
4-6 CMOS logic [1] Chapter-2 Y 1
7-9 ASIC library design [1] Chapter-3 N 1
10 Summary & Quiz on Unit-4 - -
UNIT II : PROGRAMMABLE ASICS
11 Programmable ASICs – Anti fuse [1] Chapter-4 N 2
12 Static RAM, EPROM and technology [1] Chapter-4 N 2
13 Actel ACT [1] Chapter-5 N 2
14 Xilinx LCA, Altera flex, Altera MAX Logic cells [1] Chapter-5 N 2
15-16 I/O cells [1] Chapter-6 N 2
17-18 Interconnects [1] Chapter-7 N 2
19 Low level design entry: Schematic entry. [1] Chapter-9 N 2
20 Summary & Quiz on Unit-2 - N -
UNIT III-SIMULATION AND SYNTHESIS

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 EC1115 ASIC Design
Correlation of
Session Problem
Topic Text / Chapter Topics with
# Solving
IOs
21 Logic synthesis: A comparator MUX [1] Chapter-12 N 2
22 Inside a logic synthesizer [1] Chapter-12 N 2
23 VHDL and logic synthesis systems [1] Chapter-12 N 2
24 FSM synthesis [1] Chapter-12 N 2
25 Memory synthesis [1] Chapter-12 N 2
27 Simulation: Types of simulation [1] Chapter-12 N 2
28 How logic simulation works. [1] Chapter-12 N 2
29 Summary & Quiz on Unit-3 - N -
UNIT IV-ASIC TESTING
30-31 Boundary scan test [1] Chapter-14 N 4
32 Faults ,Fault simulation [1] Chapter-14 N 4
Automatic test pattern generation algorithm:
33-34 [1] Chapter-14 Y 4
D-algorithm
35-36 PODEM [1] Chapter-14 Y 4
37-38 Built in self test. [1] Chapter-14 Y 4
Summary & Quiz on Unit-4
UNIT V: ASIC CONSTURCTION
36 System partitioning, power dissipation [1] Chapter-14 N 1
37 Partitioning methods [1] Chapter-14 N 1
38-49 Floor planning and placement [1] Chapter-14 N 1
Routing: Global
40 [1] Chapter-14 N 1
routing, detailed routing, special routing
41 Introduction to SOC [1] Chapter-14 N 1
Summary & Quiz on Unit-5 - N -

Test Schedule

S. No. Test Portions Date Duration

1 Cycle Test-1 Session 1 to 9 TBA 1 period
2 Cycle Test-2 Session 11 to 28 TBA 2 Periods
3 Model Test Session 1 to 45 TBA 3 Hrs
4 End-Sem Exam All sessions / units TBA 3 Hrs

Evaluation Methods
Cycle Test – I - 10%

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 EC1115 ASIC Design
Cycle Test – II - 10%
Model Test - 20%
Surprise Test - 5%
Attendance - 5%
Final exam - 50%

Prepared by: Mrs.K. Ferents Koni Jiavana, Assistant Professor (O.G), Department of ECE

Dated: 28-Jun-2016 Revision No.: 00 Date of revision: NA

Course Co-ordinator Academic Coordinator Professor In-charge

(K.Jiavana) (Mrs. Saraswathi N) (Dr. Ramachandran B)

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