Tutorial Problems – 1 – Feb - 2018

1. Draw the static and dynamic load lines for the circuit shown in Fig. 1.
Given : β = 100; VBE = 0.5 V

IC(sat)= 0.87 mA
IC’(sat) = 6.0 mA
ICQ = 0.2644 mA
VCQ = 6.96 V
Rb = 3.55 k
V = 0.91 V

Fig. 1
2. A silicon transistor used in potential divider bias circuit has β = 150, RC = 2k and VCC = 20V.
The operating point is selected at 10 V, 1 mA. The parallel combination of R1 and R2 is 20 k.
Find the values of RE, R1 and R2. (Take VBE = 0.6 V)
RE = 7.95 k, R1 = 45.8 k, R2 = 35.5 k
100, VBE = 0.5 V
3. Given ICQ = 2 mA and VCEQ = 10 V, determine R1 and RC for the circuit of Fig. 2. Assume VBE =
0.7 V. (Hint : Take IE = IC as β is not given) RC = 2.8 k, R1 = 106.43 k

4. The transistor circuit shown in Fig. 3 uses a silicon transistor with IC = IE and a dc current gain
of 100. Find the value of Vo.
Vo = 4.65 V

Fig. 2 Fig. 3
5. In a potential divider bias circuit, VCC = 10 V, hfe = 150 and VBE = 0.6 V. Select suitable
resistance values to establish the dc operating point of the BJT at 4 V, 2 mA with a voltage
drop of 2 V across the emitter resistor. Assume the current in the resistance connected
between VCC and base of the transistor as 20 times the base current.
RC = 2 k, RE = 0.99 k, R1 = 27.75 k, R2 = 10.26 k
100, VBE = 0.5 V

6. For the two stage amplifier shown in Fig. 4, compute (i) input and output impedances, (ii) the
individual and over all voltage gains by drawing the mid frequency ac equivalent circuit of the
amplifier. Assume hfe = 100 and hie = 3 k. hoe and hre are negligible.
Zi = 7.88 k, Zo ≈ 3 k, Av2 = - 236, Av1 = -0.64, AvT = 151

Fig. 4

7. For the circuit shown in Fig. 5 determine the input resistance and the voltage gain. Assume hfe
= 200 and hie = 1 k. hoe and hre are negligible. Ri = 34 k, Av = 0.971

Fig. 5
8. If two common emitter amplifier stages are cascaded together with f L and fH of each stages
respectively being 50 Hz and 100 kHz, calculate the overall bandwidth of the stage.

fH,T = 64.4 kHz, fL,T = 77.7 Hz, Bandwidth = 64.3 kHz

9. For the figure shown in Fig. 6, the following data are given:
For CE amplifier: RC = 1k, hie = 1k and hfe = 150.
For the Darlington Emitter Follower (DEF) : R1 = 10 k, R2 = 22 k, RE = 22 Ω, RL = 8 Ω;
hfe = 100 for each transistor.
Find (i) the voltage gain of CE amplifier directly driving the speaker
(ii) the voltage gain of CE amplifier with DEF in between CE amplifier and speaker
(iii) overall gain of the circuit.
𝐀𝐕 = − 𝟏. 𝟏𝟗, 𝐀𝐕𝟏 = 𝟏𝟐𝟗, 𝐀𝐕𝟐 = 𝟎. 𝟖𝟑𝟕, 𝐀𝐕𝐓 = 𝟏𝟎𝟖

Fig. 6