Systems for Digital Signal

Processing
5 – A/D and D/A conversion
• Ideal continuous-time/discrete-time (C/D) conversion
• Nyquist sampling theorem
• Real A/D conversion and design issues
• Examples of ADC architectures
• Ideal discrete-time/continuous-time (D/C) conversion
• Real D/A conversion and design issues
• Examples of DAC architectures
• Down-sampling and up-sampling
1
 Ideal C/D conversion
xc(t) C/D x(n)
Continuous-time signal Discrete-time sequence

T Sampling period

x n   xc nT   xc t  
n  
 t  nT  «Digital» frequency

«Analog» frequency T  
Continuous-time F

 
  
 2k  1  2k  1   2k 
 X c    
1
X e j     X c    Xc   
k   
T T  T k    T T k   T T 

The spectrum (or PSD) of a sampled signal consists of infinite (scaled) replicas
centered at 2πk/T in the continuous frequency domain Ω or at 2π in the discrete
frequency domain ω
2
 Frequency-domain representation
X c 
1

 N N 
Infinite spectral replicas
X s 
1
Multiply times 1/T T

… …

 4T  2T  N N 2 4 
T T
1
T  
X e j In the digital frequency
domain the frequency axis
is «stretched» or
«compressed»
…
…
4 2  N T  N T 2 4 
3
 Nyquist sampling theorem
• Let xc(t) be a bandlimited signal with
X c   0 for    N
• Then xc(t) is uniquely determined by its samples x(n)= xc(nT) if
2
s   2f s  2 N
T
where N is generally known as the Nyquist frequency
• The sampling frequency cannot be smaller than 2 N not to incur in
aliasing of the spectral replicas. Aliasing would lead to an
unrecoverable distortion of the frequency content

Xs j s>2 N

3 s -2 s s - N N s 2 s 3 s

Xs j s<2 N

3 s -2 s s - N N s 2 s 3 s
4
 Analog-to-digital conversion
Anti-aliasing Sample & Hold Analog-to-digital
(analog) filter Amplifier (SHA) x(n) converter (ADC)
xc(t) Zero-order Quantizer Coder
xB(n)
Ha(Ω) C/D Hold (ZOH) Q(∙) C(∙)

T
• The anti-aliasing filter ideally has a constant (e.g. unit) gain and a cutoff
frequency equal to π/T to make the signal bandlimited and to meet the Nyquist
theorem requirements. In practice, it should be as simple as possible (i.e. not
very selective)

• The SHA samples the input signal and it keeps it constant for a time long enough
to assure proper A/D conversion. The hold time TH≤T

• The ADC at first maps the input signal (e.g. a staircase voltage) into one of the
levels of the quantizer, and then it returns a binary code associated to this level.
5
 Basic sample & hold architecture
• In order to perform a correct A/D conversion correctly, the signal has to be
kept constant approximately for all the duration of the quantization process
Switch can be
modeled as a time
varying resistor

Hold capacitor CH
stores the input value

Ideal behavior
• When vc(·)=1 then vy(·)= vx(·): signal is tracked
• When vc(·)=0 then vy(·)= cost.
• Ton negligible
Real behavior
• Ton could not be negligible compared with sampling period T . In this case
we have spectral distortion
6
 General design criteria

= Low pass filter

Sampling mode
• Output must track quickly input variations without filtering then ON=RONCH small

Sample to Hold (S H) transient

• Charge stored into CH and in the parasitic capacitors of the SHA (e.g. in the
switch) are redistributed charge offset CH large
Hold mode
• Capacitor has to hold the value low discharge rate OFF= ROFFCH very large.
In particular, in the transient phase between S H, CH>>Cparasitic
Hold to sample (H S) transient
• The acquisition transient after closing the switch should be as fast as possible
ON=RONCH small RON small
7
 Quantization
Code bin width • A given range [Vmin,Vmax] is divided into
a set of separate intervals Ik=(Tk-1, Tk]
where Tk is the k-th threshold voltage
Code bin
• Each interval corresponds a certain
code bin Qk, which is wide Qk= Tk -Tk-1

• The ideal ADC characteristic is

Q(xs)=Qk for Tk-1<xs Tk

• The ADC input range can be:

– Unipolar f Vmin=0 & Vmax=FS
– Bipolar if Vmin=-FS & Vmax=FS

• Quantization error: eq=Q(xs)-xq

– If |xs| FS granularity error
– If |xs| FS overloading error
Rounding case

8
 Quantization error: stochastic model
• As quantization is a non-linear operation, a full analytic model is complex.

• However, if the input signal changes randomly and the difference between two
consecutive samples is much larger than the quantization step, the error can be
modeled as a realization of an additive stochastic process eq[·] having the
following characteristics
– White and stationary
– Uncorrelated from the input signal xs
– With a uniform pdf in: x + xq
• [-Q/2,Q/2] (if rounding is used)
• [-Q,0] (if a truncation is used) eq

• The model holds exactly if the input signal x(·) is a white noise
• The mean value and the variance of the quantization noise are respectively:

q  0 Q2
 q2  (rounding case)
12
Q Q2
q   q2  (truncation case)
2 12

9
 Signal-to-noise and quantization ratio
• If we consider an ideal bipolar ADC with B bits (i.e. 2B levels)
2   2 12   2 3 2B 
SQNR  10 log10 2  10 log10  x 2  10 log10   x
 x    2 
q   Q   FS 2 
     

3
SQNR  6.02 B  20 log10  x  20 log10
FS
• Every additional bit of resolution improves SQNR by 6 dB
• If truncation instead of rounding is used in the quantizer, for the same number of
bits the SQNR is 4 times smaller
• In order to maximize the SQNR, the input signal should be properly amplified to
exploit the whole input range of the A/D, i.e. [-FS, FS]. For this reason, most
ADCs include a programmable gain amplifier before the quantizer.
• If we assume that x(n) is uniformly distributed in [-FS, FS], then
FS 2 FS 2  2 2 B 2 2 B 1  x2
 x2  q 
2
 x 2
2
 B  log2 2
3 12 2 q
10
 Effective number of bits (ENOB)
• In real ADCs, actual performances for a given number of bits are lower than in the
ideal case due to:
– Imperfections of ADC circuitry nonuniform quantization harmonics and spurious
tones in the output spectrum
– Additional wideband noise sources due to thermal and semiconductor noises in the
front-end acquisition circuitry (SHA and anti-aliasing filter)
– Additional noise overlapped to the input signals
• All these contributions can be assumed to be uncorrelated.
Additional ADC noise Other noise sources
external to ADC
1  x2
 t2   q2   c2   a2   q2   w2 ENOB  Be  log2 2
2 t
(Total) signal-to-noise ratio (SNR)
Notes
1  x2 1  q2 • ENOB is a function of frequency
Be  log2 2  B log2 2 
2 t 2  q   w2 • ENOB can be computed as a function
of SINAD (i.e. ratio between the signal
1  2  1   2  power and the total noise power
 B  log2 1  w2   B  log2 1  2 2 B  (wideband+narrowband terms) when
w
2  q  2   2  the test signal is a FS-large sinewave
   x 
11
 Selection criterion of ADC resolution
Be
 w2   q2  Be  B  0.5 Corner points
 w2   q2  Be  B …
16

Bopt
12
w
10  w2   q2  Be   log2
8 x
…

 *w 
log2 * log2 w
x x
• In a given application, if the additional noise power can be estimated, the
optimal ADC resolution is the value of B for which the corner point is
reached, i.e.   *w  Round-to-the-nearest-
Bopt   log2 * 
  x  integer operator

• If B>Bopt the ADC is more accurate (and expensive) than necessary (the
additional bits of resolution cannot be exploited)
• If B<Bopt the performance degrades because of larger quantization noise
12
 ADC types
Typical mechatronic
applications

In general, 1 bit of nominal resolution is lost when the sampling frequency doubles

• Flash Interleaved ADCs: fs =~1 − ~10 GSa/s and B = 6 - 10 bits

• Flash ADCs: fs ~10 MSa − 1 GSa/s and B = 8 -12 bits
• Flash Two-step ADCs: fs ~ 10 − 100 MSa/s and B = 10 -12 bits
• Multi-step ADCs: fs ~ 100 kSa/s − 100 MSa/s and B = 12 -16 bits
• Sigma-delta ADCs: fs ~ 10 kSa/s − 10 MSa/s and B = 16 - 24 bits
• Integration-based ADCs: fs ~ 10 Sa/s − 10 kSa/s and B = 20 - 28 bits

13
 Example: flash ADC - 1
Example: B=3
+VR xc
• Simultaneous comparison between xc(∙) and
2B-1 Tx obtained from a resistive network 
3R/2 +
T7 -
• Comparators are clocked SHA not required 
R +
T6 -
• Comparator outputs are thermometer - R

+
encoded, e.g. all comparators for which T5 -
xc(∙) <Tk returns ‘0’, while the others return ‘1’  Decoding b2
R +
T4 Digital xB
- b1
network
• A digital binary encoder maps the comparator 
R + b0
output sequence into a classical integer or T3 -
2’complement representation 
R +
T2 -
• Good component matching is required 
R +
T1 -
XC(C2) 100 101 110 111 000 001 010 011
VXq -4 -3 -2 - 0 + +2 +3 R/2
VX
Tk -7/2 -5/2 -3/2 -/2 +/2 +3/2 +5/2
-VR

14
 Example: flash ADC - 2
• Flash ADC are simple, but the number of comparators and resistors
grows exponentially with B
– High chip area
– High design complexity
– High power consumption
– High risk of component mismatching poor accuracy due to nonuniform Tx

• Uncertainty sources more critical on Bmax than other parameters

– Static sources occur when xc changes slowly
– Dynamic sources occur when xc has high frequency components

15
 Example: multi-step ADCs
• Multi-step ADCs enable a higher output resolution at a slower sampling
frequency by dividing the conversion operations into a sequence of multiple
steps. Three possible solutions exist:
– Ripple-through
– Pipeline
– Successive approximations
Ripple-through
Clock signals N identical stages
0 1 n N • Each stage consists of an
vX VY VR1 VRn-1 VRn VRN-1 ADC, a DAC, a subtractor
SHA stage 1 stage n stage N and an amplifier
XC1 XCn XCN
• The residual (difference)
from 1 stage becomes the
quantity to be converted by
the following stage
VRn-1 ADC DAC VCn VRn
-+ 2bn
bn bit bn bit • Amplification by 2B may be
required to adapt the
n XCn data out residual to the input range
16
 When a SHA should be used?
• General rule: variations of the input signals xc(·) must be lower than 1/2 LSB
for all the time required for A/D conversion, i.e.
xc t   c TADC 
dx Q
dt t 2
• If a sine wave is considered xc t   A sin2f 0t    the previous condition is
met in the worst case (max. slope of a full scale sine wave, A=FS) if:

2  FS 1
xc t   2f 0 FS  TADC  f 0max 
2 B 1 2 2 B TADC
• This condition is very strict. If B=12 and TADC= 10 s f0=4 kHz <<1/TADC
• A SHA assures that the sampled input signal is constant, thus increasing the
input frequency range. In this case:

1 1
f 0max  

2TCmin 2 TACQ  TAP  Ts  T j max  TADC 
ADC
conversion
S/H acquisition time(tracking) S H transient time Settling time Jitter (max) time
17
 Ideal D/C conversion - 1
y(n) D/C yc(n)
Discrete-time sequence Continuous-time (reconstructed) signal


Yc   TY e jT  for   T Ideal low-pass
reconstruction filter
1
T 
Y e jT 
… T …

 4T  2T  T  N N  2 4 
T T T

• In principle, D/C conversion is very simple: it can be implemented just

using a low-pass filter with gain equal to the sampling period T and
bandwidth equal to the maximum Nyquist frequency, i.e. π/T

18
 Ideal D/C conversion - 2
• In the time domain, the low-pass filtering leads to the following result:

  
 

yc t     
1 jT T jT jT
   d 
T T
Y e d Y e e
2 2
c
 T T 

  

 y n  
j t  nT 
 y n  sinc t  nT 
T
 d 
T
e
n  
2 T 
n  
T

• This means that the analog signal can be obtained through interpolation,
namely from the linear combination of infinite replicas of sinc functions
centered at times nT. Unfortunately, as known, this implementation is not
feasible.
Hr(Ω)
Continuous-time F-1


T 
T
19
 Digital-to-Analog conversion
• Real digital-to-analog converters (DAC), typically rely on three sections
– A binary decoder, mapping binary sequences yb(·) into quantized discrete-time
sequences y(·)
– A sample-and-hold, which turns the discrete-time sequence y[·] into a staircase analog
signal yh(·).
– A feasible low-pass reconstruction filter (also called interpolator) to smooth the output
waveform and to compensate the distortion caused by the sample-and-hold (if possible)

yb(·) y(·) yh(·) Low-pass yr(·)

Sample
Decoder & Hold
reconstruction
filter (interpolator)
Typically implemented
T together

• A DAC does not perform exactly the reverse operation of an ADC, because the
role of the sample-and-hold is intrinsically different.
• Unlike the ADC case, just a few DAC architectures exist. However, also in this
case, higher resolution requires lower sampling rates and vice versa.

20
 Sample-and-hold distortion
|HH(Ω)|
hH(t) Continuous-time F
1

0 T t Ω
Inpulse response of a Magnitude of the frequency
zero-order hold function response
 
y H t   y n   rect t TnT   yn   t  nT * rect Tt 
n   n  

F
  
 
2k   j2T

2T   e 2T   Y    2Tk 
jT
YH   Y e jT 1  1
    e sinc 2
sinc 
k   
T T  T  k   
• The spectrum of the output signal is modulated by a sinc(∙) function. As a consequence,
the spectral replicas for k≠0 are strongly attenuated, while the component for k=0 is
smoothed due to the roll-off mainlobe of the sinc(∙) function.

21
 Compensated reconstruction filter
• The reconstruction filter should be designed, so as to compensate for
the distortion caused by the zero-order hold function, i.e.

 T
 H H     T
H r    
~

0 otherwise
H r 
~


T 
T

• Note: The spectral distortion due to the S/H theoretically is also present
in the acquisition stage (i.e. before the ADC). However, in that case it
does not affect the spectrum of the sampled signals, because the ADC
circuitry just operates on the «held» values as if they were numbers,
regardless of pulse duration.
22
Example: binary-weighted voltage DACs
VR
• The current flowing in the n-th
R R/2 … R/2(b-1) resistor when the switch controlled
Rr by the n-th bit is closed is:
b1 b2 bb
VR
- Vo In 
LSB MSB
+ R / 2n 1

• The ratio between successive resistors is ½

• Therefore the output DAC voltage is:

B B

 
VR VR n 1
Vo   Rr bn n 1
  Rr bn 2
n 1 R / 2 R n 1
Problems
• Difficult to build precise resistors with values in the range [R, R/2B-1] Bmax= 6-8
• Sudden large current drains from VR fluctuations due VR internal resistance and
glitches when multiple bits change at the same time low accuracy as b grows
• Voltage drop across closed switches modifies the ideal resistance values
23
Example: binary-weighted current DACs
I 2I … 2b-1I
Rr
b1 b bb

- Vo
LSB MSB
+

• By replacing the resistor network with a series of current generators, we have

a similar result, i.e.
B
Vo   Rr I 
n 1
bn 2 n 1

• Advantage: voltage drop across switches do not affect the output voltage
• Unresolved problem: it is difficult to build precise current generator with
values in the range [I, 2B-1I]

24
An example of binary weigthed DAC

25
 Example: R-2R ladder network DAC
R R 2R
VR

VR 2R 2R 2R 2R
IR  Rr
R
b1 b2 bb
0 1 0 1 0 1 0 1 Vo
-
+

• Resistors take only two values R and 2R easier to build

• The equivalent resistance seen from any node of the input ladder is always R
regardless of the input binary configuration when bi=1
i-th stage
• In order to have a perfect current division:
R Req
Req=2R
2Ii Ii
Veq 2R Ii
B B

 
V 1 1
Vo   Rr I R bn n   Rr R bn
n 1 2 R n 1 2n
26
 Example of R-2R ladder DAC
Maxim MAX541-MAX542
• Full 16-Bit Performance Without Adjustments
• +5V Single-Supply Operation
• Low Power: 1.5mW
• 1 μs settling time
• Maximum Fs=10 MHz

27
 Unit-Element Current Source DACs
• Higher conversion speed by:
1. Encoding the input binary word using a thermometer
encoder: B bits c=2B output values
2. If xb is the input integer value, we have that the xb least
significant lines of c are active (e.g. high)
3. Encoder outputs enable/disable a matrix of equal
current generators IU
4. Unit-element current values sum-up like in the binary-
weighted case so that
2B
Vo   Rr  IU  c
n 1
n

Advantages
• Unit element DACs ensure monotonicity by turning
on equal-weighted current sources in succession
• No glitches when switching times in a D/A are not
synchronized (e.g. when the input changes from 011
to 100 and MSB switch is delayed)
28
Segmented current-switched DACs
Basic idea
• Unit-element current generators for
MSBs and binary-weighted sources
for LSBs

• For instance, in a 8-bit DAC, the 4

MSBs can be thermometer-encoded
to control 15 equal current sources,
while the 4 LSBs are binary weighted

• Many different solutions exist based

on this general scheme even more
than two segments are used in
recent DACs

• High resolution at a reasonable cost

in terms of area.

29
 Digital processing of analog
signals: summary
• If we consider a complete system for real-time signal processing
xa(t) x(n) xB(n) yB(n) yH(t) yr(t)
xc(t)
r  
~
Ha(Ω) S/H ADC H(e jω) S/H H

T T
    
The total frequency response is: H eff   T H a  H e
1 jT
H H  H r 
  ~

• Possible residual nonidealities due to A/D and D/A conversion (e.g.

due to anti-aliasing filter, imperfect zero-hold compensation, track-and-
hold phenomena when the conversion time TADC is not negligible
compared with T etc…) can be compensated in the digital domain by
replacing H(ejω) with

e 
jT
w

where H eff e 
jT

 
w
H eff is the wanted
H' e jT  effective frequency response of the
H a  H H  H r  
1 ~
T whole system
30
 Down-sampling (decimation)
• Down-sampling is used to decrease the sampling rate by an integer
factor M (called decimation factor)
• It can be used when the computing platform or the communication
channel are not able to process or to transfer the samples at the
conversion rate.
x(n)=xc(nT) M xd(n)=x(nM)
Compressor: selects one samples every M

    
 
X d e j  1
MT  
k  
X c
  2k  1
MT MT
 T '
k  
X c

T'
 2'k
T

 
• Note: Aliasing can be avoided if and only if X e j  0 for    / M
If this condition is not true, the signal must be bandlimited with a low-
pass filter before compression, i.e.
Low-pass filter
x(n)=xc(nT) Gain=1 M xd(n)=x(nM)
Cutoff=π/M

31
 Examples
Downsampling without aliasing (M=2) Downsampling with aliasing (M=2)
The LPF is not strictly
necessary, but it is
better using it!  
X e j  
X e j
A LPF has to be
used!

1
1


M   
M M M


T

In the case on the right, to avoid aliasing the signal has to be preliminarily
filtered. However, some information would be lost in any case.
32
 Up-sampling (interpolation) - 1
• Up-sampling is used to increase the sampling rate by an integer factor L
(called interpolation factor)
• It can be used to relax the selectivity requirements of the anti-aliasing filter
simpler filter, since spectral replicas are farther from one another.
• Up-sampling also requires two cascade subsystems
xe(n) Low-pass filter
x(n)=xc(nT) L Gain=L xi(n)
Cutoff=π/L
Expander: adds L-1 zeros Interpolator: replace the
between 2 consecutive zero samples with those
samples resulting from interpolation
 x
xe n   
nL  n  0, L ,2 L ,...
0 otherwise

F
     2k 
 
X e e j  1
T
L  2k   1
 T T LT  c T LT
Xc X ' ' '
k   k  
33
 Up-sampling (interpolation) - 2
 
X e j

The interpolation filter

removes the unwanted
images  
X e e j
L

 L 
L
• An interpolation factor of L leads, in the digital frequency domain,
to a compression of spectrum by a factor of L and to L replicas in
the baseband images which are removed by the final LPF

       
 
X i e j  L Xc   2k'  1 Xc   2'n
LT ' T '
LT T' T '
T
k   n  
k 0 , L ,...
34
 Up-sampling (interpolation) - 3
• In the time domain ideal interpolation relies on noncausal sinc(∙) function

hi n  
 
sin Ln
n
L

• Reasonably good approximate results can be generally obtained with a

FIR linear interpolator, i.e. with
hlin n 
1

L L n


~x n  
i  k h
k  
lin n  kL   xi n 
• Note: ADCs based on «oversampling» work purposely with a sampling
rate higher than needed, to better remove the wideband noise through a
subsequent digital decimation
35