See First of all A's these are interview questions,

It varies from experience level to level.

As I have been working in VLSI industry almost 5 years and attended number of
interviews

I am consolidating my interview questions here that may help you for your
interviews

**Abbreviations: Rarely asked questions (RAQ)

Basics of Digital Design

Deign all gates using MUX.

MUX using buffers.

Gate conversion.

XOR vs XNOR �special characteristics.

Buffer vs Inverter.

Different kind of Buffers.

Latch vs Flip Flops.

Dff to Tff conversion .

JK vs RS ff.(RAQ)

Master slave flops/ edge triggers flops.

Truth tables of flops should be on tips for all quick answers.(RAQ)

Flip flop parameters like setup/hold/clock2q delay, propagation delay of

cells/fanout/fanin.

Multiplier and divider circuitry implementation and logical implementation of any

number of multiplier and divider.

Different type of adders.

Mod N counter/Frequency Dividers.

Sequence detector FSM design.

Design a FSM to detect input stream is divisible by x(any number) or not.

Glitch Jitter skew.

Edge detection circuitry.

Ripple Johnson counter.(RAQ)

Linear Feedback Shift Registers.(RAQ)

In depth Questions/Analytic questions.

Dynamic/static/leakage power etc.

MOS capacitance can be asked in different forms.

Semiconductor behavior for different pvt corners.

Basics of transistors.

CMOS vs BJT vs Bi-CMOS.

CMOS circuits ?Inverter and or nor not and others.

Noise In digital Cirguits.

Noise Margin.

Bidirectional cells.

NAND vs NOR circuitry.

Metastability.

Operating frequency calculations.

FIFO depth calculation.

Setup and hold time of flops and what it signify and what is its violations.

How to compare two input bit streams.

SOP-POS(SUM OF PRODUCT - PRODUCT OF SUM) form conversion of digital equations and

logic optimization

Implementing functions using Decoder/Encoder

Waveform deterioration

Mathematics equations design and optimized hardware

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Memory design questions

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Race conditions in Digital circuitry

How many 2:1 Muxs are needed for 8:1/16:1 Mux.

Implementation of MUX using Tristate BUFFERS.

Area calculations of Mux implementation from different ways i.e. whic MUX will have
more area on chip �1. 8:1 MUX �2. 8:1 Mux using 2:1 Mux.

HALF-ADDER ?> FULL ADDER conversion

RAS CAS in SRAM.

SRAM cells explanations working.

Ram vs FIFO.

SIPO/PISO related logic for fast implementations of any given problem

How to do Handshake between designs.

Any waveform will be given and you are supposed to draw diagram for that(FAQ)

? can find related question on my page.

Disk rotation detection/Ant walking and other probability questions, expected to be

answered as digital design concept.

Design Based Questions

Low power techniques.

Asynchronous reset vs synchronous reset.

Glitch Filters.

For more FAQ you can look into my page on below link

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�Thanks

Rajeev V.