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Centurion University of Technology and Management

Odisha

Choice Based Credit System

Course Structure & Syllabus

Domain Courses

Electronics & Communication Engineering

Basket - V

Centurion University of Technology and Management

School of Engineering & Technology

2018
Domain - Embedded System

Course
Course Course Title Credits Prerequisites
Nature
Code
Theory +
DEES0417 Linux System Programming 4
Practice

Embedded Linux using Beagle Theory +


DEES0418 4
Bone Black Practice

Theory +
DEES0419 Linux Kernel & Device Driver 4
Practice

Theory +
DEES0420 Computer Vision 4
Practice

Embedded System Design using Theory +


DEES0421 4
LABVIEW Practice

DEET0300 Project 6

DEET0800 Internship 4

Total 30

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Linux System Programming

Course Title Code Type of course T-P-P Prerequisite


Linux System DEES0417 Theory+ Practice 2-2-0 Nil
Programming

Objective
 To started with writing system programs in Linux and to Build deeper view about soft
interrupts and how Kernel handles it
 Usage of synchronous and asynchronous communication mechanisms in Linux and Linux
Kernel system call implementation
 Learning Internetworking concepts using TCP/IP and TCP/IP socket programming

Learning Outcome
Upon successful completion of this course,
 Student will able to understanding of the Operating system concepts and Linux internals
(Interfaces, API’s and system calls) and
 Helps to move to the next level of programming by considering other factors in the
system and provides ample practical classes to provide good exposure to Linux
programming.

Evaluation Systems
Internal Component % of Marks Method of Assessment
Examination Internal Theory 20 Written Examination
Internal Practice 30 (20+10) Lab Work + Learning Record
External External Theory 30 Written Examination
Examination External Practice 20 Lab Work
Total 100

Course Outline

MODULE I: INTRODUCTION & SYSTEM CALLS

Introduction to Linux & Open source, GPL, LGPL licensing, Introduction to various flavors
to Linux, Using the command line interface, Components of Linux; System Calls: User and
Kernel Space, Introduction to System Calls, System Calls in Detail, Strace – Tracing system
calls

Practice:

1. To demonstrate the basic knowledge of Linux commands and file handling utilities by
using Linux shell environment.
2. Write Programs to demonstrate the Files system calls.

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MODULE II: PROCESS & IPC

Introduction to Process, Process vs. Program, Process States, Creating Process, Process
termination, Special case of processes; Inter Process Communication (IPC): Introduction
to IPC, Pipe, FIFO, Shared Memory, Advantages and Disadvantages of various IPC
mechanisms, Application use cases

Practice:

3. Write a C program to create a child process and allow the parent to display “parent” and
the child to display “child” on the screen
4. Write a C program to create a Zombie process.

MODULE III: SIGNALS

Introduction to Signals, Default disposition of Signals, Handling the Signals, Signal Related
Functions

Practice:

5. Write a C program that illustrates how an orphan is created


6. Write a C program that illustrates how to execute two commands concurrently with a
command pipe.
7. Write C programs that illustrate communication between two unrelated processes using
named pipe.

MODULE IV: THREADS & SYNCHRONIZATION

Introduction to Threads, Creating Thread, Data handling with Thread, Types of Threads –
Thread Attributes, Thread Cancellation, Threads vs. Process; Introduction to
Synchronization: Introduction to race conditions, Critical section, Priority inversion,
Deadlock, Atomicity & Mutual exclusion, Solutions to race condition

Practice:

8. Write a C program to create a message queue with read and write permissions to write 3
messages to it with different priority numbers.
9. Write a C program that receives the messages and display them.

MODULE V: THREAD & PROCESS SYNCHRONIZATION

Thread Synchronization: Race condition in multi-threaded applications, Writing thread safe


code, Mutex, POSIX Semaphores, Usage of Binary semaphores and Mutex; Process
synchronization: Race condition in multi-process applications, Limitations of shared
memory, Semaphore (System-V) implementation

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Practice:

10. Write a program to implement the shared memory

MODULE VI: INTERNETWORKING WITH TCP/IP

OSI and TCP/IP models, Addressing in TCP/IP, IPv4 and IPv6 differences, TCP three-way
handshake, Network packet analysis in Linux, Networking commands in Linux;Linux
Network programming using Sockets: Socket APIs, Iterative and Concurrent servers,
Client-server implementation using sockets, TCP and UDP sockets, Synchronous I/O using
select(), xinetd daemon in Linux

Practice:

11. Write a client and server a program for interaction between server and client processes
using Internet Domain sockets.
12. Write a C program that illustrates two processes communicating using shared memory

MODULE VII: MEMORY MANAGEMENT & SHELL SCRIPTING

Memory Management Unit (MMU) introduction, Virtual memory – Paging & Page fault,
MMU concepts – Relocation, Protection, Sharing, Logical and physical organization; Shell
Scripting: Shell programming, what is shell, making a script executable, shell syntax, loops,
control statements, functions, array.

Practice:
13. To demonstrate the simple shell script programs.

Text Books:
1. Unix System Programming using C++, T. Chan, PHI.
2. Unix Concepts and Applications, 4th Edition, Sumitabha Das, TMH.
3. Beginning Linux Programming, 4th Edition, N.Matthew, R.Stones,Wrox, Wiley India
Edition.

Reference books:
1. Linux System Programming, Robert Love, O’Reilly, SPD.
2. Advanced Programming in the Unix environment, 2nd Edition, W.R.Stevens, Pearson
Education.
3. Unix Network Programming, W.R.Stevens,PHI. 4. Unix for programmers and users, 3rd
Edition, Graham Glass, King Ables, Pearson Education

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Embedded Linux using Beagle Bone Black

Course Title Code Type of course T-P-P Prerequisite


Embedded Linux using DEES0418 Theory+ Practice 2-2-0 Nil
Beagle Bone Black

Objective
 Know “What” is Open Source and “How it benefits” the Industry
 Understand the “Linux Boot Process & Role of a Bootloader”

Learning Outcome
 “Make the choices for Embedded Linux” , Setup and Build own tool-chain for ARM”
platforms
 Be able to “Make own root file-systems for ARM-based Embedded Linux”

Evaluation Systems
Internal Component % of Marks Method of Assessment
Examination Internal Theory 20 Written Examination
Internal Practice 30 (20+10) Lab Work + Learning Record
External External Theory 30 Written Examination
Examination External Practice 20 Lab Work
Total 100

Course Outline

Module I: INTRODUCTION TO EMBEDDED LINUX

Embedded Systems & Real Time Aspect, Open Source & Free Software Fundamentals
Linux as an Embedded OS: Architecture, Software components, Choices to make,
Applying Patches,Source Code Browsing Techniques

Module II: TARGET HARDWARE ARCHITECTURE

Overview, Processes Architecture -ARM, Hardware Peripherals available , Schematics,


Memory Mappings, Connectivity for board bring-up
Linux booting sequence: Desktop Linux booting sequence, Embedded Linux booting
sequence, Processor/Target board specific booting sequence

Practice:
1. Booting RBL and MLO on BBB
2. Testing MLO image on BBB
3. Testing U-boot image on BBB

Module III: TOOLCHAINS


What is a toolchain? Types of toolchain - native versus cross toolchain, Choosing the C
library, Finding a toolchain, Anatomy of a toolchain, Other tools in the toolchain, Looking at

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the components of the C library, Linking with libraries: static and dynamic linking, The art of
cross compiling, Problems with cross compiling.

Module IV: BOOTLOADERS


What does a bootloader do?, The boot sequence, Booting with UEFI firmware, Moving from
bootloader to kernel, Introducing device trees, Choosing a bootloader, U-Boot, Barebox.;
Porting and Configuring the Kernel: What does the kernel do?, Choosing a kernel,
Building the kernel, Compiling, Cleaning kernel sources, Booting your kernel, Porting Linux
to a new board.
Module V: BUILDING A ROOT FILESYSTEM
What should be in the root filesystem?, Programs for the root filesystem, Libraries for the
root filesystem, Device nodes, The proc and sysfs filesystems, Kernel modules, Transfering
the root filesystem to the target, Creating a boot ramdisk, The init program, Configuring user
accounts, Starting a daemon process, A better way of managing device nodes, Configuring
the network, Creating filesystem images with device tables, Mounting the root filesystem
using NFS, Using TFTP to load the kernel.

Module VI: CREATING A STORAGE STRATEGY


Storage options, NOR flash, NAND flash, Managed flash, Accessing flash memory from the
bootloader, Accessing flash memory from Linux, Filesystems for flash memory, Filesystems
for NOR and NAND flash memory, Filesystems for managed flash, Read-only compressed
filesystems, Temporary filesystems, Making the root filesystem read-only, Filesystem
choices, Updating in the field

Module VII: DEBUGGING WITH GDB


The GNU debugger, Preparing to debug, Debugging applications using GDB, Remote
debugging using gdbserver, Starting to debug, Debugging shared libraries, Just-in-time
debugging, Debugging forks and threads, Core files, GDB user interfaces, Debugging kernel
code; Profiling and Tracing: The observer effect, Beginning to profile, Profiling with top,
Introducing perf, Other profilers: OProfile and gprof, Tracing events, Introducing Ftrace,
Using LTTng, Using Valgrind for application profiling, Callgrind, Helgrind, Using strace to
show system calls,

Text Books:

1. “Mastering Embedded Linux Programming”, Chris Simmonds, Packt publishing Ltd,


December 2015,ISBN 978-1-78439-253-6.

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Linux Kernel &Device Driver

Course Title Code Type of course T-P-P Prerequisite


Linux Kernel DEES0419 Theory + Practice 2-2-0 Nil
&Device Driver

Objective
 Configure, compile, and install a Linux kernel/kernel module from sources
 Understand and use correctly the Linux kernel internal services needed by devices
drivers, including mutual exclusion, memory mapping, kernel memory allocation,
interrupt handling, timekeeping, and scheduling.
 Design and implement a kernel module and device driver.

Learning Outcome
Upon successful completion of this course,
 Students finishing it will be adequately prepared for research projects that require
kernel-level programming
 Improved understanding of internal OS security issues.

Evaluation Systems
Internal Component % of Marks Method of Assessment
Examination Internal Theory 20 Written Examination
Internal Practice 30 (20+10) Lab Work + Learning Record
External External Theory 30 Written Examination
Examination External Practice 20 Lab Work
Total 100

Course Outline

MODULE I: DEVICE DRIVERS AND CHAR DRIVERS

Theory
The Role of the Device Driver, Splitting the Kernel, Classes of Devices and Modules,
Security Issues, Building and Running Modules. The Design of scull, Major and Minor
Numbers, Some Important Data Structures, Char Device Registration, open and release,
scull’s Memory Usage, read and write.

Practice
1. Write a program to create a simple device driver.
2. Loading and unloading the device driver file.

MODULE II: DEBUGGING TECHNIQUES

Theory
Debugging Support in the Kernel, Debugging by Printing, Debugging by Querying,
Debugging by Watching, Debugging System Faults, Debuggers and Related Tools

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Practice:

3. Verifying the parameters


4. Whenever value is set to 1, you have to write a something in to a hardware register. How
can you do this if the change of value variable is not notified to you?

MODULE III: CONCURRENCY AND RACE CONDITIONS


Theory
Pitfalls in scull, Concurrency and Its Management, Semaphores and Mutexes,
Completions, Spinlocks, Locking Traps, Alternatives to Locking.

Practice

5. Program for Statically Allocating Major Number


6. Program for Dynamically Allocating Major Number

MODULE IV: ADVANCED CHAR DRIVER OPERATIONS


Theory
Ioctl, Blocking I/O, poll and select, Asynchronous Notification, Seeking a Device, Access
Control on a Device File; Time, Delays and Deferred work: Measuring Time Lapses,
Knowing the Current Time, Delaying Execution, Kernel Timers, Tasklets, Work queues

Practice

7. Manually Creating Device File


8. Automatically Creating Device File

MODULE V: ALLOCATING MEMORY AND COMMUNICATING WITH


HARDWARE
Theory
Lookaside Caches, get_free_page and Friends, vmalloc and Friends, Per- CPU Variables,
Obtaining Large Buffers, I/O Ports and I/O Memory, Using I/O Ports, An I/O Port Example,
Using I/O Memory.

Practice:

9. File Operations of Character drivers

MODULE VI: INTERRUPT HANDLING AND DATA TYPES IN THE KERNEL


Theory
Preparing the Parallel Port, Installing an Interrupt Handler, Implementing a Handler, Top and
Bottom Halves, Interrupt Sharing, Interrupt-Driven I/O, Use of Standard C Types, Assigning
an Explicit Size to Data Items, Interface-Specific Types, Other Portability Issues, Linked
Lists.

MODULE VII: PCI DRIVERS AND USB DRIVERS


Theory
The PCI Interface, A Look Back: ISA, PC/104 and PC/104+ ,Other PC Buses, SBus, NuBus,
External Buses, USB Device Basics, USB and Sysfs, USB Urbs, USB Transfers, Without
Urbs.

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Practice:
1. Writing a USB Driver.

Text Books:
1. Linux Device Drivers by Jonathan Corbet, Alessandro Rubini, and Greg Kroa
Hartman, O’Reilly Media, U.S.A.
2. Linux Kernel Development by Robert Love, Pearson India.

Weblink:
1. https://embetronicx.com/tutorials/linux/device-drivers/linux-device-driver-part-1-
introduction/

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Computer Vision

Course Title Code Type of course T-P-P Prerequisite


Computer Vision DEES0420 Theory + Practice 2-2-0 Nil

Objective
 Set up Raspberry Pi and master computer vision with OpenCV and Work with images,
videos, webcams, the Pi camera, and create amazing time lapse videos
 Blend images and create artistic effects such as image transitioning , change color spaces,
and track objects based on colors
 Use various high- and low-pass filters to remove noise from the image and finding
contours and segments in images and detect edges, lines, and circles

Learning Outcome
Upon successful completion of this course,
 Students will able to set up your Raspberry Pi for computer vision applications, exploring
the basics of OpenCV / simple CV
 To design and implement real-life computer vision applications on your own.

Evaluation Systems
Internal Component % of Marks Method of Assessment
Examination Internal Theory 20 Written Examination
Internal Practice 30 (20+10) Lab Work + Learning Record
External External Theory 30 Written Examination
Examination External Practice 20 Lab Work
Total 100

Course Outline

MODULE I: INTRODUCTION TO COMPUTER VISION AND RASPBERRY PI


Computer vision, OpenCV, Single-board computers and the Raspberry Pi, Setting up your
Raspberry Pi B+: Preparing your microSD card manually, Booting up your Raspberry Pi for
the first time, Shutting down and rebooting your Pi safely. Preparing your Pi for computer
vision: Testing OpenCV installation with Python. NumPy: Array creation, Basic operations
on arrays, Linear algebra

MODULE II: WORKING WITH IMAGES, WEBCAMS, AND GUI


Running Python programs with Raspberry Pi, Working with images, Using matplotlib,
Drawing geometric shapes, Working with trackbar and named window, Working with a
webcam, Creating a timelapse sequence using fswebcam, Webcam video recording and
playback. Working with a webcam using OpenCV: Saving a video and playback of a video
using OpenCV. Working with the Pi camera module: Using raspistill and raspivid, Using
picamera in Python with the Pi camera module, picamera and OpenCV

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MODULE III: BASIC IMAGE PROCESSING
Retrieving image properties, Arithmetic operations on images: Blending and transitioning
images, Splitting and merging image colour channels: Creating a negative of an image,
Logical operations on images.

MODULE IV: COLOR SPACES, TRANSFORMATIONS, AND THRESHOLDS


Color spaces and conversions, Tracking in real time based on color, Image transformations:
Scaling, Translation, rotation, and affine transformation, Perspective transformation,
Thresholding image, Otsu's method

MODULE V: EDGES, CIRCLES, AND LINES' DETECTION


High-pass filters, Canny Edge detector, Hough circle and line transforms; Image
Restoration, Quantization, and Depth Map: Restoring images using inpainting, Image
segmentation, Mean shift algorithm based segmentation, K-means clustering and image
quantization, Comparison of mean shift and k-means, Disparity map and depth estimation

MODULE VI: HISTOGRAMS, CONTOURS, MORPHOLOGICAL


TRANSFORMATIONS, AND PERFORMANCE MEASUREMENT
Image histogram. Image contours, Morphological transformations on image, OpenCV
performance measurement and improvement

MODULE VII: REAL-LIFE COMPUTER VISION APPLICATIONS


Barcode detection, Motion detection and tracking, Hand gesture recognition, Chroma key
with green screen

Text Book:
1. Raspberry Pi Computer Vision Programming, by Ashwin Pajankar, Packt Publishing,
ISBN: 9781784398286
2. Computer Vision: Algorithms and Applications, by Richard Szeliski, Microsoft
Research Springer London Dordrecht Heidelberg New York, ISSN 1868-0941, e-ISSN
1868-095X, ISBN 978-1-84882-934-3, e-ISBN 978-1-84882-935-0

Weblink:

1. https://learning.oreilly.com/library/view/raspberry-pi-
computer/9781784398286/ch01s05.html

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Embedded System Design using LABVIEW

Course Title Code Type of course T-P-P Prerequisite


Embedded System DEES0421 Theory + Practice 2-2-0 Nil
Design using
LABVIEW

Objective
 To understand basics, programming techniques, data acquisition and interfacing
techniques of virtual instrumentation and to use VI for different applications.
 To experiment various functions available in LabVIEW & practice various Instrument
Interfacing.

Learning Outcome
 To familiarize with the VI software and learn programming in VI.
 The student will be aware of industrial prototyping, modeling and proof of concept
prior to production of a product.

Evaluation Systems
Internal Component % of Marks Method of Assessment
Examination Internal Theory 20 Written Examination
Internal Practice 30 (20+10) Lab Work + Learning Record
External External Theory 30 Written Examination
Examination External Practice 20 Lab Work
Total 100

Course Outline

Module I: INTRODUCTION TO LABVIEW


Theory
Virtual Instruments, Data Flow Programming, Menus and Palettes, Front Panel Controls,
Block Diagram Functions, Setting Options

Practice
1. Verification of Arithmetic Operations.
2. Verification of Half Adder and Full adder.

Module II: LABVIEW FEATURES


Theory
Global and Local Variables, Shared Variables, Customizing Controls, Property Nodes,
Reentrant Vis, Libraries (.LLB) , Web Server, Web Publishing Tool, Instrument Driver
Tools, Profile Functions, Auto SubVI Creation, Advanced Functions, Source Code Control,
Graphs, Data Logging.

Practice:
3. Program to find Addition of First n natural numbers using for and while loop.
4. To perform the factorial of a given number using WHILE loop
5. To sort even numbers using WHILE loop in an array

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Module III: STATE MACHINES
Theory
Introduction, Enumerated Types and Type Definitions, Sequence-Style State Machine, Test
Executive-Style State Machine, Classical-Style State Machine, Queued-Style State Machine,
Drawbacks to Using State Machines, Recommendations and Suggestions.

Practice:
6. To find the maximum and minimum variable from an array
7. Implementation of Array functions.

Module IV: APPLICATION STRUCTURE


Theory
Planning, Purpose of Structure, Software Models, Project Administration, The Three-Tiered
Structure, Main Level, Second Level — Test Level, Bottom Level — Drivers, Style Tips.

Practice:
8. Program for implementing Seven segment display.
9. Program to perform Traffic light control.

Module V: EXCEPTION HANDLING


Theory
Exception Handling Defined, Types of Errors, Built-in Error Handling, Performing Exception
Handling, Debugging Code

Practice:
10. To create a sine wave using formula node.
11. To apply filtering technique for a given input signal.
12. To perform discrete cosine transform on the given signal
13. To perform convolution of two signals.
14. To apply different windowing technique on the give input signal (Hanning, hamming,
Blackman, Cheby Shev window)

Module VI: LABVIEW MYRIO


Theory
Downloading and Installing myRIO required toolkits, Simple Example for creating myRIO
project, Wireless communication using WI-FI, Using "Network variable engine" for
connecting myRIO with Smartphone, Installing and preparing LabVIEW machine vision
drivers for myRIO & PC, image processing using myRIO.

Module VII: INTERFACING PERIPHERALS TO NI-MYRIO


Theory
Discrete LED, Seven-Segment LED Display, Pushbutton Switch, DIP Switches, Relay,
Potentiometer, Thermistor, Photocell, Electret Microphone, Buzzer/Speaker, Motor, Rotary
Encoder, Photo Interrupter, Hall-Effect Sensor, Piezoelectric-Effect Sensor

Practice:
15. Interfacing peripherals to NI –MyRIO (LED, Seven segment Display, Switches, Relay,
Potentionmeter, Photocell, Microphone, Buzzer, Motor, Sensors).

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Text book:

1. "LabVIEW™, Advanced Programming Techniques", Rick Bitter, Taqi Mohiuddin,


Matt Nawrocki, CRC Press, Taylor & Francis Group, SECOND EDITION, ISBN-10:
0-8493-3325-3 (Hardcover), ISBN-13: 978-0-8493-3325-5 (Hardcover).
2. MyRIO Tehnical Mannual.

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Domain - VLSI Design and Verification

Course Pre-
Course Title Course Nature Credits
Code requisite
DEVL0401 Digital System Design Theory + 4 Nil
using VERILOG Practice
DEVL0101 FPGA Architecture and Theory 3 Nil
Design
DEVL0402 HDL Synthesis and Theory + 4 Nil
System Architecture Practice
DEVL403 System VERILOG Theory + 4 Nil
Practice
DEVL0201 VLSI Verification Practice 2 Nil
Methodologies
DEVL0102 VLSI Test Principle and Theory 3 Nil
Testable Design
DEET0300 Project Project 6

DEET0800 Internship Internship 4

30

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Digital System Design using VERILOG
Course Title Code Type of course T-P-P Prerequisite
Digital System Design DEVL0401 Theory & 2-2-0 Nil
using VERILOG Practice

Objective
 To Make The Student Understand Advanced Digital System Design using Verilog
Programming

Learning Outcome
 Student will be Able to Write Efficient Verilog Programme
 Student will be Able to Design Advanced Digital System Using Verilog HDL.

Evaluation Systems
Internal Component % of Marks Method of Assessment
Examination Internal Theory 20 Written Examination
Internal Practice 30(20+10) Lab Work + Learning Record
External External Theory 30 Written Examination
Examination External Practice 20 Lab Work
Total 100

Course Outline

Module I: Introduction to VLSI Design (10 Hours)


Theory
VLSI Design flow: Full Custom, ASIC and FPGA. Design Tools: CAD Tool Taxonomy,
Editors, Simulators, Simulation System, Simulation Aids, Applications of Simulation,
Synthesis Tools, and Introduction to Hardware Description Languages (HDL)

Practice
1. Introduction to Xilinx EDA Tool.
2. Introduction With XST Tool and ISIM Tool
3. Xilinx Tool Flow: Simulation and Synthesis

Module II: Verilog HDL (12 Hours)


Introduction to Verilog HDL, Abstraction levels, basic concepts, Verilog primitives,
keywords, data types, nets and registers, Verilog Modules and ports

Practice
4. Modulea and Port Declaration in Verilog Using Xilinx Tool.
5. Use of Different Data Types in Verilog Programing.
6. Design and Create Simulation Waveform for Different Digital Logic Gates Using Data
Types-1
7. Design and Create Simulation Waveform for Different Digital Logic Gates Using Data
Types-2

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Module III: Verilog Operators (12 Hours)
Theory
Logical Operators, Bitwise and Reduction Operators, Concatenation and Conditional
Operators, Relational and Arithmetic, Shift and Equality Operators, Operator Execution
Order. Assignments: Types of Assignments, Continuous Assignment, Procedural
Assignments, Blocking and Non-Blocking Assignments, Tasks and Functions

Practice
8. Design and Create Simulation Waveform for Different Digital Logic Gates Using
Operators-1
9. Design and Create Simulation Waveform for Different Combinational Logic Circuit
Using Operators-2
10. Design and Create Simulation Waveform for Different Combinational Logic Using
Continuous Assignment Statements
11. Design and Create Simulation Waveform for Different Sequential Circuits Using
Blocking and Non-Blocking Statements

Module IV: Verilog Modelling (12 Hours)

Theory
Gate Type, Design Hierarchy, Gate Delay, Propagation Delay, Logic Simulation Dataflow-
Level Modelling: Assignments, Behavioural Modeling: Always Block, Flow Control, If-Else,
Case, Cases, While Loop, For Loop, Repeat

Practice
12. Design and Create Simulation Waveform for Full Adder Using Dataflow Modelling,
Behavioral Modelling(if-else, case)
13. Design and Create Simulation Waveform for Sequential Circuits Using Behavioral
Modelling (case, while loop, for loop, repeat)
14. Design and Create Simulation Waveform for Decoder Using Dataflow Modelling,
Behavioral Modelling(if-else, case)
15. Design and Create Simulation Waveform for Multiplexer Using Behavioral
Modelling(case, while loop, for loop, repeat)
16. Design and Create Simulation Waveform for Parity Generator and Parity Checker
Using Dataflow Modelling, Behavioral Modelling(if-else, case)

Module V: Verilog for Verification (14 Hours)


Theory
Design Verification and Testing, Test Bench Writing, Initial Statement, Verilog System
Tasks: $finish, $stop, $display, $monitor, $time, $realtime, $random, $save,
$readmemh/$writememh, $fopen, $fclose, Compiler Directives, ifdef, Array, Multi-
Dimensional Array, Memory Modelling

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Practice
17. Design and Create Simulation Waveform for Full Adder Using Continuous
Assignment, Procedural Assignments With The Use of System Task and Functions-1
18. Design and Create Simulation Waveform for Full Subtractor Using Continuous
Assignment, Procedural Assignments With the Use of System Task and Functions-2
19. Design and Create Simulation Waveform for Multiplexers Using Continuous
Assignment, Procedural Assignments With the Use of System Task and Functions-3
20. Design and Create Simulation Waveform for Encoders Using Continuous Assignment,
Procedural Assignments With the Use of System Task and Functions-4
21. Design And Create Simulation Waveform For Decoders Using Continuous Assignment,
Procedural Assignments With the Use of System Task and Functions-5

Module VI: Combinational Logic Circuit Design (15 Hours)


Theory
Logic Synthesis, RTL Synthesis, High-Level Synthesis, Synthesis Design Flow, Design and
Analysis of Combinational Circuits, Synthesis of Combinational Circuits, Arithmetic
Circuits, Initial Design And Optimization, Encoder, Decoder, De-Multiplexer Circuits,
Multiplexer Circuits and their Implementation Using Verilog, Design of a 4-Bit Comparator,
Design of a 4-Bit ALU and a Simple Processor Using Verilog

Practice
22. Design and Create Simulation Waveform for Full Adder Using Continuous Assignment
and Procedural Assignments
23. Design and Create Simulation Waveform for Encoder and Decoder Using Continuous
Assignment and Procedural Assignments
24. Design and Create Simulation Waveform for De-Multiplexer Using Continuous
Assignment and Procedural Assignments
25. Design and Create Simulation Waveform For 4-Bit Comparator Using Continuous
Assignment and Procedural Assignments
26. Design And Create Simulation Waveform For 4-Bit ALU Using Continuous Assignment
and Procedural Assignments

Module VII: Sequential Logic Circuit Design (15 Hours)


Theory
Synthesis of Sequential Circuits, Study of Synchronous and Asynchronous Sequential
Circuits, Flip Flops, Shift Registers, Counters and their Design Using Verilog.
State Machine: Basic Finite State Machines (FSM) Structures, Mealy and Moore Type FSM,
Mealy Vs. Moore, Common FSM Coding Style, Serial Adder Design Using FSM, FSM as an
Arbiter Circuit, FIFO, Bus Interfaces.

Practice
27. Design and Create Simulation Waveform for SR-Flip Flop And D-Flip Flop Using
Continuous Assignment and Procedural Assignments

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28. Design and Create Simulation Waveform for JK-Flip Flop And T-Flip Flop Using
Continuous Assignment and Procedural Assignments
29. Design and Create Simulation Waveform for Shift Registers(SISO,SIPO,PISO,PIPO)
Using Continuous Assignment and Procedural Assignments
30. Design and Create Simulation Waveform for 2-Bit Ripple Counter Using Continuous
Assignment and Procedural Assignments
31. Design and Create Simulation Waveform for 8-Bit Up/Down Synchronous Binary
Counter Using Continuous Assignment and Procedural Assignments

Text Books
1. Palnitkar, Samir. “Verilog HDL: A Guide To Digital Design and Synthesis”, Pearson
Education India, 2003
2. Navabi, Zainalabedin, and Yuwen Xia. “Verilog Digital System Design: Register
Transfer Level Synthesis, Testbench, and Verification”, McGraw-Hill, 2006
3. Mishra, Kishore K. “Advanced chip design: Practical examples in Verilog”, Create
Space Independent Publishing Platform, 2013

Reference Books
1. Bhasker, Jayaram. “Verilog HDL Synthesis: A Practical Primer”, Star Galaxy
Publishing, 2008.
2. Wolf, Wayne. FPGA-Based System Design”. Pearson education, 2004.
3. Ciletti, Michael D, “Advanced Digital Design with the Verilog HDL”, Vol. 1. Upper
Saddle River: Prentice Hall, 2003.
Session plan
Topic No. of Activity Assignment Suggested
Sessions Reading
(in hrs.)
Module I [4 Hrs. Lecture+6 Hrs. Practice]
Introduction To VLSI Design 4 Lecture Assignment- TB-1(Ch.1)
VLSI Design Flow: Full Custom, 1.1
ASIC and FPGA, Design Tools:
CAD Tool Taxonomy, Editors,
Simulators, Simulation System,
Simulation Aids, Applications of
Simulation, Synthesis Tools,
Introduction to Hardware
Description Languages (HDL)
Introduction To Xilinx EDA 6 Practice
Tool.
Introduction With XST Tool And
ISIM Tool
Xilinx Tool Flow: Simulation
And Synthesis
Module II [4 Hrs. Lecture+8 Hrs. Practice]
Verilog HDL 4 Lecture Assignment- TB-1

P a g e | 19
Introduction to Verilog HDL, 2.1 (Ch.1,2,3,4)
Abstraction Levels, Basic
Concepts, Verilog Primitives,
Keywords, Data Types, Nets and
Registers, Verilog Modules and
Ports
Module and Port Declaration in 8 Practice
Verilog Using Xilinx Tool.
Use of Different Data Types in
Verilog Programing.
Design and Create Simulation
Waveform for Different Digital
Logic Gates Using Data Types-1
Design and Create Simulation
Waveform For Different Digital
Logic Gates Using Data Types-2
Module III [4 Hrs. Lecture+8 Hrs. Practice]
Verilog Operators 4 Lecture Assignment- TB-1(Ch. 3,6)
Logical Operators, Bitwise and 3.1
Reduction Operators,
Concatenation and Conditional
operators, Relational and
Arithmetic, Shift and Equality
Operators, Operator Execution
Order. Assignments: Types Of
Assignments, Continuous
Assignment, Procedural
Assignments, Blocking and Non-
Blocking Assignments, Tasks
and Functions.
1. Design And Create Simulation 8 Practice
Waveform for Different
Digital Logic Gates Using
Operators-1
2. Design and Create Simulation
Waveform for Different
Combinational Logic Circuit
Using Operators-2
3. Design And Create Simulation
Waveform For Different
Combinational Logic Using
Continuous Assignment
Statements
4. Design And Create Simulation
Waveform For Different
Sequential Circuits Using
Blocking And Non-Blocking
Statements
Module IV [4 Hrs. Lecture+8 Hrs. Practice]

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Verilog Modelling 4 Lecture Assignment- TB-1(Ch.6,7)
Gate Type, Design Hierarchy, 4.1
Gate Delay, Propagation Delay,
Logic Simulation Dataflow-Level
Modelling: Assignments,
Behavioural Modeling: Always
Block, Flow Control, If-Else,
Case, Cases, While Loop, For
Loop, Repeat
1. Design and Create Simulation 8 Practice
Waveform for Full Adder
Using Dataflow Modelling,
Behavioral Modelling (If-Else,
Case)
2. Design and Create Simulation
Waveform for Sequential
Circuits Using Behavioral
Modelling (Case, While Loop,
For Loop, Repeat)
3. Design and Create Simulation
Waveform for Decoder Using
Dataflow Modelling,
Behavioral Modelling (If-Else,
Case)
4. Design and Create Simulation
Waveform for Multiplexer
Using Behavioral Modelling
(Case, While Loop, For Loop,
Repeat)
5. Design and Create Simulation
Waveform for Parity
Generator and Parity Checker
Using Dataflow Modelling,
Behavioral Modelling (If-Else,
Case)
Module V [4 Hrs. Lecture+10 Hrs. Practice]
Verilog For Verification 4 Lecture Assignment- TB-1(Ch.9)
Design Verification And Testing, 5.1
Test Bench Writing, Initial
Statement, Verilog system Tasks:
$Finish, $Stop, $Display,
$Monitor, $Time, $Realtime,
$Random, $Save,
$Readmemh/$Writememh,
$Fopen, $Fclose, Compiler
Directives, Ifdef, Array, Multi-
Dimensional Array. Memory
Modelling
Module VI [5 Hrs. Lecture+10 Hrs. Practice]

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Combinational Logic Circuit 5 Lecture Assignment- TB-1(Ch.14)
Design 6.1
Logic Synthesis, RTL Synthesis,
High-Level Synthesis, Synthesis
Design Flow, Design and
Analysis of Combinational
Circuits, Synthesis of
Combinational Circuits,
Arithmetic Circuits, Initial
Design and Optimization,
Encoder, Decoder, De-
Multiplexer Circuits, Multiplexer
Circuits and their Implementation
Using Verilog, Design of a 4-Bit
Comparator, Design of a 4-Bit
ALU and a Simple Processor
Using Verilog.
1. Design and Create Simulation 10 Practice
Waveform for Full Adder
Using Continuous Assignment
and Procedural Assignments
2. Design and Create Simulation
Waveform for Encoder and
Decoder Using Continuous
Assignment and Procedural
Assignments
3. Design and Create Simulation
Waveform for De-Multiplexer
Using Continuous Assignment
and Procedural Assignments
4. Design and Create Simulation
Waveform for 4-Bit
Comparator Using Continuous
Assignment and Procedural
Assignments
5. Design and Create Simulation
Waveform for 4-Bit ALU
Using Continuous Assignment
and Procedural Assignments
Module VII [5 Hrs. Lecture+10 Hrs. Practice]
Sequential Logic Circuit 5 Lecture Assignment- TB-1(Ch.14)
Design 7.1
Synthesis Of Sequential Circuits,
Study of Synchronous and
Asynchronous Sequential
Circuits, Flip Flops, Shift
Registers, Counters and Their
Design Using Verilog
State Machine: Basic Finite State
Machines (FSM) Structures,

P a g e | 22
Mealy And Moore Type FSM,
Mealy Vs. Moore, Common FS
Coding Style, Serial Adder
Design Using FSM, FSM as an
Arbiter Circuit, FIFO, Bus
Interfaces
1. Design And Create Simulation 10 Practice
Waveform For SR-Flip Flop
and D-Flip Flop Using
Continuous Assignment And
Procedural Assignments
2. Design and Create Simulation
Waveform for JK-Flip Flop
and T-Flip Flop Using
Continuous Assignment and
Procedural Assignments
3. Design and Create Simulation
Waveform for Shift Registers
(SISO,SIPO,PISO,PIPO)
Using Continuous Assignment
and Procedural Assignments
4. Design and Create Simulation
Waveform for 2-Bit Ripple
Counter using Continuous
Assignment and Procedural
Assignments
5. Design and Create Simulation
Waveform for 8-Bit Up/Down
Synchronous Binary Counter
Using Continuous Assignment
and Procedural Assignments
Total (In Hrs.) 90 30 Hrs.
lecture+60
Hrs.
Practice

P a g e | 23
FPGA Architecture and Design
Course Title Code Type of course T-P-P Prerequisite
FPGA Architecture and DEVL0101 Theory 3-0-0 Nil
Design

Objective
 To Make the Student Understand of Various FPGA Architectures which
Subsequently Enables them to Design and Implement Various Complex Digital
Architectures Using Verilog and Subsequently Implement the Digital Architecture iyn
FPGA

Learning Outcome
 Student will be Able to Design Digital Systems using Verilog.
 Student will be Able to implement Digital Design in FPGA.
 Student will be Able to Handle Different FPGA Architecture.

Evaluation Systems
Component % of Marks Method of Assessment

Internal Theory 30 Written examination


Internal Examination Report or Presentation +
Assignment 5
Learning Record
Attendance 5 Based on class attended

External Examination External Theory 60 Written examination

Total 100

Course Outline
Module I: PLD (5 Hours)
Theory
Introduction to PLDS, General Structure and Classification: SPLD, CPLD, PAL, PLA, CPLD
vs. FPGA.

Module II: FPGA (6 Hours)


Theory
Organization of FPGAs, FPGA Programming Technologies, Programmable Logic Block
Architectures, Programmable Interconnects Programmable I/O Blocks in FPGAs, Dedicated
Specialized Components of FPGAs, Applications of FPGAs.

Module III: SRAM Programmable FPGAs (6 Hours)


Theory
Introduction, Programming Technology, Device Architecture, the Xilinx XC2000, XC3000
and XC4000 Architectures. Anti-Fuse Programmed FPGAs: Introduction, Programming
Technology, Device Architecture.

P a g e | 24
Module IV: Design Applications (6 Hours)
Theory
General Design Issues, Counter Examples, a Fast Video Controller, a Position Tracker for a
Robot Manipulator, a Fast DMA Controller, Designing Counters with ACT Devices,
Designing Adders and Accumulators with the ACT Architecture.

Module V: Xilinx FPGA Architecture (6 Hours)


Theory
Features and Architectures, Configurable Logic Blocks (CLBs), Input Output Blocks (I/OB),
Block RAM, Programming Interconnects, Digital Clock Manager (DCM), Power
Distribution and Configuration.

Module VI: ACTEL FPGA Architecture (8 Hours)


Theory
ACTEL Family, ACTEL Features and Logic Modules, C Modules and S Modules, I/O
Modules, I/O Pad Drivers, Clock Networks. Intel and ALTERA FPGA Architecture.

Module VII: Embedded Processor Based Design (8 Hours)


Theory
IP Cores, Hard Cores, Firm Core, Soft Cores, Advantages and Disadvantages of Hard,
Firm, Soft Cores, FPGA Embedded Processor Types, Picking the Right Core Processor,
Implementing a Design, DSP Based Design Flow.

Text Books
1. S.M. Trimberger, “Field-Programmable Gate Array Technology,” Springer Science &
Business Media,2012
2. W.Wolf, “FPGA-Based System Design,” Pearson education, 2004
3. I Grout, “Digital Systems Design with FPGAS and CPLDS,” Elsevier, 2011

Reference Books
1. J.V. Oldfield andR.C. Dorf, “Field-Programmable Gate Arrays” , John Wiley & Sons,
1995
2. P.K. Chan and S.Mourad, “Digital System Design Using Field Programmable Gate
Arrays,” PTR Prentice Hall, 1994
3. R.C. Cofer and B.F.Harding, “Rapid System Prototyping with FPGAs: Accelerating the
Design Process”. Elsevier2006

P a g e | 25
Session Plan:
Topics No. of Activity Assignment Suggested
Sessions Reading
(in hrs.)
Module I[5 Hrs. Lecture]
PLD 2 Lecture Assignment-1.1 Text book-3
PLD: Introduction to PLDS, (Ch.1)
General Structure and
Classification: SPLD, CPLD
PAL 1 Lecture Assignment-1.2 Text book-3
(Ch.1)
PLA 1 Lecture Assignment-1.3 Text book-3
(Ch.1)
CPLD vs. FPGA 1 Lecture Assignment-1.4 Text book-3
(Ch.1)
Module II[6 Hrs. Lecture]
FPGA 1 Lecture Assignment-2.1 Text book-1
Organization of FPGAs, FPGA (Ch.2)
Programming Technologies
Programmable Logic Block 1 Lecture Assignment-2.2 Text book-1
Architectures (Ch.2)

Programmable Interconnects 1 Lecture Assignment-2.3 Text book-1


(Ch.2)

Programmable I/O blocks in 1 Lecture Assignment-2.4 Text book-1


FPGAs (Ch.2)

Dedicated Specialized 1 Lecture Assignment-2.5 Text book-1


Components of FPGAs (Ch.2)

Applications of FPGAs 1 Lecture Assignment-2.6 Text book-1


(Ch.2)

Module III[6 Hrs. Lecture]


SRAM Programmable FPGAs 1 Lecture Assignment-3.1 Text book-1
Introduction, Programming (Ch.2)
Technology
Device Architecture, The Xilinx 1 Lecture Assignment-3.2 Text book-1
XC2000 (Ch.2)

XC3000 Architecture 1 Lecture Assignment-3.3 Text book-1


(Ch.2)

XC4000 Architecture 1 Lecture Assignment-3.4 Text book-1

P a g e | 26
(Ch.2)

Anti-Fuse Programmed 1 Lecture Assignment-3.5 Text book-1


FPGAs: Introduction (Ch.2)

Programming Technology, 1 Lecture Assignment-3.6 Text book-1


Device Architecture (Ch.2)

Module IV[6 Hrs. Lecture]


Design Applications 1 Lecture Assignment-4.1 Text book-1
General Design Issues, Counter (Ch.2)
Examples
A Fast Video Controller 1 Lecture Assignment-4.2 Text book-1
(Ch.2)
A Position Tracker for a Robot 1 Lecture Assignment-4.3 Text book-1
Manipulator (Ch.2)
A Fast DMA Controller 1 Lecture Assignment-4.4 Text book-1
(Ch.2)
Designing Counters with ACT 1 Lecture Assignment-4.5 Text book-1
Devices (Ch.3)
Designing Adders and 1 Lecture Assignment-4.6 Text book-1
Accumulators with the ACT (Ch.3)
Architecture
Module V[6 Hrs. Lecture]
Xilinx FPGA Architecture 1 Lecture Assignment-5.1 Text book-1
Features and Architectures, (Ch.2)
Configurable Logic Blocks
(CLBs)
Input Output Blocks (I/OB) 2 Lecture Assignment-5.2 Text book-1
(Ch.2)

Programming Interconnects 1 Lecture Assignment-5.3 Text book-


1(Ch.2)

Digital Clock Manager (DCM) 1 Lecture Assignment-5.4 Text book-1


(Ch.2)

Power Distribution and 1 Lecture Assignment-5.5 Text book-1


Configuration (Ch.2)

Module VI[8 Hrs. Lecture]


ACTEL FPGA Architecture 1 Lecture Assignment-6.1 Text book-1
ACTEL Family, ACTEL (Ch.3)
Features and Logic Modules

P a g e | 27
C Modules and S Modules 2 Lecture Assignment-6.2 Text book-1
(Ch.3)

I/O MODULEs 1 Lecture Assignment-6.3 Text book-1


(Ch.3)

Clock Networks 1 Lecture Assignment-6.4 Text book-


1(Ch.3)

I/O Pad Drivers 1 Lecture Assignment-6.5 Text book-1


(Ch.3)

Intel and ALTERA FPGA 2 Lecture Assignment-6.6 Text book-1


Architecture (Ch.3)

Module VII[8 Hrs. Lecture]


Embedded Processor based 2 Lecture Assignment-7.1 Text book-5
Design (Ch.2)
IP Cores, Hard Cores, Firm
Core, Soft cores
Advantages and Disadvantages 2 Lecture Assignment-7.2 Text book-5
of Hard Firm, Soft Cores (Ch.2)
FPGA Embedded Processor 3 Lecture Assignment-7.3 Text book-5
Types, Picking the Right Core (Ch.2)
Processor and Implementing a
Design, DSP Based Design
Flow

Total (in Hrs.) 45 45 Hrs.


Lecture

P a g e | 28
HDL Synthesis and System Architecture
Course Title Code Type of course T-P-P Prerequisite
HDL Synthesis and DEVL0402 Theory & 2-2-0 Nil
System Architecture Practice

Objective
 To Make Students Learn the Advanced Digital System Architecture, the RTL Level
Synthesis and Address the Timing Issues Associated with the Digital System
Architecture

Learning Outcome
 Students Will be Able to Design and Synthesize a Complex Digital Functional Block
Using Verilog HDL
 Students Will be Able to Demonstrate an Understanding of Issues Involved in Digital
Design Such as Technology Choice, Timing Analysis, Tool-Flow and Testability

Evaluation Systems
Internal Component % of Marks Method of Assessment
Examination Internal Theory 20 Written Examination
Internal Practice 30(20+10) Lab Work + Learning Record
External External Theory 30 Written Examination
Examination External Practice 20 Lab Work
Total 100

Course Outline
Module I: HDL Architecture Design (12 Hours)
Theory
Design of Various Subsystems by Verilog HDL in Xilinx ISE and Also They Will Check the
Performance of Each Circuit in Terms of Area, Speed And Power. Sub Systebook-2, Ch.3m
Design, Hardware Description Language (HDLs), Register Transfer Design, Pipeline and
Data Path

Practice
1. RTL Design Of 4-Bit, 8-Bit and 16-Bit ALU and Their Performance Evaluation

Module II: HDL Architecture Design (11 Hours)


Theory
Adders, Multipliers, Memories, PLAs, Buses and Network on chips

Practice
2. RTL Design of Data Path Architecture

P a g e | 29
Module III: Static Time Analysis (12 Hours)
Theory
Basic Concepts of Static Time Analysis (STA) Used in the Design and They Will Solve
Various Timing Related Issue in Their Design.], Timing and Delay and the Concept of STA,
Types of Delay, Models- Distributed, Lumped Resource

Practice
3. RTL Design of Pipelined Architecture and Its Performance Evaluation

Module IV: Static Time Analysis (STA ) (12 Hours)


Theory
Pin to Pin Delay Model, Path Delay Modelling, Timing Checks Delay Back Annotations

Practice
4. RTL Design of various adder topologies/architectures
5. Ripple Carry Adder
6. Carry Skip Adder
7. Carry Increment Adder
8. Carry Look Ahead Adder
9. Carry Save Adder
10. Carry Select Adder
11. Carry Bypass Adder
12. Ling adder
13. Prefix adder
14. Parallel prefix adder
15. Conditional Sum adder

Module V: Floorplaning, Routing, Placement (15 Hours)


Theory
Advanced Simulations, Coding For Synthesis, Synthesis Optimization

Practice
RTL Design of Various Multiplier Architectures
16. RTL Design of Booth Multiplier Architectures
17. RTL Design of Combinational Multiplier
18. RTL Design of wallace Tree Multiplier
19. RTL Design of Array Multiplier
20. RTL Design of Sequential Multiplier
21. RTL Design of Serial Parallel Multiplier
22. RTL Design of MAC Unit Design

P a g e | 30
Module VI: Floorplaning (15 Hours)
Theory
Floor Planning & Place and Route Optimization, Floorplaning Styles and Methodology,
Global Routing

Practice
RTL Design Of Various Memory Units:
23. Single Port RAM Design in Read First Mode
24. Single Port RAM Design in Write First Mode
25. Single Port RAM Design in No Change Mode
26. Single Port RAM Design With Asynchronous Read
27. Single Port RAM Design With False Asynchronous Read
28. Single Port Block RAM Design With Enable
29. Dual Port RAM With Asynchronous Read
30. Dual Port RAM With False Synchronous Read
31. Dual Port RAM With Synchronous Read
32. ROM Design With Registered Output
33. ROM Design With Registered Address

Module VII: Floorplaning, Routing, Placement (13 Hours)


Theory
Clock Distribution, Power Distribution, Packaging and Pads

Practice
34. RTL Design of PLAs

Text Books
1. Bhasker, J., “Verilog HDL Synthesis: A Practical Primer”. Star Galaxy Publishing,1998
2. Camposano, R. and Wolf, W. eds., “High-Level VLSI Synthesis” (Vol. 136). Springer
Science & Business Media,2012
3. Sherwani, N.A., “Algorithms For VLSI Physical Design Automation”. Springer Science
& Business Media,2012

Session Plan:
Topic No. of Activity Assignmen Suggested
Sessions t Reading
(in hrs.)
Module I [4 Hrs. Lecture+8 Hrs. Practice]
Hdl Architecture Design 4 Lecture Assignment
Sub System Design, Hardware -1.1
Description Language (HDLs), Register
Transfer Design, Pipeline and Data

P a g e | 31
Path
RTL Design of 4-Bit,8-Bit and 16-Bit 8 Practice
ALU and Their Performance
Evaluation
Module II [3 Hrs. Lecture+8 Hrs. Practice]
HDL Architecture Design 3 Lecture Assignment
Adders, Multipliers, Memories, PLA, -2.1
Buses and Network On Chips
RTL Design of Data Path Architecture 8 Practice
Module III [4 Hrs. Lecture+8 Hrs. Practice]
Static Time Analysis (STA ) 4 Lecture Assignment
Timing And Delay And The Concept -3.1
Of STA, Types of Delay, Models-
Distributed, Lumped
RTL Design of Any Pipelined 8 Practice
Architecture and Its Performance
Evaluation
Module IV [4 Hrs. Lecture+8 Hrs. Practice]
Static Time Analysis(STA) 4 Lecture Assignment
Pin To Pin Delay Model, Path Delay -4.1
Modelling, Timing Checks Delay Back
Annotations.
RTL Design Of Various Adder: 8 Practice
Topologies/Architectures
Ripple Carry Adder, Carry Skip Adder
Carry Increment Adder, Carry Look
Ahead Adder, Carry Save Adder
Carry Select Adder, Carry Bypass
Adder
Ling Adder, Prefix Adder, Parallel
Prefix Adder ,Conditional Sum Adder
Module V [5 Hrs. Lecture+10 Hrs. Practice]
Floorplaning, Routing, Placement 5 Lecture Assignment TB-3 (Ch.
Advanced Simulations , Coding for -5.1 6,7,8)
Synthesis , Synthesis Optimization
RTL Design of Various Multiplier 10 Practice
Architectures
Booth Multiplier, Combinational
Multiplier , Wallace Tree Multiplier
RTL Design of Various Multiplier
Architectures: Array Multiplier
Sequential Multiplier , Serial Parallel
Multiplier , MAC Unit Design

P a g e | 32
Module VI [5 Hrs. Lecture+10 Hrs. Practice]
Floorplaning, Routing, Placement 5 Lecture Assignment TB-3
Floor Planning & Place and Route -6.1 (Ch.6,7,8)
Optimization , Floorplaning Styles and
Methodology , Global Routing
RTL Design Of Various Memory Units 10 Practice
Single Port RAM Design In Read First
Mode
Single Port RAM Design in Write First
Mode
Single Port RAM Design in No Change
Mode
Single Port RAM Design With
Asynchronous Read
Single Port RAM Design with False
Asynchronous Read
Single Port Block RAM Design With
Enable
Dual Port RAM With Asynchronous
Read , Dual Port RAM With False
Synchronous Read , Dual Port RAM
With Synchronous Read
ROM Design With Registered Output
ROM Design With Registered Address
Module VII [5 Hrs. Lecture+8 Hrs. Practice]
Floorplaning, Routing, Placement 5 Lecture Assignment TB-3
Clock Distribution, Power Distribution, -7.1 (Ch.11)
Packaging and Pads.
RTL Design of PLAs 8 Practice
Total (In Hrs.) 90 30 Hrs.
Lecture
and 60
Hrs.
Practice

P a g e | 33
System VERILOG
Course Title Code Type of course T-P-P Prerequisite
System VERILOG DEVL403 Theory & 2-2-0 Nil
Practice

Objective
 To Make The Student Understand System Verilog Language And Demonstrate How
To Build Verification Environment For Performing Verifications Of VLSI Circuits
Using SystemVerilog

Learning Outcome
 Students will Be Able to Use Any Simulation or Synthesis Tool that Support System
Verilog
 Students will Learn How to Take Advantage of The System Verilog Language to
Make RTL Design ad Synthesis More Productive

Evaluation Systems
Internal Component % of Marks Method of Assessment
Examination Internal Theory 20 Written Examination
Internal Practice 30(20+10) Lab Work + Learning Record
External External Theory 30 Written Examination
Examination External Practice 20 Lab Work
Total 100

Course Outline
Module I: Data Types, Array, Queue (16 Hrs.)

Theory
Different Data Types, User-Defined and Enumerated Types: String Data Types, Event Data
Types, User-Defined Types, Enumerated Types, Nets, Reg, Logic, Type Casting, Constants,
Attributes.
Array: Packed Array and Unpacked Array, Dynamic, Associate Array, Its Methods, QUEUE
Operators and Expressions, Control Structure: If-Else, Switch. Loop

Practice
1. Write A Program to Find Out the Frequency of Character in a String
2. Write A Program to Remove All Characters From a String Keeping All Numbers

Module II: Tasks and Functions (10 Hrs.)

Theory
Tasks, functions, Enhancements to tasks and functions, Task and function argument passing,
Import and export functions, System Tasks and System Functions
Practice
3. Write a Program to Convert Celsius To Fahrenheit Using Simple Task

P a g e | 34
4. Write a Program to Calculate Parity Using Function

Module III: Processes (12 Hrs.)


Theory
Combinational Logic, Latch Logic, Sequential Logic, Fork Join (Join, Join_Any, Join_None),
Event Controls, Process Control

Practice
5. Write a Program to Dynamically Reverse the Bit Position in System Verilog
6. Write a Program to Write a Program Contents of Two Registers With and Without a
Temporary Register

Module IV: Object Oriented Programming (16


Hrs.)

Theory
OOP Basics, Classes-Object and Handles, Polymorphism, Inheritance, Composition,
Creating New Object, Object Deallocation, Static Variables Vs. Global Variables, Class
Routines, Defining Routines Outside Of The Class, Using One Class Inside Another,
Dynamic Objects, Public Vs. Private

Practice
7. Write a Program to Show Inheritance and Polymorphism by Creating an Object
8. Write a Program Showing The Use Of Class Properties by Creating an Object and
Deleting that
9. Write a Program and Declare a Static and Global Variable and Show their Use in
Subroutine
10. Write a Program of 2 Numbers by Using Class Object Concept
11. Write a Program to Show Arithmetic Operations Using Class Subroutines

Module V: Interface (14 Hrs.)


Theory
Clocking Blocks, Program Block, Interface Concepts, Interfaces: Interface Declarations,
Using Interfaces as MODULE Ports, Instantiating and Connecting Interfaces, Referencing
Signals Within an Interface, Interface Modports, Using Tasks and Functions in Interfaces,
Parameterized Interfaces, Virtual Interfaces, Using Procedural Blocks in Interfaces,
Reconfigurable Interfaces, Verification With Interfaces

Practice
12. Write a Program to Perform a Multiplication Using Function of a Class
13. Write a Program to Perform an Event At 20ns Using Task of a Class
14. Write a Program to Show the Difference Between Task and Function

P a g e | 35
Module VI: Randomization (14 Hrs.)
Theory
Randomization, Constraints: Randomization in Systemverilog, Constraint Details,
Controlling Multiple Constraints, Common Randomization Problems, Iterative and Array
Constraints, Random Controls, Random Generators, Random Device Configuration

Practice
15. Write a Program by using rand Variables and Randomize them using Randomization
Function
16. Write a Program to Show the Difference between rand and randc Variables
17. Write a Program using Constraints within Randomization Variables

Module VII: Coverage (8 Hrs.)


Theory
Semaphores, Mailboxes, Functional Coverage: Coverage Models Cover Points and Bins,
Cross Coverage, Regression Testing
Practice
18. Define 3 Bins And Also Their Coverage Points And Find Out The Coverage
19. Write Down the Script which Shows us the Regression Testing
20. Define 4 Bins Which Holds the Coverage Points and Show the Coverage as 50%

Text Books
1. Sutherland, Stuart, Simon Davidmann, and Peter Flake, “SystemVerilog for Design
Second Edition: A Guide to Using System Verilog for Hardware Design and Modeling”,
Springer Science & Business Media, 2006
2. Spear, Chris. “SystemVerilog for Verification: a Guide to Learning the Testbench
Language Features,” Springer Science & Business Media, 2008
Reference Books
1. System Verilog, 3.1a, Language reference manual
2. Vijayaraghavan, Srikanth, and MeyyappanRamanathan. “A Practical Guide for
SystemVerilog Assertions”. Springer Science & Business Media, 2005
3. Bergeron, J. "Writing Testbenches Using SystemVerilog.―NY”, Springer Science and
Busir ness Media." (2006)

Session Plan:
Topic No. of Activity Assignment Suggested
Sessions Reading
(in hrs.)
Module I [6 Hrs. Lecture+10 Hrs. Practice]
Data Types, Array, Queue New 6 Lecture Assignment-1 TB-1 (Ch.5),
Data Types, Tasks and Functions, TB-2 (Ch.2)
Interfaces, Clocking Blocks, Different
Data Types, User-Defined and

P a g e | 36
Enumerated Types: String Data
Types, Event Data Types, User-
Defined Types, Enumerated Types,
Array: Packed Array and Unpacked
Array, Dynamic, Associate Array, Its
Methods, QUEUE Operators and
Expressions, Control Structure: If-
Else, Switch. Loop
Write a Program to Find Out the 10 Practice
Frequency of Character in a String
Write A Program To Remove All
Characters From a String Keeping All
Numbers
Module II [4 Hrs. Lecture+6 Hrs. Practice]
Tasks And Functions Tasks, 4 Lecture Assignment-2 TB-1(Ch.6)
Functions, Enhancements to Tasks
and Functions, Task and Function,
Argument Passing, Import and Export
Functions, System Tasks and System
Functions, VCD Data Synthesis
Write A Program to Convert Celsius 6 Practice
to Fahrenheit Using Simple Task
Write a Program to Calculate Parity
Using Function
Module III [4 Hrs. Lecture+8 Hrs. Practice]
Combinational Logic, Latch Logic, 4 Lecture Assignment-3
Sequential Logic, Fork Join (Join,
Join_Any, Join_None), Event
Controls, Process Control
Write a Program to Dynamically 8 Practice
Reverse the Bit Position in System
Verilog
Write a Program Contents of Two
Registers With and Without a
Temporary Register
Module IV [6 Hrs. Lecture+10 Hrs. Practice]
Object Oriented Programming 6 Lecture Assignment-4 TB-2(Ch.4)
Object Oriented Programming: OOP
Basics, Classes-Object and Handles,
Polymorphism, Inheritance,
Composition, Creating New Object,
Object Deallocation, Static Variables
vs. Global Variables, Class Routines,

P a g e | 37
Defining Routines Outside of the
Class, Using One Class Inside
Another, Dynamic Objects, Public vs.
Private
Write a Program to Show Inheritance 10 Practice
and Polymorphism by Creating an
Object
Write A Program Showing the Use of
Class Properties by Creating an
Object and Deleting that
Write a Program and Declare a Static
and Global Variable and Show their
Use in Subroutine
Write A Program of 2 Numbers by
Using Class Object Concept
Write a Program to Show Arithmetic
Operations Using Class Subroutines
Module V [4 Hrs. Lecture+10 Hrs. Practice]
Interface 4 Lecture Assignment-5 TB-1(Ch.10)
Clocking Blocks , Program Block ,
Interface Concepts, Interfaces:
Interface Declarations, Using
Interfaces as MODULE Ports,
Instantiating and Connecting
Interfaces, Referencing Signals
Within an Interface, Interface
Modports, Using Tasks and Functions
In Interfaces, Parameterized
Interfaces, Virtual Interfaces, Using
Procedural Blocks in Interfaces,
Reconfigurable Interfaces,
Verification With Interfaces
Write a Program to Perform a 10 Practice
Multiplication Using Function of a
Class
Write a Program to Perform an Event
at 20ns Using Task of a Class
Write A Program to Show the
Difference Between Task and
Function
Module VI [4 Hrs. Lecture+10 Hrs. Practice]
Randomization, Constraints: 4 Lecture Assignment-6 TB-2(Ch.6)
Randomization in System Verilog,

P a g e | 38
Constraint Details, Controlling
Multiple Constraints, Common
Randomization Problems, Iterative
and Array Constraints, Random
Controls, Random Generators,
Random Device Configuration
Write a Program by Using Rand 10 Practice
Variables and Randomize them Using
Randomization Function
Write a Program to Show the
Difference Between Rand and Randc
Variables
Write a Program Using Constraints
Within Randomization Variables
Module VII[2 Hrs. Lecture+6 Hrs. Practice]
Coverage 2 Lecture Assignment-7 TB-1(Ch.12)
Semaphores, Mailboxes, Functional
Coverage: Coverage Models, Cover
Points and Bins, Cross Coverage,
Regression Testing
Define 3 Bins and Also their 6 Practice
Coverage Points and Find Out the
Coverage
Write Down the Script Which Shows
us the Regression Testing
Define 4 Bins Which Holds the
Coverage Points and Show the
Coverage as 50%
Total (In Hrs.) 90 30 Hrs.
Lecture
& 60
Hrs.
Practice

P a g e | 39
VLSI Verification Methodologies

Course Title Code Type of course T-P-P Prerequisite


VLSI Verification DEVL0201 Practice 0-2-0 Nil
Methodologies

Objective
 The Objective of this Course ss to Involve Students in Theory and Practice of
Verifications VLSI Circuits Using Methods Such as Universal Verification and Open
Verification Methodology

Learning Outcome
 Student will Gain Knowledge of Various Verification Techniques Employed for
Verifying VLSI Chips
 Students will Develop Skills of Performing Verification of the Complex VLSI Chips.

Evaluation Systems
Internal Examination Component % of Marks Method of Assessment

Internal Practice 50 (40+10) Lab work + Learning Record

External Examination External Practice 50 Lab work

Total 100

Course Outline
Module I: (5 Hours)

Practice
History of Testing, Introduction to Universal Verification Methodology (UVM): Typical
UVM Testbench Architecture, UVM Library Class

Module II: Introduction to UVM(10 Hours)

Practice
UVM Basics: UVM TB Architecture, Creating UVCs and Environment, Creating agent,
UVM simulation phases, Test Flow

Module III: Transaction Level Modelling (TLM) (10 Hours)

Practice
Overview, TLM, TLM1, Merit, Demerit, TLM 2, Implementation

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Module IV (10 Hours)

Practice
Creating and Using UVM Testbench: Configuring UVM Environment: UVM Sequences,
UVM Sequencers, Connecting DUT-Virtual Interfaces, Virtual Sequences and Sequencers,
Transaction Class

Module V (10 Hours)

Practice
Creating and Using UVM Testbench: Creating UVM Environment: Building a Scoreboard,
Building Reusable Environments, Connecting Multiple UVCs

Module VI (7 Hours)

Practice
Use of Verification Components: Test Plan And Coverage: Creating Test Plan from
Specification Coverage: Code Coverage and Functional Coverage

Module VII (8 Hours)

Practice
Assertion Based Methodology: Immediate Assertion, Simple Assertions, Sequences,
Sequence composition, Assertion Coverage

Text Books

1. R. Salemi, “The UVM Primer: A Step-By-Step Introduction To The Universal


Verification Methodology” Boston Light Press, 2013
2. V.R. Cooper, “Getting Started with UVM: A Beginner's Guide,” Austin: Verilab
Publishing, 2013
3. H. Height, “A Practical Guide To Adopting The Universal Verification Methodology
(UVM)” Lulu. Com, 2010
4. C. Spear, “SystemVerilog for verification: A Guide to Learning The Testbench Language
Features,” Springer Science & Business Media, 2008

Session Plan:

Topic No. of Activity Suggested


Sessions (in Reading
hrs.)
Design of UART Protocol by using Verilog Practice
Design of I2C master Protocol by using Verilog Practice
Design of I2C slave Protocol by using Verilog Practice

P a g e | 41
Design of Asynchronous FIFO by using Practice
Verilog
Designs of SPI protocol Transmitter by using Practice
Verilog
Design of DMA by using Verilog Practice
Verification of UART Protocol by using UVM Practice
Verification of I2C master Protocol by using Practice
UVM
Verification of I2C slave Protocol by using Practice
UVM
Verification of Asynchronous FIFO by using Practice
UVM
Verification of SPI Protocol by using UVM Practice
Verification of AMBA AXI Protocol by using Practice
UVM
Verification of AMBA AHB protocol by using Practice
UVM
Verification of AMBA APB protocol by using Practice
UVM
Verification of DMA by using UVM Practice
Total(in hrs.) 60 60 hrs.
Practice

P a g e | 42
VLSI Test Principle and Testable Design
Course Title Code Type of course T-P-P Prerequisite
VLSI Test Principle and DEVL0102 Theory 3-0-0 Nil
Testable Design

Objective
 To Make the Student Understands Defects and Faults in VLSI Chips Different Test
Pattern Generation Techniques and Understand Design-For-Testability.

Learning Outcome
 Students will Be Familiar with the Testing and Verification Methodology of VLSI
Circuits
 Student will Develop Skill of Testing Complex Analog, Digital and Mixed Signal
Chips

Evaluation Systems
Component % of Marks Method of Assessment

Internal Theory 30 Written examination


Internal Examination Report or Presentation +
Assignment 5
Learning Record
Attendance 5 Based on class attended

External Examination External Theory 60 Written examination

Total 100

Course Outline
Module I: Introduction to VLSI testing, Fault modelling (10 Hours)

Theory
Trends, Moore’s Law, Realization, Why Testing, Verification Vs Testing, Ideal Test, Real
Test, Level of Testing, Cost of Testing, Role of testing, Real Defects, Faults, Errors and
Failures, Overheads, Types, Basic Testing Principle, Design Flow, Characterization,
Manufacturing Test, Stress Test, Bathtub Component Failure Curve, Parametric Test,
Functional Test, ATPG, Test Specification and Plan, Test Program Generation, Test Data
Analysis, Yield, Clustered VLSI Defects, Defect Level
Motivation of Fault Model, Why Fault Model, Some Real Defects, Fault Models, Logic
Modelling, Behavioural Fault Models, Functional Level, Structural Level, Stuck at Fault
Model, Bridging Fault, Switch Level Fault, Stuck Open/Short Fault, Geometric Fault,
Delay Testing, Gate Delay Fault, Path Delay Fault, Redundant Fault, Operational Fault,
Fault Collapsing, Fault Dropping, Fault Equivalence, Fault Dominance

P a g e | 43
Module II: Logic Simulation (5 Hours)
Theory
Basic Concept, Modelling for Simulation, Logic Model of MOS Circuit, Signal States for
Simulation, Determining Gate Values, Two Valued Truth Table, True Value Simulation,
Compiled Code Algorithm, Logic Levelization Algorithm, Event Driven Simulation,
Parallel Simulation of Multiple Vectors

Module III: Fault Simulation (5 Hours)


Theory
Motivation, Uses of Fault Simulator, How to Simulate Fault, Fault Simulation Algorithm,
Serial Algorithm, Parallel Fault Simulation, Deductive Fault Simulation, Concurrent Fault
Simulation, Critical Path Tracing, Fault Sampling, Random Sampling Model, Probability
Density of Sample Coverage, Sampling Error Bounds

Module IV: Testability Analysis (5 Hours)


Theory
Origin, Types of Measures in SCOAP, Range of SCOAP Measures, Controllability and
Observability of Basic Gates, Error for Stems and Reconverging Fan-out, Correlation
Error, Sequential Example, Combinational and Sequential Controllability and
Observability, Testability Computation Algorithm

Module V: Combinational ATPG, Sequential Test Generation (8 Hours)


Theory
Test Generation, Test Pattern, Test Generation Methods, Boolean Difference, Roth’s 5
Valued and Muth’s 9 Valued Algebra, Deterministic ATPG, Decision Tree for Branch and
Bound Search, Backtracking, Common Concepts for Structural Test Generation, Line
Justification in a Fanout Free Circuit, Fault Propagation, Backtracking TG Algorithm, D
Frontier, J Frontier, D Algorithm, Definition of Singular Cover, D cubes, D Intersection. D
and 9V Algorithm Value Computation and Decision Tree, PODEM
Sequential Circuit, Test Generation Method, Time Frame Expansion Method,
Implementation of ATPG, Cycle Free Circuits, Asynchronous Model

Module VI: Design for Testability (5 Hours)


Theory
Basic Concept, Ad hoc DFT Method, Structured Method, Scan Path Design, Scan Cell
Design, Muxed D Scan FF, Clocked Scan Cell, Level Sensitive Scan Cell. LSSD- Adding
Scan Structure in Circuit, Combinational test vectors, Scan Testing Time, Multiple Scan
Path, Scan Overheads, Hierarchical Scan, Optimum Scan Layout, Scan Area Overhead,
Automated Scan Design, Different LSSD structure, LSSD Design Rule, Advantages and
Drawback. Partial Scan Design- Objective, Architecture, Partial Scan Method, MVFS
Problem, Test Generation, Flip Flop for Partial Scan, Random Access Scan(RAS), RAS
Flip Flop, Scan Hold Flip Flop

P a g e | 44
Module VII: Built In Self-Test (7 Hours)
Theory
Motivation, Basic Architecture, Hierarchy, Multipurpose Register Application, Drawback
and Advantages, Techniques, Pattern Generation, Exhaustive and Pseudo Exhaustive
Method, Random Pattern Testing, LFSR- Types, Analysis using Polynomial
Representation, Properties, LFSR as Pseudo Random Pattern Generator, Test Response
Compaction- Compaction Techniques, BIST Compression Techniques, Ones Count,
Transition Count, Parity Check, Syndrome Check, Signature Analysis, LFSR Response
Compacter, MISR, Modular MISR, Multiple Signature Check, Aliasing Probability
BIST Architecture- Built in Logic Block Observer (BILBO), BILBO in Different Modes,
STUMS, Circular Self-Test Path BIST

Text Books
1. M. Bushnelland,V.Agrawal, “Essentials of Electronic testing for Digital, Memory and
Mixed-Signal VLSI circuits” (Vol. 17),Springer Science & Business Media, 2004
2. M.Abramovici, M.A. Breuer, and A.D.Friedman, “Digital Systems Testing and Testable
Design” (Vol. 2). New York: Computer science press,1990

Reference Books
1. N.K. Jha, andS.Gupta,“Testing of Digital Systems”, Cambridge University Press, 2003
2. L.T.Wang, C.W. Wu, and X.Wen,. “VLSI Test Principles and Architectures: Design for
Testability”, Elsevier,2006

P a g e | 45
Session Plan:
Topic No. of Activity Assignment Suggested
Sessions Reading
(in hrs.)
Module I [10 Hrs. Lecture]
Introduction to VLSI testing, Fault 10 Lecture Assignment TB-1
Modelling 1.1 (Ch.4,5)
Trends, Moore’s Law, Realization, Why
Testing, Verification Vs Testing, Ideal Test,
Real Test, Level of Testing, Cost of Testing,
Role of testing, Real Defects, Faults, Errors
and Failures, Overheads, Types, Basic
Testing Principle, Design Flow,
Characterization, Manufacturing Test, Stress
Test, Bathtub Component Failure Curve,
Parametric Test, Functional Test, ATPG, Test
Specification and Plan, Test Program
Generation, Test Data Analysis, Yield,
Clustered VLSI Defects, Defect Level
Motivation, Why Fault Model, Some Real
Defects, Fault Models, Logic modelling,
Behavioural Fault models, Functional Level,
Structural Level, Stuck at Fault Model,
Bridging Fault, Switch Level Fault, Stuck
Open/Short Fault, Geometric Fault, Delay
Testing, Gate Delay Fault, Path Delay Fault,
Redundant Fault, Operational Fault, Fault
Collapsing, Fault Dropping, Fault
Equivalence, Fault Dominance
Module II [5 Hrs. Lecture]
Logic Simulation 5 Lecture Assignment TB-1
Basic Concept, Modelling For Simulation, 2.1 (Ch.5)
Logic Model of MOS Circuit, Signal States
for Simulation, Determining Gate Values,
Two Valued Truth Table, True Value
Simulation, Compiled Code Algorithm,
Logic Levelization Algorithm, Event Driven
Simulation, Parallel Simulation of Multiple
Vectors
Module III [5 Hrs. Lecture]
Fault Simulation 5 Lecture Assignment TB-1
Motivation, Uses of Fault Simulator, How to 3.1 (Ch.5)
simulate fault, Fault simulation Algorithm,

P a g e | 46
Serial Algorithm, Parallel Fault Simulation,
Deductive Fault Simulation, Concurrent Fault
Simulation, Critical Path Tracing, Fault
Sampling, Random Sampling Model,
Probability Density of Sample Coverage,
Sampling Error Bounds
Module IV [5 Hrs. Lecture]
Testability Analysis 5 Lecture Assignment TB-1
Origin, Types of measures in SCOAP, Range 4.1 (Ch.5,6)
of SCOAP measures, Controllability and
Observability of Basic Gates, Error for Stems
and Reconverging Fan-out, Correlation Error,
Sequential Example, Combinational and
Sequential Controllability and Observability,
Testability Computation Algorithm
Module V [8 Hrs. Lecture]
Combinational ATPG, Sequential Test 8 Lecture Assignment TB-1
Generation 5.1 (Ch.7,8)
Test Generation, Test Pattern, Test
Generation Methods, Boolean Difference,
Roth’s 5 Valued and Muth’s 9 Valued
Algebra, Deterministic ATPG, Decision Tree
for Branch and Bound Search, Backtracking,
Common Concepts for Structural Test
Generation, Line Justification in a Fanout
free Circuit, Fault Propagation, Backtracking
TG Algorithm, D Frontier, J Frontier, D
Algorithm, Definition of Singular Cover, D
cubes, D Intersection. D and 9V algorithm
Value Computation and Decision tree,
PODEM
Module VI [5 Hrs. Lecture]
Design For Testability 5 Lecture Assignment TB-1
Basic Concept, Ad hoc DFT Method, 6.1 (Ch.14)
Structured Method, Scan Path Design, Scan
Cell Design, Muxed D Scan FF, Clocked
Scan Cell, Level Sensitive Scan Cell. LSSD-
Adding Scan Structure in Circuit,
Combinational test vectors, Scan Testing
Time, Multiple Scan Path, Scan Overheads,
Hierarchical Scan, Optimum Scan Layout,
Scan Area Overhead, Automated Scan
Design, Different LSSD structure, LSSD

P a g e | 47
design rule, Advantages and Drawback.
Partial Scan Design- Objective, Architecture,
Partial Scan Method, MVFS problem, Test
Generation, Flip Flop for Partial Scan,
Random Access Scan(RAS), RAS Flip Flop,
Scan Hold Flip Flop
Module VII [7 Hrs. Lecture]
Built In Self-Test 7 Lecture Assignment TB-1
Motivation, Basic Architecture, Hierarchy, 7.1 (Ch.15)
Multipurpose Register application,
Drawback and Advantages, Techniques,
Pattern Generation, Exhaustive and Pseudo
Exhaustive Method, Random Pattern
Testing, LFSR- Types, Analysis using
Polynomial Representation, Properties,
LFSR as Pseudo Random Pattern
Generator, Test Response Compaction-
Compaction Techniques, BIST
Compression Techniques, Ones Count,
Transition Count, Parity Check, Syndrome
Check, Signature Analysis, LFSR
Response Compacter, MISR, Modular
MISR, Multiple Signature Check, Aliasing
Probability
BIST Architecture- Built In Logic Block
Observer (BILBO), BILBO in different
Modes, STUMS, Circular Self-Test Path
BIST
Total (in Hrs.) 45 45 Hrs.
Lecture

P a g e | 48
Domain - Communication Systems

Course Course Title Course Type Credit


Code
DECS0401 Optical Fiber Communication Theory & Practice 3
DECS0402 Satellite & TV Communication Theory & Practice 3
DECS0201 Cell Site and BTS Operation & Practice 2
Maintenance
DECS0202 RF Planning and Drive Test Practice 2
DECS0102 4G LTE & 5G Communications Theory 3
DECS0403 Digital Image Processing Theory & Practice 3
DECS0601 Antenna designs & Manufacturing Practice + Project 4
DEET0300 Project 6
DEET0800 Internship 4
Total Credit 30

P a g e | 49
Optical Fiber Communication

Subject Code Type of course T-P-P Prerequisite


Optical Fiber DECS0401 Theory & Practice 2-1-0 Nil
Communication

Objective
 To teach the optical fiber , optical fiber communication devices and systems

Learning Outcome
 Students will gain knowledge of various optical fiber modes, configurations, various
signal degradation factors ,optical sources and detectors
 Students will develop skill of splicing techniques, passive optical components
repairing and noise measurement in optical system

Evaluation Systems

Internal Component % of Marks Method of Assessment


Examination Internal Theory 20 Written Examination
Internal Practice 30 (20+10) Lab Work + Learning Record
External External Theory 30 Written Examination
Examination External Practice 20 Lab Work
Total 100

Course Outline

Module I: Overview of Optical fiber Communication (8Hours)


Theory
Overview of Optical fiber Communication: Introduction, Historical development, general
system, advantages, disadvantages, and applications of optical fiber communication, optical
fiber waveguides, Ray theory, cylindrical fiber, single mode fiber, cutoff wave length, mode
filed diameter. Optical Fibers: fiber materials, photonic crystal, fiber optic cables specialty
fibers.
Practice

1. Analog Link Using Optical Fiber.


2. Voice Link Using Optical Fiber.

Module II: Transmission Characteristics Ofoptical fibers, Optical sources And


Detectors (8 Hours)
Theory
TRANSMISSION CHARACTERISTICS OF OPTICAL FIBERS: Introduction, Attenuation,
absorption, scattering losses, bending loss, dispersion, Intra modal dispersion, Inter modal
dispersion. OPTICAL SOURCES AND DETECTORS: Introduction, LED’s, LASER diodes,
Photo detectors, Photo detector noise, Response time, double hetero junction structure, Photo
diodes, comparison of photo detectors.

P a g e | 50
Practice

3. PAM Signal Transmission & Reception.

4. Propagation Loss Measurement

Module III: Fiber Couplers and Connectors (10 Hours)


Theory
Fiber Couplers and Connectors: Introduction, fiber alignment and joint loss, single mode
fiber joints, fiber splices, fiber connectors and fiber couplers.

Practice

5. Bending Loss Measurement

Module IV: Optical Receiver (10 Hours)


Theory
Optical Receiver: Introduction, Optical Receiver Operation, receiver sensitivity, quantum
limit, eye diagrams, coherent detection, burst mode receiver operation, Analog receivers.
Practice

6. Numerical Aperture

Module V: Analog and Digital Links (10 Hours)


Theory
Analog And Digital Links: Analog links – Introduction, overview of analog links, CNR,
multichannel transmission techniques, RF over fiber, key link parameters, Radio over fiber
links, microwave photonics. Digital links – Introduction, point–to–point links, System
considerations, link power budget, resistive budget, short wave length band, and transmission
distance for single mode fibers, Power penalties, nodal noise and chirping.
Practice

7. Splicing & Connecting of optical cable

Module VI: WDM Concepts and Components (8 Hours)


Theory
WDM Concepts And Components: WDM concepts, overview of WDM operation principles,
WDM standards, Mach-Zehender interferometer, multiplexer, Isolators and circulators, direct
thin film filters, active optical components, MEMS technology, variable optical attenuators,
tunable optical fibers, dynamic gain equalizers, optical drop multiplexers, polarization
controllers, chromatic dispersion compensators, tunable light sources.
Practice

8. Eye Pattern Measurement

9. WDM operation

P a g e | 51
Module VII: Optical Amplifiers and Networks (6 Hours)
Theory
Optical Amplifiers And Networks: optical amplifiers, basic applications and types,
semiconductor optical amplifiers, EDFA. Optical Networks: Introduction, SONET / SDH,
Optical Interfaces, SONET/SDH rings, High – speed light – waveguides.
Practice

10. Optical Amplifiers

Text Books:

1. KeiserGerd, “Optical fiber communications” McGraw-Hill Science, Engineering &


Mathematics, 2008.

2. John M. Senior, “Optical Fiber Communications” Pearson Education ,3 rd Impression,


2007.

Reference Book:

1. Joseph C Palais , “Fiber optic communication” , 4th Edition, Pearson Education.

Session Plan
Topics No. of Activity Assignment Suggested Reading
Sessions
(in hrs.)
Module I [4hrs. Lecture + 4hrs. Practice]
Overview of Optical Fiber 1 Lecture Assignment TB CH- 1
Communication:Introduction, No- 1.1
Historical development, general
system, advantages,
disadvantages, and applications
of optical fiber communication
optical fiber waveguides, Ray 1 Lecture Assignment TB CH- 2
theory, cylindrical fiber No-1.2
cutoff wave length, mode filed 1 Lecture Assignment TB CH- 1
diameter. No-1.3
Optical Fibers: fiber materials, 1 Lecture Assignment TB CH- 1
photonic crystal, fiber optic No-1.4
cables specialty fibers
2 Practice Assignment TB CH- 1
Analog Link Using Optical Fiber
No-1.5
2 Practice Assignment TB CH- 1
Voice Link Using Optical Fiber
No-1.6
Module-II[4hrs. Lecture + 4hrs. Practice]
Introduction, Attenuation, 1 Lecture Assignment TB CH- 2
absorption, scattering losses, No- 2.1
bending loss, dispersion
Intra modal dispersion, Inter 1 Lecture + Assignment TB CH- 2

P a g e | 52
modal dispersion. Practice No- 2.2
OPTICAL SOURCES AND 1 Lecture Assignment TB CH- 2
DETECTORS: Introduction, No- 2.3
LED’s, LASER diodes, Photo
detectors,
Photo detector noise, Response 1 Lecture Assignment TB CH- 2
time, double hetero junction No- 2.4
PAM Signal Transmission & 2 Practice Assignment TB CH- 2
Reception. No- 25
2 Practice Assignment TB CH- 2
Propagation Loss Measurement No- 2.6
MODULE-III [8hrs. Lecture + 2hrs. Practice]
Fiber Couplers and Connectors: 3 Practice Assignment TB CH- 2
Introduction, fiber alignment No- 3.1
Quantum limit, eye diagrams, 2 Practice Assignment TB CH- 2
coherent detection, No- 3.2
Burst mode receiver operation, 2 Practice Assignment TB CH- 2
Analog receivers. No- 3.3
3 Practice Assignment TB CH- 2
Bending Loss Measurement No- 3.4
MODULE-IV[8hrs. Lecture + 2hrs. Practice]
2 Lecture Assignment RB- 2 CH- 4
Optical Receiver: Introduction, No- 4.1
Optical Receiver Operation
receiver sensitivity, quantum 2 Lecture
Assignment RB- 2 CH- 4
limit, eye diagrams, No- 4.2
coherent detection, burst mode2 Lecture Assignment RB- 2 CH- 5
receiver operation No- 4.7-4.10
2 Practice Assignment
Analog receivers
No- 4.11
2 Practice Assignment
Numerical Aperture No- 4.12
MODULE-V[8hrs. Lecture + 2hrs. Practice]
Analog And Digital Links: 1 Lecture Assignment TB CH- 4
Analog links – Introduction, No- 5.1
overview of analog links, CNR,
multichannel transmission
techniques
RF over fiber, key link 1 Lecture Assignment TB CH- 4
parameters, Radio over fiber No- 5.2
links, microwave photonics.
Digital links – Introduction, 2 Lecture Assignment TB CH- 4
point–to–point links, System No- 5.3
considerations
link power budget, resistive 2 Lecture Assignment TB CH- 4
budget, short wave length band No- 5.4
and transmission distance for 1 Lecture Assignment TB CH- 4
single mode fibers, No- 5.5
Power penalties, nodal noise and 1 Lecture Assignment TB CH- 4
chirping No- 5.6

P a g e | 53
Splicing & Connecting of optical 2 Practice Assignment TB CH- 4
cable No- 5.7
MODULE-VI[6hrs. Lecture + 4hrs. Practice]
WDM Concepts And 2 Lecture Assignment TB CH- 5
Components: WDM concepts, No- 6.1- 6.4
overview of WDM operation
principles, WDM standards,
Mach-Zehender interferometer,
multiplexer, Isolators and 2 Lecture Assignment TB CH- 5
circulators direct thin film filters, No- 6.6
active optical components,
MEMS technology, variable 2 Lecture Assignment TB CH- 5
optical attenuators, tunable No- 6.7
optical fibers, dynamic gain
equalizers
2 Practice Assignment TB CH- 5
optical drop multiplexers No- 6.8
Polarization controllers, 2 Practice Assignment TB CH- 5
chromatic dispersion No- 6.9
compensators, tunable light
sources.
.

MODULE-VII[8hrs. Lecture + 2hrs. Practice]


Optical Amplifiers And 2 Practice Assignment RB- 2 CH- 6
Networks: optical amplifiers, No- 7.1
basic applications and types
EDFA. Optical Networks: 2 Lecture Assignment RB- 2 CH- 6
Introduction, SONET No- 7.2
3 Lecture Assignment RB- 2 CH- 6
SDH, Optical Interfaces,
No- 7.3
Optical Interfaces, SONET/SDH 3 Lecture Assignment RB- 2 CH- 6
rings No- 7.4
2 Lecture Assignment RB- 2 CH- 6
High – speed light – waveguides
No- 7.5
Total hr 60 Hrs

P a g e | 54
Satellite & TV Communications
Course Title Code Type of course T-P-P Prerequisite
Satellite & TV DECS0402 Theory & 2-1-0 Nil
Communication. Practice

Objective
 To Teach the Basic Concept of Satellite Communication and Frequency Allocations, In
Addition to this Most Important Methods in Satellite Launching & Fundamentals of TV
Communications.

Learning Outcomes
 Students will gain knowledge of different types of satellites, calculate the orbital
determination and launching methods , monitoring power systems, developments of antennas
and different techniques like TDMA, CDMA, FDMA, DAMA.
 Students will develop skill of design antennas by providing Uplink and Down link
Frequency.

Evaluation Systems
Internal Component % of Marks Method of Assessment
Examination Internal Theory 20 Written Examination
Internal Practice 30 (20+10) Lab Work + Learning Record
External External Theory 30 Written Examination
Examination External Practice 20 Lab Work
Total 100

Course Outline

Module I: Introduction to Satellite Communication (8 Hours)

Theory
Introduction to Satellite Communication: Basic concepts of Satellite Communications,
Communication Networks and Services, Comparison of Network Transmission technologies.
Orbits and Launching Methods: Introduction, Kepler’s First Law, Kepler’s Second Law,
Kepler’s Third Law, Definitions of Terms for Earth-Orbiting Satellites, Orbital Elements,
Apogee and Perigee Heights, Orbit Perturbations, Effects of a non-spherical earth,
Atmospheric drag.

Module II: The Geostationary Orbit: (10 Hours)


Theory
Introduction, Antenna Look Angles, The Polar Mount Antenna, Limits of Visibility, Near
Geostationary Orbits, Earth Eclipse of Satellite, Sun Transit Outage, Launching Orbits. Radio
Wave Propagation: Introduction, Atmospheric Losses, Ionospheric Effects, Rain Attenuation,
Other Propagation Impairments.

Module III: The Space Segment: (10 Hours)


Theory

P a g e | 55
Introduction, The Power Supply, Attitude Control, Spinning satellite stabilization,
Momentum wheel stabilization, Station Keeping, Thermal Control, TT&C Subsystem,
Transponders, The wideband receiver, The input de-multiplexer, The power amplifier, The
Antenna Subsystem

Practice
1. To set up a satellite communication link and study of change in uplink and downlink
frequency
2. To establish an Audio-Video satellite link between Transmitter and Receiver

Module IV: The Earth Segment: (08 Hours)


Theory
Introduction, Receive-Only Home TV Systems, The outdoor unit, The indoor unit for analog
(FM) TV, Master Antenna TV System, Community Antenna TV System, Transmit-Receive
Earth Stations.

Practice
3. To Study Frequency Hopping Spread Spectrum (FHSS) Modulation and Demodulation
Technique
4. To study generation (spreading) & demodulation (Despreading) of DSSS modulated
signal.

Module V: The Space Link (10 Hours)


Theory
Introduction, Equivalent Isotropic Radiated Power, Transmission Losses, Free-space
transmission, Feeder losses, Antenna misalignment losses, Fixed atmospheric and
ionospheric losses, The Link-Power Budget Equation, System Noise, Carrier-to-Noise Ratio,
The Uplink, Saturation flux density, Input backoff, Downlink, Output back-off, Combined
Uplink and Downlink C/N Ratio

Practice
5. To study radiation pattern & calculate beam width for Yagi Uda & folded dipole antenna
6. To study radiation pattern & calculate beam width for circular & triangular patch
Antenna Study of Data and PN Sequence Generation
Module VI: Satellite Access: (08 Hours)
Theory
Introduction, Single Access, Preassigned FDMA, Demand Assigned FDMA, Spade System,
TDMA, Preassigned TDMA, Demand-assigned TDMA, Satellite-Switched TDMA, Code
Division Multiple Access.

Practice
7. To study GPS data like longitude, latitude using GPS receiver

Module VII: Direct Broadcast Satellite Television and Radio: (6 Hours)


Theory
C-Band and Ku-Band Home Satellite TV, Digital DBS TV, DBSTV System Design, DBS-TV Link
Budget, Error Control in Digital DBS-TV, Master Control Station and Uplink, Installation of DBSTV
Antennas, Satellite Radio Broadcasting, Digital Video Broadcast(DVB) Standards, Digital Video
Broadcast – Terrestrial (DVB-T)

P a g e | 56
Practice
8. Study of Minimum Shift Keying (MSK) Modulation Process
9. Study of Minimum Shift Keying (MSK) Demodulation Process
Text Book
1. Satellite Communications, by Dennis Roddy (Fourth edition), McGraw Hill
2. Satellite Communication, by Timothy Pratt, Charles Bostian, Jeremy Allnutt (Second Edition),
John Wiley & Sons
Reference Books
1. Satellite Communication Systems Engineering, by Wilbur L. Pritchard, Henri G. Suyderhoud,
Robert A. Nelson (Second Edition), Pearson
2. Satellite Technology, Principles and Applications, by Anil K. Maini, Varsha Agarwal (Second
Edition), Wiley

Session Plan

Topics No.of Activities Assignment Suggested reading


Sessions(
in hrs)

Module-I[4hrs. Lecture+4hrs. Practice]

Introduction to Satellite 2 Lecture Assignment No-1.1 TB CH-1


Communication: Basic concepts of
Satellite Communications,
Communication Networks and
Services, Comparison of Network
Transmission technologies. Orbits
and Launching Methods:
Introduction, Kepler’s First Law,
Kepler’s Second Law, Kepler’s
Third Law.

Definitions of Terms for Earth- 2 Lecture Assignment No-1.2 TB CH-1


Orbiting Satellites, Orbital
Elements, Apogee and Perigee
Heights, Orbit Perturbations,
Effects of a non-spherical earth,
Atmospheric drag.

Module-II [4hrs. Lecture+4hrs. Practice]

The Geostationary Orbit: 1 Lecture Assignment No-1.3 TB CH-2


Introduction, Antenna Look
Angles, The Polar Mount Antenna,
Limits of Visibility, Near
Geostationary Orbits, Earth
Eclipse of Satellite, Sun Transit
Outage, Launching Orbits.

Radio Wave Propagation: 1 Lecture Assignment No-1.4 TB CH-2


Introduction, Atmospheric Losses,
Ionospheric Effects, Rain
Attenuation, Other Propagation
Impairments

P a g e | 57
Module-III[4hrs. Lecture+4hrs. Practice]

The Space Segment : Introduction, 6 Lecture Assignment No-1.5 TB CH-2


The Power Supply, Attitude
Control, Spinning satellite
stabilization, Momentum wheel
stabilization, Station Keeping,
Thermal Control, TT&C
Subsystem, Transponders, The
wideband receiver, The input de-
multiplexer, The power amplifier,
The Antenna Subsystem

To set up a satellite 2 Practice Assignment No-1.6 TB CH-2


communication link and study of
change in uplink and downlink
frequency

To establish an Audio-Video 2 Practice Assignment No-1.7 TB CH-2


satellite link between Transmitter
and Receiver

Module-IV [2hrs. Lecture+4hrs. Practice]

The Earth Segment: Introduction, 2 Lecture Assignment No-1.8 TB CH-3


Receive-Only Home TV Systems,
The outdoor unit, The indoor unit
for analog (FM) TV, Master
Antenna TV System, Community
Antenna TV System, Transmit-
Receive Earth Stations.

To Study Frequency Hopping 2 Practice Assignment No-1.9 TB CH-3


Spread Spectrum (FHSS)
Modulation and Demodulation
Technique

To study generation (spreading) & 2 Practice Assignment No-2.0 TB CH-3


demodulation (despreading) of
DSSS modulated signal.

Module-V[4hrs. Lecture+4hrs. Practice]

The Space Link : Introduction, 6 Lecture Assignment No-2.1 TB CH-4


Equivalent Isotropic Radiated
Power, Transmission Losses, Free-
space transmission, Feeder losses,
Antenna misalignment losses,
Fixed atmospheric and ionospheric
losses, The Link-Power Budget
Equation, System Noise, Carrier-
to-Noise Ratio, The Uplink,

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Saturation flux density, Input
backoff, Downlink, Output back-
off, Combined Uplink and
Downlink C/N Ratio.

To study radiation pattern & 2 Practice Assignment No-2.2 TB CH-4


calculate beam width for Yagi Uda
& folded dipole antenna

To study radiation pattern & 2 Practice Assignment No-2.3 TB CH-4


calculate beam width for circular
& triangular patch antenna Study
of Data and PN Sequence
Generation

Module-VI [4hrs. Lecture+4hrs. Practice]

Satellite Access: Introduction, 6 Lecture Assignment No-2.4 TB CH-7


Single Access, Preassigned
FDMA, Demand Assigned
FDMA, Spade System, TDMA,
Preassigned TDMA, Demand-
assigned TDMA, Satellite-
Switched TDMA, Code Division
Multiple Access

To study GPS data like longitude, 2 Practice Assignment No-2.5 TB CH-7


latitude using GPS receiver

Module-VII [2hrs. Lecture+4hrs. Practice]

Direct Broadcast Satellite 1 Lecture Assignment No-2.6 TB CH-9


Television and Radio: C-Band and
Ku-Band Home Satellite TV,
Digital DBS TV, DBSTV System
Design, DBS-TV Link Budget,
Error Control in Digital DBS-TV,
Master Control Station and
Uplink,

Study of Minimum Shift Keying 1 Practice Assignment No-2.7 TB CH-9


(MSK) Modulation Process

Study of Minimum Shift Keying 2 Practice Assignment No-2.8 TB CH-9


(MSK) Demodulation Process

Installation of DBSTV Antennas, 2 Lecture Assignment No-2.9 TB CH-9


Satellite Radio Broadcasting,
Digital Video Broadcast(DVB)
Standards, Digital Video
Broadcast – Terrestrial (DVB-T)

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Cell Site and BTS Operation, Maintenance and Trouble shooting

Course Title Code Type of course T-P-P Prerequisite


Cell Site and BTS DECS0201 Practice 0-2-0 Nil
Operation,
Maintenance and
Trouble shooting

Objective
 To teach the details about Telecom mobile towers; maintain tower sites & repair
faults/issues, which are live 24x7 Hrs

Learning Outcome
 Students will gain knowledge of AC, DG, PIU, LCU, CPU, SMPS and battery bank,
as per organization’s norms.
 Students will develop skill of designing Adhere and conduct site PM (preventive
maintenance) &Task Reporting planes, as per organization’s norms.

CONTENT:
Module I
Practice

The Wireless Communication Concept and Mobile Tower Elements: Cellular concept
(GSM/CDMA/LTE), Types and height of different Towers, antennas used and need of
Mobile tower. Basic concept on mains (AC), DG, Battery bank, Solar supply system to a cell
site,
Module II
Practice

Equipment used in the Shelter (Only PIU, LCU, CPU, FCU): Power Interface Unit (PIU)
indoor & outdoor.
Block diagram & working Principle of PIU, Components of PIU, Physical wiring diagram,
Power flow of PIU, Function test of PIU.
Module III
Practice

Line Conditioning Unit (LCU): Working Principle of LCU, Components of LCU, Physical
wiring diagram, Power flow of LCU, Function test of LCU, Fault finding withinLCU.
Module IV
Practice

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Power Interface Unit (PIU): Working principle of PIU, Components, current flow and fault
finding of PIU. Free Cooling Unit (FCU): Working Principle of FCU, Components and fault
finding of FCU.
Module V
Practice

(Preventive Maintenance (PM), Task Reporting, Site management& BTS: Adhere and Ensure
PM activities plan at the tower site, conduct & fill the site PM, Operational maintenance of
the site;
Module VI
Practice

Basic functioning of alarm box and the interface, identify the reasons for site lock.
BTS/RBS hardware (both indoor & outdoor), node B (in 3G Networks),
Module VII
Practice

Concept on TRX, PA, Combiner, Multiplexer, Antenna, Control function, &Baseband


receiver unit (BBxx).

Text book:

1. “Telecom Tower Maintenance” Vol. 1, Navkar Center for Skills, 2014.

Session plan
No. of Sessions (in hrs.) No. of Activity Assignment Suggested
Sessions (in Reading
hrs.)

Module-I [4hrs. Practice]


Introduction to wire and 2
wireless communications,
Structure of mobile
communication, TB CH-1
Modulation-Analog & Practice Assignment No-1.1
Digital, Multiple access
methods, Cellular concept
(GSM/CDMA/LTE)

Basic concept on mains 2


(AC), DG, Battery bank,
TB CH-1
Solar supply system to a cell Practice Assignment No-1.2
site, (ACME PIU,TT-LAB ,
SOLAR LAB)

Module-II [2hrs. Practice]

Check leakage, rattles, 3 TB CH-1


Practice Assignment No-1.3
shakes and electrical safety

P a g e | 61
at the tower site. (EXPT. ON
SITE VISIT)

Module-III [8hrs. Practice]


PIU indoor & outdoor; 3
Block diagram & working TB CH-1
Principle of PIU, Practice Assignment No-1.4
Components of PIU(ACME
PIU,TT-LAB)
Physical wiring diagram, 2
Power flow of PIU, Function TB CH-1
Practice Assignment No-1.5
test of PIU (ACME PIU,TT-
LAB)
Fault finding within PIU, 3 TB CH-1
Different alarms process in Practice Assignment No-1.6
PIU (TT-LAB)
Module-IV [7hrs. Practice]

Assembling process demo to 2 TB CH-1


Practice Assignment No-1.7
make a PIU. (TT-LAB)
3
Line Conditioning Unit
(LCU); Working Principle
of LCU, Components of Practice
Assignment No-1.8
LCU, Physical wiring
diagram, Power flow of
LCU(TT-LAB)
Function test of LCU, Fault 2 TB CH-1
finding within LCU. (TT- Practice Assignment No-1.9
LAB)
Module-V [5hrs. Practice]

Central Processing Unit 3


(CPU); Working principle of TB CH-1
PIU, Components, current Practice Assignment No-2.0
flow and fault finding of
PIU. (TT-LAB)
Free Cooling Unit (FCU); 2
Working Principle of FCU, TB CH-1
Practice Assignment No-2.1
Components and fault
finding of FCU. (TT-LAB)
Module-VI [5hrs. Practice]
Adhere and Ensure PM 2
activities plan at the tower TB CH-1
site, conduct & fill the site Practice Assignment No-2.2
PM, Perform unique site
down PM,
Operational maintenance of 2
the site; Basic functioning of TB CH-1
Practice Assignment No-2.3
alarm box and the interface,
,(EXPT. ON SITE VISIT)

P a g e | 62
check and rectify number of 2
alarms active at the site-PIU, TB CH-1
Practice Assignment No-2.4
identify the reasons for site
lock. (TT-LAB)
Module-VII [5hrs. Practice]

Make Task Reporting on 2 TB CH-1


AC, DG, PIU, SMPS, Practice Assignment No-2.5
Battery Bank and Shelter.
BTS/RBS hardware (both 3
indoor & outdoor), node
B (in 3G Networks), concep
t on TRX, PA, Combiner, TB CH-1
Multiplexer, Antenna, Practice Assignment No-2.6
Control function,
&Baseband receiver unit
(BBxx). ,(EXPT. ON SITE
VISIT)
Total hr 60 hrs

P a g e | 63
RF Planning and Drive Test

Course Title Code Type of course T-P-P Prerequisite


RF Planning and DECS0202 Practice 0-2-0 0-4-0
Drive Test

Objective
 To teach how to improve, optimize and maintain network performances ,explains
network possible problems based on the Radio, BSS and the core network side, give
basic idea of signal strength and conversant with LTE networks

Learning Outcome
 Students will gain knowledge of RF Planning at cell site and measure the signal
strength, conversant with LTE networks and drive test tools.
 Students will develop skill on GSM RF Planning tool, Use of mapping software’s like
Map info/Google KLM, drive test tool TEMS for 3G,4G optimization with field
exposure and NEMO Tool for 4G LTE optimization with field exposure.

CONTENT:

Module I
Practice
RF Planning

RF Propagation path loss, different industry used propagation models ,GSM RF Planning
Tool, RF link budget, GSM RF Planning Tool practicing: RF Survey.

Module II
Practice
Frequency hopping and Planning

Different types of frequency hopping, Frequency Planning, Coverage Planning, and Reports
& Analysis. Fundamentals of Handover and power controlling in GSM.

Module III
Practice
RF Optimization

Use of mapping software’s like Map info/Google KLM, use of wireless network coverage
optimization using drive test tool TEMS, Pre optimization Site Audit.GSM RF Optimization
&Study of drive key RF parameters.

Module IV
Practice
GSM RF Drive Test

GSM RF Drive Test Tool – TEMS, Overview, Drive test practice using TEMS, RF
Optimization and Post Processing Tools.Layer 3 message interpretation.

P a g e | 64
Module V
Practice
3G Optimization

Introduction to 3G networks, 3G Network Architecture, WCDMA Concepts, WCDMA


Drive test and optimization.IRAT Handover.3G Drive KPI analysis. Network Performance
indicator analysis.

Module VI
Practice
EMF Radiation Calculation and testing: Introduction of EMF radiation Hazard,
Calculation of EMF radiation based on field survey. Broad band testing for Site EMF
radiation test using ARONIA/NARDA test kit.

Module VII
Practice
4G Optimization

LTE network theory-MIMO, Drive test of LTE network using NEMO, LTE Propagation
model( cost 231, Okumura Hata model, space propagation model) and Propagation loss
analysis, Parameter analysis of LTE Networks.

Text-Book:
1. Advanced cellular network planning and optimization 2G/2.5G/3G. . .evolution to 4G
, Author: Ajay R Mishra, Nokia Networks, John Wiley & Sons Ltd, The Atrium,
Southern Gate, Chichester, West Sussex PO19 8SQ, England

Reference Books:

1. Radio Network Planning and Optimisation for UMTS,SecondEdition,JaanaLaiho and


AchimWacker, Nokia Group, Finland, Toma´ sˇ Novosad,,Nokia Networks, Nokia
Group, USA, John Wiley & Sons Ltd, The Atrium, Southern Gate, Chichester, West
Sussex PO19 8SQ, England
2. Material: E1-E2 Upgradation Course –Consumer Mobility, RF Planning and Drive Test
3. Material: GTL ,RF Optimisation

Session Plan

Topics No of Activity Assignment Suggested Reading


Sessions
(in hrs.)
Module-I[RF Planning]

RF Propagation path loss, 2 Practice Assignment TB CH-1


different industry used No-1.1
propagation models.

GSM RF Planning Tool Assignment


3 Practice TB CH-1
No-1.2

P a g e | 65
RF link budget 2 Assignment
Practice TB CH-1
No-1.3
GSM RF Planning Tool
Assignment
practicing: RF Survey 3 Practice TB CH-1
No-1.4
Module-II [Frequency hopping and Planning]

Different types of frequency


hopping, Frequency Planning, Assignment
2 Practice TB CH-1
Coverage Planning, and No-1.5
Reports & Analysis
Fundamentals of Handover
and power controlling in GSM. Assignment
2 Practice TB CH-1
No-1.6

Module-III [RF Optimization]

Use of mapping softwares like TB CH-1


Map info/Google KLM, use of
Assignment
wireless network coverage 6 Practice
No-1.7
optimization using drive test
tool TEMS
Module-IV [GSM RF Drive Test]

GSM RF Drive Test Tool – TB CH-1


TEMS, Overview, Drive test
practice using TEMS, RF Assignment
6 Practice
No-1.8
Optimization and Post
Processing Tools.
Layer3 message interpretation. TB CH-1
Assignment
2 Practice
No-1.9

Module-V [3G Optimization]

TB CH-1
Assignment
Introduction to 3G networks,
2 Practice No-2.0
3G Network Architecture
WCDMA Concepts ,WCDMA TB CH-1
Drive test and optimization. Assignment
2 Practice
Network No-2.1

IRAT Handover.3G Drive KPI Assignment TB CH-1


2 Practice
analysis. No-2.2
Performance indicator TB CH-1
Assignment
analysis.. 2 Practice
No-2.3
Module-VI [EMF Radiation Calculation and testing]
Introduction of EMF radiation Assignment TB CH-1
2 Practice
Hazard, No-2.4

P a g e | 66
Calculation of EMF radiation Assignment TB CH-1
2 Practice
based on field survey. No-2.5
Broad band testing for Site TB CH-1
EMF radiation test using Assignment
4 Practice
ARONIA/NARDA test kit. No-2.6

Module-VII [4G Optimization]

LTE network theory-MIMO 2 Assignment TB CH-1


Practice
No-2.7
Drive test of LTE network
Assignment
using NEMO. 4 Practice TB CH-1
No-2.8
Parameter analysis of LTE
Assignment
Networks. 4 Practice TB CH-1
No-2.9
Total
60

P a g e | 67
4G LTE & 5G Communications
Course Title Code Type of course T-P-P Prerequisite
4G LTE & 5G DECS0102 Theory 3-0-0 Nil
Communications

Objective
 To teach students familiar with fundamentals of 4G and 5G systems

Learning Outcome
 Students will gain knowledge of Cellular Communication, GSM mobile communication
standard & its architecture, logical channels, Advantages and limitations.
 Students will develop skill of communication standard, its architecture, logical channels,
advantages and Limitations, 4GLTE mobile standards and their comparison with 2G, 3G, 5G
technologies.

Evaluation Systems
Component % of Marks Method of Assessment

Internal Theory 30 Written examination


Internal Examination Report or Presentation +
Assignment 5
Learning Record
Attendance 5 Based on class attended

External Examination External Theory 60 Written examination

Total 100

Course Outline

Module I: (6 Hours)
Theory
Introduction to 4G, Why 4G?, spectrum regulation and standardization from 3G to 5G,
Frequency standard for 4G, 3GPP LTE,LTE Basic technology,

Module II: (8 Hours)


Theory
Transmission scheme, spectrum and bandwidth flexibility, LTE Evolution, Radio access
network interfaces, Radio protocol architecture, LTE- Radio link control, Time –Frequency
structure.

Module III: (6 Hours)


Theory
Modulation and demodulation scheme of LTE (QPSK and QAM Technology), BER Analysis
of LTE Video over Wireless: Video compression basics, Video coding standards.

P a g e | 68
Module IV: (6 Hours)
Theory
Content analysis for communication: Low level feature extraction, Image segmentation,
Video object segmentation.

Module V: Network planning, Frequency planning; (8 Hours)


Theory
Modes, TDD mode, FDD mode, FDD planning TDD planning concept, TDD bands.
Coverage planning.
Module VI: (8 Hours)

Theory
LTE Capacity planning; Capacity, aim of capacity planning, LTE Link budget; DL link
budget, UL link budget. LTE guard band analysis and Guard band requirements.

Module VII: Drivers for 5G (12 Hours)


Theory
5G Roadmap , 10 Pillars of 5G, Evolution of Existing RATs, Hyperdense Small‐Cell
Deployment, Self‐Organizing Network, Allocation of New Spectrum for 5G. The 5G
Internet: Introduction, Internet of Things and Context‐Awareness, Networking
Reconfiguration and Virtualization Support, Software Defined Networking, Network
Function Virtualization, Mobility.

Text-Book:

1. 4G, LTE-Advanced Pro and The Road to 5G,3rd Edition Authors: Erik Dahlman Stefan
Parkvall Johan Skold,Hardcover ISBN: 9780128045756.
2. 4G wireless video communications, Authors: HaohongWang,Lisimachos P. Kondi, Ajay
Luthra, Song Ci, A John Wiley and Sons, Ltd., Publication.
3. Fundamentals of 5G Mobile Networks Edited by Jonathan Rodriguez This edition first
published 2015 © 2015 John Wiley & Sons, Ltd.
Reference Books:

1. An Introduction To LTE, Lte-Advanced, Sae And 4G Mobile Communications,


Christopher Cox, Director, Chris Cox Communications Ltd, UK.
2. Understanding LTE with MATLAB, Author: Houman Zarrinkoub, A John Wiley and
Sons, Ltd., Publication

P a g e | 69
Session Plan

No.of Assignment
S. Suggested
Topics Sessions(in Activity
No. Reading
hrs.)
Module-I
Introduction to 4G, Why
4G?, spectrum regulation
TB CH-1
1 and standardization from 3G 3 Theory Assignment No-1.1
to 5G,

Frequency standard for 4G,


TB CH-1
2 3GPP LTE,LTE Basic 3 Theory Assignment No-1.2
technology,
Module-II
Transmission scheme,
spectrum and bandwidth
flexibility, LTE Evolution, TB CH-1
3 4 Theory Assignment No-1.3
Radio access network
interfaces,

Radio protocol architecture,


TB CH-1
4 LTE- Radio link control, 4 Theory Assignment No-1.4
Time –Frequency structure.
Module-III
Modulation and
demodulation scheme of TB CH-1
5 LTE (QPSK and QAM 3 Theory Assignment No-1.5
Technology), BER Analysis
of LTE
Video over Wireless:
TB CH-1
6 Video compression basics, 3 Theory Assignment No-1.6
Video coding standards.
Module-IV
Content analysis for TB CH-1
7 communication: Low level 3 Theory Assignment No-1.7
feature extraction
Image segmentation, Video TB CH-1
8 3 Theory Assignment No-1.8
object segmentation.
Module-V

P a g e | 70
Modes, TDD mode, FDD TB CH-1
9 mode, FDD planning 4 Theory Assignment No-1.9

TDD planning concept,


TB CH-1
10 TDD bands. Coverage 4 Theory Assignment No-2.0
planning.
Module-VI
LTE Capacity planning; TB CH-1
11 Capacity, aim of capacity 3 Theory Assignment No-2.1
planning,
LTE Link budget; DL link
TB CH-1
12 budget, UL link budget. 3 Theory Assignment No-2.2

LTE guard band analysis


TB CH-1
13 and Guard band 2 Theory Assignment No-2.3
requirements.

Module-VII
5G Roadmap , 10 Pillars of
TB CH-1
14 5G, Evolution of Existing 3 Theory Assignment No-2.4
RATs,

Hyperdense Small‐Cell
Deployment, Self‐
TB CH-1
15 Organizing Network, 3 Theory Assignment No-2.5
Allocation of New Spectrum
for 5G.

The 5G Internet:
Introduction, Internet of
Things and Context‐ 3 TB CH-1
16 Theory Assignment No-2.6
Awareness, Networking
Reconfiguration and
Virtualization Support,.
Software Defined
Networking, Network TB CH-1
17 3 Theory Assignment No-2.7
Function Virtualization,
Mobility

TOTAL 60 hrs

P a g e | 71
Digital Image Processing

Course Title Code Type of course T-P-Pr Prerequisite


Digital Image Processing DECS0403 Theory & Practice 2-1-0 Nil

Objective
 To teach image fundamentals and mathematical transforms necessary for image
processing, image enhancement techniques, image restoration procedures & image
compression procedures.
 To provide knowledge on basic image processing techniques
 To provide hand on experience of image processing techniques using MATLAB

Learning Outcome
 Students will gain knowledge of fundamental concepts of a digital image processing
System. Analyze images in the frequency domain using various transforms.
 Students will develop skill of Interpret Image compression standards, Interpret image
segmentation and representation techniques. Student will gain on image processing
technique and its implementation.

Evaluation Systems
Internal Component % of Marks Method of Assessment
Examination Internal Theory 20 Written examination
Internal Practice 30(20+10) Lab work + Learning Record
External External Theory 30 Written examination
Examination External Practice 20 Lab work
Total 100

Course Outline
Module I: DIGITAL IMAGES FUNDAMENTALS (8 Hours)

Theory
Introduction and Fundamentals , Motivation and Perspective, Applications, Components of
Image Processing System, Element of Visual Perception, A Simple Image Model, Sampling
and Quantization, Relationships between Pixels
Practice
1. Matrix and Array operation in MATLAB
2. Image read and writes operation
3. Reading an RGB Image and extract the color components
Module II: IMAGE ENHANCEMENT IN SPATIAL DOMAIN INTRODUCTION (9
Hours)

Theory
Basic Gray Level Functions: Piecewise-Linear Transformation Functions, Contrast
Stretching, Histogram Specification, Histogram Equalization, Local Enhancement,
Enhancement using Arithmetic/Logic Operations: Image Subtraction, Image Averaging;

P a g e | 72
Basics of Spatial Filtering; Smoothing - Mean filter, Ordered Statistic Filter; Sharpening -The
Laplacian.
Practice
4. Brightness and contrast enhancement of an image
5. Simulation of Image negative and Piecewise linear Transformation of an image
6. Arithmetic images between images and display the resulted image,
7. Image smoothing using different mask
Module III: IMAGE ENHANCEMENT IN FREQUENCY DOMAIN (9
Hours)

Theory
Fourier Transform and the Frequency Domain, Basis of Filtering in Frequency Domain,
Filters – Lowpass, High-pass; Correspondence Between Filtering in Spatial and Frequency
Domain; Smoothing Frequency Domain Filters – Gaussian Lowpass Filters; Sharpening
Frequency Domain Filters – Gaussian Highpass Filters; Homomorphic Filtering.
Practice
8. Simulation of image filtering
9. Sharpening of an Digital Image
Module IV: IMAGE RESTORATION (9 Hours)

Theory
A Model of Restoration Process, Noise Models, Restoration in the presence of Noise only-
Spatial Filtering, Mean Filters: Arithmetic Mean filter, Geometric Mean Filter, Order Statistic
Filters – Median Filter, Max and Min filters; Periodic Noise Reduction by Frequency Domain
Filtering – Bandpass Filters; Minimum Mean-square Error Restoration.
Practice
10. Image noising using different noise distribution
11. Image Denoising using Arithmatic mean and median filter
12. Simulation of different order statistics filter
Module V: MORPHOLOGICAL IMAGE PROCESSING (9 Hours)

Theory
Introduction to Morphological Image Processing, Logic Operations involving Binary Images,
Dilation and Erosion, Opening and Closing, Morphological Algorithms – Boundary
Extraction, Region Filling, Extraction of Connected Components, Convex Hull, Thinning,
Thickening
Practice
13. Dilation and erosion of an image
14. Opening and closing operation of an image
Module VI: IMAGE REGISTRATION (8 Hours)

Theory
Introduction, Geometric Transformation – Plane to Plane transformation, Mapping, Stereo
Imaging – Algorithms to Establish Correspondence, Algorithms to Recover Depth

P a g e | 73
Segmentation Introduction, Region Extraction, Pixel-Based Approach, Multi-level
Thresholding, Local Thresholding
Practice
15. Simulation Image transformation
16. Simulation of thereholding operation
Module VII: IMAGE SEGMENTATION (9 Hours)

Theory
Region-based Approach, Edge and Line Detection: Edge Detection, Edge Operators, Pattern
Fitting Approach, Edge Linking and Edge Following, Edge Elements Extraction by
Thresholding, Edge Detector Performance, Line Detection, Corner Detection
Practice
17. Edge detection using different mask and Canny edge detection
Text Books

1. Gonzalez, Rafael C., and Richard E. Woods, “Digital Image Processing” 2nd Edition,
Pearson Education, 2002
2. Schalkoff RJ, “Digital Image Processing and Computer Vision”, New York: Wiley 1989
3. Jain AK, “ Fundamentals of Digital Image Processing”, Englewood Cliffs, NJ: Prentice
Hall, 1989
4. Sonka M, Hlavac V, Boyle R. “Digital Image Processing and Computer Vision”, Cengage
Learning. 2008
5. Gonzalez RC, Woods RE, “Digital Image Processing Addison-Wesley. Reading”, Ma.
1992

Reference Book
Gonzalez, Rafael C., and Richard E. Woods, Steven L Eddins “Digital Image Processing
using MATLAB” , Pearson Education, 2009

Session Plan

No. of
Topic coverage and Internal Suggested
Sessions Activity Assignment
Test Reading
(in hrs.)

Module-I [6 hrs. Lecture + 2 hrs. Practice]


Introduction and Fundamentals , 3 Lecture Question Text Book-
Motivation and Perspective, 1.1-1.4 T1 Chapter
Applications, Components of 1.1-1.5
Image Processing System

Element of Visual Perception, A 3 Lecture Question Text Book-


Simple Image Model, Sampling 1.5-1.9 T1 Chapter

P a g e | 74
and Quantization, Relationships 2.1-2.5
between Pixels
Matrix and Array operation in 1 Practice Practice 1 Reference
MATLAB Book R1
Chapter 1
Image read and writes operation, 1 Practice Practice 2-3 Reference
Reading an RGB Image and Book R1
extract the color components Chapter 2

Module-II [6 hrs. Lecture + 3 hrs. Practice]


Basic Gray Level Functions: 3 Lecture Question Text Book-
Piecewise-Linear Transformation 2.1-2.4 T1 Chapter
Functions, Contrast Stretching, 3.1-2.3
Histogram Specification,
Histogram Equalization, Local
Enhancement
Enhancement using 1 Lecture Question Text Book-
Arithmetic/Logic Operations: 2.1 T1 Chapter
Image Subtraction, Image 3.4
Averaging
Basics of Spatial Filtering; 2 Lecture Question Text Book-
Smoothing - Mean filter, Ordered 2.6-2.8 T1 Chapter
Statistic Filter; Sharpening -The 3.5-3.7
Laplacian
Brightness and contrast 1 Lecture Practice 4 Reference
enhancement of an image Book R1
Chapter 3
Simulation of Image negative and 1 Practice Practice 5 Reference
Piecewise linear Transformation Book R1
of an image Chapter 3

Arithmatic images between 1 Practice Practice 6-7 Reference


images and display the resulted Book R1
image, Image smoothing using Chapter 3
mask

Module-III [7 hrs. Lecture + 2 hrs. Practice]


Fourier Transform and the 2 Lecture Question Text Book-
Frequency Domain, Basis of No- 3.1-3.2 T1 Chapter
Filtering in Frequency Domain, 4.1-4.2
Filters – Lowpass, High-pass;
Correspondence Between Filtering
in Spatial and Frequency Domain

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Smoothing Frequency Domain 2 Lecture Question Text Book-
Filters – Gaussian Lowpass Filters No- 3.3 T1 Chapter
4.3
Sharpening Frequency Domain 2 Lecture Question Text Book-
Filters – Gaussian Highpass No- 3.4 T1 Chapter
Filters 4.4
Homomorphic Filtering 1 Lecture Question Text Book-
No- 3.5 T1 Chapter
4.5
Simulation of image filtering 1 Practice Practice 8 Reference
Book R1
Chapter 4
Sharpening of an Digital Image 1 Practice Practice 9 Reference
Book R1
Chapter 4
Module-IV [6 hrs. Lecture + 2 hrs. Practice]
A Model of Restoration Process, 3 Lecture Question Text Book-
Noise Models, Restoration in the No- 4.1-4.4 T1 Chapter
presence of Noise only-Spatial 5.1-5.3
Filtering, Mean Filters: Arithmetic
Mean filter, Geometric Mean
Filter, Order Statistic Filters –
Median Filter, Max and Min
filters
Periodic Noise Reduction by 2 Lecture Question Text Book-
Frequency Domain Filtering – No- 4.5 T1 Chapter
Bandpass Filters 5.4
Minimum Mean-square Error 1 Lecture Question Text Book-
Restoration No- 4.6 T1 Chapter
5.8
Image noising using different 1 Practice Practice 10 Reference
noise distribution Book R1
Chapter 5
Image Denoising using Arithmatic 1 Practice Practice 11 Reference
mean and median filter Book R1
Chapter 5
Simulation of different order 1 Practice Practice 12 Reference
statistics filter Book R1
Chapter 5
Module-V [7 hrs. Lecture + 2 hrs. Practice]
Introduction to Morphological 2 Lecture Question Text Book-
Image Processing, Logic No-5.1 T1 Chapter
Operations involving Binary 9.1

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Images

Dilation and Erosion, Opening 2 Lecture Question Text Book-


and Closing No-5.2-5.3 T1 Chapter
9.2-9.3
Morphological Algorithms – 2 Lecture Question Text Book-
Boundary Extraction, Region No-5.4 T1 Chapter
Filling, Extraction of Connected 9.5
Components
Convex Hull, Thinning, 1 Lecture Question Text Book-
Thickening No-5.5 T1 Chapter
9.5
Dilation and erosion of an image 1 Practice Practice 13 Reference
Book R1
Chapter 9
Opening and closing operation of 1 Practice Practice 14 Reference
an image Book R1
Chapter 9
Module-VI [6hrs. Lecture + 2 hrs. Practice]
Introduction, Geometric 2 Lecture Question Text Book-
Transformation – Plane to Plane No-6.1 T1 Chapter
transformation, Mapping, Stereo 10.1
Imaging – Algorithms to Establish
Correspondence

Algorithms to Recover Depth 2 Lecture Question Text Book-


Segmentation Introduction, No-6.1 T1 Chapter
Region Extraction 10.2

Pixel-Based Approach, Multi- 2 Lecture Question Text Book-


level Thresholding, Local No-6.3-6.4 T1 Chapter
Thresholding 10.3
Simulation Image transformation 1 Practice Practice 15 Reference
Book R1
Chapter 10
Simulation of thereholding 1 Practice Practice 16 Reference
operation Book R1
Chapter 10
Module-VII [6 hrs. Lecture + 2 hrs. Practice]
Region-based Approach, Edge and 2 Lecture Question Text Book-
Line Detection: Edge Detection, No-7.1 T1 Chapter
Edge Operators, Pattern Fitting 10.1
Approach,

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Edge Linking and Edge Following 2 Lecture Question Text Book-
No-7.2 T1 Chapter
10.2
Edge Elements Extraction by 2 Lecture Question Text Book-
Thresholding, Edge Detector No-7.3-7.4 T1 Chapter
Performance, Line Detection, 10.3
Corner Detection
Edge detection using different 2 Practice Practice 17 Reference
mask and Canny edge detetion Book R1
Chapter 10
Total (hrs.) 60 44 hrs. Lecture
+ 16 hrs.
Practice

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Antenna Designs & Manufacturing

Course Title Course Code Type of Course T-P-Pr Prerequisite


Antenna designs & DECS0601 Practice + Project 0-2-2 Nil
Manufacturing

Objective
 To teach simulate, fabricate and validate the performance of various types of antennas

Learning Outcome
 Students will gain knowledge of antennas and analyze the radiation mechanism
 Students will develop skill of discriminate between antennas on the basis of their electrical
performance

Evaluation System
Internal Examination Component % of Marks Method of Assessment
Internal Practice 50(40+10) Lab Work + Learning Record
Internal Project 50 Project Work
External Examination External Practice 50 Lab Work
External Project 50 Project Work + Report
Total 200

Course Outline

Module I: INTRODUCTION TO ANTENNAS (13 Hours)


Practice
The Basics of Antennas, Wire Dipole and Monopole Antennas: Introduction, Infinitesimal,
Small, and Finite Length Dipole Antennas, Dipole Antenna Full-Wave Simulation, Monopole
Antennas and Full-Wave Simulations, Dipole Antennas and Wireless Power Transfer, Dipole
Antenna Above a PEC Ground Plane, Dipole Antenna Near a PEC Cylinder, Dipole Antenna
Near a PEC Sphere, Dipole Antenna Near a Dielectric Sphere Quasi Log-Periodic Dipole
Antennas.

Project

1. Dipole antenna design using HFSS/FEKO.


Module II: WIRE LOOP ANTENNAS ( 10 Hours)
Practice
Introduction, Small and Large Loop Antennas, Circular Loop Antennas Square Loop
Antennas, Triangular Loop Antennas, Loop Antennas near a PEC Scatterer.

Project

2. Design of loop antenna using HFSS/FEKO.

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Module III: MICROSTRIP PATCH ANTENNAS (6 Hours)
Practice
Introduction, Patch Antenna Design and Analysis, Full-Wave Simulation of Patch Antennas
in FEKO, Circularly Polarized Patch Antennas, Microstrip-Based Feeding Networks:
Introduction, Design of Microstrip Transmission Lines, The Quarter-Wavelength
Transformer, T-Junction Power Dividers, Wilkinson Power Dividers, The Quadrature Hybrid
Project

3. Microstrip patch antenna design using HFSS/FEKO.


Module IV: BROADBAND DIPOLE ANTENNAS (7 Hours)
Practice
Introduction, Cylindrical Dipole Antennas, Biconical Antennas, Folded Dipole Antennas,
Traveling Wave and Broadband Antennas : Introduction, Helical Antennas, Yagi-Uda
Antennas.
Project
4. Design of ultra wide band (UWB) antenna using HFSS/FEKO
Module V: FREQUENCY-INDEPENDENT ANTENNAS (6 Hours)
Practice
Introduction, Spiral Antennas, Log-Periodic Antennas .

Project

5. Design of frequency independent antenna using HFSS/FEKO.


Module VI: HORN ANTENNAS (8 Hours)
Practice
Introduction, Sectoral Horn Antennas, Pyramidal Horn Antennas, Conical Horn Antennas , A
Multimode Horn Antenna: The Potter Horn , Corrugated Conical Horn Antenna.

Project
6. Design of horn antenna using HFSS/FEKO.
Module VII: REFLECTOR ANTENNAS (12 Hours)
Practice
Introduction, Corner Reflector Antennas, Design and Analysis of Parabolic Reflector
Antennas, Design and Analysis of Spherical Reflector Antennas.
Project
7. Design of reflector antenna using HFSS/FEKO
Text Books
1. Z. Elsherbeni Payam Nayeri ,C. J. Reddy , Antenna Analysis and Design Using FEKO
Electromagnetic Simulation Software, Atef EM Software & Systems (USA), Inc. Edison,
NJ theiet.org.
2. C Balanis, Antenna Theory – Analysis and Design by 2ndEdition, John Willey & Sons.
References
Online Resources
1. https://nptel.ac.in/syllabus/108101092/ [Viewed on 21.06.2019]

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Session Plan

Topics No. of Activity Assignment Suggested


Sessions Reading
(in hrs.)

Module-I INTRODUCTION TO ANTENNAS (13 Hours)


The Basics of Antennas 1 Lecture Assignment 1.1 Text Book-1
Chapter 2.1

Infinitesimal, Small, and Finite 3 1 hr. Lecture + Assignment 1.2 Text Book-1
Length Dipole Antennas, Dipole 2 hrs. Practice Chapter 2.2
Antenna Full-Wave Simulation
Monopole Antennas and Full- 3 1hr. Lecture + Assignment 1.3 Text Book-1
Wave Simulations 2 hrs. Practice Chapter 2.4

Dipole Antennas and Wireless 1 Lecture Assignment 1.4 Text Book-1


Power Transfer, Dipole Antenna Chapter 2.5-2.6
Above a PEC Ground Plane
Dipole Antenna Near a PEC 4 2 hrs. Lecture Assignment 1.5 Text Book-1
Cylinder, Dipole Antenna Near a + 2 hrs. Chapter 2.7-2.8
PEC Sphere. Practice
Dipole Antenna Near a 1 Lecture Assignment 1.6 Chapter 2.8-2.10
Dielectric Sphere, Quasi Log-
Periodic Dipole Antennas.

Module-II WIRE LOOP ANTENNAS (10 Hours)


Introduction, Small and Large 3 1hr. Lecture + Assignment 2.1 Text Book-1
Loop Antennas 2 hrs. Practice Chapter 3.1-3.2

Circular Loop Antennas, Square 3 1hr. Lecture + Assignment 2.2 Text Book-1
Loop Antennas 2 hrs. Practice Chapter 3.3-3.4

Triangular Loop Antennas 3 1hr. Lecture + Assignment 2.3 Text Book-1


2 hrs. Practice Chapter 3.5

Loop Antennas near a PEC 1 Lecture Assignment 2.4 Text Book-1


Scatterer Chapter 3.6
Design of loop antenna using Project Published journal
HFSS/FEKO.

Module III MICROSTRIP PATCH ANTENNAS (9 Hours)

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Introduction, Patch Antenna 1 Lecture Assignment 3.1 Text Book-1
Design and Analysis Chapter 4.1-4.2

Full-Wave Simulation of Patch 2 2 hrs. Practice Assignment 3.2 Text Book-1


Antennas in FEKO Chapter 4.3
Circularly Polarized Patch 2 2 hrs. Practice Assignment 3.3 Text Book-1
Antennas Chapter 4.4
Microstrip-Based Feeding 2 2 hrs. Practice Text Book-1
Networks :Introduction, Design Chapter 5.1-5.3
of Microstrip Transmission
Lines, The Quarter-Wavelength
Transformer
T-Junction Power Dividers, 2 2 hrs. Practice Text Book-1
Wilkinson Power Dividers , The Chapter 5.4-5.5
Quadrature Hybrid .

Module IV BROADBAND DIPOLE ANTENNAS (8 Hours)


Introduction, Cylindrical Dipole 2 2 hrs. Practice Assignment 4.1 Text Book-1
Antennas Chapter 6.1-6.2
Biconical Antennas, Folded 3 1hr. Lecture + Assignment 4.2 Text Book-1
Dipole Antennas 2 hrs. Practice Chapter 6.3-6.4
Traveling Wave and Broadband 3 1hr. Lecture + Text Book-1
Antennas: Introduction, Helical 2 hrs. Practice Chapter 7.1-7.3
Antennas, Yagi-Uda Antennas.
Design of ultra wide band Project
(UWB) antenna using
HFSS/FEKO

Module V FREQUENCY-INDEPENDENT ANTENNAS (7 Hours)


Introduction of frequency 1 Lecture Assignment 5.1 Text Book-1
independent antenna Chapter 8.1
Spiral Antennas 3 1hr. Lecture + Assignment 5.2 Text Book-1
2 hrs. Practice Chapter 8.2
Log-Periodic Antennas 3 1hr. Lecture + Assignment 5.3 Text Book-1
2 hrs. Practice Chapter 8.3
Design of frequency independent Project
antenna using HFSS/FEKO.

Module VI BROADBAND DIPOLE ANTENNAS (6 Hours)


Introduction of horn antenna 1 Lecture Assignment 6.1 Text Book-1
Chapter 9.1
Sectoral Horn Antennas 2 2 hrs. Practice Assignment 6.2 Text Book-1
Chapter 9.2
Pyramidal Horn Antennas 1 2 hrs. Practice Assignment 6.3 Text Book-1

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Chapter 9.3
Conical Horn Antennas 1 2 hrs. Practice Assignment 6.4 Text Book-1
Chapter 9.4
A Multimode Horn Antenna: 1 2 hrs. Practice Assignment 6.5 Text Book-1
The Potter Horn , Corrugated Chapter 9.5
Conical Horn Antenna.

Design of horn antenna using Project


HFSS/FEKO.

Module VII REFLECTOR ANTENNAS (7 Hours)


Introduction of reflector antenna 1 Lecture Assignment 7.1 Text Book-1
Chapter 10.1
Corner Reflector Antennas 1 Lecture Assignment 7.2 Text Book-1
Chapter 10.2
Design and Analysis of Parabolic 3 1hr. Lecture + Assignment 7.3 Text Book-1
Reflector Antennas 2 hrs. Practice Chapter 10.3
Design and Analysis of Spherical 2 2 hrs. Practice Assignment 7.4 Text Book-1
Reflector Antennas. Chapter 10.4
Design of reflector antenna using Project
HFSS/FEKO.
Total (hrs.) 60

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