An Introduction to 8085

Microprocessor

PREPARED BY NIKUNJ TAHILRAMANI

Intel 8085
Block diagram of microprocessor

Microprocessor
INPUT As OUTPUT
CPU

MEMORY
 Operation Types in a Microprocessor
• All of the operations of the microprocessor
can be classified into one of three types:
- Microprocessor Initiated Operations
- Internal Operations
- Peripheral Initiated Operations

4
 Microprocessor Initiated Operations
• These are operations that the microprocessor
itself starts.
• These are usually one of 4 operations:
– Memory Read
– Memory Write
– I/O Read (Get data from an input device)
– I/O write (Send data to an output device)

5
 Microprocessor Initiated Operations
• It is important to note that the microprocessor treats
memory and I/O devices the same way.
– Input and output devices simply look like memory
locations to the microprocessor.
• For example, the keyboard may look like memory address A3F2H.
To get what key is being pressed, the microprocessor simply reads
the data at location A3F2H.

– The communication process between the microprocessor

and peripheral devices consist of the following three steps:
– Identify the address.
– Transfer the binary information.
– Provide the right timing signals.

6
 The Read Operation
– To read the contents of a memory location, the
following steps take place:
• The microprocessor places the 16-bit address of the
memory location on the address bus.
• The microprocessor activates a control signal called
“memory read” which enables the memory chip.
• The memory decodes the address and identifies the
right location.
• The memory places the contents on the data bus.
• The microprocessor reads the value of the data bus
after a certain amount of time.

7
 Internal Data Operations
• The 8085 can perform a number of internal
operations. Such as: storing data, Arithmetic &
Logic operations, Testing for condition, etc.
– To perform these operations, the microprocessor
needs an internal architecture similar to the
following:
Accumulator Flags
B C
D E
H L
Program Counter
Stack Pointer

Address 16 8 Data
8
Register Set
 Arithmetic and Logical group

Flag Register is given by:

S Z X AC X P X CY
S:Sign flag is set when result of an operation is negative.
Z:Zero flag is set when result of an operation is 0.
Ac:Auxiliary carry flag is set when there is a carry out of lower
nibble or lower four bits of the operation.
CY:Carry flag is set when there is carry generated by an
operation.
P:Parity flag is set when result contains even number of 1’s.
Rest are don’t care flip flops.
 The Internal Architecture
• We have already discussed the general purpose
registers, the Accumulator, and the flags.

• The Program Counter (PC)

– This is a register that is used to control the sequencing
of the execution of instructions.
– This register always holds the address of the next
instruction.
– Since it holds an address, it must be 16 bits wide.

11
 The Internal Architecture
• The Stack pointer
– The stack pointer is also a 16-bit register that is
used to point into memory.
– The memory this register points to is a special
area called the stack.
– The stack is an area of memory used to hold data
that will be retreived soon.
– The stack is usually accessed in a Last In First Out
(LIFO) fashion.

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 Externally Initiated Operations
• External devices can initiate (start) one of the 4
following operations:
– Reset
• All operations are stopped and the program counter is reset
to 0000.
– Interrupt
• The microprocessor’s operations are interrupted and the
microprocessor executes what is called a “service routine”.
• This routine “handles” the interrupt, (perform the necessary
operations). Then the microprocessor returns to its previous
operations and continues.

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 Externally Initiated Operations
– Ready
• The 8085 has a pin called RDY. This pin is used by external
devices to stop the 8085 until they catch up.
• As long as the RDY pin is low, the 8085 will be in a wait state.
– Hold
• The 8085 has a pin called HOLD. This pin is used by external
devices to gain control of the busses.
• When the HOLD signal is activated by an external device, the
8085 stops executing instructions and stops using the
busses.
• This would allow external devices to control the information
on the busses. Example DMA.

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 The Design and Operation of Memory
• Memory in a microprocessor system is where
information (data and instructions) is kept. It can be
classified into two main types:
• Main memory (RAM and ROM)
• Storage memory (Disks , CD ROMs, etc.)

– The simple view of RAM is that it is made up of registers

that are made up of flip-flops (or memory elements).
• The number of flip-flops in a “memory register” determines the
size of the memory word.
– ROM on the other hand uses diodes instead of the flip-
flops to permanently hold the information.

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 Accessing Information in Memory
• For the microprocessor to access (Read or
Write) information in memory (RAM or ROM),
it needs to do the following:
– Select the right memory chip (using part of the
address bus).
– Identify the memory location (using the rest of the
address bus).
– Access the data (using the data bus).

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 Tri-State Buffers
• An important circuit element that is used
extensively in memory.
• This buffer is a logic circuit that has three
states:
– Logic 0, logic1, and high impedance.
– When this circuit is in high impedance mode it
looks as if it is disconnected from the output
completely.

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 The Tri-State Buffer
• This circuit has two inputs and one output.
– The first input behaves like the normal input for
the circuit.
– The second input is an “enable”.
• If it is set high, the output follows the proper circuit
behavior.
• If it is set low, the output looks like a wire connected to
nothing.
Input Output OR Input Output

Enabe Enable

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 The Basic Memory Element
• The basic memory element is similar to a D
latch.
• This latch has an input where the data comes
in. It has an enable input and an output on
which data comes out.
Data Input Data Output
D Q

Enable
EN

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 The Basic Memory Element
• However, this is not safe.
– Data is always present on the input and the
output is always set to the contents of the latch.
– To avoid this, tri-state buffers are added at the
input and output of the latch.
Data Input Data Output
D Q

WR RD
Enable
EN

20
 The Basic Memory Element
• The WR signal controls the input buffer.
– The bar over WR means that this is an active low
signal.
– So, if WR is 0 the input data reaches the latch
input.
– If WR is 1 the input of the latch looks like a wire
connected to nothing.
• The RD signal controls the output in a similar
manner.
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 A Memory “Register”
• If we take four of these latches and connect
them together, we would have a 4-bit memory
register
I0 I1 I2 I3

WR
D D D D
Q Q Q Q
EN EN EN EN
EN

RD O0 O1 O2 O3

22
 A group of Memory Registers
– If we represent each memory location (Register)
as a block we get the following
I I I I
0 1 2 3
WR Input Buffers

EN0 Memory Reg. 0

EN1 Memory Reg. 1

EN2 Memory Reg. 2

EN3 Memory Reg. 3

RD Output Buffers

O O1 O2 O3
0

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 8085 INTRODUCTION

The features of INTEL 8085 are :

• It is an 8 bit processor.
• It is a single chip N-MOS device with 40 pins.
• It has multiplexed address and data bus.(AD0-AD7).
• It works on 5 Volt dc power supply.
• The maximum clock frequency is 3 MHz while
minimum frequency is 500kHz.
• It provides 74 instructions with 5 different addressing
modes.
 8085 INTRODUCTION
• It provides 16 address lines so it can access 2^16 =64K bytes
of memory.
• It generates 8 bit I/O address so it can access 2^8=256 input
ports.
• It provides 5 hardware interrupts:TRAP, RST 5.5, RST 6.5, RST
7.5,INTR.
• It provides Acc ,one flag register ,6 general purpose registers
and two special purpose registers(SP,PC).
• It provides serial lines SID ,SOD.So serial peripherals can be
interfaced with 8085 directly.
Intel 8085 Pin
Configuration

26
Signals and I/O Pins
27
 8085 PIN DESCRIPTION

Some important pins are :

• AD0-AD7: Multiplexed Address and data lines.
• A8-A15: Tri-stated higher order address lines.
• ALE: Address latch enable is an output signal.It goes high
when operation is started by processor .
• S0,S1: These are the status signals used to indicate type of
operation.
• RD¯: Read is active low input signal used to read data from I/O
device or memory.
• WR¯:Write is an active low output signal used write data on
memory or an I/O device.
 8085 PIN DESCRIPTION

 READY:This an output signal used to check the status of

output device.If it is low, µP will WAIT until it is high.
 TRAP:It is an Edge triggered highest priority , non mask
able interrupt. After TRAP, restart occurs and execution
starts from address 0024H.
 RST5.5,6.5,7.5:These are maskable interrupts and have
low priority than TRAP.
 INTR¯&INTA:INTR is a interrupt request signal after which
µP generates INTA or interrupt acknowledge signal.
 IO/M¯:This is output pin or signal used to indicate
whether 8085 is working in I/O mode(IO/M¯=1) or
Memory mode(IO/M¯=0 ).
 8085 PIN DESCRIPTION
 HOLD&HLDA:HOLD is an input signal .When µP receives HOLD
signal it completes current machine cycle and stops executing
next instruction.In response to HOLD µP generates HLDA that
is HOLD Acknowledge signal.
 RESET IN¯:This is input signal.When RESET IN¯ is low µp
restarts and starts executing from location 0000H.
 SID: Serial input data is input pin used to accept serial 1 bit
data .
 X1X2 :These are clock input signals and are connected to
external LC,or RC circuit.These are divide by two so if 6 MHz is
connected to X1X2, the operating frequency becomes 3 MHz.
 VCC&VSS:Power supply VCC=+ -5Volt& VSS=-GND reference.
Control and Status Signals.

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Generation of control signal
 Interrupt Signals
• 8085 μp has several interrupt signals as shown in the following
table.

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 Interrupt signals

• INTR input is enabled when EI instruction is

executed.
• The status of the RST 7.5, RST 6.5 and RST 5.5
pins are determined by both EI instruction
and the condition of the mask bits in the
interrupt mask register.

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 Interrupt signals

• An interrupt is a hardware-initiated subroutine CALL.

• When interrupt pin is activated, an ISR will be called,
interrupting the program that is currently executing.

Pin Subroutine Location

TRAP 0024
RST 5.5 002C
RST 6.5 0034
RST 7.5 003C
INTR *
Note: * the address of the ISR is determined by the external hardware.
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 RESET signal

• Following are the two kind of RESET signals:

– RESET IN: an active low input signal, Program
Counter (PC) will be set to 0 and thus MPU will
reset.
– RESET OUT: an output reset signal to indicate that
the μp was reset (i.e. RESET IN=0). It also used to
reset external devices.

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 The 8085 and Its Buses
• The 8085 is an 8-bit general purpose microprocessor that can address 64K
Byte of memory.
• It has 40 pins and uses +5V for power. It can run at a maximum frequency
of 3 MHz.
– The pins on the chip can be grouped into 6 groups:
• Address Bus.
• Data Bus.
• Control and Status Signals.
• Power supply and frequency.
• Externally Initiated Signals.
• Serial I/O ports.
 The Address and Data Bus Systems
• The address bus has 8 signal lines A8 – A15 which are unidirectional.
• The other 8 address bits are multiplexed (time shared) with the 8 data
bits.
– So, the bits AD0 – AD7 are bi-directional and serve as A0 – A7 and D0 –
D7 at the same time.
• During the execution of the instruction, these lines carry the
address bits during the early part, then during the late parts of the
execution, they carry the 8 data bits.
– In order to separate the address from the data, we can use a latch to
save the value before the function of the bits changes.
 The Control and Status Signals
• There are 4 main control and status signals. These are:
• ALE: Address Latch Enable. This signal is a pulse that become 1
when the AD0 – AD7 lines have an address on them. It becomes 0
after that. This signal can be used to enable a latch to save the
address bits from the AD lines.
• RD: Read. Active low.
• WR: Write. Active low.
• IO/M: This signal specifies whether the operation is a memory
operation (IO/M=0) or an I/O operation (IO/M=1).
• S1 and S0 : Status signals to specify the kind of operation being
performed. Usually not used in small systems.
 Frequency Control Signals
• There are 3 important pins in the frequency control group.
– X0 and X1 are the inputs from the crystal or clock generating circuit.
• The frequency is internally divided by 2.
– So, to run the microprocessor at 3 MHz, a clock running at 6
MHz should be connected to the X0 and X1 pins.

– CLK (OUT): An output clock pin to drive the clock of the rest of the
system.

• We will discuss the rest of the control signals as we get to them.

A closer look at the 8085 Architecture

• Now, let’s look at some of its features with

more details.
 The ALU
• In addition to the arithmetic & logic circuits, the ALU includes
an accumulator, which is a part of every arithmetic & logic
operation.

• Also, the ALU includes a temporary register used for holding

data temporarily during the execution of the operation. This
temporary register is not accessible by the programmer.
More on the 8085 machine cycles

• The 8085 executes several types of instructions with

each requiring a different number of operations of
different types. However, the operations can be
grouped into a small set.
• The three main types are:
• Memory Read and Write.
• I/O Read and Write.
• Request Acknowledge.
• These can be further divided into various smaller
operations (machine cycles).
 Opcode Fetch Machine Cycle
• The first step of executing any instruction is the Opcode fetch cycle.
– In this cycle, the microprocessor brings in the instruction’s Opcode
from memory.
• To differentiate this machine cycle from the very similar “memory
read” cycle, the control & status signals are set as follows:
– IO/M=0, s0 and s1 are both 1.
– This machine cycle has four T-states.
• The 8085 uses the first 3 T-states to fetch the opcode.
• T4 is used to decode and execute it.
– It is also possible for an instruction to have 6 T-states in an opcode
fetch machine cycle.
 Memory Read Machine Cycle
• The memory read machine cycle is exactly the
same as the opcode fetch except:
– It only has 3 T-states
– The s0 signal is set to 0 instead.
 The Memory Read Machine Cycle
– To understand the memory read machine cycle, let’s study
3E
the execution of the following instruction:
2000H

• MVI A, 32 32
2001H

– In memory, this instruction looks like:

• The first byte 3EH represents the opcode for loading a
byte into the accumulator (MVI A), the second byte is the
data to be loaded.
– The 8085 needs to read these two bytes from memory before
it can execute the instruction. Therefore, it will need at least
two machine cycles.
– The first machine cycle is the opcode fetch discussed
earlier.
– The second machine cycle is the Memory Read Cycle.
 Machine Cycles vs. Number of bytes
in the instruction
• Machine cycles and instruction length, do not have a direct
relationship.
– To illustrate, let’s look at the machine cycles needed to execute
the following instruction.
• STA 2065H 32H 2010H

• This is a 3-byte instruction requiring 4 machine 65H 2011H

cycles and 13 T-states. 20H 2012H

• The machine code will be stored

in memory as shown to the right
• This instruction requires the following 4 machine cycles:
– A ‘Opcode fetch’ to fetch the opcode (32H) from location 2010H, ‘decode’ it and
determine that 2 more bytes are needed (4 T-states).
– A ‘Memory read’ to read the low order byte of the address (65H) (3 T-states).
– A ‘Memory read’ to read the high order byte of the address (20H) (3 T-states).
– A ‘memory write’ to write the contents of the accumulator into the memory
location.
 The Memory Write Operation
• In a memory write operation:
– The 8085 places the address (2065H) on the address bus
– Identifies the operation as a ‘memory write’ (IO/M=0,
s1=0, s0=1).
– Places the contents of the accumulator on the data bus
and asserts the signal WR.
– During the last T-state, the contents of the data bus are
saved into the memory location.
 Memory interfacing
• There needs to be a lot of interaction between the
microprocessor and the memory for the exchange of
information during program execution.
– Memory has its requirements on control signals and their
timing.
– The microprocessor has its requirements as well.

• The interfacing operation is simply the matching of these

requirements.
 MPU Communication and Bus Timing

Figure 3: Moving data form memory to MPU using instruction MOV C, A

(code machine 4FH = 0100 1111) 50
 MPU Communication and Bus Timing

Figure 4: 8085 timing diagram for Opcode

51 fetch cycle for MOV C, A .
 MPU Communication and Bus Timing

• The Fetch Execute Sequence :

1. The μp placed a 16 bit memory address from PC
(program counter) to address bus.
– Figure 4: at T1
– The high order address, 20H, is placed at A15 – A8.
– the low order address, 05H, is placed at AD7 - AD0 and ALE is
active high.
– Synchronously the IO/M is in active low condition to show it is a
memory operation.
2. At T2 the active low control signal, RD, is activated so
as to activate read operation; it is to indicate that the
MPU is in fetch mode operation.
52
MPU Communication and Bus Timing

3. T3: The active low RD signal enabled the

byte instruction, 4FH, to be placed on AD7 –
AD0 and transferred to the MPU. While RD
high, the data bus will be in high impedance
mode.
4. T4: The machine code, 4FH, will then be
decoded in instruction decoder. The
content of accumulator (A) will then copied
into C register at time state, T4.
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 Detailed Look At 8085 Architecture

Intel 8085 CPU Block Diagram

55
 Arithmetic and Logical group

Accumulator: It is 8 bit general purpose register.

• It is connected to ALU.
• So most of the operations are done in Acc.
Temporary register: It is not available for user
• All the arithmetic and logical operations are done in the
temporary register but user can’t access it.
Flag: It is a group of 5 flip flops used to know status of various
operations done.
• The Flag Register along with Accumulator is called PSW
or Program Status Word.
 Register Group
• Temporary registers (W,Z):These are not available for user.
These are loaded only when there is an operation being
performed.
• General purpose:There are six general purpose registers in
8085 namely B,C,D,E,H,L.These are used for various data
manipulations.
• Special purpose :There are two special purpose registers in
8085:
1. SP :Stack Pointer.
2. PC:Program Counter.
 Register Group

Stack Pointer: This is a temporary storage memory 16 bit register.

Since there are only 6 general purpose registers, there is a need
to reuse them .
• Whenever stack is to be used previous values are PUSHED on
stack and then after the program is over these values are
POPED back.
Program Counter: It is 16 bit register used to point the location
from which the next instruction is to be fetched.
• When a single byte instruction is executed PC is automatically
incremented by 1.
• Upon reset PC contents are set to 0000H and next instruction is
fetched onwards.
 INSTRUCTION REGISTER,DECODER &
CONTROL

• Instruction register:When an instruction is fetched , it is

executed in instruction register.This register takes the
Opcode value only.
• Instruction decoder: It decodes the instruction from
instruction register and then to control block.
• Timing and control:This is the control section of µP.It
accepts clock input .
 INTERRUPT CONTROL
• It accepts different interrupts like TRAP INT5.5,6.5,7.5and
INTR.

SERIAL IO CONTROL
GROUP
• It is used to accept the serial 1 bit data by
using SID and SOD signals and it can be
performed by using SIM & RIM
instructions.
 TIMING AND STATE DIAGRAM

• The µP operates with reference to clock signal.The rise and

fall of the pulse of the clock gives one clock cycle.
• Each clock cycle is called a T state and a collection of several T
states gives a machine cycle.
• Important machine cycles are :
1. Op-code fetch.
2. Memory read.
3. Memory write.
4. I/Op-read.
5. I/O write.
 TIMING AND STATE DIAGRAM
Op-code Fetch:It basically requires 4 T states from T1-T4
• The ALE pin goes high at first T state always.
• AD0-AD7 are used to fetch OP-code and store the lower byte
of Program Counter.
• A8-A15 store the higher byte of the Program Counter while
IO/M¯ will be low since it is memory related operation.
• RD¯ will only be low at the Op-code fetching time.
• WR¯ will be at HIGH level since no write operation is done.
• S0=1,S1=1 for Op-code fetch cycle.
 TIMING AND STATE DIAGRAM

Memory Read Cycle: It basically requires 3T states from T1-T3 .

• The ALE pin goes high at first T state always.
• AD0-AD7 are used to fetch data from memory and store the
lower byte of address.
• A8-A15 store the higher byte of the address while IO/M¯ will
be low since it is memory related operation.
• RD¯ will only be low at the data fetching time.
• WR¯ will be at HIGH level since no write operation is done.
• S0=0,S1=1 for Memory read cycle.
 TIMING AND STATE DIAGRAM
Memory write Cycle: It basically requires 3T states from T1-T3 .
• The ALE pin goes high at first T state always.
• AD0-AD7 are used to fetch data from CPU and store the
lower byte of address.
• A8-A15 store the higher byte of the address while IO/M¯ will
be low since it is memory related operation.
• RD¯ will be HIGH since no read operation is done.
• WR¯ will be at LOW level only when data fetching is done.
• S0=1,S1=0 for Memory write cycle.
• Ex: 2000h:MVI A,32h
Timing for Execution of the Instruction MVI
A,32H
M1 Opcode Fetch M2 Memory Read
T1 T2 T3 T4 T1 T2 T3

CLX

A15
20H High-Order Memory Address Unspecified 20H High- Order Memory Addresss
A8
Low-Order
AD7
00H 3EH Opcode 01H 32H Data
AD0
Memory Address Memory Address

ALE

IO/M
Status IO/M = 0, S0 = 1, S1 = 1 Opcode Fetch IO/M = 0, S1 = 1, S0 = 0 Status
S1, S0

RD
 8085 Memory Interfacing
• Generally µP 8085 can address 64 kB of memory .
• Generally EPROMS are used as program memory and RAM as
data memory.
• We can interface Multiple RAMs and EPROMS to single µP .
• Memory interfacing includes 3 steps :
1. Select the chip.
2. Identify register.
3. Enable appropriate buffer.
 8085 Memory Interfacing

•In this example we saw that some address lines are used for
interfacing while others are for decoding.
•It is called absolute decoding.
•We sometimes don’t requires that many address lines.So
we ignore them.But this may lead to shadowing or multiple
address.
•This type of decoding is called linear decoding or partial
decoding.
•In partial decoding wastage of address takes place but it
requires less hardware and cost is also less as compared with
absolute one.
 Memory structure & its requirements

ROM
Data Lines
RAM
Input Buffer WR

Address CS
Lines

Address CS
Lines

Output Buffer RD

Output Buffer RD
Date
Lines
Data Lines

• The way of interfacing the above two chips to the

microprocessor is the same.
– However, the ROM does not have a WR signal.
 Address decoding
• The result of ‘address decoding’ is the identification of
a register for a given address.
– A large part of the address bus is usually connected
directly to the address inputs of the memory chip.
– This portion is decoded internally within the chip.
– What concerns us is the other part that must be
decoded externally to select the chip.
– This can be done either using logic gates or a
decoder.
Interfacing of 4096×8 EPROM with 8085 with only NAND and 3×8 Decoder
2048×8 R/W memory Interfacing with 8085 using 3×8 Decoder
 8085 Memory Interfacing
• Example: Interface 2Kbytes of Memory to 8085 with starting
address 8000H.
Initially we realize that 2K memory requires 11 address lines
(2^11=2048). So we use A0-A10 .
• Write down A15 –A0

A15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADD

1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8000H

1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 87FFH
 8085 Memory Interfacing
• Address lines A0-A10 are used to interface memory while
A11,A12,A13,A14,A15 are given to 3:8 Decoder to provide an
output signal used to select the memory chip CS¯or Chip
select input.
• MEMR¯ and MEMW¯are given to RD¯and WR¯pins of Memory
chip.
• Data lines D0-D7 are given to D0-D7 pins of the memory chip.
• In this way memory interfacing can be achieved.
 8085 Memory Interfacing
• The diagram of 2k interfacing is shown below:

3:8DECODER
A15- A11

8085
CS
A15-A8

ALE
A10- A0 2K Byte
Latch Memory
AD7-AD0 A7- A0 Chip

WR RD IO/M D7- D0

RD WR
 8085 interfacing with I/O Devices
Microprocessor need to Identify I/O devices with binary number.

IO devices can be interfaced:

•Memory-Mapped I/O (using addresses from memory space)

• Device is identified by 16-bit address (Space ranges from 0000H –
FFFFH

•Standard I/O mapped or isolated I/O mapping /Peripheral Mapped I/O

has separate numbering scheme for I/O devices
• Instructions IN/OUT are used for data transfer
• Device is identified by 8-bit address (Space ranges from 00H –FFH)

*
Memory Mapping Vs Peripheral
I/O

*
 Peripheral I/O Instructions
Instruction IN (code DB) inputs data from an input device into accumulator.

Opcode Operand Description

IN 8-bit Port address 2-byte instruction with hexadecimal
instruction DB and second byte is port
number of input device.
Memory Machine Code Mneumonics
Address
2065 DB IN 84
2066 84

Instruction OUT (code D3) sends the content of the accumulator to output
device such as LED display.
Opcode Operand Description
OUT 8-bit Port address 2-byte instruction with hexadecimal
instruction D3 and Second byte is port
number of output device.
Memory Machine Code Mneumonics
Address
2050 D3 OUT 01
2051 01
*
OUT Instruction

*
•
OUT Instruction
In First Machine cycle M1(Opcode Fetch), microprocessor places the 16-bit memory
address from the program counter (PC) on the address bus. At T1 20H is placed on A15-
A8 and 50H is placed on AD7-AD0. ALE goes high, IO/M’ goes low indicates memory
related operations. ALE indicates the availability of the address on AD7-AD0. At T2
microprocessor sends RD’ control signal which is combined with IO/M’ to generate
MEMR’ signal and processor fetches the instruction code D3 using data bus.

• M2 (memory Read), 8085 places next address 2051H on address bus and get device
address 01H.

• M3 (I/O write), 8085 place device address 01H on low and high address bus
both.IO/M’ goes high to indicate I/O operation. At T2 AC contents are placed on data bus
followed by control signal WR’. If we connect data bus to latch we can catch the
information and display on LEDs and Printer. By ANDing IO/M’ and WR’ signals IOW’
signal enable output device.

Information necessary for interfacing output device is available during T2 and T3

of
the M3 cycle.
*
IN Instruction

*
 IN Instruction
• In First Machine cycle M1 (Opcode Fetch), microprocessor places the 16-bit
memory address from the program counter (PC) on the address bus. At T1 20H is
placed on A15-A8 and 65H is placed on AD7-AD0. ALE goes high, IO/M’ goes
low indicates memory related operations. ALE indicates the availability of the
address on AD7-AD0. At T2 microprocessor sends RD’ control signal which is
combined with IO/M’ to generate MEMR’ signal and processor fetches the
instruction code DB using data bus.

• M2 (Memory Read), 8085 places next address 2066H on address bus and get
device address 84H.

• M3 (Memory Read), 8085 place device address 84H on low and high address
bus both and asserts RD’ signal. IO/M’ goes high to indicate IO operation. At T2
data from input port are paced on data bus and transferred to AC. By ANDing
IO/M’ and WR’ signals IOR’ signal to enable input port.

*
 Data Transfer
For data transfer from input device to processor the following operations
are performed.
•The input device will load the data to the port.
•When the port receives a data, it sends message to the processor to read the
data.
•The processor will read the data from the port.
•After a data have been read by the processor the input device will load the
next data into the port.
For data transfer from processor to output device the following operations
are performed.
•The processor will load the data to the port.
•The port will send a message to the output device to read the data.
•The output device will read the data from the port.
•After the data have been read by the output device the processor can load the
next data to the port.
*
 Device Selection and Data
Transfer
Steps are summarized as:
•Decode the address bus to generate unique pulse corresponding to device address on
the bus called device address bus or I/O address pulse.
•Combine the device address pulse with the control signal to generate a device select
pulse(I/O select) that is generated only when both signals are asserted.
•Use the I/O select pulse to activate interfacing device(I/O port).

Figure: Block Diagram of IO interface

 Device Selection and Data
Transfer

Figure: Practical decoding circuit for the output device with address 01H

• Address lines A7-A0 are connected to 8-input NAND gate that functions as
decoder (A0-Directly connected; A7-A1 with inverters).
• When Address bus is carries 01H, gate G1 generated a low pulse otherwise
output remain high.
• G1 and G2 are combined to generate I/O select pulse which clocks data (AC
content on data bus available for few microsecond) into latch for display by
LEDs.
*
 Absolute Vs Partial Decoding
• All eight lines are decoded to generate one unique pulse called absolute
decoding like device will be selected only with the address 01H(good design
practice).
• To minimize the cost, the output port can be selected by decoding some
address lines called partial decoding (device has multiple addresses).
• A1 and A0 are at don’t care logic level so output port can access by address
00, 01, 02 and 03(commonly used techniques in small systems).

Partial Decoding Output Latch with Multiple Addresses

 Input Interfacing
Decode logic for a Dip-Switch Input Port

• Address lines are high(FFH), output of NAND gate goes low which is
combined by control signal IOR’ which generates Device Select Pulse.

• Device select pulse enable Tri-state Buffer (used as interfacing port).

Data flow from keys to the AC.
 Interfacing I/O Using Decoders
Decode logic for a Dip-Switch Input Port

• First Step is to decode the address bus using 3x8 Decoder and 4-input NAND
gate. A0 to A2 are used as input and remaining A3 to A7 are used to enable
decoder.
• Second step is to decode address with appropriate control signal (IOR’/IOW’)
output will generate select pulse.
• Third step is to use this pulse to enable I/O port (pulse enables LED latch with
the output port address F8H similarly input buffer is enable with address FAH).
 Input Interfacing
Decode logic for a Dip-Switch Input Port
Interfacing I/O Using Decoders
Seven segment LED interfacing
Interfacing DIP switches
 Memory Mapped I/O
• Instead of using 8-bit address, the full 16-bits of
the address bus must be used.
• Instead of using IORD and IOWR, use MEMR
and MEMW.
• To transfer data Memory Related Instructions
such as LDA(Load AC Direct transfers data from
memory to Accumulator), STA (Store contents of
AC into Memory)are used.
• IN STA 8000H output device instead of a
memory Register is connected to the address, so
that accumulator contents will be transferred to
output device.
 Memory Mapped I/O
• IN LDA 8000H accumulator receives data from input
device rather than Memory.
Execution of Memory Related data Transfer Instruction STA 8000H
Memory mapped I/O interfacing