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Since there is many advancement in VLSI technology and there are many efficient styles of
designing VLSI circuits. Some of the styles are CMOS, PTL, GDI (Gate Diffusion Input)
techniques. GDI technique helps in designing low-power digital combinatorial circuit by
which we can eradicate demerits of CMOS, PTL techniques. This technique allows reducing
power consumption, propagation delay, and area of digital circuits while maintaining low
complexity of logic design. This paper discusses about the performance characteristics of a
Full Adder based Carry Select Adder using various logics and also GDI-MUX technique. The
adders are used in many data path applications and also the area, power consumption and
delay in the design can be reduced. The proposed technique is the GDI-Mux which enables
the reduction of above mentioned parameters and also reduce the number of transistors. The
Full Adder based Carry Select Adder designed in Complementary Pass Transistor Logic,
Complementary Metal Oxide Semiconductor Logic and Gate Diffusion Input –Mux and they
are compared and the most efficient technique is identified. The different methods are
compared with respect to the layout area; transistor count, delay, and power dissipation are
discussed here in this paper showing advantages and drawbacks of GDI compared to CMOS

Complementary metal–oxide–semiconductor (CMOS) is a technology for constructing

integrated circuits. CMOS technology is used in microprocessors, microcontrollers, static
RAM, and other digital logic circuits. CMOS technology is also used for several analog circuits
such as image sensors (CMOS sensor), data converters, and highly integrated transceivers
for many types of communication. Frank Wanlass patented CMOS in 1963 (US patent
3,356,858) while working for Fairchild Semiconductor.

CMOS is also sometimes referred to as complementary-symmetry metal–oxide–

semiconductor (COS-MOS).[1] The words "complementary-symmetry" refer to the typical
design style with CMOS using complementary and symmetrical pairs of p-type and n-type
metal oxide semiconductor field effect transistors (MOSFETs) for logic functions.[2]

Two important characteristics of CMOS devices are high noise immunity and low static power
consumption.[3] Since one transistor of the pair is always off, the series combination draws
significant power only momentarily during switching between on and off states.
Consequently, CMOS devices do not produce as much waste heat as other forms of logic, for
example transistor–transistor logic (TTL) or N-type metal-oxide-semiconductor logic (NMOS)
logic, which normally have some standing current even when not changing state. CMOS also
allows a high density of logic functions on a chip. It was primarily for this reason that CMOS
became the most used technology to be implemented in very-large-scale integration (VLSI)

The phrase "metal–oxide–semiconductor" is a reference to the physical structure of certain

field-effect transistors, having a metal gate electrode placed on top of an oxide insulator,
which in turn is on top of a semiconductor material. Aluminium was once used but now the
material is polysilicon. Other metal gates have made a comeback with the advent of high-κ
dielectric materials in the CMOS process, as announced by IBM and Intel for the 45
nanometer node and smaller sizes.
NAND gate in CMOS logic
More complex logic functions such as those involving AND and OR gates require
manipulating the paths between gates to represent the logic. When a path consists of two
transistors in series, both transistors must have low resistance to the corresponding supply
voltage, modelling an AND. When a path consists of two transistors in parallel, either one or
both of the transistors must have low resistance to connect the supply voltage to the output,
modelling an OR.
Shown on the right is a circuit diagram of a NAND gate in CMOS logic. If both of the A and
B inputs are high, then both the NMOS transistors (bottom half of the diagram) will conduct,
neither of the PMOS transistors (top half) will conduct, and a conductive path will be
established between the output and Vss (ground), bringing the output low. If both of the A and
B inputs are low, then neither of the NMOS transistors will conduct, while both of the PMOS
transistors will conduct, establishing a conductive path between the output and Vdd (voltage
source), bringing the output high. If either of the A or B inputs is low, one of the NMOS
transistors will not conduct, one of the PMOS transistors will, and a conductive path will be
established between the output and Vdd (voltage source), bringing the output high. As the only
configuration of the two inputs that results in a low output is when both are high, this circuit
implements a NAND (NOT AND) logic gate.
An advantage of CMOS over NMOS logic is that both low-to-high and high-to-low output
transitions are fast since the (PMOS) pull-up transistors have low resistance when switched
on, unlike the load resistors in NMOS logic. In addition, the output signal swings the full
voltage between the low and high rails. This strong, more nearly symmetric response also
makes CMOS more resistant to noise.
See Logical effort for a method of calculating delay in a CMOS circuit.
Example: NAND gate in physical layout
The physical layout of a NAND circuit. The larger regions of N-type diffusion and P-type
diffusion are part of the transistors. The two smaller regions on the left are taps to prevent
Simplified process of fabrication of a CMOS inverter on p-type substrate in semiconductor
microfabrication. Note: Gate, source and drain contacts are not normally in the same plane
in real devices, and the diagram is not to scale.
This example shows a NAND logic device drawn as a physical representation as it would be
manufactured. The physical layout perspective is a "bird's eye view" of a stack of layers. The
circuit is constructed on a P-type substrate. The polysilicon, diffusion, and n-well are referred
to as "base layers" and are actually inserted into trenches of the P-type substrate. (See steps
1 to 6 in the process diagram below right) The contacts penetrate an insulating layer between
the base layers and the first layer of metal (metal1) making a connection.
The inputs to the NAND (illustrated in green color) are in polysilicon. The CMOS transistors
(devices) are formed by the intersection of the polysilicon and diffusion; N diffusion for the N
device & P diffusion for the P device (illustrated in salmon and yellow coloring respectively).
The output ("out") is connected together in metal (illustrated in cyan coloring). Connections
between metal and polysilicon or diffusion are made through contacts (illustrated as black
squares). The physical layout example matches the NAND logic circuit given in the previous
The N device is manufactured on a P-type substrate while the P device is manufactured in an
N-type well (n-well). A P-type substrate "tap" is connected to VSS and an N-type n-well tap is
connected to VDD to prevent latchup.

Cross section of two transistors in a CMOS gate, in an N-well CMOS process

With the rapid increase in the use of portable electronic devices, the power dissipation has
become a major constraint. As the technology grows rapidly and the device size scales down
to the nanometer range, power dissipation, area and propagation delay are the major factors
to be considered. The look for improving the performance of circuits based on CMOS logic
resulted in the introduction of many logic styles like Pass Transistor logic, Transmission Gate
logic, Double Pass Transistor logic and also many other hybrid logics. Pass Transistor logic is
one of the most widely used logics for low power digital circuits. It has many advantages over
CMOS, i.e. high speed, low power dissipation and lower interconnection effects. GDI
Technique can overcome certain drawbacks of PTL Logic. A wide range of complex logic
functions in which PTL was used, can be replaced by GDI Technique and this makes the
circuit simple. Easier design of fast, low power circuits, with less number of transistors are
enabled using GDI Technique. Arithmetic and logic operations are the inevitable part of all
high speed and low power circuits in the field of microprocessors, digital signal processing,
image processing etc. An Arithmetic Logic Unit with low power dissipation, lesser transistor
count and lesser propagation delay can contribute much to the modern era.


The power consumed in a device is composed of two types – dynamic, sometimes called
switching power, and static, sometimes called leakage power. In geometries smaller than
90nm, leakage power has become the dominant consumer of power whereas for larger
geometries, switching is the larger contributor. Power reduction strategies can be used to
minimize both types of power.

Power Dissipation in CMOS

Total power is a function of switching activity, capacitance, voltage, and the transistor
structure itself.

Total power is the sum of the dynamic and leakage power

Total Power = Pswitching + Pshort-circuit + Pleakage
Dynamic power is the sum of two factors: switching power plus short-circuit power.
Switching power is dissipated when charging or discharging internal and net capacitances.
Short-circuit power is the power dissipated by an instantaneous short-circuit connection
between the supply voltage and the ground at the time the gate switches state.
Pswitching = a.f.Ceff.Vdd2
Where a = switching activity, f = switching frequency, Ceff = the effective capacitance and Vdd
= the supply voltage.
Pshort-circuit = Isc.Vdd.f
Where Isc = the short-circuit current during switching, Vdd = the supply voltage and f =
switching frequency.

Dynamic power can be lowered by reducing switching activity and clock frequency, which
affects performance; and also by reducing capacitance and supply voltage. Dynamic power
can also be reduced by cell selection-faster slew cells consume less dynamic power.
Leakage power is a function of the supply voltage Vdd, the switching threshold voltage Vth,
and the transistor size.
PLeakage = f (Vdd, Vth, W/L)
Where Vdd = the supply voltage, Vth = the threshold voltage, W = the transistor width and L
= the transistor length.

Of the following leakage components, sub-threshold leakage is dominant.

• I1: Diode reverse bias current
• I2: Sub-threshold current
• I3: Gate-induced drain leakage
• I4: Gate oxide leakage
While dynamic power is dissipated only when switching, leakage power due to leakage
current is continuous.
Switching power dissipation
The word ‘switching’ over here means a lot. It’s not just that inputs are switching, it’s the
outputs also. Now why do I stress on the word ‘outputs also’? That’s because, there’s also
power dissipation that happens while inputs switch and outputs do not switch. Stay with me,
I will introduce it just after this section.Coming back to switching power dissipation, take the
below example:

So here, whenever your input switches from logic 1 to logic 0, the output switches from logic
0 to logic 1 and you see charging current flowing from Vdd to CLOAD which results to
rise_power (this is a liberty attribute used to denote rise_power). And vice-versa holds true
when input switches from logic 1 to logic 0
This was easy…Next, there is another kind of power that dissipates when your inputs and
outputs are switching, that’s short-circuit power

short circuit power dissipation in CMOS inverter

This power dissipation is another beast. Look at below image:
When your input is at logic ‘0’ and assuming your VDD is at 1.8V (considering it’s a 180nm
technology node), why do you think, from physics point of view, does your PMOS turns ON?
The reason is, logic ‘0’ at gate means its at 0V, Vdd is at 1.8V, the PMOS Vgs = 0 – 1.8 = -1.8v
which is far above the threshold voltage of PMOS transistor, which makes the PMOS to turn
Similarly, Vgs of NMOS is 0V – 0V = 0V, which is below the threshold voltage of NMOS
transistor and hence NMOS is OFF. Now look at the highlighted area in the input
transitioning waveform. In that area, if gate input rises from 0v to (say) 0.5v, the Vgs of
NMOS is 0.5v, which is just above the threshold voltage of NMOS (assuming NMOS Vt is
0.2V for 180nm technology node), so it just turns ON
Now the Vgs of PMOS is roughly, say 0.5v – 1.8v = -1.3V which is again, far above threshold
voltage of PMOS transistor, so your PMOS transistor is still ON. You see, at this point, both
PMOS and NMOS transistor are ON. Looking Vdd at higher potential, and GND at lower
potential, there is now a direct path from Vdd to Gnd.
That’s short circuit current, and hence the name short-circuits power dissipation
So now the big question? What if the outputs do not switch, while only the inputs switch, like
the below case of AND gate
Here, if you see, even though your input ‘B’ switches from logic ‘0’ to logic ‘1’, your NAND
output and hence, the AND output doesn’t switch. So do we still see power dissipation in these
kind of scenarios?
Hidden power
That’s me…”hidden power”. That’s how I introduced myself in the beginning of the post. Now
even though, in the above image, the outputs do not switch, the switching of input ‘B’ creates
a unique path for current flow from Vdd to Gnd. Look at below image:
During the transitioning of ‘B’, due to similar reasons of Vgs being greater than threshold
voltage of PMOS and NMOS transistors, M2 is ON momentarily, and I flow from Vdd – M2 –
M6 – GND. Since I am hidden inside the boundary of the cell, the name hidden power.


1) Design time techniques
The design time techniques are static, they can‟t be modified or changed once they are
fixed, while the circuit is operating.

To reduce leakage it exploit the delay slack.

a) Dual threshold CMOS.
This technique compromise between the high performance and low leakage power.
Transistors those are located on critical paths are assigned as low threshold voltage
and the transistors that are not critical to timing can tolerate high threshold
voltages and slow switching speeds. The selection of the control voltages are
conducted at design times, no additional circuits are required. The below table
shows the leakage current for high and low threshold voltage transistors in a 70nm
process technology. We observe that leakage energy of transistors of low threshold
voltage is larger than a factor of 75 than the high threshold voltage transistors.
Hence if we replace the low –Vt transistor with a high –Vt transistor it will reduce
the energy or power.

b) Multiple supply voltage Supply voltage scaling also reduces the leakage power, because
subthreshold leakage due to the GIDL and DIBL as well as the gate leakage component
when the supply voltage is scaled down. To achieve low power with respect to high
performance two methods can be employed i.e. dynamic and voltage scaling.
2) Runtime leakage reduction
a) Transistor stacking (self reverse biased)
Subthreshold leakage current reduces when it flows through a stack of series
connected transistors. The below figures shows the transistor stacking
process.When both M1 and M2 are turned off, the voltage at the intermediate
nodeVm is positive due to small drain current. Due to positive source potential, gate
to source voltage of M1 becomes negative, hence subthreshold current reduces.

b) Sleep transistor technique

The sleep transistor approach is most commonly used technique for the leakage
power reduction. In this technique an extra “sleep” PMOS transistor is placed
between pull up network and VDD and an additional NMOS transistor is place
between the ground and pull down network. These transistors turn off the circuit
by cutting off the power in the sleep mode. So this technique can reduce the leakage
power in good margin by cutting off the power source. However this technique
causes floating output in the sleep mode.
a. Sleepy stack approach
i. We have discussed the stack approach already, so when the stack
approach effectively merged with sleep transistor technique, this sleep
stack approach is developed. By using stack effect this technique
divides transistors into two half-length transistors.
Then the sleep transistorsare connected parallel to one of the divided
transistor. During the sleep mode sleep transistors are off, stacked
transistors reduces the leakage current. The main cons of this
technique is the power delay since we are replacing the transistors
ii. Sleepy keeper approachIn sleepy keeper technique, sleep transistors
is parallel in both pull up and pull down network. It uses the leakage
feedback technique.

In this technique a PMOS and NMOS is placed in parallel transistors.

In sleep mode sleep transistors are turned off and one of the parallel
connected transistors keep on track power rail.
iii. Dual sleep technique
1. In dual sleep methods two transistors are connected in parallel
similar to the keeper approach. In both active and inactive mode
sleep transistors is always in both pull down and pull up
2. So output is connected to GND and VDD always. In this method
less number of transistors is needed to apply a certain logic
circuit. This method has good tradeoff between the delay, power
and area.
iv. Dual stack technique
1. In dual stack method two PMOS and two NMOS transistors are
used. The two PMOS transistors are used in the pull down
network and two NMOS network are used in pull up network.
2. The advantage of this method is, NMOS degrades at high logic
level and PMOS degrades at low logic level. But the
disadvantages of this technique compared to previous technique
is delay, the delay increases
v. Variable threshold CMOS (VTCMOS)
1. This is a body biasing design technique. To achieve different
threshold voltages, a self-substrate bias circuit is used to control
body bias.
2. In the active mode a zero body bias is applied, while in standby
mode a reverse body bias is applied to control the threshold
voltage and cut off leakage current.

1 Introduction & Installation

The present document introduces the design and simulation of CMOS integrated circuits, in
an attractive way thanks to user-friendly PC tools DSCH3 and MICROWIND3. The lite
version of these tools only includes a subset of available commands. The Lite version is
freeware, available on the web site www.microwind.org. The complete version of the tools is
available at a very low cost from

About DSCH3 The DSCH3 program is a logic editor and simulator. DSCH3 is used to
validate the architecture of the logic circuit before the microelectronics design is started.
DSCH3 provides a user-friendly environment for hierarchical logic design, and fast
simulation with delay analysis, which allows the design and validation of complex logic
structures. Some techniques for low power design are described in the manual. DSCH3 also
features the symbols, models and assembly support for 8051 and 18f64. DSCH3 also includes
an interface to SPICE.
About Microwind3 The MICROWIND3program allows the student to design and simulate an
integrated circuit at physical description level. The package contains a library of common
logic and analog ICs to view and simulate. MICROWIND3includes all the commands for a
mask editor as well as original tools never gathered before in a single module (2D and 3D
process view, Verilog compiler, tutorial on MOS devices). You can gain access to Circuit
Simulation by pressing one single key. The electric extraction of your circuit is automatically
performed and the analog simulator produces voltage and current curves immediately.


From The web

Connect to page <ni2>
Click <ni2>

 Click <ni2>
 Test: double-click MICROWIND3.EXE. Click "File ->Load", select "CMOS.msk".
Click "Simulate".

 Click <ni2>
 Extract all files in the selected directory.
 Test: double click in DSCH3.EXE. Load "base.sch". Click "Simulate".

C:\Program Files\


Executable (.EXE)
Executable (.EXE) Exemples (.SCH) IEEE HTML
Examples (.MSK) Rule HTML
files (.RUL)

Symbols of Dsch3 Help on line

Help on line

Figure 1: The architecture of Microwind and Dsch

Once installed, two directories are created, one for MICROWIND3, one for DSCH3. In each
directory, a sub- directory called html contains help files.
The MOS device

This chapter presents the CMOS transistor, its layout, static characteristics and dynamic
characteristics. The vertical aspect of the device and the three dimensional sketch of the
fabrication are also described.

2.1 Logic Levels

Three logic levels 0,1 and X are defined as follows:

Logical Voltage Name Symbol in Symbol in


0 0.0V VSS

(Green in
(Green in

1 1.2V in VDD
0.12µm (Red in analog
(Red in simulation)
X Undefined X (Gray in (Gray in simulation)

2.2 The MOS as a switch

The MOS transistor is basically a switch. When used in logic cell design, it can be on or off.
When on, a current can flow between drain and source. When off, no current flow between
drain and source. The MOS is turned on or off depending on the gate voltage. In CMOS
technology, both n-channel (or nMOS) and p- channel MOS (or pMOS) devices exist. The
nMOS and pMOS symbols are reported below. The symbols for the ground voltage source (0
or VSS) and the supply (1 or VDD) are also reported in figure 2-1.
0 1

0 1

Fig. 2-1: the MOS symbol and switch

The n-channel MOS device requires a logic value 1 (or a supply VDD) to be on. In contrary,
the p-channel MOS device requires a logic value 0 to be on. When the MSO device is on, the
link between the source and
drain is equivalent to a resistance. The order of range of this ‘on’ resistance is 100 -5K . The
‘off’ resistance is considered infinite at first order, as its value is several M .

2.3 MOS layout

We use MICROWIND3 to draw the MOS layout and simulate its behavior. Go to the directory
in which the software has been copied (By default microwind3). Double-click on the
MicroWind3 icon.
The MICROWIND3 display window includes four main windows: the main menu, the layout
window, the icon menu and the layer palette. The layout window features a grid, scaled in
lambda ( ) units. The lambda unit is fixed to half of the minimum available lithography of
the technology. The default technology is a CMOS 6-metal layers 0.12µm technology,
consequently lambda is 0.06µm (60nm).

Fig. 2-23 The MICROWIND3 window as it appears at the initialization stage..

The palette is located in the lower right corner of the screen. A red color indicates the current
layer. Initially the selected layer in the palette is polysilicon. By using the following
procedure, you can create a manual design of the n-channel MOS.
Fix the first corner of the box with the mouse. While keeping the mouse button pressed,
move the mouse to the opposite corner of the box. Release the button. This creates a box
in polysilicon layer as shown in Figure 2-3. The box width should not be inferior to 2 , which
is the minimum width of the polysilicon box.

Change the current layer into N+ diffusion by a click on the palette of the Diffusion N+
button. Make sure that the red layer is now the N+ Diffusion. Draw a n-diffusion box at the
bottom of the drawing as in Figure 2-3. N-diffusion boxes are represented in green. The
intersection between diffusion and polysilicon creates the channel of the nMOS device.
Fig. 2-3. Creating the N-channel MOS transistor

2.4 Vertical aspect of the MOS

Click on this icon to access process simulation (Command Simulate Process section in 2D).
The cross- section is given by a click of the mouse at the first point and the release of the
mouse at the second point.


Thin gate

Fig. 2-4. The cross-section of the nMOS devices.

In the example of Figure 2-4, three nodes appear in the cross-section of the n-channel MOS
device: the gate (red), the left diffusion called source (green) and the right diffusion called
drain (green), over a substrate (gray). A thin oxide called the gate oxide isolates the gate.
Various steps of oxidation have lead to stacked oxides on the top of the gate.

The physical properties of the source and of the drain are exactly the same. Theoretically, the
source is the origin of channel impurities. In the case of this nMOS device, the channel
impurities are the electrons. Therefore, the source is the diffusion area with the lowest
voltage. The polysilicon gate floats over the channel, and splits the diffusion into 2 zones, the
source and the drain. The gate controls the current flow from the drain to the source, both
ways. A high voltage on the gate attracts electrons below the gate, creates an electron channel
and enables current to flow. A low voltage disables the channel.
2.5 Static Mos Characteristics

Click on the MOS characteristics icon. The screen shown in Figure 2-5 appears. It represents
the Id/Vd static characteristics of the nMOS device.

Fig. 2-5. N-Channel MOS characteristics.

The MOS size (width and length of the channel situated at the intersection of the polysilicon
gate and the diffusion) has a strong influence on the value of the current. In Figure 2-5, the
MOS width is 1.74µm and the length is 0.12µm. A high gate voltage ( Vg =1.2V) corresponds
to the highest Id/Vd curve. For Vg=0, no current flows. You may change the voltage values of
Vd, Vg, Vs by using the voltage cursors situated on the right side of the window. A maximum
current around 1.5mA is obtained for Vg=1.2V, Vd=1.2V, with Vs=0.0. The MOS parameters
correspond to SPICE Level 3. A tutorial on MOS model parameters is proposed later in this

2.6 Dynamic MOS behavior

This paragraph concerns the dynamic simulation of the MOS to exhibit its switching
properties. The most convenient way to operate the MOS is to apply a clock to the gate,
another to the source and to observe the drain. The summary of available properties that can
be added to the layout is reported below.
VDD property

High voltage property Node visible Sinusoidal wave

VSS property

Clock property Pulse property

Apply a clock to the gate. Click on the Clock icon and then, click on the polysilicon gate.
The clock menu appears again. Change the name into Vgate and click on OK to apply a clock
with 0.5ns period (0.225ns at 0, 25ps rise, 0.225ns at 1, 25ps fall).

Fig. 2-6. The clock menu.

Apply a clock to the drain. Click on the Clock icon, click on the left diffusion. The Clock
menu appears. Change the name into Vdrain and click on OK. A default clock with 1ns period
is generated. The Clock property is sent to the node and appears at the right hand side of the
desired location with the name Vdrain.
ΠWatch the output: Click on the Visible icon and then, click on the right diffusion. Click OK.
The Visible property is then sent to the node. The associated text s1 is in italic, meaning that
the waveform of this node will appear at the next simulation.

Always save BEFORE any simulation. The analog simulation algorithm may cause run-time
errors leading to a loss of layout information. Click on File Save as. A new window appears,
into which you enter the design name. Type for example myMos. Then click on Save. The
design is saved under that filename.

2.7 Analog Simulation

Click on Simulate Start Simulation. The timing diagrams of the nMOS device appear, as
shown in Figure 2-7.

Fig. 2-7. Analog simulation of the MOS device.

When the gate is at zero, no channel exists so the node vsource is disconnected from the drain.
When the gate is on, the source copies the drain. It can be observed that the nMOS device
drives well at zero but poorly at the high voltage. The highest value of vsource is around
0.85V, that is VDD minus the threshold voltage. This means that the n-channel MOS device
do not drives well logic signal 1, as summarized in figure 2-8. Click on More in order to
perform more simulations. Click on Close to return to the editor.

0 1

1 2.8 Layout considerations

0 Good 0

Fig. 2-9. The nMOS device behavior summary

1 Poor 1

The safest way to create a MOS device is to use the MOS generator. In the palette, click the
MOS generator icon. A window appears as reported below. The programmable parameters
are the MOS width, length, the number of gates in parallel and the type of device (n-channel
or p-channel). By default metal interconnects
and contacts are added to the drain and source of the MOS. You may add a supplementary
metal2 interconnect on the top of metal 1 for drain and source.

Access to MOS

Fig. 2-10. The MOS generator

2.9 The MOS Models

Mos level 1
For the evaluation of the current Ids between the drain and the source as a function of Vd,Vg
and Vs, you may use the old but nevertheless simple MODEL 1 described below.

Mode Condition Expression for the current Ids

CUT-OFF Vgs<0 Ids 0

LINEAR Vds<Vgs-Vt Ids UO ε0 εr .W (V vt)2
TOX L gs
SATURATED Vds>Vgs-Vt Ids UO ε0 εr .W (V vt)2
TOX L gs

0 = 8.85 10-12 F/m is the absolute permittivity

r = relative permittivity, equal to 3.9 in the case of SiO2 (no unit)

Mos Model 1 parameters

Parameter Definition Typical Value 0.12µm


VTO Theshold voltage 0.4V -0.4V

U0 Carrier mobility 0.06m2/V-s 0.02m2/V


TOX Gate oxide thickness 2nm 2nm

PHI Surface potential at strong 0.3V 0.3V


GAMMA Bulk threshold parameter 0.4 V0.5 0.4 V0.5

W MOS channel width 1µm 1µm

L MOS channel length 0.12µm 0.12µm

Table 2-1: Parameters of MOS level 1 implemented into Microwind3

When dealing with sub-micron technology, the model 1 is more than 4 times too optimistic
regarding current prediction, compared to real-case measurements, as shown above for a
10x0,12µm n-channel MOS.

The MOS Model 3

For the evaluation of the current Ids as a function of Vd,Vg and Vs between drain and source,
we commonly use the following equations, close from the SPICE model 3 formulations. The
formulations are derived from the model 1 and take into account a set of physical limitations
in a semi-empirical way.
Ids Model 1 would
do this
Linear Saturation in model 3

Cutt-off Vgs<Vt


Fig. 2-11: Introduction of the saturation voltage VdSat which truncates the equations issued
from model 1

One of the most important change is the introduction of VdSAT, a saturation voltage from
which the current saturates and do not rise as the LEVEL1 model would do (Figure 2-11).
This saturation effect is significant for small channel length.
The BSIM4 MOS Model

A new MOS model, called BSIM4, has been introduced in 2000. A simplified version of this
model is supported by MICROWIND3, and recommended for ultra-deep submicron
technology simulation. BSIM4 still considers the operating regions described in MOS level 3
(linear for low Vds, saturated for high Vds, subthreshold for Vgs<Vt), but provides a perfect
continuity between these regions. BSIM4 introduces a new region where the impact ionization
effect is dominant.

The number of parameters specified in the official release of BSIM4 is as high as 300. A
significant portion of these parameters is unused in our implementation. We concentrate on
the most significant parameters, for educational purpose. The set of parameters is reduced to
around 20, shown in the right part of figure 2-12.
Fig.2-12: Implementation of BSIM4 within Microwind3

2.10 The PMOS Transistor

The p-channel transistor simulation features the same functions as the n-channel device, but
with opposite voltage control of the gate. For the nMOS, the channel is created with a logic 1
on the gate. For the pMOS, the channel is created for a logic 0 on the gate. Load the file
pmos.msk and click the icon MOS characteristics. The p-channel MOS simulation appears,
as shown in Figure 2-13. Note that the pMOS gives approximately half of the maximum
current given by the nMOS with the same device size. The highest current is obtained with
the lowest possible gate voltage, that is 0.
Fig. 2-13. Layout and simulation of the p-channel MOS (pMOS.MSK)
From the simulation of figure 3-21, we see that the pMOS device is able to pass well the logic
level 1. But the logic level 0 is transformed into a positive voltage, equal to the threshold
voltage of the MOS device. The summary of the p-channel MOS performances is reported in
figure 3-20.

0 1

0 0
0 Poor 0 1 Good 1

Fig. 2-14. Summary of the performances of a pMOS device

2.11 The Transmission Gate

Both NMOS devices and PMOS devices exhibit poor performances when transmitting one
particular logic information. The nMOS degrades the logic level 1, the pMOS degrades the
logic level 0. Thus, a perfect pass gate can be constructed from the combination of nMOS and
pMOS devices working in a complementary way, leading to improved switching performances.
Such a circuit, presented in figure 2-15, is called the transmission gate. In DSCH3, the symbol
may be found in the Advance menu in the palette. The transmission gate includes one
inverter, one nMOS and one pMOS.
0 1
Transmission gate

0 0
0 Good 0 1 Good 1

Fig. 2-15. Schematic diagram of the transmission gate (Tgate.SCH)

Fig. 2-16: Layout of the transmission gate (TGATE.MSK)

The layout of the transmission gate is reported in figure 2-16. The n-channel MOS is situated
on the bottom the p- channel MOS on the top. Notice that the gate controls are not connected,
as ~Enable is the opposite of Enable.

2.12 Features in the full version

Technology A detailed description of technological trends, and several

Scale illustrations with
MICROWIND3 showing the impact of the progresses in
lithography in terms of switching speed and layout shrinking.

High Speed Mos A new kind of MOS device has been introduced in deep
submicron technologies,
starting the 0.18µm CMOS process generation. The new MOS,
called high speed MOS (HS) is available as well as the normal
one, recalled Low leakage MOS (LL).

High Voltage For I/Os operating at high voltage, specific MOS devices called
MOS "High voltage MOS" are used. The high voltage MOS is built
using a thick oxide, two to three times thicker than the low
voltage MOS, to handle high voltages as required by the
I/O interfaces..

Temperature Three main parameters are concerned by the sensitivity to

Effects temperature: the threshold voltage VTO, the mobility U0 and the
slope in sub-threshold mode. The
modeling of the temperature effect is described and illustrated .

Process Due to unavoidable process variations during the hundreds of

Variations chemical steps for the fabrication of the integrated circuit, the
MOS characteristics are never exactly identical from one device
to another, and from one die to an other. Monte-carlo
simulation, min/max/typ simulations are provided in the full
3 The Inverter

This chapter describes the CMOS inverter at logic level, using the logic editor and simulator
DSCH3, and at layout level, using the tool MICROWIND3.

3.1 The Logic Inverter

In this section, an inverter circuit is loaded and simulated. Click File Open in the main
menu. Select INV.SCH in the list. In this circuit are one button situated on the left side of the
design, the inverter and a led. Click Simulate Start simulation in the main menu.

Fig. 3.1: The schematic diagram including one single inverter (Inverter.SCH)

Now, click inside the buttons situated on the left part of the diagram. The result is displayed
on the leds. The red value indicates logic 1, the black value means a logic 0. Click the button
Stop simulation shown in the picture below. You are back to the editor.
Fig. 3.2: The button Stop Simulation

Click the chronogram icon to get access to the chronograms of the previous simulation (Figure
3-3). As
seen in the waveform, the value of the output is the logic opposite of that of the input.
Fig. 3-3 Chronograms of the inverter simulation (CmosInv.SCH)

Double click on the INV symbol, the symbol properties window is activated. In this window
appears the VERILOG description (left side) and the list of pins (right side). A set of drawing
options is also reported in the same window. Notice the gate delay (0.03ns in the default
technology), the fanout that represents the number of cells connected to the output pin (1 cell
connected), and the wire delay due to this cell connection (An extra 0.140ns delay).


The CMOS inverter design is detailed in the figure below. Here the p-channel MOS and the
n-channel MOS transistors function as switches. When the input signal is logic 0 (Fig. 3-4
left), the nMOS is switched off while PMOS passes VDD through the output. When the input
signal is logic 1 (Fig. 3-4 right), the pMOS is switched off while the nMOS passes VSS to the

Fig. 3-4: The MOS Inverter (File CmosInv.sch)

The fanout corresponds to the number of gates connected to the inverter output. Physically,
a large fanout means a large number of connections, that is a large load capacitance. If we
simulate an inverter loaded with one single output, the switching delay is small. Now, if we
load the inverter by several outputs, the delay and the power consumption are increased. The
power consumption linearly increases with the load capacitance. This is mainly due to the
current needed to charge and discharge that capacitance.

In this paragraph, the procedure to create manually the layout of a CMOS inverter is
described. Click the icon MOS generator on the palette. The following window appears. By
default the proposed length is the minimum length available in the technology (2 lambda),
and the width is 10 lambda. In 0.12µm technology, where lambda is 0.06µm, the
corresponding size is 0.12µm for the length and 0.6µm for the width. Simply click Generate
Device, and click on the middle of the screen to fix the MOS device.

Click again the icon MOS generator on the palette. Change the type of device by a tick on p-
channel, and click Generate Device. Click on the top of the nMOS to fix the pMOS device. The
result is displayed in figure 3-4.

Fig. 3-4. Selecting the nMOS device

3.4 Connection between Devices

(1) Bridge between nMos and pMos

(5) Connexio
n to power
(3) Bridge between nMos and pMos

(4) Connexion to output

(2) Contact to input

(6) Connexion to

Fig. 3-6 Connections required to build the inverter

Within CMOS cells, metal and polysilicon are used as interconnects for signals. Metal is a
much better conductor than polysilicon. Consequently, polysilicon is only used to interconnect
gates, such as the bridge
(1) between pMOS and nMOS gates, as described in the schematic diagram of figure 3-5.
Polysilicon is rarely used for long interconnects, except if a huge resistance value is

In the layout shown in figure 3-5, the polysilicon bridge links the gate of the n-channel MOS
with the gate of the p-channel MOS device. The polysilicon serves as the gate control and the
bridge between MOS gates.

(1) Polysilicon Bridge between pMOS and nMOS gates

2 lambda polysilicon gate size to achieve fastest switching

Fig. 3-6 Polysilicon bridge between nMOS and pMOS devices (InvSteps.MSK)

3.5 Useful Editing Tools

The following commands may help you in the layout design and verification processes.

Command Icon/Short Menu Description


UNDO CTRL+U Edit menu Cancels the last editing


DELETE Edit menu Erases some layout

included in the given area
CTRL+X or pointed by the mouse.

STRETCH Edit menu Changes the size of one box,

or moves the layout
included in the given area.

COPY Edit Menu Copies the layout included

in the given area.

VIEW View Menu Verifies the electrical net


2D Simulate Shows the aspect of the

CRO Menu circuit in
vertical cross-section.

Table 3-1: A set of useful editing tools

3.6 Metal-to-poly

As polysilicon is a poor conductor, metal is preferred to interconnect signals and supplies.

Consequently, the input connection of the inverter is made with metal. Metal and polysilicon
are separated by an oxide which prevents electrical connections. Therefore, a box of metal
drawn across a box of polysilicon does not allow an electrical connection (Figure 3-6). To build
an electrical connection, a physical contact is needed. The corresponding layer is called
"contact". You may insert a metal-to-polysilicon contact in the layout using a direct macro
situated in the palette.
Metal (4 min) Contact
(2x2 )

Enlarged poly area (4x4 )

Polysilicon (2 min)

Fig. 3-7 Physical contact between metal and polysilicon

Metal bridge between
nMOS and pMOS
gates drains

Metal extension for future interconnection

Fig. 3-8 Adding a poly contact, poly and metal bridges to construct the CMOS inverter

The Process Simulator shows the vertical aspect of the layout, as when fabrication has been
completed. This feature is a significant aid to understand the circuit structure and the way
layers are stacked on top of each other. A click of the mouse on the left side of the n-channel
device layout and the release of the mouse at the right side give the cross-section reported in
figure 3-9.
Thick oxide
Metal 1

NMOS gate


Source (N+

Drain (N+

Fig. 3-9 The 2D process section of the inverter circuit near the nMOS device (InvSteps.MSK)

3.7 Supply Connections

The next design step consists in adding supply connections, that is the positive supply VDD
and the ground supply VSS. We use the metal2 layer (Second level of metallization) to create
horizontal supply connections. Enlarging the supply metal lines reduces the resistance and
avoids electrical overstress. The simplest way to build the physical connection is to add a
metal/Metal2 contact that may be found in the palette. The connection is created by a plug
called "via" between metal2 and metal layers.
The final layout design step consists in adding polarization contacts. These contacts convey
the VSS and VDD voltage supply close to the bulk regions of the device. Remember that the
n-well region should always be polarized to a high voltage to avoid short-circuit between VDD
and VSS. Adding the VDD polarization in the n-well region is a very strict rule.
Fig.3-10 Adding polarization contacts
3.8 Process steps to build the Inverter

At that point, it might be interesting to illustrate the steps of fabrication as they would
sequence in a foundry. MICROWIND3 includes a 3D process viewer for that purpose. Click
Simulate Process steps in 3D. The simulation of the CMOS fabrication process is performed,
step by step by a click on Next Step. On figure 3-11, the picture on the left represents the
nMOS device, pMOS device, common polysilicon gate and contacts. The picture on the right
represents the same portion of layout with the metal layers stacked on top of the active

Fig.3-11 The step-by-step fabrication of the Inverter circuit (InvSteps.MSK)

3.9 Inverter Simulation

The inverter simulation is conducted as follows. Firstly, a VDD supply source (1.2V) is fixed
to the upper metal2 supply line, and a VSS supply source (0.0V) is fixed to the lower metal2
supply line. The properties are located in the palette menu. Simply click the desired property
, and click on the desired location in the layout. Add a clock on the inverter input node (The
default node name clock1 has been changed into Vin)and a visible property on the output node

VDD property Visible node

Clock property


VDD Sinus

VSS property High VDD Clock Pulse

Fig.3-12 Adding simulation properties (InvSteps.MSK)

The command Simulate Run Simulation gives access to the analog simulation.
Select the simulation mode Voltage vs. Time. The analog simulation of the circuit is
performed. The time domain waveform, proposed by default, details the evolution of
the voltages in1 and out1 versus time. This mode is also called transient simulation,
as shown in figure 3-13.

Fig. 3-13 Transient simulation of the CMOS inverter (InvSteps.MSK)

The truth-table is verified as follows. A logic zero corresponds to a zero voltage and a
logic 1 to a 1.20V. When the input rises to 1, the output falls to 0, with a 6 Pico-second
delay (6.10-12 second).



WHIS rapid development of portable digital applications, the demand for increasing
speed, compact implementation, and low power dissipation triggers numerous
research efforts [1]–[3]. The wish to improve the performance of logic cir-cuits, once
based on traditional CMOS technology, resulted in the development of many logic
design techniques during the last two decades [17]. One form of logic that is popular
in low-power digital circuits is pass-transistor logic (PTL).

Formal methods for deriving pass-transistor logic have been presented for nMOS.
They are based on the model, where a set of control signals is applied to the gates of
nMOS transistors. Another set of data signals are applied to the sources of the n-
transistors [1]. Many PTL circuit implementations have been proposed in the
literature [1], [2], [4]–[6], [14].

Some of the main advantages of PTL over standard CMOS design are

1) high speed, due to the small node capacitances;

2) low power dissipation, as a result of the reduced number of transistors; and 3)

lower interconnection effects [7], [8], due to a small area.

However, most of the PTL implementations have two basic problems. First, the
threshold drop across the single-channel pass transistors results in reduced current
drive and hence slower operation at reduced supply voltages; this is particularly
important for low-power design since it is desirable to operate at the lowest possible
voltage level. Second, since the “high” input voltage level at the regenerative inverters
is not , the PMOS device in the inverter is not fully turned off, and hence direct-
path static power dissipation could be significant [4].
There are many sorts of PTL techniques that intend to solve the problems mentioned
above [5].

1) Transmission gate CMOS (TG) uses transmission gate logic to realize complex
logic functions using a small number of complementary transistors. It solves the
problem of low logic level swing by using pMOS as well as nMOS [1].

2) Complementary pass-transistor logic (CPL) features complementary

inputs/outputs using nMOS passtransistor logic with CMOS output inverters. CPL’s
most important feature is the small stack height and the internal node low swing,
which contribute to lowering the power consumption. The CPL suffers from static
power consumption due to the low swing at the gates of the output inverters. To lower
the power consumption of CPL circuits, LCPL and SRPL circuit styles are used. Those
styles contain pMOS restoration transistors or cross-coupled inverters (respectively).

3) Double pass-transistor logic (DPL) uses complementary transistors to keep full

swing operation and reduce the dc power consumption. This eliminates the need for
restoration circuitry. One disadvantage of DPL is the large area used due to the
presence of pMOS transistors.

An additional problem of existing PTL is top-down logic de-sign complexity, which

prevents the pass transistors from capturing a major role in real logic LSIs [6]. One
of the main reasons for this is that no simple and universal cell library is available
for PTL-based design.
The design of the for GDI proposes a new low-power design technique that allows
solving most of the problems mentioned above—gate diffusion input (GDI) technique.
The GDI approach allows implementation of a wide range of complex logic functions
using only two transistors. This method is suitable for design of fast, low-power
circuits, using a reduced number of transistors (as compared to CMOS and existing
PTL techniques), while improving logic level swing and static power characteristics
and allowing simple top-down design by using small cell library.


The GDI method is based on the use of a simple cell as shown in Fig. 1. At first
glance, the basic cell reminds one of the stan-dard CMOS inverter, but there are some
important differences.

1) The GDI cell contains three inputs: G (common gate input of nMOS and pMOS),
P (input to the source/drain of pMOS), and N (input to the source/drain of nMOS).

2) Bulks of both nMOS and pMOS are connected to N or P (respectively), so it can

be arbitrarily biased at contrast with a CMOS inverter.

It must be remarked that not all of the functions are possible in standard p-well
CMOS process but can be successfully imple-mented in twin-well CMOS or silicon on
insulator (SOI) tech-nologies. This issue will be discussed in Section VII.

Table I shows how a simple change of the input configuration of the simple GDI cell
corresponds to very different Boolean functions.

Most of these functions are complex (6–12 transistors) in CMOS, as well as in

standard PTL implementations, but very simple (only two transistors per function)
in the GDI design method.
In this design, most of the designed circuits were based on the F1 and F2 functions.
The reasons for this are as follows.

1) Both F1 and F2 are complete logic families (allows real-ization of any possible
two-input logic function).

2) F1 is the only GDI function that can be realized in a standard p-well CMOS
process, because the bulk of any nMOS is constantly and equally biased.

3) When N input is driven at high logic level and P input is at low logic level, the
diodes between NMOS and PMOS
bulks to Out are directly polarized and there is a short between N and P,
resulting in static power dissipation and .

This causes a drawback for OR, AND, and MUX implementations in regular CMOS
with configuration. The effect can be reduced if the design is performed in
floating-bulk SOI technologies [22], where a full GDI library can be implemented. In
that case, floating-bulk effects have to be considered.

As can be seen, the GDI cell structure is different from the existing PTL techniques,
reviewed in Section I, and has some important features, which allow improvements
in design complexity level, transistor count, and power dissipation (all of these will
be discussed in Sections IV–VI). Understanding of GDI cell properties demands a
deeper operational analysis of the basic cell in different cases and configurations.


In this section, we analyze GDI circuits. First we explain their operation and
analyze their transient behavior. Then we consider swing restoration issues and
switching characteristics.

A. Operational Analysis of GDI Cell

As mentioned in Section I, one of the common problems of PTL design methods is

the low swing of output signals because of the threshold drop across the single-
channel pass transistors. In existing PTL techniques, additional buffering circuitry
is used to overcome this problem.

To understand the effects of the low swing problem in a GDI cell, we suggest the
following analysis, based on the example of F1 function, and can be easily extended
to use in other GDI functions. Table II presents a full set of logic states and related
functionality modes of F1.

As can be seen from Table II, the only state where low swing occurs in the output
value is , . In this case, the voltage level of F1 is (instead of the expected
0 V) because of the poor high-to-low transition characteristics of the pMOS pass
transistor [4]. It is obvious that the only case (among all the possible transitions)
where the effect occurs is the transition from , to , .The fact that
demands special emphasis is that in about 50% of the cases (for ), the GDI cell
operates as a regular CMOS inverter, which is widely used as a digital buffer for
logic-level restoration. In some of these cases, when

Transient Analysis

The exact transient analysis for a basic GDI cell, in most cases, is similar to a
standard CMOS inverter, widely presented in the literature [9], [10]. This classic
analysis is based on the

Shockley model, where the drain current is expressed as fol-lows:

subthreshold region

(1) linear region

saturation region

where is drivability factor, is threshold voltage, is channel width, and is

channel length.
In contrast with CMOS inverter analysis [8], where was taken as an input voltage,
in most of GDI circuits must be considered as a variable of input voltage in the
Shockley model. In this paper, we shall only discuss the aspects in which GDI differs
from CMOS. The case of most interest is when a step signal is supplied to diffusion
of nMOS transistor and causes a swing drop in output. Fig. 2 shows the schematic
and a transient response for this case.

During this response, the nMOS transistor passes from sat-uration to subthreshold
region. In assuming the fast transition in the input, the linear region can be neglected
in our analysis. Analytical expressions that describe the transient response can be
derived from (1), while considering capacitive load in the output. The capacitive
current is

where is the output capacitance, is the voltage across the capacitance , is

the current charging the capacitor, and is the drain current through the N-channel
device. The expression for as a function of time is derived as fol-lows:
In saturation region


where, in the case of GDI cells linked through diffusion inputs, the capacitance
includes both diffusion and well capacitances of the driven cell.

The integral form of (3) is

where , , and are constants of the process or the given cir-cuit. The final
expression of transient response in the saturation region is


where is time in the saturation region and is a constant of integration and is

calculated for initial conditions ( ). The solution of (7) is done numerically (e.g.,

for specific values of ( ).

After entering the subthreshold region, continues rising

while the output capacitance is charged by according to (1)

In Subthreshold Region:
where is temperature in K, is Boltzmann’s constant, is charge of an electron, and
is a constant

where is constant of integration defined by the initial conditions, is from (10),

and is the threshold voltage. It must be noted that the analysis of propagation
delay of a basic GDI cell given by (2)–(7) can be refined by taking into account the
effect of the diode between the NMOS source and body. This diode is forward biased
during the transient (Fig. 2). By conducting an additional current, it contributes to
charging the output capacitance . This current contribution can be calculated to be

where is the diode current, is the reverse current, and is a factor between one
and two. This current should be added in
(2) to derive an improved propagation delay, resulting in a faster transient
operation of GDI cell.

C. Analysis of Swing-Restoring Buffers

As mentioned above, an important concern in PTL circuit de-sign is the problem of
swing degradation. This section presents a methodology for swing restoration in GDI
circuits under constraints of area (power) and circuit frequency (delay). The simplest
method of swing restoration is to add a buffer stage after every GDI cell. This will
certainly prevent the voltage drop, but the payment will be in additional area, delay,
and power dissipation, which makes this method highly inefficient. Note that our
approach to swing restoration is rather simple; various buffering techniques are
presented in the literature, e.g., and [14]. Given a clocked logic circuit with known
Tcycle and Tsetup, buffering of cascaded GDI cells will be optimal if the following
conditions are preserved.

1) Successive Swing Restoration: While cascading GDI cells, each cell contributes
a voltage drop in the output that is equal to . Assuming 0.3 as a maximal
allowed voltage drop of the whole cascade, the number of linked GDI cells between
two buffers is limited by

As shown above, after exiting the saturation area, the value of is equal to and
decreasing with time as follows, using (9):

Equation (15) applies for subthreshold region only, namely, for


According to (15), remaining in the subthreshold region for will assure a

significant decrease of and as a result, increasing in the number of linked cells
. This allows achieving successive swing restoration while using a lower number
of buffers. Fig. 3 presents Cadence Spectre simulation results of operation in the
subthreshold region in an AND gate implemented in GDI.
If interconnection effects are essential, a signal potential loss over long
interconnects has to be treated. In this case, (15) will be extended with respect to IR
Suppose that the voltage has to be applied to the drain input of the NMOS (Fig.
2) through a long wire. For given and dimensions, the resistance of the
interconnect is defined by

where is a metal sheet resistance per square. The current flowing through the
wire voltage drop is given by

can be determined by the equalization between the wire and NMOS transistor’s
currents as follows:

where is found from (1) according to the operation region of the transistor.
Equation (18) can be solved numerically,

and its contribution to the final expression is represented by

with from (15).

The operation in the subthreshold region causes increase of delay. Therefore, this
method can be efficiently used mostly in low-frequency design. Scaling, namely,
reduction and threshold no scalability, influences the number of required buffers in
GDI design (14). As a result, when operation with the lower supply voltages is
performed, while the same technology and remain, insertion of additional buffers
has to be considered. The direct impact of this is on the area and number of gates.

Finally, several points have to be emphasized concerning the buffer insertion topology
in GDI.

1) Buffer insertion has to be considered only in the case of linking GDI cells
through diffusion inputs. No buffers are needed before gate inputs of GDI cells.

2) Due to this feature, the “mixed path” topology can be used as an efficient
method for buffer insertion. It allows one to reduce the number of buffers by
intermittently involving diffusion and gate inputs in a given signal path.

3) The designer should check the tradeoff between buffer insertion and delay,
area, and power consumption to achieve an efficient swing restoration.

A multiplexer or mux is a combinational circuits that selects several analog or digital

input signals and forwards the selected input into a single output line. A multiplexer
of 2n inputs has n selected lines, are used to select which input line to send to the


Figure 5 shows how a 4:1 MUX can be constructed out of two 2:1 MUXs.

Design using pass-transistor logic

A multiplexer can be designed using various logics. Fig.5.1 shows how a 2:1 MUX is
implemented using a pass-transistor logic.
The pass-transistor logic attempts to reduce the number of transistors to implement
a logic by allowing the primary inputs to drive gate terminals as well as source-drain
terminals. The implementation of a 2:1 MUX requires 4 transistors (including the
inverter required to invert S), while a complementary CMOS implementation would
require 6 transistors. The reduced number of devices has the additional advantage of
lower capacitance.

Design using transmission gate logic

A transmission gate is an electronic element and good non mechanical relay built
with CMOS technology. It is made by parallel combination of nMOS and pMOS
transistors with the input at the gate of one transistor (C) being complementary to
the input at the gate () of the other. The symbol of a transmission gate is shown below
in fig.5. The transmission gate acts as a bidirectional switch controlled by the gate
signal C. When C=1, both MOSFETs are on, allowing the signal to pass through the
gate. In short, A=B, if C=1. On the other hand, C=0, places both transistors in cut-
off, creating an open circuit between nodes A and B. Fig.5. b shows the
implementation of a 2:1 MUX using transmission gate logic.

Here, the transmission gates selects input A or B on the basis of the value of the
control signal S. When S=0, Z=A and when S=1, Z=B.

The GDI technique offers realization of extensive variety of logic functions using
simple two transistor based circuit arrangement. This scheme is appropriate for fast
and low-power circuit design, which reduces number of MOS transistors as compared
to CMOS and other existing low power techniques, while the logic level swing and
static power dissipation improves. It also allows easy top-down approach by means of
small cell library [5]. The basic cell of GDIis shown in Fig. 2.1.The GDI cell consists
of one nMOS and one pMOS. The structure looks like a CMOS inverter. Though in
case of GDI both the sources and corresponding substrate terminals of transistors are
not connected with supplyand it can be randomly biased.2.It has three input
terminals: G (nMOS and pMOS shorted gate input), P (pMOS source input), and N
(nMOS source input). The output is taken from D (nMOS and pMOS shorted drain
terminal) [11].

GDI logic style approach consumes less silicon area compared to other logic styles as
it consists of less transistor count. In view of the fact that, the area is less, the value
of node capacitances will be less and for this reason GDI gates have faster operation
which presents that GDI logic style is a power efficient method of design. We can
realize different Boolean functions with GDI basic cell. Table I shows how different
Boolean functions can be realized by using different input arrangements of the GDI

GDI technique solves the problem of poor ON to OFF transition characteristic of

PMOS and providing the full swing at internal node of circuit. Fig.5.1a show the b is
to 1 MUX select line S is common input for gate terminal of PMOS_1 and NMOS_1.
Input A and input B is connected to the source terminal of PMOS_1 and NMOS_1
respectively. When S is low then PMOS_1 is ON and pass the input B from source
terminal to drain terminal. When S is high then NMOS_1 is ON and PMOS_1 is off.
Output is common for drain terminal for PMOS_1 and NMOS_1
FIGURE 5.1 a) Inverter design b) 2X1 MUX

c) 4X1 Mux
1. Each model for the CMOS and GDI based design is modelled and implemented
in DSCH as spice diagram shown in chapter 5.
2. Such spice models are being converted to Verilog modules and are
implemented as Layouts in Microwind software.
3. The results are obtained based on the BSIM4 simulation of the design
(Layouts). Each condition from the Chapter 5 table is verified and accordingly
4. Finally the power, area and delay are represented as a tabulated for each
design models utilized.

The main aim behind the whole works is to design and propose new low power digital
circuits for the Multiplexer employing the GDI technique for power reductions and
area reduction also. The GDI technique for MUX is chosen for the work as a
systematic and simple approach for Boolean expressions with multiple terms. The
proposed circuit consumes only about a quarter amount of power in comparison to the
conventional CMOS in this converter. 72.43% decreases power consumption of GDI
MUX with respect to CMOS logic. Whereas, 25.42% decreases power consumption of
GDI mux with respect to Pass transistor.

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