LAPTOP CHIPS VOLTAGES

CPU 2.5V (VDD)

3.3V
VCORE (1V Aprox
1.25V (VTT )
DDR 1 LAN 5V HDD
30Amp current)
3.3V (SPD) 3.3V
1.05VCCP

Vtt CPU
1.8V (VDD)
BIOS FAN
DDR 2 5V
0.9V (VTT DDR) 3.3V
1.05VCCP or 1.5v 3.3V (SPD)
MCH
1.8V North
1.5V (VDD) 5V USB 5V
bridge
3.3V
0.75V (VTT ) DDR 3 AUDIO
3.3V
3.3V (SPD)

CARD
1.35V (VDD) 3.3V
READER THERMAL
RTC 0.65V (VTT ) DDR 3L 3.3V
1.05VCCP 3.3V (SPD)
ICH
3.3V
South V IN
LCD/ DVD
3.3V CLOCK 5V
5V
bridge 3.3V LED

CORE i3,i5,i7
GFXCORE1.1V 3.3V
VCORE
GPU 1.05V
1.8V GFX Core i3 PCH
3.3V SIO GFXCORE
1.8V
(KBC) CHIP CPU
1.5 V 1.05VCCP RTC

1.5V 1.5V

7
 Up to C2D CPU
3volt VCC 1
(cpu)
32.7KHZ
BIOS VR_ON (B

PWR_ON ( main_on, Run on)

KBC_PWRBTN SIO
3
2 6 SUSp_ON

4 5

PM_PWRBTN

PM_SLP_S3

PM_SLP_S4
3 VOLT VCC
RSMRST

susb

susc
RSMRST

PWRBTN

ICH PM_PWRBTN

SLP_S3

SLP_S4

POWER ON BUTTON SEQ.

 3volt VCC
32.7KHZ
Pin No 8 1
EC BIOS

VR_ON (cpu)

7 PWR_ON (Bridge, Ram supply)

2 KBC_PWRBTN Main on(sys on)
SIO
SUSP_ON
4 3
RSMRST

PM_PWRBTN
5 6

PM_SLP_S3

PM_SLP_S4
susb

susc

PCH

POWER ON BUTTON SEQ.

Core i3 power sequence
S
W

1 S
W

R304 Y1

C345 R491
R490
R503

SIO
EC R105

ITE-8518 PCH
9
SUS_ON

RUN_ON
10 1
EC_PWROK 13
HWPG
3
VR_ON
12 11
Core i3 VRM section 1 Vin voltage

5volt
VCC

2
3 CPU core
From SIO 1 v to 1.5v
VR_ON

6 VRM 5
Clock enable Core v
To SIO 4

VRM
6 power good Core i3
CPU
VID signal from CPU

GFX Core

GND

32
 Power Block Diagram
230v AC
CPU Core 0.8v or 1v VCORE
volt
Battery Adopter
17
18
1

Volt In 0.9v
Step down
2
1.8v 14
1.05v
SM BUS

CHG_ENABLE

2 15

MOSFET 3.3vSUS

On\off
VR_ON 16
12
switch 5vSUS
SYS_ON 13 MOSFET
Enable

8 SUSP 11

(SIO) 4 SLP_S5 Step 3.3VALWS

down 5
Enab VRMPWRGD
1 5VALWS
PG OK

sig
KBC
32.7khz crystal

ICH
6 3
3VL
3v supply
RSMRST 7
PG 9 PWRBTN
PWRBTN
signal
SLP3,SLP4,
10
3 volt
19 EC_PWRGD(PWRGD)
 SUS_PWRGD Power Block Diagram
MAIN_PWRGD 230v AC
GFX_PWRGD
CPU Core 0.8v or 1v VCORE
volt
Adopter 18
Battery

1
GFX 15
Volt In
1.8v
Step down
13
SM BUS

CHG_ENABLE

2 1.05v
0.9v
ACIN

2 15

MOSFET 3.3vSUS
VR_ON 17

GFX_ON 14 11
16 5vSUS
12
SYS_on(Runon)
MOSFET
Enable

HWPG
SUSP 10

SIO Step 3.3VALWS

19 VRMPWRGD
down
Enab 5 5VALWS
KBCsig
32.7khz crystal

1
SLP_S5 4

ICH
3
3v supply
RSMRST 6
On\off
PG 8 PM_PWRBTN
PWRBTN
switch signal
9 SLP3,SLP4,
3 volt
7
20 ECPWROK(PWR_GD)
 On/off
SW
POWER ON AND RESET SEQUENCE

18v adopter 10.8 Battary

Input Input 8
ON/OFF SLP4
SW 10
SLP3
Clock start

ACIN
PM_PWRBTN Clock 20
V In 9
CPU 23
SIO RSMRST
19
CORE_V
17 CPU_PWRGD
16 7

CK_PWRGD
HWPG 15 22 M_PWRGD

CPU Reset
1 SYS_ON (MAIN ON) 13
ECPWORK 25
21

CPU_PWRGD
RST KBC_RST
CKT PLTRST
3
VRMPWRGD
MCH
KBC_3D3_ALWS

6
(VGATE)
SUSON North Bridge
BIOS
PWRGD
SLP_S5

2 RSTIN CL_RST
11
4
Step 6 24
down 12 PLTRST
3.3v_ALWS 3.3V_SUSP
1 5 CL_RST
5V_ALWS 5v_SUSP CLK_PWRGD

SLP4/ 5
1.8v SLP3
Step To DDR
Down 0.9v 14
PWROK
15
2 1.05V 7 RSMRST
PWROK
ICH 23
South Bridge
3.3V

VR_ON 1.05V
CPU 17 CPU_CORE
Core
VRMPWRGD 18
VRMPWRGD
www.shriraminfotech.net
CPU RESET
R322

SIO CPU
R313

R605

ECPWROK PCH
ADOPTER Battery
ALWS PWRGD
CLOCK
MAIN PWRGD
SUS PWRGD HWPG

PWRBTN 18
ACIN
13

DRAM PWRGD
3

CPU PWRGD
Slp _S5

PLTRST
Step
down 3.3VAL 2 ECPWORK 19 22 21 20
1 1 EC BIOS
SUSB, SLP_S3
5V SUSC, SLP_S4 8 PCH
4 PM_PWRBTN 7
SUS ON

MOSFET
RSMRST
6
3.3V
MOSFET
5V 5
9 MAINON
Step
Down
10 1.05V(PCH, CPU)
2 1.5V(DDR3)
1.8V
14
11 GFX ON
VR_PWRGD

GFX
CORE 12 GFXCORE V BIOS
VR_ON
CS
23
CPUCORE V
CPU 15 16 CLOCK
Core 17
CK_PWRGD
CHIP
ADOPTER Battery
ALWS PWRGD
CLOCK
MAIN PWRGD
SUS PWRGD HWPG

PWRBTN
ACIN
13

DRAM PWRGD
3

CPU PWRGD
SLP _S5

PLTRST
Step
down 3.3VAL 2 ECPWORK 19
22 21 20
1 1
SUSB, SLP_S3

5V SUSC, SLP_S4 8 PCH

4 PM_PWRBTN 7
SUS ON

MOSFET
RSMRST
6
3.3V
MOSFET 5
9 MAINON
Step 1.05V(PCH, CPU)
Down
2 10 1.5V(DDR3)
GFX ON 14
11 16
VR_PWRGD

GFX GFXCORE V
CORE 12
VR_ON
CPUCORE V
CPU
15
Core
17
CK_PWRGD 47
 5 4 3 2 1

ATX P/S WITH 1A STBY CURRENT ATX4P

5VSB 5V 3.3V 12V -12V 12V
+/-5% +/-5% +/-5% +/-5% +/-5% Intel Sandy Bridge CPU Fans
+/-5% Vcore:0.65~1.3V 112Amax
Switching VID
UP6230 VCCP 0.25~1.52V 85A(95W) 12V_200mA
Vaxg:0.65~1.3V 35Amax
4 hases VID
VAXG 0.25~1.52V 25A
D
V_CPU_VTT:1.05V 17Amax SPI D
Switching VTT 1.05V(1V) 8.5A
UP6123 Linear VCC_SA:0.925V(0.85V) 8.8Amax VCC3_30mA
1 phase OP358 VCC_SA 0.925V(0.85V) 8.8A

VCCPLL 1.8V 1A
V_DIMM:1.5V 28.5Amax CRT
VCC Switching
5VDUAL APW 7120 VDDQ 1.5V 4.5A
5VSB P/N MOS VCC_1A fuse

DDR3 DIMM (4) 1333MHz

LDO HDMI/DP
APL5336
LDO VDDQ 15A_S0
3VSB Intel Cougar Point (TDP 5.5W) VCC3_0.5A fuse x 2
1.0A_S3
DDR_VTT:0.75V V_PROC_IO 1.05V 1mA
V_SM_VTT 1.0A_S0
HDMI L.S.
VccDMI 1.05V 0.057A
Linear PCH_CORE:1.05V 6.2Amax VCC3_180mA
OP358 VccCORE 1.05V 1.6A

VccIO 1.05V 4.07A

Flash/NVM
VccADPLLA 1.05V 0.1A
VCC3 _0.3A
VccADPLLB 1.05V 0.1A
C 1.8V_0.1A C

VccCLKDMI 1.05V 0.02A

Non AMT:
VccASW(ME) short to V1P05_PCH VccSSC 1.05V 0.105A

VccDIFFCLKN 1.05V 0.055A

V_ME:1.05V 1.8Amax
VccASW(ME) 1.05V 1.61A

VccDFTERM 1.8V 0.2A

Linear V_SFR:1.8V 1.6Amax
OP358 VccVRM 1.8V 0.159A

Vcc3_3 3.3V 0.409A

VccADAC 3.3V 0.068A

Not support DSW mode:
VccDSW short to 3VSB VccSPI 3.3V 0.02A

VccDSW3_3 3.3V 0.003A

VccSUS3_3 3.3V 0.097A

VccSUSHDA 3.3V 0.01A

B
Battery B
VccRTC 3.3V 6uA(G3) 3V

V5REF 5V 1mA

V5REF_SUS 5V 1mA

VCC3
NEC_D720200
3VDUAL
3VSB P/N MOS VDD3P3 3.3V TBD
Extrenal from V1P05_PCH
VDD1P05 1V TBD

VCC CTRL1P0 internal LVR Output

5VDUAL
5VSB Switch IC
UP7536
SUPER I/O F71808A
3VSB
3VSB 3.3V TBD
USB_5V
VCC3
VCC3 3.3V TBD

BAT 3.3V 3.3V TBD

X16 PCIE Slot per X1 PCIE Slot per PCI Slot per USB X4 Header USB X4 IO USB3.0
A A
3.3V 3A(S0) 3.3V 3A(S0) 5V 5A(S0) VDD VDD
5VDual AUDIO VT1705CE
12V 5.5A(S0) 12V 0.5A(S0) 12V 0.5A(S0) 5VDual 5VDual VCC3
2A
3.3Vaux 0.375A 3.3Vaux 0.375A 3.3Vaux 0.375A 2.0A 2.0A DVDD 3.3V 3.3V 23mA
5VSB
3.3V 7.6A(S0)
Total 1 Slot Total 2 Slots AVDD 5V 38mA
Elitegroup Computer Systems
Total 1 Slot
Title
Power Delivery
Size Document Number Rev
C H61H2-M12 1.0
Date: Wednesday, July 13, 2011 Sheet 27 of 29
5 4 3 2 1
 5 4 3 2 1

9 V_1P05_PCH 7 EN CPUVTT
12

CPUVTT RT8121
D D

13 VTT_PWRGD 18 VCORE

38 EN_VTT VCORE
Bi-direction
19 SVDATA
17 VIDSOUT

VCORE RT8859A
40 VR_RDY
19 VR_RDY

Slot:PCIEx16/x1/LAN

21 SIO_PCIRST1_L SVDATA(B37) VCCCORE VCCIO

SIO_PCIRST2_L
C
21 C

21 SIO_PCIRST2_L CMOS 1.1V

RESET#(F36)

12 PCIRST2# 44 PCIRST3#
CPU
PCH Cougar Point Sandy Bridge
20 PLTRST_L
2 FP_PWRBTN_L LRESET 15 PLTRST#(BK48) SYS_PWROK(BJ53) Desktop Processor
35 PANSHW# Socket H2
POWER BUTTON 4 RSMRST_L
RSMRST# 45 RSMRST#(BK38) 16 CPU_PWROK
PROCPWRGD(D53) UNCOREPWRGOOD(J40)
3 3VSB 6 SLP4_L
31 SYS_3VSB SUSC# 37 SLP_S4#(BN52)

7 SLP3_L 15 CPU_BCLK
Super I/O SUSB# 32 SLP_S3#(BM53) CPUCLK(P31/R31) BCLK(W1/W2)
29 3VSB ITE 8758
5 SIO_PWRBTN_L
PWRON# 33 PWRBTN#(BT43)
B B

PWROK DRAMPWROK(BG46)
14 DRAM_PWROK SM_DRAMPWROK(AJ19)
54 ATXPG PWRGD[1..3] 32/18/78
11 PWROK(BJ38)
55 VIN1 36 PSON#

9 8 SYSRST_L
SYS_RESET#(BE52)
+VCC PSON_L
RESET BUTTON

4, 6, [21..23] 16
10 VCC5 PS_ON
ATX_PWRGD
8 PWROK

ATX_POWER
1 3VSB_IO 9 5VSB
A A

Elitegroup Computer Systems

Title
Power Sequence, Reset Diagram
Size Document Number Rev
Custom H61H2-M12 1.0
Date: Wednesday, July 13, 2011 Sheet 28 of 29
5 4 3 2 1
 +1.05V_RUN PCH SIO_PWRBTN#
PWRBTN#

Timing Diagram for S5 to S0 mode VCC

VCCIO
VCCUSBPLL
RSMRST#
PCH_RSMRST#

SIO_SLP_S5#
4
V_PROC_IO
+1.05V_M SLP_S5#
VCCCLK
VCCASW SIO_SLP_S4#
SLP_S4#
+1.5V_RUN SIO_SLP_S3#
VCCADAC1_5 SLP_S3#
VCCVRM
SIO_SLP_A#
5
+3.3V_ALW_PCH SLP_A#
VCCSUS3_3 SIO_SLP_LAN#
VCCSUSHDA SLP_LAN#
CPU +3.3V_RUN SIO_SLP_WLAN#
+VCC_CORE SLP_WLAN#/GPIO29
PM_DRAM_PWRGD_CPU VCCADACBG3_3
14 SM_DRAMPWROK VCC VCC3_3_R30
VCC3_3_R32
SYS_PWROK
SYS_PWROK
16
+VCCIO_OUT RESET_OUT#
VCC3_3
VCCIO_OUT PWROK
H_CPUPWRGD VCCCLK3_3
15 PWRGOOD +VCOMP_OUT 3 +3.3V_ALW 13
VCOMP_OUT VDDDSW3_3 PM_DRAM_PWRGD
DRAMPWROK

17
CPU_PLTRST#_R
PLTRSTIN
+1.35V_MEM 14
VDDQ PCH_PLTRST#
17 PLTRST# H_CPUPWRGD

PM_APWROK_R
PROCPWRGD
15
7 APWROK

PCH_DPWROK
DPWROK
4
Pop option
DGPU_PWR_EN# DGPU_PWR_EN
GPIO54 DMN65D8LW-7 11

+3.3V_ALW
LCD_ENVDD_SW
+LCDVDD TPS22965
GPIO17
DGPU_PWROK MXM 12
+3.3V_ALW
Pop option
SIO_SLP_LAN# DGPU_PEX_RST#
6 +3.3V_M +3.3V_LAN TPS22965

17

+5V_ALW Power Button

RUN_ON
SIO_SLP_S3#
+5V_RUN +5V_HDD
SIO 5048 TPS22965 1BAT 2AC
SIO_SLP_S4# +3.3V_ALW
+PWR_SRC 1BAT
5 ADAPTER
SIO_SLP_M#
TPS22965 +3.3V_RUN 9 ALWON +5V_ALW
SIO_SLP_LAN#
EC 5075 TPS5125
+3.3V_ALW 2AC
+1.05V_M
ALW_PWRGD_3V_5V

SI4164DY +1.05V_RUN
1.35V_SUS_PWRGD
+3.3V_ALW BATTERY 5048

SYN470DBC +1.5V_RUN
DGPU_PWROK

PCH_RSMRST#
MXM
DGPU_PWR_EN 4
11 +PWR_SRC
+3.3V_ALW
+PWR_SRC_MXM PCH_ALW_ON
IMVP_VR_ON
ISL95812 +VCC_CORE 12 TPS22965 +3.3V_ALW_PCH 3
10 +MXM_PWR_SRC SI4835D 3.3V_RUN_GFX_ON
PM_APWROK
IMVP_PWRGD
7 +3.3V_ALW
6 Pop option
A_ON
+3.3V_ALW TPS22965 +3.3V_M +3.3V_LAN
10 +3.3V_MXM 3.3V_RUN_GFX_ON +PWR_SRC 8 RESET_OUT#
TPS22965 SUS_ON 14 +PWR_SRC
+1.35V_MEM VDDQ A_ON
0.75V_DDR_VTT_ON
RT8207MZ VTT
DDR TPS51212 +1.05V_M 6
+5V_ALW +0.675V_DDR_VTT SIO_SLP_S5#
10 +5V_MXM 3.3V_RUN_GFX_ON
1.35V_SUS_PWRGD
5 1.05V_A_PWRGD
TPS22965 5075
+3.3V_ALW +PWR_SRC
+3.3V_ALW
MCARD_MISC_PWREN
SUS_ON
TPS22965 +3.3V_SUS 8
PCH_ALW_ON
TP0610K +PWR_SRC_S 3
+3.3V_PCIE_FLASH
TPS22965
+5V_ALW
+3.3V_ALW
MODC_EN
+3.3V_WLAN
TPS22965
AUX_EN_WOWL TPS22965 +5V_MOD 12
+PWR_SRC
+3.3V_ALW EN_INVPWR
NVRAM_PWR_EN FDC654P +BL_PWR_SRC
+3.3V_PCIE_WWAN
TPS22965 BC BUS
 5 4 3 2 1

Wistron HURON RIVER POWER UP SEQUENCE DIAGRAM

5V_S5 DCBATOUT
-6
AC AD+
Adapter in
Page38
-3a -3a -3a 3a
VDDP VIN 1D5V_S3
D PWR_5V3D3V_ENC 3V_5V_EN S5_ENABLE VOUT D

3
PM_SLP_S4#
EN
-3b -3c DDR_VREF_S3 3b
PWR_CHG_ACOK REF
SWITCH ENC 5V_S5 15V_S5
LL1 PUMP
Page40
3D3V_S5 TPS51216RUKR
LL2
SWITCH 5a 0D75V_S0
Page40 5V_AUX_S5 VTT
TPS51123RGER VREG5 1.05VTT_PWRGD
DC/DC 3D3V_AUX_S5 -4 VTT_EN
-5 (3V/5V) VREG3 3 RUNPWROK
PGD

DCBATOUT 3V_5V_POK PM_SLP_S4# Page46

VIN PGOOD 5
Page41

4 5V_S5 3D3V_S5
DC BQ24707 5V_S0
BT+ PM_SLP_S3#
Battery Charger SWITCH
Page39 -3 Page37
3D3V_AUX_KBC -3a VDD VIN 1D8V_S0
VOUT
Page40 ACOK 3D3V_S0 4
S5_ENABLE SWITCH
-6a Page37 PM_SLP_S3# TPS53311RGTR
EN
RUNPWROK
AC_IN# GPIO34 1D5V_S0
PGD
GPIO70 Page47
C SWITCH C

Page37 5
1 SLP_S4# SLP_S3#
-1 KBC
KBC_PWRBTN#
GPIO6 NPCE795P -2
9 AND GATE
Power Button PM_RSMRST# 0D75V_EN
PM_SLP_S4# GPIO43 RSMRST# B VDDPWRGOOD
GPIO44 PM_PWRBTN# PM_DRAM_PWRGD Y SM_DRAMPWROK
PM_SLP_S3# GPIO20 PWRBTN# DRAMPWRGD A
GPIO01
2 H_CPUPWRGD H_CPUPWRGD_R
PROCPWRGD UNCOREPWRGOOD
Page27 Cougar Point 10
GPIO77 PCH Sandy Bridge
8
15 CPU
S0_PWR_GOOD
APWROK
PWROK PLT_RST# BUF_CPU_RST#
PLTRST# RSTIN#
SYS_PWROK SVID
SYS_PWROK

SVID
14
11
5V_S5 DCBATOUT

B V5IN VIN 1D05_VTT 5a B

VOUT
5
RUNPWROK TPS51218DSCR
EN 1.05VTT_PWRGD
Page45 PGOOD
14
5V_S5 DCBATOUT 5b IMVP_PWRGD SYS_PWROK

VDDP VIN 0D85_S0 5c -4

VOUT
5b -7 3D3V_AUX_S5
1.05VTT_PWRGD TPS51461RGER RTC_AUX_S5
EN D85V_PWRGD
Page48 PGOOD -8
+RTC_VCC
6
DCBATOUT
RTC battery

11 VIN VCC_CORE
OUTPUT
SVID 12
A
SVID
VR OUTPUT VCC_GFXCORE A

6 7 ISL95831HRTZ
D85V_PWRGD IMVP_VR_ON 13 DV15 HR Vos GIGA HDMI NoSurge
VR_ON IMVP_PWRGD
Page42 & 43 & 44 PGOOD
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Power Up Sequence: -8 ~ 15 Title

Size Document Number

Power Sequence Diagram
Rev
A2
Enrico/Caruso 15 HR X01
Date: Thursday, June 02, 2011 Sheet 99 of 104
5 4 3 2 1