_

Subject Code: C3801

M.Tech I Semester [R09] Regular Examinations,April 2011
Digital System Design
(DECS, DSCE, VLSI&ES, VLSID&VLSD/VLSI)
Time: 3 Hours Max Marks: 60
Answer any FIVE questions All questions carry EQUAL marks
_
1. a) What are the basic building blocks of an ASM chart? Explain about
these blocks.
b) Describe the rules for state assignment. Give an example.
2. Describe the design of Iterative circuits and sequential circuits using
ROMs and PLAs
3. a) Explain the procedure involved in the path sensitization technique
with an example.
b) Give the classification of faults that may occur in digital circuits with
examples.
4. a) Explain the procedure involved in D- Algorithm with an example.
b) With an example explain about the transition count testing method.
5. a) Distinguish between maximum folding and optimum folding.
b) With an example explain about minimization and folding of a PLA
using SCF method.
6. Explain the Design of fault detection experiment.
7. a) Describe various faults that may occur in PLAs.
b) Discuss briefly about testable PLA design.
8. Write short notes on
i) flow table
ii) state reduction
iii) cycles and hazards
_

Subject Code: C5502

M.Tech I Semester [R09] Regular Examinations,April 2011
Embedded Systems Design
(ES, VLSI&ES, VLSID&VLSD/VLSI)
Time: 3 Hours Max Marks: 60
Answer any FIVE questions All questions carry EQUAL marks
_
1. a) Write about processor in an embedded system and other hardware
units.
b) Write about processor based embedded system design concepts.
2. a) Write about the internal processor design.
b) Write about RAM and ROM.
3. a) Explain about Bus arbitration and timing.
b) Write about I/O components and performance.
4. a) Explain about above drivers with suitable examples.
b) Write about On-board bus device drivers.
5. a)_write about Embedded operating systems.
b) write about Board support packages. .
6. a) Write about Multitasking and process Management.
b) Write about Middleware and Application Software.
7. a) Explain CAD and the hardware.
b) Write about Debugging tools.
8. Decribe briefly about
a)POSIX.
b)Implementing the design.
_

Subject Code: C5503

M.Tech I Semester [R09] Regular Examinations,April 2011
Analog and Digital IC Design
(ES, VLSI&ES, VLSID&VLSD/VLSI)
Time: 3 Hours Max Marks: 60
Answer any FIVE questions All questions carry EQUAL marks
1)
__ a) Explain the operation of a Wilder current source with a neat diagram.
b) Assuming the slew rate of op-amp is 0.3V/μs, justify whether it is possible
to amplify a
square wave of peak – to – peak value 400mV, with a rise time of 3 μs or less,
to a
peak – to – peak amplitude of 4.5 V .
2) a) Derive the expressions for the lock-in and capture ranges of IC 565 PLL.
b) What are the applications of PLL?
3) a)Prove that the input impedance for this common gate amplifies is much
larger
than1/8m1.
b) What is parasitic sensitive integrator and explain briefly?
4. a)What are the factors that affect gate – source voltage – explain?
b) Explain the importance of voltage controlled oscillators and how do you
classify
the oscillators.
5) a)Write data flow style VHDL program for a 8 bit multiplexer
b) Write a VHDL model of 2 to n priority encodes.
6) a) Discuss in detail ROM access mechanism with the help of timing
mechanism
b) Compare CMOS, TTL and ECL with reference to logic levels, propagation
delay and fan-out.
7) a) Write a behavior model of negative edge triggered JK flip flop with set
and clear.
b) Briefly explain FPGA classification based on CLB arrangement.
8) a) Explain successive approximation A/D converter with a neat circuit
diagram
b) Draw and explain the Nyquist rate D/A converter using binary scaled
converter.

Subject Code: C3802

M.Tech I Semester [R09] Regular Examinations, March/April
2011
VLSI Technology and Design
(DECS, DIP, DSCE, ECE, ES, SSP, VLSI&ES, VLSID&VLSD/VLSI)
Time: 3 Hours Max Marks: 60
Answer any FIVE questions All questions carry EQUAL marks
_
1. a) Explain the operation of enhancement mode MOS transistor and
give the conditions
for different regions of operation in terms of Vgs,Vds,Vt?
b) Compare the CMOS technology and bipolar technologies?
2. a) Derive the expression for drain to source current for an NMOS
enhancement
mode transistor in non-saturated or linear region?
b) Determine of pull up to pull down ratio(Zpu/Zpd) ?
3. a) Explain scalable design rules?
b) What is the importance of layout diagram and write about layout
design and
tools?
4. a) Explain briefly about switched logic and also explain pass
transistors and
transmission gates .how transmission gates are advantageous than
transmission
gate?
b) Design parity generator with neat sketch?
5. a) Describe the rules of for floor planning?
b) What are the chip design methodologies and explain them briefly?
6. a) What are the different types of memories and explain basic
transistor SRAM
cell?
b) Explain system level testing techniques with a neat diagram?

7. Explain the terms

` a) architecture design
b) High level synthesis
c) Power optimization in CMOS circuits
8. a) Write short notes on CAD tools for design and simulation?
b) Explain layout synthesis and analysis in chip design?