Altera Tutorial Quartus I

Graduate Institute of Electronics Engineering, NTU
Introduction to Quartus II
Adviser: An-Yu Wu
Speaker: 張龍豪
Date: 12/25/2002
ACCESS IC LAB
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU
Outline
9 Introduction
¾ Design Entry
¾ Project Compilation
¾ Timing analysis
¾ Function simulation
¾ Device Programming
¾ Conclusion
12/25/2002 PP. 2
Introduction to Quartus II
¾ Operate in a self-contained environment
Design Design Verification &
Entry Compilation Programming
•Graphic Design Entry •Logic Synthesis •Timing simulation

and Fitting
•Megafunctions •Functional simulation
•Text Design Entry •Timing analysis
•Hierarchical Design Entry •Device Programming
12/25/2002 PP. 3
Quartus II Design Methodology

Design Specification
Design Entry
Design Modification
Project Compilation
simulation
Timing analysis
Device programming
In-System Verification
System Production
12/25/2002 PP. 4
Outline
¾ Introduction
9 Design Entry
¾ Timing analysis
¾ Conclusion
12/25/2002 PP. 5
Design Entry Process

¾ Project Setup/Management
¾ Multiple design entry methods
MAX+PLUS II
Graphic design entry
Text design entry
AHDL, VHDL, Verilog
3rd party EDA tools
EDIF, OrCAD schematics
Add flexibility and optimization to the Design entry
process by:
mixing and matching design files
using and Megafunctions to accelerate design entry
12/25/2002 PP. 6
Project Setup/Management
¾ What is a Project?
A design file
A project is:
checked for design entry errors
compiled
simulated (functional or with timing)
analyzed for timing
used to generate programming file
¾ Projects can be archived
12/25/2002 PP. 7
New Project Wizard

¾ Select File => New Project
Wizard
Working Directory
Project name
Top-level design name
¾ Save as *.QAR (QuARtus)
Click finish
12/25/2002 PP. 8
New Project Wizard

Add design files
•Graphic (.BDF, .GDF)
•AHDL/VHDL/Verilog
•EDIF
Note:
•All files in the project
directory do not need to
be added
Add user library

pathnames and files
12/25/2002 PP. 9
New Project Wizard
Review result and

click on finish
12/25/2002 PP. 10
Block Diagram/Schematic File Editor

¾ Block diagram entry is mainly for top-down design
methodology
¾ Schematic file entry is the traditional schematic
design entry
¾ User can enter blocks, primitives, and megafunctions
from Quartus II-provided or user libraries
¾ Provides “smart” block connection and mapping
12/25/2002 PP. 11
Block Editor – Create a New File

¾ Select File => New
¾ Select Block Diagram /
Schematic File
¾ Save as *.BDF (Block
Design File)
¾ Add file to current project
Click OK
12/25/2002 PP. 12
Block Design File
Block and
symbol editors
12/25/2002 PP. 13
Block Editor – Enter Symbols

¾ Schematic file entry
¾ Click the symbol tool button
Symbol library Preview the symbol

12/25/2002 PP. 14
Block Editor – Use Megafunction

¾ Click MegaWizard Plug-In Manager
Click
12/25/2002 PP. 15
Create a New Symbol

¾ Custom megafunction variations are based on Altera-
provided megafunctions.
¾ Select the Megafunction item that you want to create.
¾ Modify the item by your own.
12/25/2002 PP. 16
Create a New Symbol (cont.)
Input cell
name
Click Finish
12/25/2002 PP. 17
Create a New Symbol (cont.)
Click OK
12/25/2002 PP. 18
Block Editor – Draw Block

¾ Text Design Entry
¾ Click the Block Tool button
¾ Click and drag on the block diagram
and you can see the Block symbol
12/25/2002 PP. 19
Block Editor – Specify I/Os

¾ Right click on the block symbol,
choose Block Property
¾ Select I/Os, input your I/O
name and type
Click OK
12/25/2002 PP. 20
Block Editor – Make connections

Wire (single bit line)
Bus (Multiple bits)
Conduit (Multiple bits)
Wire
Bus
conduit
Connects blocks to
any other objects
12/25/2002 PP. 21
Block Editor – Mapper properties

¾ Map the block I/Os when the I/O names are different
between the blocks.
¾ Label the connector
Right-click on the connector and choose Properties
12/25/2002 PP. 22
Block Editor – Mapper properties (cont.)

¾ Double-click on the mapper
¾ Set the I/O on block and connector signal
Double-click on the mapper
12/25/2002 PP. 23
Block Editor – Make connections

¾ Now, the I/Os are connected
12/25/2002 PP. 24
Block Editor – Add I/O pins

¾ Click the symbol tool button
Click OK
12/25/2002 PP. 25
Block Diagram
¾ Arrange the Blocks, Primitives, and Megafunction
12/25/2002 PP. 26
Block Editor – Generate Design File

¾ Right-click on block symbol
¾ Select Create Design file from Selected Block
Input file
name
Click OK
12/25/2002 PP. 27
Create Design File

These lines are necessary
for Quartus II to update
the source code
Your design
12/25/2002 PP. 28
Block Editor – Generate Design File

¾ Select File => New
Click OK
12/25/2002 PP. 29
Outline
¾ Introduction
¾ Design Entry
9 Project Compilation
¾ Timing analysis
¾ Conclusion
12/25/2002 PP. 30
Compiler Settings
¾ Compiler control information
Level of compilation
Device & Device options
Pin assignments
Synthesis & Fitting
Timing analysis
¾ Accessed via the Processing Menu
¾ Information stored in a Compiler Settings File (*.CSF)
12/25/2002 PP. 31
Compiler Settings – General

¾ Select processing =>
Compile Mode
¾ Select processing =>
Compiler Settings…
12/25/2002 PP. 32
Compiler Settings – Chips & Devices
12/25/2002 PP. 33
Pin assignment – all I/Os

¾ Select a pin number
¾ Invoke Node Finder to find pin name or type
Available
I/Os
Click
12/25/2002 PP. 34
Pin assignment – Add I/Os

¾ Select Filter: Pins: all and click Start
¾ Add to assignment list
Click OK
12/25/2002 PP. 35
Compiler Settings – Mode
12/25/2002 return PP. 36

Compiler Settings – Synthesis & Fitting
12/25/2002 PP. 37
Compiler Settings – Verification
12/25/2002 PP. 38
Compiling in Quartus II
¾ Select Processing => Start Compilation
Compilation
Result
Compiler
Report
Status Bar
Compiler Messages
12/25/2002 PP. 39
The Compiler Report

¾ Contains all information on how a design was
implemented in the targeted device
Device Summary Statistics
Compiler Settings
Floorplan Views
Device Resources Used
State Machines Implemented
Equations
Timing Analysis Results
CPU Resources
¾ This a read-only window
12/25/2002 PP. 40
Outline
¾ Introduction
¾ Design Entry
9 Timing analysis
¾ Conclusion
12/25/2002 PP. 41
Reporting Timing Results

Timing information is part of the Compilation Report
Summary Timing Analyses
fmax (not include delays to/from pins) or
fmax (include delays to/from pins)
Register-to-Register Table
tsu (Input Setup Time)
th (Input Hold Time)
tco (Clock to Out Delays)
tpd (Pin to Pin Delays)
All timing results are reported here
12/25/2002 PP. 42
Outline
¾ Introduction
¾ Design Entry
¾ Timing analysis
9 Function simulation
¾ Conclusion
12/25/2002 PP. 43
Simulations
¾ Run Functional Simulation
Fast compilation
Logical model only, no logic synthesis
All nodes are retained and can be simulated
Outputs are updated without delay
¾ Run Timing Simulation
Slower compilation
Timing model: logical & delay model
Nodes may be synthesized away
Outputs are updated after delay
12/25/2002 PP. 44
Create Waveform file

¾ Create a waveform for
simulation
¾ Select File => New =>
Other Files
¾ Select Vector Waveform
File
¾ Save as *.VWF (Vector
Waveform File)
Click OK
12/25/2002 PP. 45
Setup end time

¾ Specify maximum length of simulation end time
Select Time => End time
Waveform Editor Window

12/25/2002 PP. 46
Add I/O pins – select

¾ Select View => Auxiliary Windows => Node Finder
¾ Select Filter: Pins: all and Click Start
¾ Select all pin and drop them into the Name in
waveform file
Click
Start
12/25/2002 PP. 47
Add I/O pins

¾ All pins are in the Name list
¾ With initial values or Hi-Z
12/25/2002 PP. 48
Creating a Clock
¾ Right-click on the waveform name and choose Value
=> Clock
12/25/2002 PP. 49
Creating Counting Pattern

¾ Right-click on the waveform name and choose Value
=> Count Value
12/25/2002 PP. 50
Input value
¾ All input pins have input values
12/25/2002 PP. 51
Simulator Settings – General

¾ Select Processing =>
Simulate Mode
¾ Select Processing =>
Simulation Settings
12/25/2002 PP. 52
Simulator Settings – Time/Vectors
12/25/2002 PP. 53
Simulator Settings – Mode
Refer to PP. 36
12/25/2002 PP. 54
Simulator Settings – Options
12/25/2002 PP. 55
Simulator Result
¾ Select Processing => Start Compilation
Master time bar handle New time bar handle
12/25/2002 PP. 56
Outline
¾ Introduction
¾ Design Entry
¾ Timing analysis
9 Device Programming
¾ Conclusion
12/25/2002 PP. 57
APEX 20K Configuration Overview

¾ APEX 20K devices are SRAM-based
Must be reconfigured with every power-up
¾ Can configure the APEX 20K device via configuration
device or download cable
¾ APEX 20K family supports configuration through its
JTAG ports
12/25/2002 PP. 58
ByteBlaster
JTAG port
12/25/2002 PP. 59
Configuration
¾ Select Processing => open programmer
¾ Save as *.CDF (Chain Description File)
12/25/2002 PP. 60
Configuration
¾ Select Setup => Add => Hardware Setup dialog box,
select ByteBlasterMV
Click Add
12/25/2002 PP. 61
Configuration
¾ Select Add File => *.SOF (SRAM Object File)
¾ Check on Program/Configure.
Click Start
12/25/2002 PP. 62
Conclusion
¾ Use Hierarchical Design methodology
¾ Use Hierarchy Display for fast access to design file at
any level
¾ Compile top-level design without any pin assignments
first to determine if the design actually fits in the
targeted device
¾ Use Compiler Report to study design implementation
and resource usage
¾ Use Functional Simulation to verify proper operation
12/25/2002 PP. 63

Altera Tutorial Quartus I

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Altera Tutorial Quartus I

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Graduate Institute of Electronics Engineering, NTU

•Graphic Design Entry •Logic Synthesis •Timing simulation

Quartus II Design Methodology

Design Entry Process

New Project Wizard

New Project Wizard

Add user library

New Project Wizard

Review result and

Block Diagram/Schematic File Editor

Block Editor – Create a New File

Block Design File

Block Editor – Enter Symbols

Symbol library Preview the symbol

Block Editor – Use Megafunction

Create a New Symbol

Create a New Symbol (cont.)

Create a New Symbol (cont.)

Block Editor – Draw Block

Block Editor – Specify I/Os

Block Editor – Make connections

Block Editor – Mapper properties

Block Editor – Mapper properties (cont.)

Double-click on the mapper

Block Editor – Make connections

Block Editor – Add I/O pins

Block Editor – Generate Design File

Create Design File

Block Editor – Generate Design File

Compiler Settings – General

Compiler Settings – Chips & Devices

Pin assignment – all I/Os

Pin assignment – Add I/Os

Compiler Settings – Mode

12/25/2002 return PP. 36

Compiler Settings – Synthesis & Fitting

Compiler Settings – Verification

The Compiler Report

Reporting Timing Results

Create Waveform file

Setup end time

Waveform Editor Window

Add I/O pins – select

Add I/O pins

Creating Counting Pattern

Simulator Settings – General

Simulator Settings – Time/Vectors

Simulator Settings – Mode

Simulator Settings – Options

Master time bar handle New time bar handle

APEX 20K Configuration Overview

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