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Resonant Tunneling Devices:

physics, technology and


applications

Alessandro Cidronali
Dept. Electronics and Telecomm. Univ. of
Florence

A. Cidronali, Dept. Electronics and Telecommunications, University of Florence – Italy # 1/53


Outline

• motivations
• RTD basics
• RTDs physics and models
• Applications
Š Exploitation of the NDR
Š Digital applications (gate logic, memory)

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Beyond the MOSFET

Moore's laws • Mesoscale :


• Integration has quadrupled every
Š An intermediate scale, on the order of ~10
three year nm,
• Minimum dimension has been Š Materials have some properties of bulk
scale by 0.7 material, but surface effects are important,
Š And more quantum phenomena become
important
• Bulk :
Š Materials & structures fabricated using bulk
processes with atomic precision
• Electronics :
Š Electron states are used for primary
information-processing operations
ƒ not photons (optical), or whole atoms
(mechanical)

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What happens @ mesoscale?

• MOSFET scaling hampered by quantization of:


Š charge:
ƒ becomes important @ L ≈ 10 nm in all materials
Š energy levels:
ƒ important in semiconductors @ L ≈ 10 nm
• Can alternative device operating principles exploit these
quantization effects rather than be hampered by them?
• Some approaches:
Š Single-electron transistors
Š Quantum wells / wires / dots, quantum-dot CAs
Š Resonant tunneling diodes / transistors
A. Cidronali, Dept. Electronics and Telecommunications, University of Florence – Italy 6/29/2005 # 4/53
Resonant Tunneling Diodes

• Usually based on quantum wells or wires


Š 1-2 effectively “classical” degrees of freedom

Source Drain
Island (narrow bandgap)
Tunnel barriers (wide bandgap)
Electron tunnels
through barrier
Quantized momentum state
Electron flow Unoccupied states
Occupied states in
conduction band

Energy
A. Cidronali, Dept. Electronics and Telecommunications, University of Florence – Italy 6/29/2005 # 5/53
Resonant Tunneling Transistors

• Like RTDs, but an adjacent gate electrode helps adjust the energy
levels in the island

Gate

Source Drain

Electron reflection Gate controlled charge induction

Occupied states in
conduction band

A. Cidronali, Dept. Electronics and Telecommunications, University of Florence – Italy 6/29/2005 # 6/53
Why RTDs?

• Intrinsic bistability and high-speed switching


capability (e.g., 1 ps switch, fmax~1 THz)
• Low power consumption
• Small device footprint
• Increased functionality

A. Cidronali, Dept. Electronics and Telecommunications, University of Florence – Italy 6/29/2005 # 7/53
How does an RTD work?

Peak current density: IP=ION


Peak-to-valley current ratio (PVCR)
= ION/IVALLEY

A. Cidronali, Dept. Electronics and Telecommunications, University of Florence – Italy 6/29/2005 # 8/53
Valley Current

Š Theory underestimates valley current


I because of:
IP
ƒ (i) scattering by phonons and impurities
ƒ (ii) extra tunneling via impurity states in the
barriers

IV ƒ (iii) tunneling via X and L states/bands


ƒ (iv) disorder in alloy barriers
V
ƒ (v) interface steps and roughness

A. Cidronali, Dept. Electronics and Telecommunications, University of Florence – Italy 6/29/2005 # 9/53
Typical RTD structures

A. Cidronali, Dept. Electronics and Telecommunications, University of Florence – Italy 6/29/2005 # 10/53
III-V RTDs

• GaAs family
Š AlGaAs/GaAs/AlGaAs
• InP family (IP=500 kA/cm2, PVCR=52)
Š InGaAs/AlAs/InAs

A. Cidronali, Dept. Electronics and Telecommunications, University of Florence – Italy 6/29/2005 # 11/53
RITDs

• p-n type I heterojunction double quantum well RITD

PVCR = 144
H. H. Tsai, et al., IEEE EDL, Vol. 15, no. 9, Sep. 1994
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RTDs in other materials systems:
Molecular RTDs
• Small (~1.5 nm): ultra-dense IC based on poly-
phenylene
• Natural nanometer-scale structure: identical in vast
quantities
methylene

James C. Ellenbogen, “A brief overview of nanoelectronic devices”


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A. Cidronali, Dept. Electronics and Telecommunications, University of Florence – Italy 6/29/2005 # 14/53
Conventional Methods of Device Modeling

• Electrons are waves. de Broglie wavelength of an electron is:


h/p,
where p is the momentum
• Device dimensions are much larger than the electron wave length
• Transit time through the device is much larger than the scattering
time
• Diffusion equation for semiconductors

Diffusive Ballistic Phase-coherent

A. Cidronali, Dept. Electronics and Telecommunications, University of Florence – Italy 6/29/2005 # 15/53
Transport processes in RTD

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Quantum device modeling

A. Cidronali, Dept. Electronics and Telecommunications, University of Florence – Italy 6/29/2005 # 17/53
coherent approach: Scroedinger eq.

Boundary conditions !
The system is open since there is a current flux.
Usual boundary conditions, like infinite barrier or periodic repetition of the system, cannot be
used.
A. Cidronali, Dept. Electronics and Telecommunications, University of Florence – Italy 6/29/2005 # 18/53
Transfer Matrix: envelope function

A. Cidronali, Dept. Electronics and Telecommunications, University of Florence – Italy 6/29/2005 # 19/53
Tunneling current

A. Cidronali, Dept. Electronics and Telecommunications, University of Florence – Italy 6/29/2005 # 20/53
Self-consistent calculations

A. Cidronali, Dept. Electronics and Telecommunications, University of Florence – Italy 6/29/2005 # 21/53
Wigner function

∂ 1.Change of basis
i= ψ ( x, t ) = Hˆ ψ ρ ( r, s, t ) = ψ ( r, t ) ⋅ ψ ( s, t )
∂t
Density matrix 2.Fourier transform

+∞
n (r ) = ∫ f W (r , k )dk
−∞
+∞
J (r ) = −q ∫ k ⋅ f W (r , k )dk
−∞

A. Cidronali, Dept. Electronics and Telecommunications, University of Florence – Italy 6/29/2005 # 22/53
Wigner function: results

Simulated GaAs RTD structure: equilibrium Self-consistent, steady-state RTD I-V curve
selfconsistent conduction band, Fermi levels, showing negative differential resistance,
and doping. The 0.3 eV Al0.3 Ga0.7 As tunnel hysteresis, and bistability.
barriers are 3 nm thick, and the GaAs The RTD is unstable (oscillates perpetually) in
quantum well width is 5 nm. The center 17 nm the plateau between 0.239 V and 0.254 V, and
of the device (including 3 nm outside each it is marginally stable (oscillates with slow
tunnel barrier) are undoped. damping) in the remainder of the plateau.
Biegel and Plummer IEEE TED-44, 733 (1997)
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Wigner function: results

A. Cidronali, Dept. Electronics and Telecommunications, University of Florence – Italy 6/29/2005 # 24/53
Applications

• Analog circuits ------ NDR & I\V square law


• Digital Logic ------ Bistability

A. Cidronali, Dept. Electronics and Telecommunications, University of Florence – Italy 6/29/2005 # 25/53
the HITFET structure for uW
Applications: QMMIC
HITD grown by MBE on top of HEMT layers
improved Esaki diode (+1 well\1barrier): higher
better Jp/Jv and Fmax
reliability
because InP substrate, PVCR~50, Fmax~60GHz
p+ - InGaAs Top contact layer (anode)
drain
nid - InAlAs Barrier H
nid - InGaAs Well I
p++ T
source n++ - InAlAs Ohmic contact D
gate n++ n+ InGaAs Bottom contact layer (catode)
Ohmic
nid - InAlAs Schottky contact (gate)
InAlAs Schottky
n- InGaAs Si δ-doping H
InAlAs Spacer F
nid - InAlAs Spacer
InGaAs channel E
nid - InGaAs Channel T
InAlAs buffer
InP substrate nid - InAlAs Buffer

InP Substrate

A. Cidronali, Dept. Electronics and Telecommunications, University of Florence – Italy 6/29/2005 # 26/53
The drain-HITFET reflection
coefficients
at 6.2GHz, Vdrain=500mV as seen from the:

8
CD-HITFET 7

bias

dB(Γ)
5

Γ 2
-0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5
Vgs
Γ -50

CS-HITFET
phase(Γ) -60

bias
-70

-80
-0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5

Vgs
A. Cidronali, Dept. Electronics and Telecommunications, University of Florence – Italy 6/29/2005 # 27/53
HITFET based VCO
topologies\prototypes
Common-Drain (CD) VCO Common-Source (CS) VCO

V_DC Lr
V_DC

HITD Cr

HITFET
RF-Port
HEMT

HITD

Rc Ca HITFET
HEMT
Lr Cr RF-Port Rc

V_T
V_T

prototypes, all working at the bias voltage Vdc=0.5V :

‘A’ : CD-VCO @ 6.1GHz ‘B’ : CS-VCO @ 6.3GHz

A. Cidronali, Dept. Electronics and Telecommunications, University of Florence – Italy 6/29/2005 # 28/53
HITFET based VCO prototype ‘A’

6.3 -14

6.25 -17
Oscillation Frequency [GHz]

Power Output [dBm]


6.2 -20

6.15 -23

6.1 -26

6.05 -29

6 -32
-0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5

Tuning Voltage [V]

output frequency 6.18 GHz


output power -16dBm
tuning range 140 MHz
SSCR -105dBc/Hz @ 5MHz
efficiency 3%
power supply 850µW
supply voltage 500mV
die size 450x550µm2

A. Cidronali, Dept. Electronics and Telecommunications, University of Florence – Italy 6/29/2005 # 29/53
HITFET based VCO prototype ‘B’

6.38 -14

-17
Oscillation Frequency [GHz]

6.378

to S.A.

Power Output [dBm]


-20
6.376
-23
Rc=1KΩ
6.374
-26
Lext

6.372
-29
V_T V_dd=0.5mV

6.37 -32
-0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5

Tuning Voltage [V]

output frequency 6.37 GHz


output power -17dBm
tuning range 3 MHz
SSCR -97dBc/Hz @ 230KHz
efficiency 3%
power supply 850µW
supply voltage 500mV
die size 450x550µm2

A. Cidronali, Dept. Electronics and Telecommunications, University of Florence – Italy 6/29/2005 # 30/53
figure of merit (4-6.5GHz)

⎛f ⎞⎟2 1
175
FOM = ⎜⎜ 0 ⎟⎟
170
[11] ⎝ fn ⎠ PDC ⋅ SSCR ( fn )
[13]
[12] 1. Arhens, MOS w/ resonator, proc. ISSC 1996
165
[this work: prot.’B’ ] 2. Kinget, 0.35um CMOS, proc. ISSC 1998
[this work: prot.’C’ ]
160
Figure of Merit, dB

3. Shealy, GaN FET, IEEE MWCL 2001


[this work: prot.’A’ ]
155 [9] 4. Yu, InP HBT, IEEE MWCL 2001
[10]
5. Mostafa, 0.35um CMOS sub-1V, IEEE T-CS-II 2001
150
6. Mostafa, 0.35um CMOS, proc. IEEE CS 2001
145 [5] [6]
[7] [8] 7. Loo, BJT differential, 2000 Canadian Conf.
[2] 8. Liu, 0.35um CMOS, proc. ISSC 1998
140 [1]
[4]
9. Vaananen, 0.35um BiCMOS, IEEE JSSC 2001
135
10. Van de Ven, LC MOS, 2001 Sym. VLSI
130
Si - devices
11. Ellinger, classE GaAs VCO, IEEE T-MTT 2001
III-V - devices [3]
12. Deval, Synchronous CMOS VCO, IEEE RFIC Sym. 2001
125
4 4.5 5 5.5 6 6.5
13. Klepser, SiGe BiCMOS, IEEE RFIC Sym. 2001
freq, GHz

HITFET-VCOs
HITFET-VCOsshow
showthe
thelowest
lowestpower
powersupply
supply
A. Cidronali, Dept. Electronics and Telecommunications, University of Florence – Italy 6/29/2005 # 31/53
the QMMIC limitation

• Not all the active functions can be replaced; e.g.


difficult to replace LNA, PA, Switch

• On a one-to-one basis, the individual functions in


QMMIC could be more effective than conventional
ones (e.g. VCOs and mixers)

• In the overall budget, however, the benefit might


be marginal

A. Cidronali, Dept. Electronics and Telecommunications, University of Florence – Italy 6/29/2005 # 32/53
the QMMIC as enabling technology

How to improve the effectiveness taking advantage of


the unique features of QMMIC technology?
By introducing appropriate architectures whose
application is enabled by the features of QMMIC
technology
- enabling technology approach -

the Quantum Bi-Directional Amplifer (QBDA) for

Tagging Applications

A. Cidronali, Dept. Electronics and Telecommunications, University of Florence – Italy 6/29/2005 # 33/53
Bi-directional amplifier based on HITD

The basic idea:


The reflection coefficient (Γ) of a device exhibiting a NDR is >1
Combining by a 90° directional coupler two HITDs, the output
signal is Γ times the input one
The scattering matrix
is of the form:
Γa*0.5+Γ(j*j)a*0.5=0 a/ 2 NDR
device
input:a
Γ(a / 2)
Sr St
ouput: S =
Γja*0.5+Γja*0.5
ja / 2
St Sr
Γ(ja/ 2) NDR
device

A. Cidronali, Dept. Electronics and Telecommunications, University of Florence – Italy 6/29/2005 # 34/53
QBDA prototype
10
A Quantum MMIC bi-directional amplifier has been

dB(S12), dB (S21)
demostrated @ 5.8GHz; main characteristics: 5

450mV\0.5mA power supply, gain 4.7dB. More work to


0

dB(S(1,2))
dB(S(2,1))
control the HITD parameters is required.
-5

-10

-15
3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0

freq, GHz

dB(S11), dB (S22)

A. Cidronali, Dept. Electronics and Telecommunications, University of Florence – Italy 6/29/2005 # 35/53
An application of the QBDA: the PM
reflective TAG
Terminating a port of the QBDA by a two-state load (e.g. a HITD
properly biased) a reflection equal to 2 times the QBDA gain is
obtained with a phase swing of 180°

QBDA

A. Cidronali, Dept. Electronics and Telecommunications, University of Florence – Italy 6/29/2005 # 36/53
An application of the QBDA:
the PM reflective TAG

0.02 200

Terminating a 0.01
150

port of the 100


10*inc

d3, mV
ref, V

0.00

QBDA by a two- 50

-0.01
state load (e.g. a 0

HITD properly -0.02


8 10 12 14
-50

biased) a time, nsec

reflection equal
to 2 times the 200
430

QBDA gain is 150


420

410
obtained with a

d2, mV
d1, mV
d3, mV

100
400
phase swing of 50 390

180° 0 380

370
-50
8 9 10 11 12 13 14 15
0 20 40 60 80 100
time, nsec
time, nsec

A. Cidronali, Dept. Electronics and Telecommunications, University of Florence – Italy 6/29/2005 # 37/53
QMMIC Summary

Highlights:
– TDs may be considered as an optimizing technology for
extremely low power (<500mV) RF electronics, (e.g. VCO).
– new circuit functionalities are enabled by Tunnel Devices.
– at system and circuit levels, TDs introduce new degree of
freedom, (e.g. BDA).

Next steps:
– Tight control of series resistance and parasitics.
– Device engineering at quantum mechanic level.
– Application to millimeter-wave transceiver

A. Cidronali, Dept. Electronics and Telecommunications, University of Florence – Italy 6/29/2005 # 38/53
Applications — Digital Logic

• Logic circuits ------ Bistability


• Integration with transistors (HEMT, HBT, CMOS) is a
requirement for a complete IC technology based on RTDs
Š Transitors: Input/output isolation, controllable gain
Š RTDs: increased functionality, enhanced circuit speed,
reduced power consumption
• It’s all about Load lines!

A. Cidronali, Dept. Electronics and Telecommunications, University of Florence – Italy 6/29/2005 # 39/53
Inverter

VDD
I I

VIN=LO
VOUT=HI
VOUT
VIN
VIN=HI VOUT
VOUT=LO

• Concept: A digital inverter cell with a low on-state current for low
static power dissipation
• Evaluation: The low on-state current also reduces the switching speed
because the current stays low until the RTD again reaches resonance
A. Cidronali, Dept. Electronics and Telecommunications, University of Florence – Italy 6/29/2005 # 40/53
Monostable-bistable transition

two stable states


RTD latch:
RTD load
Iin

RTD drive

• Voltage biasing two RTD’s in series results in a bistable circuit.


• The state of a bistable pair is given by the voltage of the DATA NODE
(OUT).
• the stable equilibrium states are labeled as “0” STATE and “1” STATE.

A. Cidronali, Dept. Electronics and Telecommunications, University of Florence – Italy 6/29/2005 # 41/53
Non-equilibrium RTD-latch switching

‘0’ state

time

‘1’ state

• To establish a new state in a latch, it must first be brought to a monostable bias and returned quickly to
the bistable level.
• To set a latch to ‘1’, an input current, Iin, must be supplied to the data node during the restoration of
the bias voltage to the bistable level; otherwise: ‘0’ the latch will be reset to the low-voltage state.
• When the total drive current is less than the drive-RTD conduction current, the capacitive current is
negative and the voltage is driven lower.
• Likewise, when the total drive current is above the drive RTD conduction current, the voltage is driven
higher.
A. Cidronali, Dept. Electronics and Telecommunications, University of Florence – Italy 6/29/2005 # 42/53
RTD logic gates

delay XOR (NOT: one input kept 1)

OR AND
A. Cidronali, Dept. Electronics and Telecommunications, University of Florence – Italy 6/29/2005 # 43/53
Monostable BIstable Logic Element
(MOBILE)

• To establish a new state in a latch, it must first be brought to a monostable bias and returned quickly to
the bistable level.
• To set a latch to ‘1’, the HFET is OFF: if Al>Ad, a net current charge the RTD driver capacitance,
resulting in a switch toward the high voltage
• otherwise: the HFET is ON the net current in the DATA NODE is such that the capacitive current is
negative and the voltage is driven lower.

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MOBILE Flip-Flop Circuit
Operating at up to 35 Gb/s

A. Cidronali, Dept. Electronics and Telecommunications, University of Florence – Italy 6/29/2005 # 45/53
Multivalued Logic

• Operating Principle of Ternary Quantizer

Ip(A)> Ip(B)> Ip(X)> Ip(Y)

A. Cidronali, Dept. Electronics and Telecommunications, University of Florence – Italy 6/29/2005 # 46/53
Multivalued Logic

A. Cidronali, Dept. Electronics and Telecommunications, University of Florence – Italy 6/29/2005 # 47/53
RTD-CMOS

• Substantial improvement in speed, power dissipation,


and circuit complexity over CMOS only circuits.
• A hybrid integration process for RTD to be
transferred and bonded to CMOS

J. I. Bergman, et al., IEEE EDL, Vol. 20, no. 3, March 1999


A. Cidronali, Dept. Electronics and Telecommunications, University of Florence – Italy 6/29/2005 # 48/53
RTD-CMOS

A 1-bit conventional CMOS A 1-bit RTD/CMOS comparator:


comparator: 18 devices 6 devices
J. I. Bergman, et al., EDL, 1999
A. Cidronali, Dept. Electronics and Telecommunications, University of Florence – Italy 6/29/2005 # 49/53
Memory cell

VRTD
IRTD
Write Read RTD2 RTD1
Select Select
RTD1
Write Read
Data Data

Storage
Node IRTD
RTD2
VLO VHI VRTD
Storage Node

• Concept: A static memory cell with a low


device count and low static power dissipation
A. Cidronali, Dept. Electronics and Telecommunications, University of Florence – Italy 6/29/2005 # 50/53
T-SRAM

TSRAM cell test circuit.


Vref is 1.0 V and RTD bias Vref+ is
0.45 V (2-state) or 1.0 V (3-state). The
source follower at the storage node,
SN, provides the read output Vout.
A. Cidronali, Dept. Electronics and Telecommunications, University of Florence – Italy 6/29/2005 # 51/53
T-SRAM

Write–read cycles for high and low


inputs for the 4x4-bit TSRAM chip.
Horizontal grid scale is 50 ns/div,
Fabricated 4x4 1T-cell TSRAM vertical grid scale is 100 mV/div. The
array. letters “W,” “S,” and “R” stand for
write, store, and read, respectively.

A. Cidronali, Dept. Electronics and Telecommunications, University of Florence – Italy 6/29/2005 # 52/53
Promising Future

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