Adsp-Bf518f Ez-Board Rev1.0 Jan 2009

ADSP-BF518F EZ-Board TM
Evaluation System Manual
Revision 1.0, January 2009

Part Number
82-000217-01
Analog Devices, Inc.

One Technology Way
Norwood, Mass. 02062-9106
Copyright Information
© 2009 Analog Devices, Inc., ALL RIGHTS RESERVED. This docu-
ment may not be reproduced in any form without prior, express written
consent from Analog Devices, Inc.
Printed in the USA.
Disclaimer
Analog Devices, Inc. reserves the right to change this product without
prior notice. Information furnished by Analog Devices is believed to be
accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use; nor for any infringement of patents or other rights of
third parties which may result from its use. No license is granted by impli-
cation or otherwise under the patent rights of Analog Devices, Inc.
Trademark and Service Mark Notice

The Analog Devices icon bar and logo, VisualDSP++, the VisualDSP++
logo, Blackfin, the Blackfin logo, the CROSSCORE logo, EZ-KIT Lite,
and EZ-Extender are registered trademarks of Analog Devices, Inc.
EZ-Board is a trademark of Analog Devices, Inc.
All other brand and product names are trademarks or service marks of
their respective owners.
Regulatory Compliance
The ADSP-BF518F EZ-Board is designed to be used solely in a laboratory
environment. The board is not intended for use as a consumer end prod-
uct or as a portion of a consumer end product. The board is an open
system design which does not include a shielded enclosure and therefore
may cause interference to other electrical devices in close proximity. This
board should not be used in or near any medical equipment or RF devices.
The ADSP-BF518F EZ-Board is currently being processed for certifica-
tion that it complies with the essential requirements of the European
EMC directive 89/336/EEC amended by 93/68/EEC and therefore carries
the “CE” mark.
The EZ-Board evaluation system contains ESD (electrostatic discharge)

sensitive devices. Electrostatic charges readily accumulate on the human
body and equipment and can discharge without detection. Permanent
damage may occur on devices subjected to high-energy discharges. Proper
ESD precautions are recommended to avoid performance degradation or
loss of functionality. Store unused EZ-Board boards in the protective ship-
ping package.
CONTENTS
PREFACE
Purpose of This Manual .................................................................. xv
Intended Audience .......................................................................... xv
Manual Contents ........................................................................... xvi
What’s New in This Manual ........................................................... xvi
Technical or Customer Support ..................................................... xvii
Supported Processors ..................................................................... xvii
Product Information .................................................................... xviii
Analog Devices Web Site ........................................................ xviii
VisualDSP++ Online Documentation ....................................... xix
Technical Library CD ............................................................... xix
Related Documents ................................................................... xx
Notation Conventions .................................................................... xxi
USING ADSP-BF518F EZ-BOARD

Package Contents .......................................................................... 1-3
Default Configuration ................................................................... 1-4
EZ-Board Installation ................................................................... 1-4
EZ-Board Session Startup .............................................................. 1-6
ADSP-BF518F EZ-Board Evaluation System Manual v

CONTENTS
Evaluation License Restrictions ..................................................... 1-8

Memory Map ............................................................................... 1-9
SDRAM Interface ....................................................................... 1-11
Parallel Flash Memory Interface .................................................. 1-11
eMMC Interface ......................................................................... 1-12
SD Interface ............................................................................... 1-13
SPI Interface .............................................................................. 1-13
Parallel Peripheral Interface (PPI) ................................................ 1-15
Rotary Encoder Interface ............................................................ 1-15
Ethernet Interface ....................................................................... 1-16
Audio Interface ........................................................................... 1-17
ADC Interface ............................................................................ 1-18
UART Interface .......................................................................... 1-19
RTC Interface ............................................................................ 1-20
LEDs and Push Buttons .............................................................. 1-21
JTAG Interface ........................................................................... 1-22
Land Grid Array ......................................................................... 1-22
Expansion Interface II ................................................................. 1-23
Power Measurements .................................................................. 1-24
Power-On-Self Test ..................................................................... 1-24
Example Programs ...................................................................... 1-25
Background Telemetry Channel .................................................. 1-25
Reference Design Information ..................................................... 1-25
vi ADSP-BF518F EZ-Board Evaluation System Manual

CONTENTS
ADSP-BF518F EZ-BOARD HARDWARE REFERENCE

System Architecture ...................................................................... 2-2
Programmable Flags ...................................................................... 2-3
Push Button and Switch Settings ................................................... 2-7
Boot Mode Select Switch (SW1) .............................................. 2-8
PB Enable Switch (SW2) ......................................................... 2-8
Flash Enable Switch (SW3) ...................................................... 2-9
SPORT1 Enable Switch (SW4) ................................................ 2-9
MIC Gain Switch (SW5) ....................................................... 2-10
Mic/HP LPBK, Audio Mode Switch (SW6) ........................... 2-10
Ethernet Port 1 Configuration Switch (SW7) ......................... 2-11
Ethernet Configuration Switch (SW8) ................................... 2-11
UART Setup Switch (SW10) ................................................. 2-12
Reset Push Button (SW11) .................................................... 2-12
Programmable Flag Push Buttons (SW12–13) ........................ 2-12
Rotary Encoder with Momentary Switch (SW14) .................. 2-13
SPORT0 ENBL Switch (SW15) ............................................. 2-13
SPI/TWI Switch (SW16) ....................................................... 2-13
Ethernet Mode Switch (SW17) .............................................. 2-14
Ethernet Port 2 Configuration Switch (SW18) ....................... 2-14
Encoder Enable Switch (SW19) ............................................. 2-14
eMMC Enable Switch (SW20–21) ......................................... 2-15
ADC Loopback Switches (SW22–23) ..................................... 2-15
Jumpers ...................................................................................... 2-16
ADSP-BF518F EZ-Board Evaluation System Manual vii

CONTENTS
Flash WP Jumper (JP3) ......................................................... 2-17

ADC Range Jumper (JP4) ..................................................... 2-17
LED Select Jumpers (JP11–12) ............................................. 2-17
Ethernet Power Down Jumper (JP13) .................................... 2-17
OTP Flag Enable Jumper (JP14) ........................................... 2-18
MIC Select Jumper (JP15) .................................................... 2-18
SPI FLASH CS Enable Jumper (JP16) ................................... 2-18
ADC Channel Select Jumpers (JP17–28) ............................... 2-19
VDDINT Power Jumper (P8) ............................................... 2-19
VDDEXT Power Jumper (P9) ............................................... 2-19
VDDMEM Power Jumper (P10) ........................................... 2-20
VDDFLASH Power Jumper (P11) ......................................... 2-20
LEDs ......................................................................................... 2-21
GPIO LEDs (LED1–3) ......................................................... 2-22
Ethernet LEDs (LED4–8, LED10–12) .................................. 2-22
Reset LED (LED9) ............................................................... 2-22
Power LED (LED13) ............................................................ 2-23
Connectors ................................................................................. 2-24
Expansion Interface II Connector (J1) ................................... 2-25
RS-232 Connector (J2) ......................................................... 2-25
Power Connector (J3) ........................................................... 2-25
Dual Audio Connectors (J4–5) .............................................. 2-26
SMA Connectors (J7, J16–26) .............................................. 2-26
Battery Holder (J12) ............................................................. 2-26
viii ADSP-BF518F EZ-Board Evaluation System Manual

CONTENTS
SD Connector (J13) .............................................................. 2-26

Ethernet Connectors (J14–15) ............................................... 2-27
JTAG Connector (P1) ........................................................... 2-27
Expansion Interface II Connectors (P2 and P4) ...................... 2-27
Expansion Interface II Connector (P3) ................................... 2-28
DMAX Land Grid Array Connectors (P5–7) .......................... 2-28
Standalone Debug Agent Connector (ZP1) ............................ 2-29
ADSP-BF518F EZ-BOARD BILL OF MATERIALS

ADSP-BF518F EZ-BOARD SCHEMATIC
Title Page .................................................................................... B-1
Processor EBIU and Control ........................................................ B-2
Processor Power, Bypass Caps ....................................................... B-3
External Memory ......................................................................... B-4
ADC ........................................................................................... B-5
Audio Codec ................................................................................ B-6
Ethernet Switch ........................................................................... B-7
Ethernet Config/LEDs ................................................................. B-8
Ethernet Jacks .............................................................................. B-9
Rotary Encoder, JTAG, RS-232, RSI .......................................... B-10
Logic Analyzer Conn .................................................................. B-11
Push Buttons, Reset, LEDs ......................................................... B-12
Expansion Interface .................................................................... B-13
OTP and Dual Power ................................................................. B-14
ADSP-BF518F EZ-Board Evaluation System Manual ix

CONTENTS
Power ......................................................................................... B-15

Series Terminators ...................................................................... B-16
INDEX
x ADSP-BF518F EZ-Board Evaluation System Manual

PREFACE
Thank you for purchasing the ADSP-BF518F EZ-Board™, Analog

Devices, Inc. evaluation system for Blackfin® processors.
Blackfin processors embody a new type of embedded processor designed
specifically to meet the computational demands and power constraints of
today’s embedded audio, video, and communications applications. They
deliver breakthrough signal-processing performance and power efficiency
within a reduced instruction set computing (RISC) programming model.
Blackfin processors support a media instruction set computing (MISC)
architecture. This architecture is the natural merging of RISC, media
functions, and digital signal processing (DSP) characteristics. Blackfin
processors deliver signal-processing performance in a microprocessor-like
environment.
Based on the Micro Signal Architecture (MSA), Blackfin processors com-
bine a 32-bit RISC instruction set, dual 16-bit multiply accumulate
(MAC) DSP functionality, and eight-bit video processing performance
that had previously been the exclusive domain of very-long instruction
word (VLIW) media processors.
ADSP-BF518F EZ-Board Evaluation System Manual xi

The evaluation board is designed to be used in conjunction with the Visu-
alDSP++® development environment to test the capabilities of the
ADSP-BF518F Blackfin processors. The VisualDSP++ development envi-
ronment aids advanced application code development and debug, such as:
• Create, compile, assemble, and link application programs written
in C++, C, and ADSP-BF518F assembly
• Load, run, step, halt, and set breakpoints in application programs
• Read and write data and program memory
• Read and write core and peripheral registers
• Plot memory
Access to the ADSP-BF518F processor from a personal computer (PC) is
achieved through a USB port or an external JTAG emulator. The USB
interface of the standalone debug agent gives unrestricted access to the
ADSP-BF518F processor and evaluation board’s peripherals. Analog
Devices JTAG emulators offer faster communication between the host PC
and target hardware. To learn more about Analog Devices emulators and
processor development tools, go to http://www.analog.com/dsp/tools/.
The ADSP-BF518F EZ-Board provides example programs to demonstrate
the capabilities of the product.
L The ADSP-BF518F EZ-Board installation is part of the Visu-

alDSP++ installation. As an EZ-KIT Lite, an EZ-Board is a
licensed product that offers an unrestricted evaluation license for
the first 90 days. For details about evaluation license restrictions
after the 90 days, refer to “Evaluation License Restrictions” on
page 1-8 and the VisualDSP++ Installation Quick Reference Card.
xii ADSP-BF518F EZ-Board Evaluation System Manual

Preface
The board features:

• Analog Devices ADSP-BF518F Blackfin processor
D Core performance up to 400 MHz
D External bus performance up to 80 MHz
D 176-pin LQFP package
D 25 MHz crystal
• Programmable VDDINT core power
D Analog Devices AD5258 TWI digital potentiometer
D Analog Devices ADP1715 low dropout linear regulator
• Synchronous dynamic random access memory (SDRAM)
D Micron MT48LC32M16A2TG – 64 MB (32M x 16-bits)
• Parallel flash memory
D Numonyx M29W320EB – 4 MB (2M x 16-bits)
• eMMC flash memory
D Micron MTFC2GDKDM – 2 GB
• SPI flash memory
D Numonyx M25P16 – 16 Mb
• Analog audio interface
D Analog Devices SSM2602 low-power audio codec
D One stereo LINE OUT jack
D One headphone LINE IN
D One input MIC jack

D One input stereo LINE IN jack
ADSP-BF518F EZ-Board Evaluation System Manual xiii

• Ethernet interface
D Micrel KSZ8893M PHY device
D 10-BaseT and 100-BaseTX Ethernet controller
D Auto-MDIX
• ADC interface
D Analog Devices AD7266 2 MSPS, 12-bit, 3-channel SAR
analog-to-digital converter
• Thumbwheel
D Panasonic EVQ-WKA001 rotary encoder
• Universal asynchronous receiver/transmitter (UART)
D ADM3202 RS-232 line driver/receiver
D DB9 female connector
• LEDs
D Thirteen LEDs: one board reset (red), three general-purpose
(amber), eight configurable ethernet LEDs (amber) and one
power (green)
• Push buttons
D Three push buttons: one reset, two programmable flags with
debounce logic
• Expansion interface II™
D Next generation of the expansion interface design, provides
access to most of the ADSP-BF518F processor signals
• Land grid array
D Easy probing of all port pins and most EBIU signals
xiv ADSP-BF518F EZ-Board Evaluation System Manual

Preface
• Other features
D JTAG ICE 14-pin header
D Blackfin power measurement jumpers
For information about the hardware components of the EZ-Board, refer
to “ADSP-BF518F EZ-Board Hardware Reference” on page 2-1.
Purpose of This Manual

The ADSP-BF518F EZ-Board Evaluation System Manual provides instruc-
tions for installing the product hardware (board). The text describes
operation and configuration of the board components and provides guide-
lines for running your own code on the ADSP-BF518F EZ-Board.
Finally, a schematic and a bill of materials are provided as a reference for
future designs.
The product software installation is detailed in the VisualDSP++ Installa-
tion Quick Reference Card.
Intended Audience
The primary audience for this manual is a programmer who is familiar
with Analog Devices processors. This manual assumes that the audience
has a working knowledge of the appropriate processor architecture and
instruction set. Programmers who are unfamiliar with Analog Devices
processors can use this manual, but should supplement it with other texts
(such as the ADSP-BF51x Blackfin Processor Hardware Reference and
Blackfin Processor Instruction Set Reference) that describe your target
architecture.
Programmers who are unfamiliar with VisualDSP++ should refer to the
VisualDSP++ online Help and user’s or getting started guides. For the
locations of these documents, see “Related Documents”.
ADSP-BF518F EZ-Board Evaluation System Manual xv

Manual Contents
Manual Contents
The manual consists of:
• Chapter 1, “Using ADSP-BF518F EZ-Board” on page 1-1
Describes EZ-Board functionality from a programmer’s perspective
and provides an easy-to-access memory map.
• Chapter 2, “ADSP-BF518F EZ-Board Hardware Reference” on
page 2-1
Provides information on the EZ-Board hardware components.
• Appendix A, “ADSP-BF518F EZ-Board Bill Of Materials” on
page A-1
Provides a list of components used to manufacture the EZ-Board.
• Appendix B, “ADSP-BF518F EZ-Board Schematic” on page B-1
Provides the resources to allow EZ-Board board-level debugging or
to use as a reference design. Appendix B is part of the online Help.
What’s New in This Manual

This is the first revision of the ADSP-BF518F EZ-Board Evaluation System
Manual.
xvi ADSP-BF518F EZ-Board Evaluation System Manual

Preface
Technical or Customer Support

You can reach Analog Devices, Inc. Customer Support in the following
ways:
• Visit the Embedded Processing and DSP products Web site at
http://www.analog.com/processors/technical_support
• E-mail tools questions to

processor.tools.support@analog.com
• E-mail processor questions to

processor.support@analog.com (World wide support)
processor.europe@analog.com (Europe support)
processor.china@analog.com (China support)
• Phone questions to 1-800-ANALOGD

• Contact your Analog Devices, Inc. local sales office or authorized
distributor
• Send questions by mail to:
Analog Devices, Inc.
One Technology Way
P.O. Box 9106
Norwood, MA 02062-9106
USA
Supported Processors
This evaluation system supports Analog Devices ADSP-BF518F Blackfin
embedded processors.
ADSP-BF518F EZ-Board Evaluation System Manual xvii

Product Information
Product Information
Product information can be obtained from the Analog Devices Web site,
VisualDSP++ online Help system, and a technical library CD.
Analog Devices Web Site

The Analog Devices Web site, www.analog.com, provides information
about a broad range of products—analog integrated circuits, amplifiers,
converters, and digital signal processors.
To access a complete technical library for each processor family, go to
http://www.analog.com/processors/technical_library. The manuals
selection opens a list of current manuals related to the product as well as a
link to the previous revisions of the manuals. When locating your manual
title, note a possible errata check mark next to the title that leads to the
current correction report against the manual.
Also note, MyAnalog.com is a free feature of the Analog Devices Web site
that allows customization of a Web page to display only the latest infor-
mation about products you are interested in. You can choose to receive
weekly e-mail notifications containing updates to the Web pages that meet
your interests, including documentation errata against all manuals.
MyAnalog.com provides access to books, application notes, data sheets,
code examples, and more.
Visit MyAnalog.com to sign up. If you are a registered user, just log on.
Your user name is your e-mail address.
xviii ADSP-BF518F EZ-Board Evaluation System Manual

Preface
VisualDSP++ Online Documentation

Online documentation comprises the VisualDSP++ Help system, software
tools manuals, hardware tools manuals, processor manuals, Dinkum
Abridged C++ library, and FLEXnet License Tools software documenta-
tion. You can search easily across the entire VisualDSP++ documentation
set for any topic of interest.
For easy printing, supplementary Portable Documentation Format (.pdf)
files for all manuals are provided on the VisualDSP++ installation CD.
Each documentation file type is described as follows.
File Description
.chm Help system files and manuals in Microsoft help format
.htm or Dinkum Abridged C++ library and FLEXnet License Tools software documenta-
.html tion. Viewing and printing the .html files requires a browser, such as Internet
Explorer 6.0 (or higher).
.pdf VisualDSP++ and processor manuals in PDF format. Viewing and printing the
.pdf files requires a PDF reader, such as Adobe Acrobat Reader (4.0 or higher).
Technical Library CD
The technical library CD contains seminar materials, product highlights, a
selection guide, and documentation files of processor manuals, Visu-
alDSP++ software manuals, and hardware tools manuals for the following
processor families: Blackfin, SHARC, TigerSHARC, ADSP-218x, and
ADSP-219x.
To order the technical library CD, go to http://www.analog.com/proces-
sors/technical_library, navigate to the manuals page for your
processor, click the request CD check mark, and fill out the order form.
ADSP-BF518F EZ-Board Evaluation System Manual xix

Product Information
Data sheets, which can be downloaded from the Analog Devices Web site,
change rapidly, and therefore are not included on the technical library
CD. Technical manuals change periodically. Check the Web site for the
latest manual revisions and associated documentation errata.
Related Documents
For information on product related development software, see the follow-
ing publications.
Table 1. Related Processor Publications

Title Description
ADSP-BF512/ADSP-BF514/ADSP-BF516/ADSP- General functional description, pinout, and

BF518 Blackfin Embedded Processor Preliminary timing of the processor.
Data Sheet
ADSP-BF51x Blackfin Processor Hardware Refer- Description of internal processor architec-

ence ture and all register functions.
Blackfin Processor Programming Reference Description of all allowed processor assem-

bly instructions.
Table 2. Related VisualDSP++ Publications

Title Description
ADSP-BF518F EZ-Board Evaluation System Man- Description of the hardware capabilities of

ual the evaluation system; description of how to
access these capabilities in the VisualDSP++
environment.
VisualDSP++ User’s Guide Description of VisualDSP++ features and

usage.
VisualDSP++ Assembler and Preprocessor Manuals Description of the assembler function and
commands.
VisualDSP++ C/C++ Complier and Library Man- Description of the complier function and
ual for Blackfin Processors commands for Blackfin processors.
xx ADSP-BF518F EZ-Board Evaluation System Manual

Preface
Table 2. Related VisualDSP++ Publications (Cont’d)

Title Description
VisualDSP++ Linker and Utilities Manual Description of the linker function and com-
mands.
VisualDSP++ Loader and Utilities Manual Description of the loader/splitter function

and commands.
VisualDSP++ Device Drivers and System Services Description of the device drivers’ and system
Manual for Blackfin Processors services’ functions and commands.
Notation Conventions
Text conventions used in this manual are identified and described as
follows.
Example Description
Close command Titles in reference sections indicate the location of an item within the
(File menu) VisualDSP++ environment’s menu system (for example, the Close com-
mand appears on the File menu).
{this | that} Alternative required items in syntax descriptions appear within curly
brackets and separated by vertical bars; read the example as this or
that. One or the other is required.
[this | that] Optional items in syntax descriptions appear within brackets and sepa-
rated by vertical bars; read the example as an optional this or that.
[this,…] Optional item lists in syntax descriptions appear within brackets delim-
ited by commas and terminated with an ellipse; read the example as an
optional comma-separated list of this.
.SECTION Commands, directives, keywords, and feature names are in text with
letter gothic font.
filename Non-keyword placeholders appear in text with italic style format.
ADSP-BF518F EZ-Board Evaluation System Manual xxi

Notation Conventions
Example Description
Note: For correct operation, ...
L
A Note provides supplementary information on a related topic. In the
online version of this book, the word Note appears instead of this
symbol.
Caution: Incorrect device operation may result if ...
a
Caution: Device damage may result if ...
A Caution identifies conditions or inappropriate usage of the product
that could lead to undesirable results or product damage. In the online
version of this book, the word Caution appears instead of this symbol.
Warning: Injury to device users may result if ...
[
A Warning identifies conditions or inappropriate usage of the product
that could lead to conditions that are potentially hazardous for the
devices users. In the online version of this book, the word Warning
appears instead of this symbol.
xxii ADSP-BF518F EZ-Board Evaluation System Manual

1 USING ADSP-BF518F
EZ-BOARD
This chapter provides specific information to assist you with development

of programs for the ADSP-BF518F EZ-Board evaluation system.
The following topics are covered.
• “Package Contents” on page 1-3
• “Default Configuration” on page 1-4
• “EZ-Board Installation” on page 1-4
• “EZ-Board Session Startup” on page 1-6
• “Evaluation License Restrictions” on page 1-8
• “Memory Map” on page 1-9
• “SDRAM Interface” on page 1-11
• “Parallel Flash Memory Interface” on page 1-11
• “eMMC Interface” on page 1-12
• “SPI Interface” on page 1-13
• “Parallel Peripheral Interface (PPI)” on page 1-15
• “Rotary Encoder Interface” on page 1-15
• “Ethernet Interface” on page 1-16
• “Audio Interface” on page 1-17
ADSP-BF518F EZ-Board Evaluation System Manual 1-1

• “ADC Interface” on page 1-18
• “UART Interface” on page 1-19
• “RTC Interface” on page 1-20
• “LEDs and Push Buttons” on page 1-21
• “JTAG Interface” on page 1-22
• “Land Grid Array” on page 1-22
• “Expansion Interface II” on page 1-23
• “Power Measurements” on page 1-24
• “Power-On-Self Test” on page 1-24
• “Example Programs” on page 1-25
• “Background Telemetry Channel” on page 1-25
• “Reference Design Information” on page 1-25
For information about VisualDSP++, including the boot loading, target
options, and other facilities, refer to the online Help.
For more information about the ADSP-BF518F Blackfin processor, see
documents referred to as “Related Documents”.
1-2 ADSP-BF518F EZ-Board Evaluation System Manual

Using ADSP-BF518F EZ-Board
Package Contents
Your ADSP-BF518F EZ-KIT Lite evaluation system package contains the
following items.
• ADSP-BF518F EZ-Board
• VisualDSP++ Installation Quick Reference Card
• CD containing:
D VisualDSP++ software
D ADSP-BF518F EZ-Board debug software
D USB driver files
D Example programs
D ADSP-BF518F EZ-Board Evaluation System Manual
• Universal 5.0V DC power supply
• 256 MB SD card
• 7-foot Ethernet patch cable
• Two 6-foot 3.5 mm male-to-male audio cables
• 18-inch SMA to SMA coaxial cable
If any item is missing, contact the vendor where you purchased your
EZ-Board or contact Analog Devices, Inc.

Default Configuration
Default Configuration
The ADSP-BF518F EZ-Board board is designed to run outside your per-
sonal computer as a stand-alone unit. You do not have to open your
computer case.
The EZ-Board evaluation system contains ESD (electrostatic discharge) sensi-
tive devices. Electrostatic charges readily accumulate on the human body and
equipment and can discharge without detection. Permanent damage may
occur on devices subjected to high-energy discharges. Proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.
Store unused EZ-Board in the protective shipping package.
When removing the EZ-Board from the package, handle the board care-
fully to avoid the discharge of static electricity, which can damage some
components. Figure 1-1 shows the default jumper and switch settings,
connector locations, and LEDs used in installation. Confirm that your
board is in the default configuration before using the board.
EZ-Board Installation
For correct operation, install the software in the order presented in the
VisualDSP++ Installation Quick Reference Card. Substitute instructions in
step 3 with instructions in this section.
There are two options to connect the EZ-Board hardware to a personal
computer (PC) running VisualDSP++ 5.0: via an Analog Devices emula-
tor or via a standalone debug agent module. The standalone debug agent
allows a debug agent to interface to the ADSP-BF518F EZ-Board. The
standalone debug agent is shipped with the kit.

Figure 1-1. Default EZ-Board Hardware Setup

EZ-Board Session Startup
To connect the EZ-Board to a PC via an emulator:

1. Plug the 5V adaptor into connector J3 (labeled 5V).
2. Attach the emulator header to connector P1 (labeled JTAG) on the
back side of the EZ-Board.
To connect the EZ-Board to a PC via a standalone debug agent:
a wall
The debug agent can be used only when power is supplied from the
adaptor.
1. Attach the standalone debug agent to connectors P1 (labeled JTAG)
and ZP1 on the backside of the EZ-Board, watching for the keying
pin of P1 to connect correctly. Plug the 5V adaptor into connector
J3 (labeled 5V).
2. Plug one side of the provided USB cable into the USB connector of
the standalone debug agent. Plug the other side of the cable into a
USB port of the PC running VisualDSP++ 5.0 update 5 or later.
3. Verify that the yellow USB monitor LED on the standalone debug
agent (LED4, located on the back side of the board) is lit. This signi-
fies that the board is communicating properly with the host PC
and ready to run VisualDSP++.
EZ-Board Session Startup

1. If you are running VisualDSP++ for the first time, navigate to the
VisualDSP++ environment via the Start–>Programs menu. The
main window appears. Note that VisualDSP++ is not connected to
any session. Skip the rest of this step to step 2.
If you have run VisualDSP++ previously, the last opened session

appears on the screen. You can override the default behavior and
force VisualDSP++ to start a new session by pressing and holding

down the Ctrl key while starting VisualDSP++. Do not release the
Ctrl key until the Session Wizard appears on the screen. Go to
step 3.
2. To connect to a new EZ-KIT Lite session, start Session Wizard by
selecting one of the following.
• From the Session menu, New Session.
• From the Session menu, Session List. Then click New Ses-
sion from the Session List dialog box.
• From the Session menu, Connect to Target.
3. The Select Processor page of the wizard appears on the screen.
Ensure Blackfin is selected in Processor family. In Choose a target
processor, select ADSP-BF518F. Click Next.
4. The Select Connection Type page of the wizard appears on the
screen. For standalone debug agent connection, select EZ-KIT Lite
and click Next. For emulator connection select Emulator, and click
Next
5. The Select Platform page of the wizard appears on the screen.
For standalone debug agent connection, ensure that the selected
platform is ADSP-BF518F EZ-KIT Lite via Debug Agent. For
emulator connection, choose the type of emulator that is connected.
Specify your own Session name for the session or accept the default
name.
The session name can be a string of any length; although, the box
displays approximately 32 characters. The session name can
include space characters. If you do not specify a session name,
VisualDSP++ creates a session name by combining the name of the
selected platform with the selected processor. The only way to
change a session name later is to delete the session and open a new

Evaluation License Restrictions
session.
Click Next.
6. The Finish page of the wizard appears on the screen. The page dis-
plays your selections. Check the selections. If you are not satisfied,
click Back to make changes; otherwise, click Finish. VisualDSP++
creates the new session and connects to the EZ-Board. Once con-
nected, the main window’s title is changed to include the session
name set in step 5.
L Toor select
disconnect from a session, click the disconnect button
Session–>Disconnect from Target.
To delete a session, select Session –> Session List. Select the ses-
sion name from the list and click Delete. Click OK.
Evaluation License Restrictions

The ADSP-BF518F EZ-Board installation is part of the VisualDSP++
installation. The EZ-Board is a licensed product that offers an unrestricted
evaluation license for the first 90 days. Once the initial unrestricted
90-day evaluation license expires:
• VisualDSP++ restricts a connection to the ADSP-BF518F
EZ-Board via the USB port of the standalone debug agent interface
only. Connections to simulators and emulation products are no
longer allowed.
• The linker restricts a user’s program to 20 KB of memory for code
space with no restrictions for data space.
• The EZ-Board hardware must be connected and powered up to use
VisualDSP++ with a valid evaluation or permanent license.
Refer to the VisualDSP++ Installation Quick Reference Card for details.

Memory Map
The ADSP-BF518F processor has internal static random access memory
(SRAM) used for instructions and data storage. See Table 1-1. The inter-
nal memory details can be found in the ADSP-BF51x Blackfin Processor
Hardware Reference.
The ADSP-BF518F EZ-Board includes four types of external memory:
synchronous dynamic random access memory (SDRAM), serial peripheral
interconnect (SPI) flash, parallel flash, and eMMC. See Table 1-2. For
more information about a specific memory type, go to the respective sec-
tion in this chapter.
Table 1-1. EZ-Board Internal Memory Map

Start Address Content
0xEF00 0000 BOOT ROM (32K BYTE)
0xEF00 8000 Reserved
0xFF80 0000 DATA BANKA SRAM (16K BYTE)
0xFF80 4000 DATA BANKA SRAM/CACHE (16K BYTE)
0xFF80 8000 Reserved
0xFF90 0000 DATA BANKB SRAM (16K BYTE)
0xFF90 4000 DATA BANKB SRAM/CACHE (16K BYTE)

0xFF90 8000 Reserved
0xFFA0 0000 INSTRUCTION BANK A SRAM (16K BYTE)

0xFFA0 4000 Reserved
0xFFA0 8000 INSTRUCTION BANK B SRAM (16 BYTE)
0xFFA0 C000 Reserved
0xFFA1 0000 INSTRUCTION SRAM/CACHE (16K BYTE)
0xFFA1 4000 Reserved

Memory Map
Table 1-1. EZ-Board Internal Memory Map (Cont’d)

Start Address Content
0xFFB0 0000 SCRATCHPAD SRAM (4K BYTE)
0xFFB0 1000 Reserved
0xFFC0 0000 SYSTEM MMR REGISTERS
0xFFE0 0000 CORE MMR REGISTERS
Table 1-2. EZ-Board External Memory Map

Start Address End Address Content
0x0000 0000 0x03FF FFFF SDRAM (SDRAM)
0x0800 0000 0x1FFF FFFF Reserved
0x2000 0000 0x200F FFFF ASYNC memory bank 0 (flash)
0x2040 0000 0xEEFF FFFF Reserved

SDRAM Interface
The ADSP-BF518F processor connects to a 64 MB Micron
MT48LC32M16A2TG-75 chip through the external bus interface unit
(EBIU). The SDRAM chip can operate at a maximum clock frequency of
80 MHz, which is the ADSP-BF518F processor limitation.
With a VisualDSP++ session running and connected to the EZ-Board via
the USB standalone debug agent, the SDRAM registers are configured
automatically each time the processor is reset. The values are used when-
ever SDRAM is accessed through the debugger (for example, when
viewing memory windows or loading a program).
To disable the automatic setting of the SDRAM registers, select Target
Options from the Settings menu in VisualDSP++ and uncheck Use XML
reset values. For more information on changing the reset values, refer to
the online Help.
An example program is included in the EZ-Board installation directory to
demonstrate how to setup and access the SDRAM interface. For more
information on how to initialize the registers after a reset, search the Visu-
alDSP++ online Help for “reset values”.
Parallel Flash Memory Interface

The parallel flash memory interface of the ADSP-BF518F EZ-Board con-
tains a 4 MB (2M x 16 bits) Numonyx M29W320EB chip. Flash memory
connects to the 16-bit data bus and address lines 1 through 19. Chip
enable is decoded by the AMS0—3 select lines through NAND and AND
gates. The address range for flash memory is 0x2000 0000 to 0x203F FFFF.

eMMC Interface
Flash memory is pre-loaded with boot code for the power-on-self test
(POST) program. For more information, refer to “Power-On-Self Test”
on page 1-24. Flash memory also is preloaded with configuration flash
information, which contains board revision, BOM revision, and other
data.
By default, the EZ-Board boots from the 16-bit parallel flash memory.
The processor boots from flash memory if the boot mode select switch
(SW1) is set to position 1 (see “Boot Mode Select Switch (SW1)” on
page 2-8).
Flash memory code can be modified. For instructions, refer to the online
Help and example program included in the EZ-Board installation
directory.
For more information about the parallel flash device, refer to the Num-
onyx Web site: http://www.numonyx.com/.
eMMC Interface
The ADSP-BF518F processor is equipped with a removable storage inter-
face (RSI), which allows the 2 Gb Micron eMMC device to be attached
gluelessly to the processor. The eMMC device is attached via the proces-
sor’s specific RSI control and data lines. The eMMC device shares pins
with the secure digital (SD) interface, push buttons, analog-to-digital con-
verter (ADC) and expansion interface II.
The RSI signals can be disconnected from the eMMC device by turning
switches SW20 and SW21 all OFF. See “eMMC Enable Switch (SW20–21)”
on page 2-15 for more information.
For more information about the eMMC device, refer to the Micron Web
site: http://www.micron.com/.
demonstrate how to setup and access the eMMC device.

SD Interface
The ADSP-BF518F processor has a secure digital interface. The SD inter-
face consists of a clock pin, a command pin, and a four-bit data bus. The
SD interface of the processor connects gluelessly to the on-board SD con-
nector. The SD interface is attached via the processor’s specific RSI
control and data lines. The interface shares pins with the eMMC interface,
codec, and expansion interface II. The memory can be written to in both
one-bit and four-bit modes. For more information, refer to “SD Connec-
tor (J13)” on page 2-26. An example program is included in the EZ-Board
installation directory to demonstrate how to setup and access the SD
interface.
SPI Interface
The ADSP-BF518F processor has two serial peripheral interface (SPI)
ports with multiple chip select lines. The SPI0 port connects directly to
serial flash memory, audio codec, Ethernet IC, and the expansion
interface II.
Serial flash memory is a 16 Mb ST M25P16 device, which is selected
using the SPISEL2 line of the processor.
SPI flash memory is factory programmed with Das U-Boot—the universal
boot loader. Das U-Boot (U-Boot for short) is open source firmware for
embedded processors, including the ADSP-BF518F Blackfin processors.
U-Boot can load files from a variety of peripherals, such as a serial connec-
tion, an Ethernet network connection, or flash memories. U-Boot is
executed at system reset, which automatically loads up another application
(such as the Linux kernel or a stand alone application). U-Boot can parse
many types of files on many types of storage devices.

SPI Interface
U-Boot is controlled via a serial connection. The default setting is 56700

baud, 8 data bits, No parity, 1 stop bit. See “RS-232 Connector (J2)” on
page 2-25 for information on the serial connector.
For more information about U-Boot, refer to the online documentation
at:
http://docs.blackfin.uclinux.org/doku.php?id=bootloaders:u-boot.
For U-Boot support on the Blackfin processors, refer to the online help
forums at:
http://black-
fin.uclinux.org/gf/project/u-boot/forum/?action=ForumBrowse&foru
m_id=51.
SPI flash can be modified. For instructions, refer to the VisualDSP++

online Help, example program included in the EZ-Board installation
directory, and U-Boot documentation. U-Boot includes an SPI flash
driver and can be used to download a new file over Ethernet or serial con-
nection, and write the file to SPI flash.
By default, the EZ-Board boots from the 16-bit flash parallel memory. SPI
flash can be selected as the boot source by setting the boot mode select
switch (SW1) to position 3. See “Boot Mode Select Switch (SW1)” on
page 2-8.
The audio codec is set up to use the SPISEL3 signal as the SPI chip select.
The chip select is shared with the CUD signal. For more information, refer
to “Audio Interface” on page 1-17.
The Ethernet IC is set up to use the SPISEL1 signal as the SPI chip select.
For more information, refer to “Ethernet Interface” on page 1-16.

Parallel Peripheral Interface (PPI)

The ADSP-BF518F processor provides a parallel peripheral interface
(PPI), supporting data widths up to 16 bits. The PPI interface provides
three multiplexed frame syncs, a multiplexed clock, and 16 multiplexed
data lines. The full PPI port is accessible on the expansion interface II
connector (P3). See “Expansion Interface II Connector (P3)” on
page 2-28.
The PPI signals connect to multi-functional pins. The PPI is shared with
the on-board codec, eMMC, SD, and Ethernet IC. To use the PPI on the
expansion interface, disable the codec by turning switch SW15 to all OFF
(see “SPORT0 ENBL Switch (SW15)” on page 2-13). The eMMC is dis-
abled by turning switches SW20 and SW21 to all OFF, and the SPI flash is
disabled by removing the jumper from JP16. See “eMMC Enable Switch
(SW20–21)” on page 2-15 and “SPI FLASH CS Enable Jumper (JP16)”
on page 2-18.
The PPI is not used on the EZ-Board, the PPI is intended for use on the
expansion interface II.
Rotary Encoder Interface

The ADSP-BF518F processor has a built-in, up-down counter with sup-
port for a rotary encoder. The three-wire rotary encoder interface connects
to the thumbwheel rotary switch (SW19) and expansion interface II. The
rotary encoder can be turned clockwise for the up function, counter clock-
wise for the down function, or can be pushed towards the center of the
board to clear the counter.
The rotary switch is a two-bit quadrature (gray code) counter with a
detent, meaning that both the down signal (CDG) and up signal (CUD) tog-
gle when the count register increases on a rotation to the right. Upon
rotating to the left, CDG and CUD toggle, and the overall count decreases.

Ethernet Interface
If the processor pins are needed for the expansion interface II, disconnect
the rotary encoder switch via the three-position rotary enable switch
(SW19). For more information, see “Encoder Enable Switch (SW19)” on
page 2-14.
demonstrate how to set up and access the rotary encoder interface.
Ethernet Interface
The ADSP-BF518F processor has an integrated Ethernet MAC with
media independent interface (MII) which connects to an external PHY.
The EZ-Board provides a Micrel KSZ8893M Integrated 3-Port 10/100
Managed Switch with PHYs, fully compliant with IEEE 802.3u standards.
The KSZ8893M chip supports 10BASE-T and 100BASE-TX operations.
The part is attached gluelessly to the processor.
The Ethernet signals are shared with the PPI signals connected to the
expansion interface II.
The Ethernet mode is set by three switches. Switch SW7 controls the con-
figuration of the port 1 connector. SW7 configures the flow control,
duplex, speed, and auto-negotiation. Switch SW18 controls the configura-
tion of the port 2 connector. SW18 configures the flow control, duplex,
speed, auto-negotiation, auto MDI/MDI-X, and MDI/MDI-X settings.
Switch SW8 controls the Ethernet IC configuration. SW8 configures the
flow control, hardware pin overwrite, and serial bus mode. See “Ethernet
Port 1 Configuration Switch (SW7)” on page 2-11, “Ethernet Port 2 Con-
figuration Switch (SW18)” on page 2-14, and “Ethernet Configuration
Switch (SW8)” on page 2-11 for more information.
The Ethernet chip is pre-loaded with a MAC address. The MAC address
for the EZ-Board is stored in the configuration flash section of the parallel
flash memory and can be found on a sticker on the bottom side of the
board.

The PHY portion of the Ethernet chip connects to a Pulse HX1188 mag-
netics, then to standard RJ-45 Ethernet connectors (J14 and J15). For
more information, see “Ethernet Connectors (J14–15)” on page 2-27.
Example programs are included in the EZ-Board installation directory to
demonstrate how to use the Ethernet interface.
Audio Interface
The audio interface of the EZ-Board consists of a low-power stereo codec,
SSM2602, with an integrated headphone driver and associated passive
components. There are two inputs, a stereo line in, and a mono micro-
phone, as well as two outputs, a headphone, and a stereo line out. The
codec has integrated stereo ADCs, digital-to-analog converters (DACs),
and requires minimal external circuitry.
The codec connects to the ADSP-BF518F processor via the processor’s
serial port 0. The SPORT0 is disconnected from the codec by turning switch
SW15 OFF, which enables SPORT0 for the SD/eMMC interface or the expan-
sion interface II. See “SPORT0 ENBL Switch (SW15)” on page 2-13 for
more information.
The control interface of the codec is selected by switching SW16 between
the 2-wire interface (TWI) and SPI. The board’s default is SPI mode.
Refer to“SPI/TWI Switch (SW16)” on page 2-13 for more information.
Mic gain values of 14 dB, 0 dB, or –6 dB are selectable through switch
SW5. For more information, see “MIC Gain Switch (SW5)” on page 2-10.
Microphone bias is provided through a low-noise reference voltage. A

jumper on positions 2&3 of JP15 connects the MICBIAS signal to the audio
jack. Placing a jumper on positions 1&2 of JP15 connects the bias directly
to the mic signal. For more information, see “MIC Select Jumper (JP15)”
on page 2-18.

ADC Interface
J4 and J5 are 3.5 mm connectors for the audio portion of the board. J5
connects the mic on the top portion and line-in on the bottom. J4 con-
nects the headphone on the top portion and line-out on the bottom. If
there is no 3.5 mm cable plugged into the bottom of either J4 or J5, the
signals are looped back inside the connector. For more information, see
“Dual Audio Connectors (J4–5)” on page 2-26.
For testing, SW6 positions 1&2 connect the MICIN signal to either the left
or right headphone. Do not connect the left and right to the MICIN signal
at the same time—only position 1 or 2 of SW6 should be ON at the same
time. For more information, see “Mic/HP LPBK, Audio Mode Switch
(SW6)” on page 2-10.
The EZ-Board is shipped with two 3.5 mm cables, which allow you to run
the example programs provided in the EZ-Board installation directory and
learn about the audio interface.
ADC Interface
The ADC interface of the EZ-Board consists of a dual, 12-bit, high-speed,
low-power, successive approximation analog-to-digital converter. The
device contains two converters, each preceded by a 3-channel multiplexer,
a low-noise, wide-bandwidth track, and holds an amplifier that can handle
input frequencies in excess of 30 MHz. There are four differential and
four single-ended inputs on the EZ-Board that are accessed via SMA
connectors.
The ADC connects to the ADSP-BF518F processor via the processor’s
serial port 1. SPORT1 is disconnected from the ADC by turning switch SW4
OFF, which enables SPORT1 for the expansion interface II or for the
multi-function pins, in which case the port’s signals can be used for the
RSI or as push buttons. See “SPORT1 Enable Switch (SW4)” on page 2-9
for more information.

The ADC range is controlled by jumper JP4. This jumper selects whether
the input range for the ADC is 2.5V or 5 V. The max voltage range for a
signal connected to the SMA connector is 0–5V. Any voltage outside of
this range can damage the EZ-Board. For more information, see “ADC
Range Jumper (JP4)” on page 2-17.
Jumpers JP17–28 are used to connect the SMA connector to the ADC
input. When there is no input connected to the SMA connector, the
jumper should have the shunt installed on pins 2&3. This setting con-
nects the signal going to the ADC input to ground and keeps the noise
level low. When an input signal is connected to the SMA connector, the
shunt should be installed on position 1&2. For more information, see
“ADC Channel Select Jumpers (JP17–28)” on page 2-19.
For testing, switches SW22–23 connect an audio output signal from the
codec to the input channels of the ADC. Do not connect to the SMA con-
nectors and have these switches ON at the same time. For more
information, see “Mic/HP LPBK, Audio Mode Switch (SW6)” on
page 2-10.
UART Interface
The ADSP-BF518F processor has two built-in universal asynchronous
receiver transmitters (UARTs). UART0—1 share the processor’s pins with
other peripherals on the EZ-Board.
UART0 has full RS-232 functionality via the Analog Devices 3.3V
ADM3202 line driver and receiver (U21). When using UART0, do not set
switch SW10 position 4 to ON. This setting enables UART loopback and
should be installed only when running the POST program.
UART0 and UART1 are connected to the expansion interface II connectors.
For more information, see “Expansion Interface II Connectors (P2 and
P4)” on page 2-27.

RTC Interface

demonstrate UART and RS-232 operations.
For more information on the UART interface, refer to the ADSP-BF51x
Blackfin Processor Hardware Reference.
RTC Interface
The ADSP-BF518F processor has a real-time clock (RTC) and a watchdog
timer. Typically, the RTC interface is used to implement a real-time
watchdog or a life counter of the time elapsed since the last system reset.
The EZ-Board is equipped with a Panasonic CR1632 lithium coin and 3V
battery supplying 125 mAh. The 3V battery and 3.3V supply of the board
connect to the RTC power pin of the processor. When the EZ-Board is
powered, the RTC circuit uses the board power to supply voltage to the
RTC pin. When the EZ-Board is not powered, the RTC circuit uses the
lithium battery to maintain power to the RTC pin. After removing the
mylar, the battery lasts for about one year with the EZ-Board unpowered.
demonstrate the RTC features.
L The EZ-Board is shipped with a protective Mylar sheet placed

between the coin battery and positive pin of the battery holder.
Remove the Mylar sheet before using the RTC in the processor.
For more information on the RTC and watchdog timer, refer to the
ADSP-BF51x Blackfin Processor Hardware Reference.

LEDs and Push Buttons

The EZ-Board provides two push buttons and three LEDs for gen-
eral-purpose I/O, as well as two additional push buttons intended for
power down and wake functionality, which also can be used as GPIO flag
pins.
The three LEDs, labeled LED1 through LED3, are accessed via the PH3, PH5,
and PH6 pins of the processor (respectively). For information on how to
program the flag pins, refer to the ADSP-BF51x Blackfin Processor Hard-
ware Reference.
LED1 is shared with the ADC_A0, MMC_D7, and OTP_EN signals. LED2 is shared
with the CDG and ADC_A1 signals. LED3 is shared with the CZM and ADC_A2
signals.
The LED1—3 signals also connect to the expansion interface II connectors.
See “Expansion Interface II Connector (J1)” on page 2-25 and “Expansion
Interface II Connectors (P2 and P4)” on page 2-27 for more information.
The two general-purpose push buttons are labeled PB1 and PB2. The status
of each individual button can be read through programmable flag inputs
PH0 and PH1. The flag reads ‘1’ when a corresponding switch is being
pressed. When the switch is released, the flag reads ‘0’. A connection
between the push buttons and processor inputs is established through
positions 1&2 of the DIP switch SW2.
Push buttons 1 and 2 of SW2 are used as GPIO signals on the expansion
interface II connectors (J1, P2, P4). To use the PH0 and PH1 port pins as
GPIO signals on the expansion interface II, turn SW2 to all OFF.
PB1 is shared with the DR1PRI and MMC_D4 signals. PB2 is shared with the
RFS1 and MMC_D5 signals.
An example program is included in the ADSP-BF518F installation direc-

tory to demonstrate functionality of the LEDs and push buttons.

JTAG Interface
JTAG Interface
The JTAG connector (P1) allows the standalone debug agent to connect a
debug session to the ADSP-BF518F processor. The debug agent operates
only when the external 5V wall adaptor is used (J3). When operating the
EZ-Board from a battery or USB bus power, the debug agent is not
powered.
The standalone debug agent can be removed, and an external emulator
can be attached to the EZ-Board. Be careful not to damage the connectors
when removing the debug agent. The emulator connects to P1 on the back
side of the board. See “EZ-Board Installation” on page 1-4 for more
information.
For more information about emulators, contact Analog Devices or go to:
http://www.analog.com/processors/blackfin/evaluationDevelop-
ment/crosscore/.
Land Grid Array

The ADSP-BF518F EZ-Board has provisions for probing every port pin
and the EBIU interface of the processor on connectors P5—7. The connec-
tor locations are intended for use with a Tektronix DMAX logic analyzer
connector, but can be probed with any oscilloscope or logic analyzer. For
pinout information, refer to“ADSP-BF518F EZ-Board Schematic” on
page B-1.
For more information on the Tektronix DMAX logic analyzer interface,
go to the Tektronix Web site.

Expansion Interface II
The expansion interface II allows an Analog Devices EZ-Extender or a
custom-design daughter board to be tested across various hardware plat-
forms that have the same expansion interface.
The expansion interface II implemented on the ADSP-BF518F EZ-Board
consists of four connectors, three of which are 0.1 in. shrouded headers
(P2—4), and the last of which is a Samtec QMS series header (J1). The con-
nectors contain a majority of the ADSP-BF518F processor signals. For
pinout information, go to “ADSP-BF518F EZ-Board Schematic” on
page B-1. The mechanical dimensions of the expansion connectors can be
obtained by contacting Technical or Customer Support.
For more information about daughter boards, visit the Analog Devices
Web site at:
http://www.analog.com/processors/blackfin/evaluationDevelop-
ment/crosscore/.
Limits to current and interface speed must be taken into consideration

when using the expansion interface II. Current for the expansion
interface II is sourced from the EZ-Board; therefore, the current should be
limited to 1A for 5V and 500 mA for the 3.3V planes. If more current is
required, then a separate power connector and a regulator must be
designed on a daughter card. Additional circuitry can add extra loading to
signals, decreasing their maximum effective speed.
L Analog Devices does not support and is not responsible for the
effects of additional circuitry.

Power Measurements
Power Measurements
Several locations are provided for measuring the current draw from vari-
ous power planes. Precision 0.1 ohm shunt resistors are available on the
VDDINT, VDDEXT, VDDMEM, and VDDFLASH voltage domains.
For current draw measuments, the associated jumper (P8—11) should be
removed. Once the jumper is removed, the voltage across the resistor can
be measured using an oscilloscope. Once voltage is measured, current can
be calculated by dividing the voltage by 0.1. For the highest accuracy, a
differential probe should be used for measuring voltage across the resistor.
For more information, see “VDDINT Power Jumper (P8)” on page 2-19,
“VDDEXT Power Jumper (P9)” on page 2-19, “VDDMEM Power
Jumper (P10)” on page 2-20, and “VDDFLASH Power Jumper (P11)” on
page 2-20.
Power-On-Self Test
The power-on-self-test program (POST) tests all EZ-Board peripherals
and validates functionality as well as connectivity to the processor. Once
assembled, each EZ-Board is fully tested for an extended period of time
with a POST. All EZ-Boards are shipped with the POST preloaded into
one of its on-board flash memories. The POST is executed by resetting the
board and pressing the proper push button(s). The POST also can be used
as a reference for a custom software design or hardware troubleshooting.
Note that the source code for the POST program is included in the Visu-
alDSP++ installation directory along with the readme text file, which
describes how the EZ-Board is configured to run a POST.

Example Programs
Example programs are provided with the ADSP-BF518F EZ-Board to
demonstrate various capabilities of the product. The programs are
installed with the VisualDSP++ software and can be found in the
<install_path>\Blackfin\Examples\ADSP-BF518F EZ-Board directory.
Refer to the readme file provided with each example for more
information.
Background Telemetry Channel

The USB debug agent supports the background telemetry channel (BTC),
which facilitates data exchange between VisualDSP++ and the processor
without interrupting processor execution.
The BTC allows you to read and write data in real time while the proces-
sor continues to execute. For increased performance of the BTC,
including faster reading and writing, please check our latest line of proces-
sor emulators at:
http://www.analog.com/en/embedded-processing-dsp/sharc/USB-EMU-
LATOR/products/product.html. For more information about BTC, see the
online help.
Reference Design Information

A reference design info package is available for download on the Analog
Devices Web site. The package provides information on the design, lay-
out, fabrication, and assembly of the EZ-KIT Lite and EZ-Board
products.
The information can be found at:
http://www.analog.com/en/embedded-processing-dsp/con-
tent/reference_designs/fca.html.

Reference Design Information

2 ADSP-BF518F EZ-BOARD
HARDWARE REFERENCE
This chapter describes the hardware design of the ADSP-BF518F

EZ-Board board.
The following topics are covered.
• “System Architecture” on page 2-2
Describes the ADSP-BF518F EZ-Board configuration and explains
how the board components interface with the processor.
• “Programmable Flags” on page 2-3
Shows the locations and describes the programming flags (PFs).
• “Push Button and Switch Settings” on page 2-7
Shows the locations and describes the push buttons and switches.
• “Jumpers” on page 2-16
Shows the locations and describes the configuration jumpers.
• “LEDs” on page 2-21
Shows the locations and describes the LEDs.
• “Connectors” on page 2-24
Shows the locations and provides part numbers for the on-board
connectors. In addition, the manufacturer and part number infor-
mation is provided for the mating parts.

System Architecture
System Architecture
This section describes the processor’s configuration on the EZ-Board
(Figure 2-1).
64 MB 4 MB
SDRAM Flash
(32M x 16) (2M x 16 )
32.768 KHz SD
3.3 Volts 3.3 Volts
Oscillator
3.3 volt Connector
eMMC
RTC EBIU RSI
2GB
JTAG
IDC Conn
Port
UP/DN
CNTR
14 Pin 0.1
Rotary
High Speed I/O
Low Speed Group
Micrel ADSP-BF518F
Low Speed
Low Speed
Group 2A
Group 1A
Processor
MAC
LEDs KSZ8893
400 MHz
1B
(8)
3.3 Volts 176-lead LQFP LEDs (3)
GPIO
PBs (2)
RJ45 RJ45
UARTs CLKIN SPI SPORT TWI SPORT
16 Mb
SPI Flash
3.3 Volts
12 bit 4
RS-232 25 MHz SSM2602 3 Channel A/D Differential
TX/RX Oscillator Codec AD7266 Inputs
3.3 Volts 3.3 Volts
3.3 Volts
4 Single
Ended
RS-232 Inputs
Female
12 MHz
Mic Aud Head Aud
Oscillator
In In Out Out
3.3 Volts
Figure 2-1. System Architecture
This EZ-Board is designed to demonstrate the ADSP-BF518F Blackfin

processor capabilities. The processor has an I/O voltage of 3.3V. The core
voltage of the processor is controlled by an Analog Devices ADP1715 low
dropout regulator (LDO) and an Analog Devices AD5258 digipot, which

ADSP-BF518F EZ-Board Hardware Reference
is configurable over the 2-wire interface (TWI) signals. Refer to the

power-on-self test (POST) example in the ADSP-BF518F installation
directory of VisualDSP++ for information on how to set up the TWI
interface.
The core voltage and clock rate can be set on the fly by the processor. The
input clock is 25 MHz. A 32.768 kHz crystal supplies the real-time clock
(RTC) inputs of the processor. The default boot mode for the processor is
external parallel flash boot. See “Boot Mode Select Switch (SW1)” on
page 2-8 for information on how to change the default boot mode.
Programmable Flags
The processor has 40 general-purpose input/output (GPIO) signals spread
across three ports (PF, PG, and PH). The pins are multi-functional and
depend on the ADSP-BF518F processor setup. The following tables show
how the programmable flag pins are used on the EZ-Board.
• PF programmable flag pins – Table 2-1
• PG programmable flag pins – Table 2-2
• PH programmable flag pins – Table 2-3
Table 2-1. PF Port Programmable Flag Connections

Processor Pin Other Processor Function EZ-Board Function
PF0 ETxD2/PPID0/SPI1_SSEL2/TA Default: ETXD2

CLK6 Land grid array, expansion interface II
PF1 ERxD2/PPID1/PWM_AH/TACLK7 Default: ERXD2

Land grid array, expansion interface II
PF2 ETxD3/PPID2/PWM_AL Default: ETXD3

PF3 ERxD3/PPID3/PWM_BH/TACLK0 Default: ERXD3


Programmable Flags
Table 2-1. PF Port Programmable Flag Connections (Cont’d)

PF4 ERx- Default: ERXCLK

CLK/PPID4/PWM_BL/TACLK1 Land grid array, expansion interface II
PF5 ERxDV/PPID5/PWM_CH/TACI0 Default: ERXDV

PF6 COL/PPID6/PWM_CL/TACI1 Default: COL

PF7 SPI0_SSEL1/PPID7/PWM_SYNC Default: SPI0_SSEL1

PF8 MDC/PPID8/SPI1_SSEL4 Default: MDC

PF9 RMIIMDIO/PPID9/TMR2 Default: MDIO

PF10 ETxD0/PPID10/TMR3 Default: ETXD0

PF11 ERxD0/PPID11/PWM_AH/TACI3 Default: ERXD0

PF12 ETxD1/PPID12/PWM_AL Default: ETXD1

PF13 ERxD1/PPID13/PWM_BH Default: ERXD1

PF14 ETxEN/PPID14/PWM_BL Default: ETXEN
PF15 RMII_PHYINT/PPID15/ Default: RMII_PHYINT

PWM_SYNC Land grid array, expansion interface II

Table 2-2. PG Port Programmable Flag Connections

PG0 MIICRS/RMII- Default: MIICRS

CRS/HWAIT/SPI1_SSEL3 HWAIT, land grid array, expansion interface II
PG1 ERxER/DMAR1/PWM_CH Default: ERXER

PG2 MIITxCLK/RMIIREF_CLK/ Default: MIITXCLK

DMAR0/PWM_CL Land grid array, expansion interface II
PG3 DR0PRI/RSI_DATA0/ Default: DR0PRI

SPI0_SSEL5/TACLK3 SD_D0, land grid array, expansion interface II
PG4 RSCLK0/RSI_DATA1/TMR5/ Default: RSCLK0

TACI5 SD_D1, land grid array, expansion interface II
PG5 RFS0/RSI_DATA2/PPICLK_1/ Default: RFS0

TMRCLK SD_D2, land grid array, expansion interface II
PG6 TFS0/RSI_DATA3/TMR0/ Default: TFS0

PPIFS1_1 SD_D3, land grid array, expansion interface II
PG7 DT0PRI/RSI_CMD/TMR1/ Default: DT0PRI

PPIFS2_1 SD_CMD, land grid array, expansion interface II
PG8 TSCLK0/RSI_CLK/TMR6/TACI6 Default: TSCLK0

SD_CLK, land grid array, expansion interface II
PG9 DT0SEC/UART0_TX/TMR4 Default: UART0_TX

PG10 DR0SEC/UART0_RX/TACI4 Default: UART0_RX
PG11 SPI0_SS/AMS[2]/SPI1_SSEL5/ Default: AMS2

TACLK2 Land grid array, expansion interface II
PG12 SPI0_SCK/PPICLK_2/TMRCLK Default: SPI0_SCK
PG13 SPI0_MISO/TMR0/PPIFS1_2 Default: SPI0_MISOI


Programmable Flags
Table 2-2. PG Port Programmable Flag Connections (Cont’d)

PG14 SPI0_MOSI/TMR1/PPIFS2_2/ Default: SPI0_MOSI

PWM_TRIPB Land grid array, expansion interface II
PG15 SPI0_SSEL2/PPIFS3/AMS[3] Default: AMS3

SPI0_SEL2, land grid array, expansion
interface II
Table 2-3. PH Port Programmable Flag Connections

PH0 DR1PRI/SPI1_SS/RSI_DATA4 Default: PB1

DR1PRI, MMC_D4, land grid array, expansion
interface II
PH1 RFS1/SPI1_MISO/RSI_DATA5 Default: PB2
RFS1, MMC_D5, land grid array, expansion
interface II
PH2 RSCLK1/SPI1_SCK/RSI_DATA6 Default: not used

RSCLK1, MMC_D6, land grid array, expansion
interface II
PH3 DT1PRI/SPI1_MOSI/RSI_DATA7 Default: LED1
ADC_A0, MMC_D7, OTP_EN, land grid array,
expansion interface II
PH4 TFS1/AOE/SPI0_SSEL3/CUD Default: SPI0_SSEL3
CUD, land grid array, expansion interface II
PH5 TSCLK1/ARDY/ECLK/CDG Default: LED2

CDG, ADC_A1, land grid array, expansion
interface II
PH6 DT1SEC/UART1_TX/ Default: LED3
SPI1_SSEL1/CZM CZM, ADC_A2, land grid array, expansion
interface II
PH7 DR1SEC/UART1_RX/TMR7/TACI2 Default: not used
DR1SEC, land grid array, expansion interface II

Push Button and Switch Settings

This section describes operation of the push buttons and switches. The
push button and switch locations are shown in Figure 2-2.
Figure 2-2. Push Button and Switch Locations

Boot Mode Select Switch (SW1)

The boot mode select switch (SW1) determines the boot mode of the pro-
cessor. Table 2-4 shows the available boot mode settings. By default, the
ADSP-BF518F processor boots from the on-board parallel flash memory.
L entire
The selected position of is marked by the notch down the
SW1
rotating portion of the switch, not the small arrow.
Table 2-4. Boot Mode Select Switch (SW1)

SW1 Position Processor Boot Mode
0 Reserved
1 Boot from 8- or 16-bit external flash memory (default)
2 Boot from 16-bit asynchronous FIFO
3 Boot from serial SPI memory
4 Boot from SPI host device
5 Boot from serial TWI memory
6 Boot from TWI host
7 Boot from UART0 host
PB Enable Switch (SW2)

The PB enable switch (SW2) disconnects the associated push buttons from
the GPIO pins of the processor and allows the signals to be used for other
purposes (see Table 2-5).

Table 2-5. Push Button Enable Switch (SW2)

SW2 Position (Default) From To Function
1 (ON) Push button 1 (SW12) Processor ON (PB1)

(U12, PH0) OFF (ADC DR1PRI, eMMC,
expansion interface II)
2 (ON) Push button 2 (SW13) Processor ON (PB2)

(U12, PH1) OFF (ADC RFS1, eMMC,
expansion interface II)
Flash Enable Switch (SW3)

The flash enable switch (SW3) disconnects the ~AMSx signals from parallel
flash memory (U5) and allows other devices to utilize the signals via the
expansion interface II. For each switch listed in Table 2-6 that is turned
OFF, the size of available flash memory is reduced by 1 MB. ~AMS3 is shared
with ~SPI0_SEL2 of the external SPI flash. When using the external SPI
flash, the available size for parallel flash is 3 MB.
Table 2-6. Flash Enable Switch (SW3)

SW3 Switch Position (Default) Processor Signal
1 (ON) ~AMS0
2 (ON) ~AMS1
3 (ON) ~AMS2
4 (ON) ~AMS3
SPORT1 Enable Switch (SW4)

The SPORT1 enable switch (SW4) connects the SPORT1 interface of the pro-
cessor to the ADC7266 (U2) device. When the SPORT1 interface is used on
the expansion interface II, turn SW4 all OFF. SW4 is set to all OFF by default.

The SPORT1 interface is shared with other on-board components, such as

the eMMC device and push buttons.
MIC Gain Switch (SW5)

The microphone gain switch (SW5) sets the gain of the MIC signal, which is
connected to the top 3.5 mm jack (J5). The gain can be set to 14 dB,
0 dB, or –6 dB by turning position 1, 2, or 3 of SW5 ON (see Table 2-7).
When the corresponding position for the desired gain is ON, the remaining
positions must be OFF. Refer to “Audio Interface” on page 1-17 for more
information about the audio codec.
Table 2-7. MIC Gain Switch (SW5)

Gain SW5 Switch Settings
5 (14 dB) ON, OFF, OFF, OFF
1 (0 dB) OFF, ON, OFF, OFF
0.5 (–6 dB) OFF, OFF, ON, OFF (default)
Unused OFF, OFF, OFF, OFF
Mic/HP LPBK, Audio Mode Switch (SW6)

The SW6 switch places the EZ-Board in a loopback to test the board for
signal/circuit continuity and functionality. SW6 positions 1&2 connect the
MICIN signal to the headphone’s left and right outputs for audio loopback.
Do not turn SW6 positions 1&2 ON at the same time. See “Power-On-Self
Test” on page 1-24 for more information.
SW6 positions 3&4 select the control interface for the audio codec.
SW6 positions 3 ON and 4 OFF select the SPI interface, while position 3 OFF
and position 4 ON select TWI mode. By default, SW6 is OFF, OFF, ON, OFF.
See “SPI/TWI Switch (SW16)” on page 2-13 for more information.

Ethernet Port 1 Configuration Switch (SW7)

The Ethernet port 1 configuration switch (SW7) is used to configure cer-
tain Ethernet settings related to port 1 via hardware, instead of software
(see Table 2-8).
Table 2-8. Ethernet Port 1 Configuration Switch (SW7)

SW7 Position (Default) Description Position Function
1 (ON) Force flow control OFF Disable

ON Enable
2 (ON) Force full/half OFF Half duplex

ON Full duplex
3 (ON) Force speed OFF 10BaseT

ON 100BaseTX
4 (OFF) Auto-negotiation OFF Enable

ON Disable
Ethernet Configuration Switch (SW8)

The Ethernet configuration switch (SW8) is used to configure certain
Ethernet settings via hardware, instead of software (see Table 2-9).
Table 2-9. Ethernet Configuration Switch (SW8)

1 (ON) Advertise flow control OFF Disable

ON Enable
2 (ON) Hardware pin overwrite OFF Enable

ON Disable
3, 4 (ON, OFF) Serial bus mode OFF OFF Not used

OFF ON TWI slave
ON OFF SPI slave
ON ON Not used

UART Setup Switch (SW10)

The UART setup switch (SW10) configures the UART0 signals from the
GPIO pins of the processor. Position 4 is used to place the UART0 port of
the processor in a loopback condition. The jumper connects the UART0_TX
line of the processor to the UART0_RX signal of the processor. This is
required when a POST program is run to test the serial port interface. By
default, SW10 is ON, OFF, ON, OFF.
Reset Push Button (SW11)

The reset push button (SW11) resets the following ICs.
• Processor (U12), parallel flash (U5), and Ethernet IC (U4)
The reset push button does not reset the following ICs.
• SDRAM (U14), eMMC (U16)
• Audio codec (U1), UART0 (U21), schmitt trigger hex inverter (U6)
• Digipot (U7), power (VR1—5)
The reset push button does not reset the standalone debug agent once the
debug agent is connected to a personal computer (PC). After communica-
tion between the debug agent and PC is initialized, pushing a reset button
does not reset the USB chip on the debug agent. The only way to reset the
USB chip on the debug agent is to power down the EZ-Board.
Programmable Flag Push Buttons (SW12–13)

Two momentary push buttons (SW12 and SW13) are provided for gen-
eral-purpose user input. The buttons connect to the PH0 and PH1 GPIO
pins of the processor. The push buttons are active high and, when pressed,

send a high (1) to the processor. The GPIO enable switch (SW2) discon-
nects the push buttons from the corresponding push button signals. Refer
to “PB Enable Switch (SW2)” on page 2-8 for more information.
Rotary Encoder with Momentary Switch (SW14)

The rotary encoder (SW14) can be turned clockwise for an up count or
counter-clockwise for a down count. The encoder also features a momen-
tary switch, activated by pushing the switch towards the processor, which
resets the counter to zero. The rotary encoder is a two-bit quadrature (gray
code) encoder. Refer to the Rotary Counter section of the ADSP-BF51x
Blackfin Processor Hardware Reference for more information.
The rotary encoder is disconnected from the processor by setting SW19
positions 1, 2, and 3 to OFF. See “Encoder Enable Switch (SW19)” on
page 2-14 for more information.
SPORT0 ENBL Switch (SW15)

The SPORT0 enable switch (SW15) connects the SPORT0 interface of the pro-
cessor to the audio codec, SSM2602 (U1). When the SPORT0 interface is
used on the expansion interface II, turn SW15 all OFF. By default, SW15 is
set to all ON.
SPI/TWI Switch (SW16)

The SPI/TWI switch (SW16) selects the control interface for the SSM2602
audio codec. By default, SW16 is ON, OFF, ON, OFF, ON, OFF and selects the
SPI interface. TWI is selected by setting SW16 to OFF, OFF, OFF, ON, OFF, ON.

Ethernet Mode Switch (SW17)

The Ethernet mode switch (SW17) selects the control interface for the
KSZ8893M device. By default, SW17 is ON, ON, ON, OFF, ON, OFF and
selects the SPI interface. TWI is selected by setting SW17 to OFF, OFF, OFF,
ON, OFF, ON.
Ethernet Port 2 Configuration Switch (SW18)

The Ethernet port 2 configuration switch (SW18) is used to configure cer-
tain Ethernet settings related to port 1 via hardware, instead of software
(see Table 2-10).
Table 2-10. Ethernet Port 2 Configuration Switch (SW18)

1 (ON) Force flow control OFF Disable

ON Enable
2 (ON) Force full/half OFF Half duplex

ON Full duplex
3 (ON) Force speed OFF 10BaseT

ON 100BaseTX
4 (OFF) Auto-negotiation OFF Enable

ON Disable
5 (OFF) Auto MDI/MDI-X OFF Enable

ON Disable
6 (OFF) MDI/MDI-X setting OFF MDI-X
ON MDI
Encoder Enable Switch (SW19)

The encoder enable switch (SW19) disconnects the rotary encoder signals
from the GPIO pins of the processor. When SW19 is OFF, its associated
GPIO signals can be used on the expansion interface II (see Table 2-11).

Table 2-11. Encoder Enable Switch (SW19)

SW19 Position (Default) From To
1 (OFF) Encoder (SW14) Processor (U1, PF13)
eMMC Enable Switch (SW20–21)

The eMMC enable switches (SW20 and SW21) connect the RSI signals to
the on-board eMMC memory device. The eMMC interface and the SD
interface share the same signals; therefore, no card should be inserted into
the SD connector when the eMMC device is used. The default for the
switches is all OFF so that the SD connector can be used.
ADC Loopback Switches (SW22–23)

The ADC loopback switches (SW22 and SW23) are used for testing only.
The switches are used to send an analog signal generated from the codec to
the ADC circuit for evaluation.

Jumpers
Jumpers
This section describes functionality of the configuration jumpers.
Figure 2-2 shows the jumper locations.
Figure 2-3. Configuration Jumper Locations

Flash WP Jumper (JP3)

The flash WP jumper (JP3) is used to write-protect block 70 of the paral-
lel flash chip. Block 70 contains 64 KB of configuration data at address
range 0x203 F0000—0x203 FFFFF. When the jumper is installed on JP3,
and the parallel flash driver from Analog Devices is used, block 70 is
read-only. By default, JP3 is installed.
ADC Range Jumper (JP4)

The ADC range jumper JP4 is used to select the range of the input signal
to the ADC. The jumper determines whether the input range for the ADC
is 2.5V or 5 V. The max voltage range for a signal connected to the SMA
connector is 0–5V. Any voltage outside of this range can damage the
EZ-Board. By default, JP4 is installed.
LED Select Jumpers (JP11–12)

The LED select jumpers (JP11 and JP12) are used to configure how Ether-
net status is reported on the LEDs. By default, JP11 is installed, and JP12
is not installed. The LEDs can be used to report the status of the link,
activity on the line, duplex mode speed, and collisions. For more informa-
tion about the LEDs, refer to the KSZ8893M data sheet provided by the
product manufacturer.
Ethernet Power Down Jumper (JP13)

The Ethernet power down jumper (JP13) is used to put the KSZ8893M
PHY into a power down mode. In this mode, the entire chip is powered
down, and the register configuration is not saved. By default, JP13 is not
installed.

Jumpers
OTP Flag Enable Jumper (JP14)

The OTP flag enable jumper (JP14) controls the precise 7V OTP voltage
regulator. When installed, JP14 allows OTP writes.
JP14 must be installed for OTP writes to be successful. The nominal 2.5V
for OTP is temporarily raised to 7V when PH3 is set high. Care must be
taken when using the OTP_FLAG signal in order to avoid driving 7V for an
extended amount of time.
a There is a limited amount of time 7V can be applied to the proces-

sor’s OTP interface. Violating the specifications listed in the
ADSP-BF512/ADSP-BF514/ADSP-BF516/ADSP-BF518 Blackfin
Embedded Processor data sheet can damage the processor.
Configured properly, JP14 connects the processor’s PH3 flag pin to the
shut-down pin of the ADP1611 switching converter. Refer to the
ADSP-BF51x Blackfin Processor Hardware Reference Manual and the
ADSP-BF512/ADSP-BF514/ADSP-BF516/ADSP-BF518 Blackfin Embed-
ded Processor data sheet for more information about OTP writes.
MIC Select Jumper (JP15)

The microphone select jumper (JP15) connects the MICBIAS signal to the
MICIN signal (JP15 on positions 1&2) or connects the MICBIAS signal to
the 3.5 mm connector J5 (JP15 on positions 2&3). By default, JP15 is
installed on positions 2&3.
SPI FLASH CS Enable Jumper (JP16)

The SPI flash CS enable jumper (JP16) connects the SPI0_SSEL2 signal to
the SPI flash. When installing JP16, position 3 of SW3 needs to be turned
OFF since the SPI0_SSEL2 signal is shared with the ~AMS3 signal connected

to parallel flash. When using SPI flash, the available memory that is acces-
sible on parallel flash is reduced from 4 MB to 3 MB. By default, JP16 is
not installed.
ADC Channel Select Jumpers (JP17–28)

The ADC channel select jumpers JP17—28 are used to connect the SMA
connector to the ADC input. When there is no input connected to the
SMA connector, the jumper should have the shunt installed on pins 2&3.
This connects the signal going to the ADC input to ground and keeps the
noise level low. When an input signal is connected to the SMA connector,
the shunt should be installed on position 1&2. By default, JP17—28 are
installed on positions 2&3.
VDDINT Power Jumper (P8)

The VDDINT power jumper (P8) is used to measure the core voltage and
current supplied to the processor core. P8 is ON by default, and the power
flows through the two-pin IDC header. To measure power, remove P8 and
measure voltage across the 0.1 ohm resistor. Once voltage is measured,
power can be calculated. For more information, refer to “Power Measure-
ments” on page 1-24.
VDDEXT Power Jumper (P9)

The VDDEXT power jumper (P9) is used to measure the processor’s I/O
voltage and current. By default, P9 is ON, and the power flows through the
two-pin IDC header. To measure power, remove the jumper and measure
voltage across the 0.1 ohm resistor. Once voltage is measured, power can
be calculated. For more information, refer to “Power Measurements” on
page 1-24.

Jumpers
VDDMEM Power Jumper (P10)

The VDDMEM power jumper (P10) is used to measure the voltage and
current supplied to the memory interface of the processor. By default, P10
is ON, and the power flows through the two-pin IDC header. To measure
power, remove P10 and measure voltage across the 0.1 ohm resistor. Once
voltage is measured, power can be calculated. For more information, refer
to “Power Measurements” on page 1-24.
VDDFLASH Power Jumper (P11)

The VDDFLASH power jumper (P11) is used to measure the flash voltage
and current supplied to the processor core. P11 is ON by default, and the
power flows through the two-pin IDC header. To measure power, remove
P11 and measure voltage across the 0.1 ohm resistor. Once voltage is mea-
sured, power can be calculated. For more information, refer to “Power
Measurements” on page 1-24.

LEDs
This section describes the on-board LEDs. Figure 2-4 shows the LED
locations.
Figure 2-4. LED Locations

LEDs
GPIO LEDs (LED1–3)

Three LEDs connect to three general-purpose I/O pins of the processor
(see Table 2-12). The LEDs are active high and lit by writing a ‘1’ to the
correct programmable flag signal.
Table 2-12. GPIO LEDs

LED Reference Designator Processor Programmable Flag Pin
LED1 PH3
LED2 PH5
LED3 PH6
Ethernet LEDs (LED4–8, LED10–12)

The Ethernet LEDs LED4—8 and LED10—12 are used to report the status of
port 1 and port 2 of the KSZ8893M switch. The status displayed by the
LEDs is controlled by jumpers JP11 and JP12. The LEDs can be used to
report the status of the link, activity on the line, duplex mode speed, and
collisions. For more information on the LEDs, refer to the KSZ8893M
data sheet provided by the product manufacturer. For more information,
see “LED Select Jumpers (JP11–12)” on page 2-17.
Reset LED (LED9)

When LED9 is lit, it indicates that the master reset of all major ICs is
active. The reset LED is controlled by the Analog Devices ADM708
supervisory reset circuit. You can assert the reset push button (SW11) to
assert the master reset and activate LED9. For more information, see “Reset
Push Button (SW11)” on page 2-12.

Power LED (LED13)

When LED13 is lit solid, it indicates that the board is powered.

Connectors
Connectors
This section describes connector functionality and provides information
about mating connectors. The connector locations are shown in Figure 2-5.
Connectors shown with a dotted line are on the backside of the PCB
Figure 2-5. Connector Locations

Expansion Interface II Connector (J1)

J1 is a board-to-board connector providing signals from the external bus
interface unit (EBIU) of the processor. The connector is located on the
left edge of the board. For more information, see “Expansion Interface II”
on page 1-23. For availability and pricing of the connector, contact
Samtec.
Part Description Manufacturer Part Number
104-position 0.025”, SMT header SAMTEC QMS-052-11-L-D-A
Mating Connector
104-position 0.025”, SMT socket SAMTEC QFS-052-01-L-D-A
RS-232 Connector (J2)
DB9, female, vertical mount NORCOMP 191-009-213-L-571
Mating Cable
2m female-to-female cable DIGI-KEY AE1020-ND
Power Connector (J3)

The power connector (J3) provides all of the power necessary to operate
the EZ-Board.
0.65 mm power jack CUI 045-0883R
Mating Power Supply (shipped with the EZ-Board)
5.0VDC@2.5A power supply CUI STACK DMS050260-P12P-SZ

Connectors
Dual Audio Connectors (J4–5)
3.5 mm dual stereo jack SWITCHCRAFT 35RAPC7JS
Mating Cable (shipped with the EZ-Board)
3.5 mm male/male 6’ cable RANDOM 10A3-01106
SMA Connectors (J7, J16–26)
SMA straight jack receptacle JOHNSON COMPONENTS 142-0701-201
SMA male/male 18" cable CRYSTEK CORPORATION CCMA-MM-18
Battery Holder (J12)
16 mm battery holder MEMORY PROTECTION BH600
Mating Battery (shipped with the EZ-Board)
3V 125MAH 16 mm LI-COIN PANASONIC CR1632
SD Connector (J13)
SD 9-pin connector ITT CANON CCM05-5777LFT T50
Mating Memory Card (shipped with the EZ-Board)
256 MB SANDISK STACK SDSDB-256-A10

Ethernet Connectors (J14–15)
RJ-45 Ethernet jack STEWART SS-6488-NF
Cat 5E patch cable RANDOM PC10/100T-007
JTAG Connector (P1)

The JTAG header is the connecting point for a JTAG connection to the
ADSP-BF518F processor. The standalone debug agent requires both con-
nectors P1 and ZP1.
Pin 3 is missing to provide keying. Pin 3 in the mating connector should
have a plug.
When using an emulator with the EZ-Board, the standalone debug agent
must be removed. Follow the installation instructions provided in
“EZ-Board Installation” on page 1-4, using P1 as the JTAG connection
point.
Expansion Interface II Connectors (P2 and P4)

P2 and P4 are board-to-board connectors providing signals for the SPI,
TWI, UART, SPORT interfaces and GPIO signals of the processor. The
connectors are located on the upper and lower edges of the board. For
more information, see “Expansion Interface II” on page 1-23. For avail-
ability and pricing of the connectors, contact Samtec.
50-position 0.1”, SMT header SAMTEC TSSH-125-01-L-DV-A
A D S P -B F 5 1 8 F E Z -B o a rd E v a lu a tio n S y ste m M a n u a l 2-27

Connectors
Mating Connector
50-position 0.1”, SMT socket SAMTEC SSW-125-22-F-D-VS
Expansion Interface II Connector (P3)

P3 is a board-to-board connector providing signals for the PPI, TWI, and
GPIO signals of the processor. The connector is located on the upper edge
of the board. For more information, see “Expansion Interface II” on
page 1-23. For availability and pricing of the connector, contact Samtec.
70-position 0.1”, SMT header SAMTEC TSSH-135-01-L-DV-A
Mating Connector
70-position 0.1”, SMT socket SAMTEC SSW-135-22-F-D-VS
DMAX Land Grid Array Connectors (P5–7)

The land grid array areas (P5—7) are intended for the probing of the pro-
cessor signals. The pads are exposed and designed to attach a Tektronix
logic analyzer to the connectors listed in the following table. For more
information about the land grid array, consult the Tektronix Web site.
Primary retention TEKTRONIX 020290800
Alternate retention TEKTRONIX 020291000

Standalone Debug Agent Connector (ZP1)

ZP1 connects the standalone debug agent to the EZ-Board. The standalone
debug agent requires both the ZP1 and P1 connectors. For more informa-
tion, see “EZ-Board Installation” on page 1-4.

Connectors

A ADSP-BF518F EZ-BOARD
BILL OF MATERIALS
The bill of materials corresponds to “ADSP-BF518F EZ-Board Schematic” on

page B-1.
Ref. Qty. Description Reference Manufacturer Part Number

Designator
1 1 74LVC14A U6 TI 74LVC14AD
SOIC14
2 1 IDT74FCT3244A U10 IDT IDT74FCT3244APYG

PY SSOP20
3 1 32.768KHZ U3 EPSON MC-156-32.7680KA-A0:

OSC008 ROHS
4 1 25MHZ OSC003 U19 EPSON SG-8002CA MP
5 4 SN74LVC1G08 U23-26 TI SN74LVC1G08DBVR

SOT23-5
6 1 MT48LC32M16A U14 MICRON MT48LC32M16A2P-75

2TG-75 TSOP54
7 1 SI4411DY SO-8 U8 VISHAY Si4411DY-T1-E3
8 2 HX1188 ICS007 U27-28 DIGI-KEY 553-1340-ND
9 1 12MHZ OSC003 U20 EPSON SG-8002CA-MP
10 1 SN74AUC1G00 U13 TI SN74AUC1G00DBVR

SOT23-5
11 1 KS8893M U4 MICREL KSZ8893MQL

PQFP128
12 1 BF518 M25P16 U9 ST MICRO M25P16-VMW6G

“U9”
ADSP-BF518F EZ-Board Evaluation System Manual A-1

Designator
13 1 BF518 U5 STMICRO M29W320EB70ZE6E
M29W320EB
"U5"
14 1 MTFC2GDKDM U16 MICRON MTFC2GDKDM-WT

FBGA169
15 1 ADM708SARZ U22 ANALOG ADM708SARZ

SOIC8 DEVICES
16 1 ADM3202ARNZ U21 ANALOG ADM3202ARNZ

SOIC16 DEVICES
17 1 ADSP-BF518F U12 ANALOG ADSP-BF518BSWZ-4F4

LQFP176 DEVICES
18 1 ADP1864AUJZ VR1 ANALOG ADP1864AUJZ-R7

SOT23-6 DEVICES
19 1 ADP1611 VR6 ANALOG ADP1611ARMZ-R7

MSOP8 DEVICES

MSOP8
21 1 ADP1710 TSOT5 VR3 ANALOG ADP1710AUJZ-R7

DEVICES
22 1 ADR550B U11 ANALOG ADR550BRTZ-REEL7
SOT23-3 DEVICES
23 1 AD5258 U7 ANALOG AD5258BRMZ10

MSOP10 DEVICES
24 1 SSM2602 ICS009 U1 ANALOG SSM2602CPZ-R2

DEVICES
25 1 ADP1715 VR4 ANALOG ADP1715ARMZ-1.8R7

MSOP8 DEVICES
26 6 AD8022 MSOP8 U29-34 ANALOG AD8022ARMZ

DEVICES
27 1 AD7266 U2 ANALOG AD7266BCPZ

LFCSP32 DEVICES
A-2 ADSP-BF518F EZ-Board Evaluation System Manual

ADSP-BF518F EZ-Board Bill Of Materials

Designator
MSOP8 DEVICES
29 1 DIP3 SWT015 SW19 DIGI-KEY CKN6114-ND
30 1 DIP8 SWT016 SW20 C&K TDA08H0SB1
31 6 DIP6 SWT017 SW15-18,SW22- CTS 218-6LPST

23
32 7 DIP4 SWT018 SW3-8,SW10 ITT TDA04HOSB1
33 12 SMA XPINS J7,J16-26 JOHNSON 142-0701-201

CON043 COMP
34 1 DB9 9PIN J2 NORCOMP 191-009-213-L-571

CON038
35 2 DIP2 SWT020 SW2,SW21 C&K CKN9064-ND
36 4 IDC 2X1 P8-11 FCI 90726-402HLF

IDC2X1
37 5 IDC 2X1 JP3,JP11-14 FCI 90726-402HLF

IDC2X1
38 13 IDC 3X1 JP15,JP17-28 FCI 90726-403HLF

IDC3X1
39 1 3A RESETABLE F1 TYCO SMD300F-2

FUS004
40 24 IDC SJ1-24 DIGI-KEY S9001-ND

2PIN_JUMPER_
SHORT
41 1 PWR .65MM J3 CUI 045-0883R

CON045
42 2 3.5MM J4-5 SWITCHCRAFT 35RAPC7JS

DUAL_STEREO
CON050
43 1 SD_CONN 9PIN J13 DIGI-KEY 401-1954-ND

CON051

Designator
44 2 RJ45 8PIN J14-15 DIGI-KEY 380-1022-ND
CON_RJ45_12P
45 3 MOMENTARY SW11-13 PANASONIC EVQ-Q2K03W

SWT024
46 1 ROTARY_ENC_ SW14 PANASONIC EVQ-WKA001

EDGE SWT025
47 1 QMS 52x2 J1 SAMTEC QMS-052-06.75-L-D-A

QMS52x2_SMT
48 2 IDC 25x2 P2,P4 SAMTEC TSSH-125-01-L-DV-A

IDC25x2_SMTA
49 1 IDC 35x2 P3 SAMTEC TSSH-135-01-L-DV-A

IDC35x2_SMTA
50 1 IDC 7x2 P1 SAMTEC TSM-107-01-T-DV-A

IDC7x2_SMTA
51 1 BATT_HOLDER J12 MEMORY PRO- BH600

16MM TECTI
BATT_COI
52 2 IDC 2X1 JP4,JP16 SAMTEC TSM-102-01-T-SV

IDC2X1_SMT
53 1 ROTARY SW1 COPAL S-8010
SWT027
54 3 YELLOW LED1-3 PANASONIC LN1461C

LED001
55 2 100 1/10W 5% R165,R167 VISHAY CRCW0805100RJNEA

0805
56 11 600 100MHZ FER2-9,FER12- DIGI-KEY 490-1014-2-ND

200MA 0603 14
57 2 600 100MHZ FER15-16 STEWARD HZ1206B601R-10

500MA 1206
58 2 10UF 16V 20% CT1-2 PANASONIC EEE1CA100SR

CAP002


Designator
59 1 0 1/10W 5% 0805 R69 VISHAY CRCW08050000Z0EA
60 1 190 100MHZ 5A FER17 MURATA DLW5BSN191SQ2

FER002
61 8 YELLOW LED4-8,LED10- PANASONIC LNJ416Q8YRA

LED009 12
62 2 0.47UF 16V 10% C59-60 AVX 0805YC474KAT2A

0805
63 2 1UF 10V 10% C123-124 AVX 0805ZC105KAT2A

0805
64 18 10UF 6.3V 10% C7,C10,C15- AVX 08056D106KAT2A

0805 16,C37,C41,C61,
C64,C66,C71,
C75,C88,C90,
C94-95,C98,
C101,C106
65 1 4.7UF 6.3V 10% C145 AVX 08056D475KAT2A

0805
66 47 0.1UF 10V 10% C4-6,C9,C11- AVX 0402ZD104KAT2A

0402 14,C25,C39,C42-
45,C47-48,C62-
63,C65,C72,C76,
C86-87,C89,
C108-110,C113,
C115-118,C140,
C152,C188-194,
C211-216
67 59 0.01UF 16V 10% C1,C8,C17-24, AVX 0402YC103KAT2A

0402 C26-36,C38,C46,
C49-58,C73,C92-
93,C96-97,C99-
100,C102-105,
C119-122,C139,
C154,C179-187

Designator
68 48 10K 1/16W 5% R1,R11,R18-21, VISHAY CRCW040210K0FKED
0402 R26,R56-59,R85-
87,R89,R106-
108,R110-115,
R117,R143-145,
R152,R154-156,
R161-164,R168,
R170-173,R203,
R245,R268,R270,
R353-355
69 9 4.7K 1/16W 5% R6-8,R13-17, VISHAY CRCW04024K70JNED

0402 R269
70 27 0 1/16W 5% 0402 R9,R202,R205- PANASONIC ERJ-2GE0R00X

206,R209-212,
R214-215,R217-
218,R221-222,
R224-225,R227-
228,R230-233,
R235-236,R238-
239,R267
71 10 22 1/16W 5% R146-151,R241- PANASONIC ERJ-2GEJ220X

0402 244
72 3 33 1/16W 5% R313-314,R325 VISHAY CRCW040233R0JNEA

0402
73 7 33 1/16W 5% R3,R12,R60,R66- VISHAY CRCW040233R0JNEA

0402 67,R78,R199
74 2 18PF 50V 5% C2-3 AVX 08055A180JAT2A

0805
75 2 2.2UF 10V 10% C150-151 AVX 0805ZD225KAT2A

0805
76 24 10PF 50V 5% C155-178 AVX 08055A100JAT2A

0805
77 2 0.1UF 16V C40,C136 AVX 0603YC104KAT2A

10%0603


Designator
78 5 1UF 16V 10% C79-81,C199, PANASONIC ECJ-1VB1C105K
0603 C208
79 1 68PF 50V 5% C144 AVX 06035A680JAT2A

0603
80 3 4.7UF 6.3V 20% C137-138,C141 PANASONIC ECJ-1VB0J475M

0603
81 1 470PF 50V 5% C143 AVX 06033A471JAT2A

0603
82 3 220UF 6.3V 20% CT3-4,CT6 SANYO 10TPE220ML

D2E
83 1 10M 1/10W 5% R10 VISHAY CRCW060310M0FNEA

0603
84 5 330 1/10W 5% R153,R157-160 VISHAY CRCW0603330RJNEA

0603
85 4 0 1/10W 5% 0603 R52-53,R195, PHYCOMP 232270296001L

R346
86 34 49.9 1/16W 1% R68,R71-77,R79- VISHAY CRCW060349R9FNEA

0603 84,R118-126,
R128-135,R137-
139
87 15 10 1/10W 5% R166,R169,R207- VISHAY CRCW060310R0JNEA
0603 208,R213,R216,
R219-220,R223,
R226,R229,R234,
R237,R240,R349
88 1 10.0K 1/10W 1% R183 DIGI-KEY 311-10.0KHRTR-ND

0603
89 8 100PF 50V 5% C67-70,C82-85 AVX 06035A101JAT2A

0603
90 1 1000PF 50V 5% C207 PANASONIC ECJ-1VC1H102J

0603

Designator
91 1 2200PF 50V 5% C130 PANASONIC ECJ-1VB1H222K
0603
92 2 75.0 1/10W 1% R127,R136 DALE CRCW060375R0FKEA

0603
93 3 100 1/16W 5% R49,R54,R70 DIGI-KEY 311-100JRTR-ND

0402
94 1 4.99K 1/16W 1% R347 VISHAY CRCW06034K99FKEA

0603
95 1 24.9K 1/10W 1% R192 DIGI-KEY 311-24.9KHTR-ND

0603
96 3 511.0 1/16W 1% R140-142 DIGI-KEY 311-511LCT-ND

0402
97 2 10UF 10V 10% C107,C111 PANASONIC ECJ-2FB1A106K

0805
98 1 2.0K 1/16W 1% R182 PANASONIC ERJ-3EKF2001V

0603
99 6 0.05 1/2W 1% R190-191,R194, SEI CSF 1/2 0.05 1%R

1206 R196,R198,R204
100 11 10UF 16V 10% C125-127,C135, AVX 1210YD106KAT2A

1210 C146,C149,C200
-203,C205
101 1 GREEN LED001 LED13 PANASONIC LN1361CTR
102 1 RED LED001 LED9 PANASONIC LN1261CTR
103 2 1000PF 50V 5% C147-148 AVX 12065A102JAT2A

1206
104 1 255.0K 1/10W R197 VISHAY CRCW06032553FK

1% 0603
105 1 80.6K 1/10W 1% R193 DIGI-KEY 311-80.6KHRCT-ND

0603
106 8 270 1/10W 5% R95-102 PANASONIC ERJ-3GEYJ271V

0603


Designator
107 2 22000PF 25V C131,C197 DIGIKEY 490-3252-1-ND
10% 0402
108 2 5A D7-8 ON SEMI MBRS540T3G

MBRS540T3G
SMC
109 1 20MA D1 PANASONIC MA3X717E

MA3X717E
DIO005
110 1 2.5UH 30% L3 COILCRAFT MSS1038-252NLB

IND013
111 1 33.0K 1/16W 1% R201 ROHM MCR01MZPF3302

0402
112 5 47.0K 1/16W 1% R46,R48,R50- ROHM MCR01MZPF4702

0402 51,R55
113 1 3.01K 1/16W 1% R63 ROHM MCR01MZPF3011

0402
114 1 5.6K 1/16W 5% R247 PANASONIC ERJ-2GEJ562X

0402
115 15 1.0K 1/16W 1% R61-62,R64-65, PANASONIC ERJ-2RKF1001X

0402 R88,R91,R93-94,
R103,R105,R109,
R116,R189,R271-
272
116 2 1000PF 2000V C112,C114 AVX 1206GC102KAT1A

10% 1206
117 3 220PF 50V 10% C153,C195-196 DIGI-KEY 311-1035-2-ND

0402
118 4 5.6K 1/16W 0.5% R40,R43-45 SUSUMU RR0510P-562-D

0402
119 1 680 1/16W 1% R42 BC COMPO- 2312 275 16801

0402 NENTS

Designator
120 1 90.9K 1/16W 5% R41 DIGI-KEY 541-90.9KLCT-ND
0402
121 1 40.2K 1/16W 5% R47 DIGI-KEY 541-40.2KLCT-ND

0402
122 2 100K 1/16W 5% R200,R350 DIGI-KEY 541-100KJTR-ND

0402
123 4 2.2UF 25V 10% C129,C132, DIGIKEY 490-3331-1-ND

0805 C204,C206
124 1 21.5K 1/10W 1% R179 DIGI-KEY 311-21.5KHRCT-ND

0603
125 6 1A D2-5,D9-10 ON SEMI MBR130LSFT1G

MBR130LSFT1G
SOD-123FL
126 1 22UH 20% L1 COILCRAFT MSS4020-223MLB

IND018
127 3 1UH 20% L2,L6-7 COILCRAFT ME3220-102MLB

IND019
128 13 33 1/32W 5% RN4-13,RN17-19 PANASONIC EXB-28V330JX

RNS005
129 3 1.2K 1/16W 1% R4-5,R186 PANASONIC ERJ-2RKF1201X
0402
130 2 4.3 1/4W 5% R185,R188 PANASONIC ERJ-8GEYJ4R3V

1206
131 1 2.67K 1/16W 1% R187 PANASONIC ERJ-2RKF2671X

0402
132 3 1.0M 1/16W 1% R248-250 VISHAY CRCW04021M00FKED

0402
133 2 22UH 20% L8-9 COILCRAFT MSD7342-223MLC

IND024
134 4 330 100MHZ FER1,FER19-21 MURATA BLM21PG331SN1D

1.5A 0805


Designator
135 8 22 1/32W 5% RN1-3,RN14-16, PANASONIC EXB-28V220JX
RNS005 RN20-21
136 1 3300PF 50V 5% C198 PANASONIC ECJ-1VB1H332K

0603

0603
138 1 140.0K 1/10W R181 PANASONIC ERJ-3EKF1403V

1% 0603

0603
140 1 1.91K 1/10W .1% R180 SUSUMU RG1608P-1911-B-T5

0603
141 1 3.01K 1/10W .1% R184 SUSUMU RG1608P-3011-B-T1

0603
142 1 20.0K 1/16W 1% R344 VISHAY CRCW040220K0FKED

0402

A B C D
1 1
2 2
ADSP-BF518F EZ-BOARD
SCHEMATIC
3 3
ANALOG 20 Cotton Road

Nashua, NH 03063
4 DEVICES PH: 1-800-ANALOGD 4
Title ADSP-BF518F EZ-BOARD

TITLE
Size Board No. Rev
C A0217-2008 0.2
Date 12-3-2008_14:30 Sheet 1 of 16
A B C D
A B C D
3.3V
A[1:19]_Z
U12 D[0:15]_Z
A1_Z 107 76 D0_Z
A1 D0
A2_Z 106 74 D1_Z
A2 D1
A3_Z 105 73 D2_Z
A3 D2
A4_Z 103 72 D3_Z
A4 D3
A5_Z 102 71 D4_Z R4 R5
A5 D4 U12 1.2K 1.2K
A6_Z 101 70 D5_Z 0402 0402
A6 D5
A7_Z 97 69 D6_Z
A7 D6
1 A8_Z 96 66 D7_Z 19
1
A8 D7 ETXD2 PF0/ETXD2/PPID0/SPI1_SSEL2/TACLK6
A9_Z 94 65 D8_Z 18 173 R314 33
A9 D8 ERXD2 PF1/ERXD2/PPID1/PWM_AH/TACLK7 PJ0/SCL 0402 SCL
A10_Z 93 64 D9_Z 13 172 R313 33
A10 D9 ETXD3 PF2/ETXD3/PPID2/PWM_AL PJ1/SDA 0402 SDA
A11_Z 92 62 D10_Z 12
A11 D10 ERXD3 PF3/ERXD3/PPID3/PWM_BH/TACLK0
A12_Z 91 61 D11_Z 11
A12 D11 ERXCLK PF4/ERXCLK/PPID4/PWM_BL/TACLK1
A13_Z 86 60 D12_Z 10
A13 D12 ERXDV PF5/ERXDV/PPID5/PWM_CH/TACI0 162
A14_Z 85 58 D13_Z 6 PH0/DR1PRI/SPI1_SS/RSI_DATA4 PB1/DR1PRI/MMC_D4_Z
A14 D13 COL PF6/COL/PPID6/PWM_CL/TACI1 161
A15_Z 84 57 D14_Z 5 PH1/RFS1/SPI1_MISO/RSI_DATA5 PB2/RFS1/MMC_D5_Z
A15 D14 SPI0_SSEL1 PF7/SPI0_SSEL1/PPID7/PWM_SYNC 160
A16_Z 81 56 D15_Z 4 PH2/RSCLK1/SPI1_SCK/RSI_DATA6 RSCLK1/MMC_D6_Z
A16 D15 MDC PF8/MDC/PPID8/SPI1_SSEL4 159
A17_Z 80 3 PH3/DT1PRI/SPI1_MOSI/RSI_DATA7 ADC_A0/LED1/MMC_D7/OTP_EN_Z
A17 MDIO PF9/RMIIMDIO/PPID9/TMR2 156
A18_Z 78 108 174 PH4/TFS1/AOE/SPI0_SSEL3/CUD SPI0_SSEL3/CUD_Z
A18 ABE1#/SDQM1 ABE1#/SDQM1_Z ETXD0 PF10/ETXD0/PPID10/TMR3 155
A19_Z 77 109 171 PH5/TSCLK1/ARDY/ECLK/CDG CDG/ADC_A1/LED2_Z
A19 ABE0#/SDQM0 ABE0#/SDQM0_Z ERXD0 PF11/ERXD0/PPID11/PWM_AH/TACI3 154
168 PH6/DT1SEC/UART1_TX/SPI1_SSEL1/CZM CZM/ADC_A2/LED3_Z
ETXD1 PF12/ETXD1/PPID12/PWM_AL 153
119 167 PH7/DR1SEC/UART1_RX/TMR7/TACI2 DR1SEC_Z
SCKE_Z SCKE ERXD1 PF13/ERXD1/PPID13/PWM_BH
113 166
SWE_Z SWE ETXEN PF14/ETXEN/PPID14/PWM_BL
110 120 165
SA10_Z SA10 AMS1 AMS1_Z RMII_PHYINT PF15/RMII_PHYINT/PPID15/PWM_SYNC
114 123
SCAS_Z SCAS AMS0 AMS0_Z
115 48
SRAS_Z SRAS MIICRS/HWAIT PG0/MIICRS/RMIICRS/HWAIT/SPI1_SSEL3
118 47
SMS_Z SMS 121 ERXER PG1/ERXER/DMAR1/PWM_CH
3.3V ARE ARE_Z 39
143 122 MIITXCLK PG2/MIITXCLK/RMIIREF_CLK/DMAR0/PWM_CL
DSP_CLKIN CLKIN AWE AWE_ZR3 38
2 144 33 DR0PRI/SD_D0_Z PG3/DR0PRI/RSI_DATA0/SPI0_SSEL5/TACLK3 2
XTAL 0402 37
125 RSCLK0/SD_D1_Z PG4/RSCLK0/RSI_DATA1/TMR5/TACI5
CLKOUT CLKOUT 36
RFS0/SD_D2_Z PG5/RFS0/RSI_DATA2/PPICLK/TMRCLK
141 34
DSP_RTXI RTXI TFS0/SD_D3_Z PG6/TFS0/RSI_DATA3/TMR0/PPIFS1
R1 140 117 33
10K DSP_RTXO RTXO GND TEST DT0PRI/SD_CMD_Z PG7/DT0PRI/RSI_CMD/TMR1/PPIFS2
0402 135 32
PG PG TSCLK0/SD_CLK_Z PG8/TSCLK0/RSI_CLK/TMR6/TACI6
31
TP10 UART0_TX_Z PG9/DT0SEC/UART0_TX/TMR4
147 130
NMI EXT_WAKE R199 WAKE 28
TP9 UART0_RX_Z PG10/DR0SEC/UART0_RX/TACI4
127 33
NMI NC 0402 27
146 150 AMS2_Z PG11/SPI0_SS/AMS[2]/SPI1_SSEL5/TACLK2
RESET RESET CLKBUF CLKBUF 26
SPI0_SCK_Z PG12/SPI0_SCK/PPICLK/TMRCLK
ADSP-BF518F 25
LQFP176_SOCKET SPI0_MISO_Z PG13/SPI0_MISO/TMR0/PPIFS1
21
SPI0_MOSI_Z PG14/SPI0_MOSI/TMR1/PPIFS2/PWM_TRIPB
R325 33 20
R202 AMS3/SPI0_SEL2 0402 PG15/SPI0_SSEL2/PPIFS3/AMS[3]
0
0402
3.3V "BOOT MODE" 3.3V
SW1
3.3V 42 1 C
BMODE0 2
3 1
41 2
54 BMODE1
TRST TRST 4 0
R11 40 4
10K 55 BMODE2 5 7
0402 TMS TMS 6
3 R12 51 3
C1 U19 4 33 R9 EMU EMU SWT027
0.01UF VDD 0402 0 53 ROTARY
0402 1 3 0402 TCK TCK
OE OUT DSP_CLKIN 50
GND TDO TDO R7 R8 R6
25MHZ 2 52 4.7K 4.7K 4.7K
OSC003 TDI TDI 0402 0402 0402
ADSP-BF518F
LQFP176_SOCKET
3.3V
DSP_RTXI DSP_RTXO SW1: Boot Mode Select Switch

R200 POSITION BOOT MODE
R10 100K
10M 0402
0 Idle-No Boot
0603
Default 1 Boot from 8 or 16-bit external flash memory
PG
2 Boot from internal SPI memory
U3
3 Boot from external SPI memory
R201 C153
4 1 33.0K 220PF
TERM2 TERM1 4 Boot from SPI0 host
0402 0402
3 2
NC2 NC1 5 Boot from OTP memory
6 Boot from SDRAM

C2 32.768KHZ C3
18PF OSC008 18PF
7 Boot from UART0 host
0805 0805
Nashua, NH 03063

DSP EBIU + CONTROL
RTC Size Board No. Rev
C A0217-2008 0.2
Date 12-17-2008_11:04 Sheet 2 of 16
A B C D
A B C D
VDDEXT
1 1
VDDEXT
C7 C37 C6 C5 C4 C39 C8 C22 C23 C21 C24 C38
U12 10UF 10UF 0.1UF 0.1UF 0.1UF 0.1UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF
0805 0805 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402
7 1
VDDEXT1 GND1
24 2
VDDEXT2 GND2
35 15
VDDEXT3 GND3
49 22
VDDEXT4 GND4
128 43
VDDEXT5 GND5
129 44
VDDEXT6 GND6
136 45
VDDEXT7 GND7
145 46
VDDEXT8 GND8 VDDMEM
148 67
VDDEXT9 GND9
158 83
VDDEXT10 GND10
VDDMEM 170 87
VDDEXT11 GND11
88
GND12
59 89 C10 C16 C9 C25 C19 C18 C20 C17 C27 C26
VDDMEM1 GND13 10UF 10UF 0.1UF 0.1UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF
68 90 0805 0805 0402 0402 0402 0402 0402 0402 0402 0402
VDDMEM2 GND14
75 99
VDDMEM3 GND15
82 111
VDDMEM4 GND16
95 131
VDDMEM5 GND17
2 104 132 2
VDDMEM6 GND18
112 133
VDDINT VDDMEM7 GND19
124 134
VDDMEM8 GND20
137
GND21
14 139
VDDINT1 GND22
23 149 VDDINT
VDDINT2 GND23
30 151
VDDINT3 GND24
63 157
VDDINT4 GND25
79 163
VDDINT5 GND26
98 169 C15 C14 C13 C12 C11 C31 C30 C32 C29 C33 C28 C36
VDDINT6 GND27 10UF 0.1UF 0.1UF 0.1UF 0.1UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF
100 175 0805 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402
VDDINT7 GND28
116 176
VDDINT8 GND29
138 177
VDDINT9 GND30
152
VDDFLASH VDDINT10
3.3V 164
VDDINT11
D1
MA3X717E 16
20MA VDDFLASH1
DIO005 17
VDDFLASH2
29 VDDFLASH
J12 VDDFLASH3
126
2 1 VDDFLASH4
3 C34 3
0.01UF 142
0402 VPPOTP VDDOTP VDDRTC
BATT_COIN16MM C41 C42 C43 C44 C45
BATTHOLDER 10UF 0.1UF 0.1UF 0.1UF 0.1UF
9 0805 0402 0402 0402 0402
VDDOTP
8
VPPOTP
"RTC BATTERY"
ADSP-BF518F
C40 C35 LQFP176_SOCKET
0.1UF 0.01UF
0603 0402

Nashua, NH 03063

DSP POWER, BYPASS CAPS
Size Board No. Rev
C A0217-2008 0.2
Date 12-17-2008_11:04 Sheet 3 of 16
A B C D
A B C D
4 MB FLASH 64MB SDRAM (32M x 16)
(2M x 16)
U14
3.3V A[1:19]
D[0:15]_ZZ
A1 23 2 D0_ZZ
A0 DQ0
1 A2 24 4 D1_ZZ 1
A1 DQ1
A3 25 5 D2_ZZ
SW3: FLASH ENABLE A2 DQ2
J5
U5 A4 26 7 D3_ZZ
A[1:19] D[0:15] A3 DQ3
VDD
A1 G2 G3 D0 A5 29 8 D4_ZZ
POS. FROM TO DEFAULT ALTERNATE FUNCTION / OFF MODE A0 D0 A4 DQ4
A2 F2 K3 D1 A6 30 10 D5_ZZ
A1 D1 A5 DQ5
1 DSP (U12) FLASH (U5) ON Expansion Interface A3 E2 G4 D2 A7 31 11 D6_ZZ
A2 D2 A6 DQ6
A4 C2 K4 D3 A8 32 13 D7_ZZ
2 DSP (U12) FLASH (U5) ON Expansion Interface A3 D3 A7 DQ7
A5 D2 K5 D4 A9 33 42 D8_ZZ
A4 D4 A8 DQ8
3 DSP (U12) FLASH (U5) ON Expansion Interface A6 F3 G5 D5 A10 34 44 D9_ZZ
A5 D5 A9 DQ9
A7 E3 K6 D6 22 45 D10_ZZ
4 DSP (U12) FLASH (U5) ON Expansion Interface, SPI FLASH CS A6 D6 SA10 A10 DQ10
A8 C3 G6 D7 3.3V A12 35 47 D11_ZZ
A7 D7 A11 DQ11
A9 D6 H3 D8 A13 36 48 D12_ZZ
A8 D8 A12_NC DQ12
A10 C6 J3 D9 50 D13_ZZ
A9 D9 DQ13
A11 E6 H4 D10 A18 20 51 D14_ZZ
3.3V A10 D10 BA0 DQ14
A12 F6 J4 D11 A19 21 53 D15_ZZ
A11 D11 BA1 DQ15
A13 D7 H5 D12
A12 D12 C54
A14 C7 J6 D13 0.01UF 16 19
A13 D13 0402 SWE WE CS SMS
A15 E7 H6 D14 17 37
A14 D14 SCAS CAS CKE SCKE
A16 F7 J7 D15 18 38
A15 D15/A-1 SRAS RAS CLK CLKOUT
A17 G7
R13 R14 R15 R16 R17 R269 A16
4.7K 4.7K 4.7K 4.7K 4.7K 4.7K A18 D3 15
0402 0402 0402 0402 0402 0402 A17 ABE0#/SDQM0 DQML
2 A19 E4 39 2
A18 ABE1#/SDQM1 DQMH
F5
A19
F4 MT48LC32M16A2TG-75
A20 TSOP54
"FLASH ENBL" U23
3.3V
1
4 D5
2 RESET
SW3 H7
SN74LVC1G08 BYTE
1 8
ON
AMS0 SOT23-5
1
C4
U25 RY/BY~
2 7 1
AMS1
2
4 H2
U13 CE
3 6 1 2
AMS2
3
4 J2
SN74LVC1G08 OE
4 5 2 C47 C48 C49 C50 C51 C52 C53
AMS3/SPI0_SEL2 SOT23-5
4
C5 0.1UF 0.1UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF

SN74AUC1G00 WE
DIP4 0402 0402 0402 0402 0402 0402 0402
SOT23-5
SWT018 D4
K7GND1
GND2
VPP/WP~
U24
K2
1 M29W320EB
4 TFBGA63_80
2
SN74LVC1G08
SOT23-5
RESET
ARE
AWE
JP3
3 1 SJ1 3.3V 3
SHORTING
"FLASH WP" 2 JUMPER
DEFAULT=NOT INSTALLED 16 Mb SPI FLASH
IDC2X1
MEMORY MAP R18

10K
R20
10K R21
ADDRESS RANGE SELECT LINE TYPE 0402 0402 10K
0402
0x2030 0000 - 0x203F FFFF ASYNC BANK 3 FLASH U9 8

0x2020 0000 - 0x202F FFFF ASYNC BANK 2 FLASH VCC
5 2
SPI0_MOSI SI SO SPI0_MISO
0x2010 0000 - 0x201F FFFF ASYNC BANK 1 FLASH 6
SPI0_SCK SCK
0x2000 0000 - 0x200F FFFF ASYNC BANK 0 FLASH 1
CS
0x0000 0000 - 0x03FF FFFF NONE SDRAM JP16 3
1 2 WP
3.3V AMS3/SPI0_SEL2 7
IDC2X1_SMT HOLD
GND
M25P16 4
"SPI FLASH CS ENBL" SO8W 3.3V
SJ9
SHORTING
JUMPER
DEFAULT=NOT INSTALLED
C58
0.01UF
C57
0.01UF
C56
0.01UF
C55
0.01UF
R19
10K
Nashua, NH 03063
0402 0402 0402 0402 0402 C46
4 0.01UF

EXTERNAL MEMORY
Size Board No. Rev
C A0217-2008 0.2
Date 1-16-2009_12:36 Sheet 4 of 16
A B C D
A B C D
PS_5V 3.3V
DIFFERENTIAL INPUTS SJ10

SHORTING
JUMPER
J18 J20
DEFAULT=2&3
SMA SMA
R214 R222
SJ11
0 0 FER1
SHORTING
0402 R216 0402 R220 330
U29 U31 JUMPER
1 3 +12V;8 10 1 3 10 0805
DEFAULT=2&3
0603 JP17 0603 JP24
1 1 1 1
SJ12
SHORTING
2 2 -12V;4 2 2 2 2
V1+ V2+ JUMPER
AD8022 AD8022 DEFAULT=2&3
AVDD32
VDD31
3 3 U2
3
MSOP8 MSOP8
VDRIVE
C160 C165
SJ13
1 10PF IDC3X1 10PF IDC3X1 3.3V 1
SHORTING
R215 0805 R221 0805
JUMPER
0 0
DEFAULT=2&3
0402 0402 30
7 DOUTA DOUTA
AGND AGND
SJ17
SHORTING
V1+ VA1
DOUTB
28
DOUTB
"ADC RANGE"
8
JUMPER V1- VA2
C161 C164 27 JP4
DEFAULT=2&3 SCLK ADC_SCLK
10PF 10PF 9 1
0805 AGND 0805 AGND V2+ VA3 26
SJ16 CS ADC_CS
10 2
SHORTING V2- VA4
J19 J21
JUMPER
SMA SMA 11 IDC2X1_SMT
DEFAULT=2&3 VSE1 VA5
R217 R225
0 0 12 21
SJ14 VSE2 VA6 RANGE RANGE
0402 R219 0402 R223
U29 U31 SHORTING
1 5 10 1 5 10 22
JUMPER SGL/DIFF~
0603 JP18 0603 JP23
DEFAULT=2&3
7 1 7 1 18 25
V3+ VB1 A0 ADC_A0/LED1/MMC_D7/OTP_EN
SJ15
2 6 2 2 6 2 17 24 SJ2
V1- V2- SHORTING V3- VB2 A1 CDG/ADC_A1/LED2 SHORTING
AD8022 AD8022 JUMPER
3 3 16 23 JUMPER
MSOP8 MSOP8 DEFAULT=2&3 V4+ VB3 A2 CZM/ADC_A2/LED3
C162 C167 DEFAULT=INSTALLLED
10PF IDC3X1 10PF IDC3X1 15
R218 0805 R224 0805 V4- VB4 2
0 0 14 REF_SELECT Install for a range of 2 X Vref (0-5V)
0402 0402 VSE3 VB5 4 DCAPA
13 DCAPA Remove for a range of Vref (0-2.5V)
AGND AGND VSE4 VB6 20 DCAPB
DCAPB
C163 C166
10PF 10PF
0805 AGND 0805 AGND
29DGND1
DGND2
6AGND1
19AGND2
1AGND3
C59 C60 R26
J22 J25 +12V 0.47UF 0.47UF 10K
SMA SMA 0805 0805 0402
5
R228 R235
0 0
0402 R226 0402 R237
U30 U32
1 3 10 1 3 10
0603 JP19 0603 JP22
2 1 1 1 1 2
2 2 2 2 2 2 C189 C190 C191 C192 C193 C194
V3+ V4+ 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
AD8022 AD8022
3 3 0402 0402 0402 0402 0402 0402
MSOP8 MSOP8
C169 C174
10PF IDC3X1 10PF IDC3X1
R227 0805 R236 0805 AGND AGND
0 0
0402 0402
AGND AGND
3.3V PS_5V AVDD_ADC
C168 C175 -12V
10PF 10PF
0805 AGND 0805 AGND AGND
J23 J24
SMA SMA
R231 R232
0 0
0402 R229 0402 R234
U30 U32
1 5 10 1 5 10 C211 C212 C213 C216 C215 C214 C61 C62 C64 C63 C66 C65
0603 JP20 0603 JP21 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 10UF 0.1UF 10UF 0.1UF 10UF 0.1UF
7 1 7 1 0402 0402 0402 0402 0402 0402 0805 0402 0805 0402 0805 0402
2 6 2 2 6 2
V3- V4-
AD8022 AD8022
3 3
MSOP8 MSOP8
C171 C172
10PF IDC3X1 10PF IDC3X1
R230 0805 R233 0805
0 0
0402 0402
AGND
AGND AGND
J17
C170 C173 SMA AGND
10PF 10PF R210
0805 AGND 0805 AGND 0
0402 R208
3 U33 3
1 3 10
0603 JP28
1 1
SW22 SW23
SJ21
1 12 1 12 2 2 2
ON
ON
SMA_V1+ RHPOUT_RDIV SMA_V1- LHPOUT_RDIV SHORTING VSE1

1
JUMPER AD8022
2 11 2 11 3
SMA_V2+ SMA_V2- DEFAULT=2&3 MSOP8
2
C157 SW4
3 10 3 10 10PF IDC3X1 1 8
ON
SMA_V3+ SMA_V3- SJ20 PB1/DR1PRI/MMC_D4 DOUTA
3
1
R209 0805
SHORTING
4 9 4 9 0 2 7
SMA_V4+ SMA_V4- JUMPER DR1SEC DOUTB
4
2
0402
DEFAULT=2&3
5 8 5 8 3 6
SMA_VSE1 SMA_VSE3 RSCLK1/MMC_D6 ADC_SCLK
5
3
AGND
SJ18
6 7 6 7 4 5
SMA_VSE2 SMA_VSE4 SHORTING PB2/RFS1/MMC_D5 ADC_CS
6
4
C156
JUMPER
SWT017 SWT017 10PF DIP4
DEFAULT=2&3
DIP6 DIP6 0805 AGND SWT018
SJ19
J16
SINGLE ENDED INPUTS SHORTING
JUMPER
DEFAULT=2&3
SMA
R205
SW4 disconnects DSP from ADC
0
0402 R207
J7 J26 1 5
U34
10 "SPORT1 ENBL"
SMA SMA 0603 JP27
R212 R238 7 1
0 0
0402 R213 0402 R240 2 6 2
U33 U34 VSE4
1 5 10 1 3 10
AD8022
0603 JP25 0603 JP26 3
MSOP8
7 1 1 1 C178
10PF IDC3X1
2 6 2 2 2 2 R206 0805
VSE2 VSE3 0
AD8022 AD8022
3 3 0402
MSOP8 MSOP8
C159 C176
R211
0
10PF
0805
IDC3X1
R239
0
10PF
0805
IDC3X1 AGND
C155
Nashua, NH 03063
0402 0402 10PF
4
AGND AGND
0805 AGND
DEVICES PH: 1-800-ANALOGD 4
C158 C177
10PF
0805 AGND
10PF
0805 AGND
ADC
Size Board No. Rev
C A0217-2008 0.2
Date 12-10-2008_14:21 Sheet 5 of 16
A B C D
A B C D
J4 J5 "MIC GAIN"
SW4: MIC GAIN
3.3V
HP OUT MIC IN POS. GAIN
R47 SW5
40.2K 1 8
ON
1
0402 1 5 (14dB)
2 7 "MIC/HP LPBK"
2
R41
90.9K 3 6 2 1 (0dB) "AUDIO MODE"
3
0402
4 5 R57
4
3.3V DEFAULT 3 0.5 (-6dB) 3.3V 10K SW6
DIP4 0402 1 8
ON
MICIN LHPOUT_RDIV
1
SWT018
4 NC 2 7
RHPOUT_RDIV
2
1 FER19 1
C79 330 3 6
3
1UF 0805
0603 AVDD 4 5
AUDIO_MODE
4
LINE OUT LINE IN DIP4
SWT018
C88 C87 C86 C71 C72
10UF 0.1UF 0.1UF U1 10UF 0.1UF R56
R46 C74 0805 0402 0402 0805 0402 10K
47.0K 220PF 5 18 0402
0402 0402 DBVDD AVDD
DNP 4 19
DGND AGND
3
DCVDD SW6 allows the MICIN signal to be looped back,
FER4 R247 for test purposes, to the Left and Right headphone.
600 5.6K FER20
0603 0402 MICIN_RDIV 22 AGND 330 DO NOT switch positions 1 & 2 ON at the same time.
MICIN 0805
AGND MICBIAS_Z 21 12 HPVDD Ensure that JP15 is on 2&3 or OFF when using SW6.
MICBIAS HPVDD
JP15 R42 15
1 680 HPGND C75 C76
FER3 0402 10UF 0.1UF AUDIO CODEC INTERFACE MODE:
600 2 0805 0402
"MIC" 0603 SW6.3 ON and SW6.4 OFF = SPI MODE
3
LLINEIN_RDIV 24 SW6.3 OFF and SW6.4 ON = TWI MODE
"LINE IN" IDC3X1 C91 LLINEIN
220PF RLINEIN_RDIV 23
0402 RLINEIN
J5 "MIC SELECT" DNP
2 MICIN
SJ3 AGND
CT4
220UF
R53 FER8 "HEAD PHONE"
SHORTING 0 600
D2E
JUMPER 0603 0603
DEFAULT=2&3
LHPOUT
13 LHPOUT LHPOUT_RDIV "LINE OUT"
3 MICBIAS AGND 14 RHPOUT
RHPOUT CT3
FER5 R45 C80
2 1 600 5.6K 1UF
220UF
J4 2
D2E
0603 0402 0603 9 2
4 LLINEIN CODEC_DACLRC DACLRC
CT1
8
CODEC_DACDAT DACDAT 10UF
7 R52 FER7
LEFT_LPBK CAP002
FER2 R40 C81 10 0 600
8 600 5.6K 1UF CODEC_ADCDAT ADCDAT 16 LOUT 0603 0603
RIGHT_LPBK 0603 0402 0603 11 LOUT RHPOUT_RDIV 3
5 RLINEIN CODEC_ADCLRC ADCLRC 17 ROUT
ROUT CT2
7 1
BCLK BCLK 10UF
6
CAP002
LOUT_RDIV 4
CON050 R50 R51
25 47.0K 47.0K 7
C67 C68 C69 C70 C195 R43 R44 C196 AUDIO_MODE MODE 0402 0402 LEFT_LPBK
100PF 100PF 100PF 100PF 220PF 5.6K 5.6K 220PF 26 6 8
XTI/MCLK
0603 0603 0603 0603 0402 0402 0402 0402 CSB CSB CLKOUT RIGHT_LPBK
27 ROUT_RDIV 5
AGND SDIN SDIN
XTO
28 20 6
3.3V SCLK SCLK VMID VMID
2
SSM2602 CON050
ICS009
AGND
AGND AGND
R49 FER6 AGND
100 600
AGND 0402 0603
"AUDIO CLK"
3.3V R59
10K
MICIN_RDIV 0402 R54 FER9
R60 100 600
LLINEIN_RDIV U20 4 33 0402 0603
VDD 0402
RLINEIN_RDIV 1 3 AUDIO_CLK
OE OUT
GND
C73 12MHZ 2
R248 R249 R250 0.01UF OSC003
3 1.0M 1.0M 1.0M 0402 3
0402 0402 0402 R55 R48
47.0K 47.0K C82 C83 C84 C85
0402 0402 100PF 100PF 100PF 100PF
0603 0603 0603 0603
AGND
AGND
3.3V VMID AGND
FER21
330
0805 C90 C89
10UF 0.1UF
0805 0402
"SPORT0 ENBL" C77

R58 1000PF
1
SW15
12
"SPI/TWI" 10K
0402
0805
DNP
ON
TFS0/SD_D3 CODEC_DACLRC
1
2 11 AGND
DT0PRI/SD_CMD CODEC_DACDAT
2
SW16
3 10 1 12 C78
ON
DR0PRI/SD_D0 CODEC_ADCDAT SPI0_SSEL3/CUD CSB

3
1000PF
4 9 2 11 0805
RFS0/SD_D2 CODEC_ADCLRC
4
DNP
5 8 3 10
TSCLK0/SD_CLK BCLK SPI0_MOSI
5
6 7 4 9
RSCLK0/SD_D1 SDA SDIN
6
DIP6 5 8
SPI0_SCK
5
SWT017 Nashua, NH 03063

6 7
SCL SCLK
DEVICES
6
4 PH: 1-800-ANALOGD 4
DIP6 AGND
SWT017
SW15 disconnects DSP from AUDIO CODEC Title ADSP-BF518F EZ-BOARD

AUDIO CODEC MODE INTERFACE:
AUDIO CODEC
SPI MODE: ON, OFF, ON, OFF
TWI MODE: OFF, ON, OFF, ON Size Board No. Rev
C A0217-2008 0.2
Date 12-10-2008_14:21 Sheet 6 of 16
A B C D
A B C D
R68
49.9
0603
VCCO_SW VCCPLL_SW
MDIO SMDIO
R71
49.9
0603 3.3V VCCA_SW
VCC3A_SW
MDC SMDC
R72
49.9
0603
MIICRS/HWAIT SCRS
R73
49.9
0603
1 COL SCOL 1
VDDIO1107
VDDC1123
VDDIO079
22
VDDC091
38
VDDA043
VDDA157
63
51
VDDARX50
R75 U4
VDDIO2
VDDC2
VDDA2
VDDAP
VDDATX
49.9
0603 48
TXP1 TXP1
ERXD0 SMRXD0 3.3V 49
R76 TXM1 TXM1
49.9 45
0603 RXP1 RXP1
46
ERXD1 SMRXD1 95 RXM1 RXM1
R77 SMDIO MDIO
49.9 94
0603 SMDC MDC 56
87 TXP2 TXP2
ERXD2 SMRXD2 R355 SCRS SCRS 55
R74 10K 86 TXM2 TXM2
49.9 0402 SCOL SCOL 53
0603 85 RXP2 RXP2
SMRXD0 SMRXD0 52
ERXD3 SMRXD3 84 RXM2 RXM2
R79 SMRXD1 SMRXD1
49.9 SMDIO 83
0603 SMRXD2 SMRXD2 3
82 P1LED0 P1LED0
ERXDV SMRXDV SMRXD3 SMRXD3 2
R67 81 P1LED1 P1LED1
33 SMRXDV SMRXDV 1
0402 80 P1LED2 P1LED2
SMRXC SMRXC 25
ERXCLK SMRXC 77 P1LED3 P1LED3
R66 SMTXC/REFCLK SMTXC/REFCLK
33 ERXER 76
0402 SMTXER SMTXER 6
75 P2LED0 P2LED0
MIITXCLK SMTXC/REFCLK SMTXD0 SMTXD0 5
R78 R353 74 P2LED1 P2LED1
33 10K SMTXD1 SMTXD1 4
0402 0402 73 P2LED2 P2LED2
SMTXD2 SMTXD2 20 3.3V VCC3A_SW
RMII_PHYINT SMTXER 72 P2LED3 P2LED3
2 R82 SMTXD3 SMTXD3 2
49.9 71 70
0603 SMTXEN SMTXEN LEDSEL0 LEDSEL0 FER13
23 600
ETXD0 SMTXD0 LEDSEL1 LEDSEL1 0603
R81 99
49.9 SPIS SPIS
0603 98 68
SSDA SDA UNUSED1 3.3V
ETXD1 SMTXD1 97 69 C94 C93 C92 C101 C102 C103
R80 SSCL SCL UNUSED2 10UF 0.01UF 0.01UF 10UF 0.01UF 0.01UF
49.9 96 92 0805 0402 0402 0805 0402 0402
0603 SMTXER SPIQ SPIQ UNUSED3 R62
93 1.0K
ETXD2 SMTXD2 UNUSED4 0402
R83 30 102
49.9 R354 P1ANEN P1ANEN UNUSED5
0603 10K 31 103
0402 P1SPD P1SPD UNUSED6 R70
ETXD3 SMTXD3 32 104 100
R84 P1DPX P1DPX UNUSED7 0402
49.9 33 105 AGND
0603 P1FFC P1FFC UNUSED8
13 108
ETXEN SMTXEN P2ANEN P2ANEN UNUSED9
14 109
P2SPD P2SPD UNUSED10 VCCO_SW VCCA_SW VCCPLL_SW
15 110
P2DPX P2DPX UNUSED11 FER12 FER14
16 111 600 600
P2FFC P2FFC UNUSED12 0603 0603
29 112
P2MDIX P2MDIX UNUSED13
28 113
P2MDIXDIS P2MDIXDIS UNUSED14
12 114 C95 C96 C97 C98 C99 C100 C106 C105 C104
ADVFC ADVFC UNUSED15 10UF 0.01UF 0.01UF 10UF 0.01UF 0.01UF 10UF 0.01UF 0.01UF
26 115 0805 0402 0402 0805 0402 0402 0805 0402 0402
RMIIEN UNUSED16
27 116
HWPOVR HWPOVR UNUSED17
3 89 117 3
SCONFIG0 SCONFIG0 UNUSED18
88 118
3.3V SCONFIG1 SCONFIG1 UNUSED19
101 119
PS0 PS0 UNUSED20
100 120 AGND
PS1 PS1 UNUSED21
121
UNUSED22
36 124
PWRDN PWRDN UNUSED23 R61
125 1.0K
R86 R85 UNUSED24 0402
10K 10K 67 126
0402 0402 RESET RESET UNUSED25
65 40 R69
CLKBUF X1 MUX1 0
66 41 0805
"ETHERNET MODE" X2 MUX2
44
FXSD1
59
TEST1 R63
60 3.01K
SW17 TEST2 0402
1 12 61
ON
SPI0_SSEL1 SPIS ISET

1
2 11 127 R64 SHGND

SPI0_MISO SPIQ TESTEN
2
39ADGND1
42ADGND2
47ADGND3
54ADGND4
58ADGND5
62ADGND6
64ADGND7
ADGND8
1.0K
21DGND1
78DGND2
90DGND3
106DGND4
122DGND5
DGND6
3 10 128 0402
SPI0_MOSI SCANEN
3
4 9
SDA SSDA
4
37
KS8893M R65
5 8 PQFP128 1.0K
SPI0_SCK
5
0402
6 7
SCL SSCL
6
DIP6
Nashua, NH 03063
4 SWT017
SPI MODE: ON,ON,ON, OFF, ON, OFF

AGND Title ADSP-BF518F EZ-BOARD
TWI MODE: OFF,OFF,OFF, ON, OFF, ON
ETHERNET SWITCH
Size Board No. Rev
C A0217-2008 0.2
Date 12-3-2008_14:30 Sheet 7 of 16
A B C D
A B C D
3.3V
3.3V
PORT 1 CONFIG SJ24

SJ23 SHORTING
"PORT 1 CFG" SHORTING JUMPER
"ETHERNET CFG" JUMPER DEFAULT=INSTALLLED
DEFAULT=NOT INSTALLLED
R108 R106 R107

10K 10K 10K R117 R115 R87
0402 0402 0402 10K 10K 10K
0402 0402 0402
1 3.3V 3.3V 1
SW7
1 8 SW8 "LED SEL0" "LED SEL1"
ON
P1FFC
1
1 8
ON
ADVFC
1
2 7
P1DPX
2
2 7
HWPOVR
2
3 6
P1SPD
3
3 6 JP11 JP12
PS1
3
4 5 1 2 1 2
P1ANEN LEDSEL0 LEDSEL1
4
4 5
PS0
4
DIP4
SWT018 DIP4
SWT018 R91 R93
R103 1.0K 1.0K
1.0K R116 0402 0402
SW7: Port 1 Configuration Switch 0402 1.0K
0402
Switch Description Position Function
SW8: Ethernet Configuration Switch
1 Force Flow Control OFF Disable Switch Description Position Function
ON Enable
1 Advertise Flow Control OFF Disable
2 Force Full/Half OFF Half Duplex ON Enable
JPx: LED Configuration Switch
ON Full Duplex
2 Hardware Pin Overwrite OFF Enable
OFF OFF OFF ON ON OFF ON ON
3 Force Speed OFF 10BaseT ON Disable
ON 100BaseTX PxLED3 tri-state,PD tri-state,PD ACT NU
3,4 Serial Bus Mode OFF OFF Not Used
4 Auto-Negotiation OFF Enable OFF ON TWI Slave PxLED2 LINK/ACT 100LINK/ACT LINK NU
ON Disable ON OFF SPI Slave
PxLED1 FULL DPX/COL 10LINK/ACT FULL DPX/COL NU
ON ON Not Used
PxLED0 SPEED FULL DPX SPEED NU
2 2
PS1
R94
1.0K
PS0 0402
3.3V P1LED3
R271 R272
1.0K 1.0K
0402 0402
PORT 2 3.3V
"PORT 2 CFG" LED10 R95

R110 R111 R112 R113 R114 YELLOW 270
10K 10K 10K 10K 10K LED009 0603
0402 0402 0402 0402 0402
P1LED0
SW18 3.3V LED11 R96

1 12 YELLOW 270
ON
P2FFC
1
LED009 0603
2 11
P2DPX P1LED1
2
3 10
P2SPD
3
LED12 R97
P2ANEN
4 9 PORT 1 YELLOW 270
4
LED009 0603
5 8 R89
P2MDIXDIS P1LED2
5
10K
6 7 0402
P2MDIX "ETHERNET PD"
6
LED4 R98
DIP6 YELLOW 270
SWT017 JP13 LED009 0603
SCONFIG0 1 2
R109 PWRDN P1LED3
3 1.0K SCONFIG1 3
SW18: Port 2 Configuration Switch 0402
Switch Description Position Function R88 R105

1.0K 1.0K
0402 0402
1 Force Flow Control OFF Disable SJ22
SHORTING LED5 R99
ON Enable JUMPER YELLOW 270
DEFAULT=NOT INSTALLLED LED009 0603
2 Force Full/Half OFF Half Duplex P2LED0
ON Full Duplex LED6 R100

YELLOW 270
LED009 0603
3 Force Speed OFF 10BaseT
P2LED1
ON 100BaseTX
PHY mode MII Power Down PORT 2 LED7
YELLOW
R101
270
4 Auto-Negotiation OFF Enable LED009 0603
ON Disable P2LED2
LED8 R102
5 Auto MDI/MDI-X OFF Enable YELLOW 270
LED009 0603
ON Disable
P2LED3
6 MDI/MDI-X Setting OFF MDI-X

ON MDI

Nashua, NH 03063

ETHERNET CONFIG/LEDS
Size Board No. Rev
C A0217-2008 0.2
Date 12-10-2008_14:21 Sheet 8 of 16
A B C D
A B C D
VCC3A_SW
PORT 1
U28 J15
1 16 1
TXP1 TD+ TX+
1 2 2
1
TCT
3 14 3
TXM1 TD- TX-
1CT:1CT 15 4
TCM
5
6 11 6
RXP1 RD+ RX+
7 7
RCT
8 9 8
RXM1 RD- RX-
10
TCM_
NC1
NC2
NC3
NC4
R118 R119 R120 R121
49.9 49.9 49.9 49.9
0603 0603 0603 0603
12
13
HX1188 R136 R138 R139 R137 R135
ICS007 75.0 49.9 49.9 49.9 49.9
0603 0603 0603 0603 0603
C108 C109 C107

0.1UF 0.1UF 10UF
0402 0402 0805
R134 R133
49.9 49.9
0603 0603
C114
1000PF
1206
2 2
SHGND
VCC3A_SW
PORT 2
U27 J14
1 16 1
TXP2 TD+ TX+
2 2
TCT
3 14 3
TXM2 TD- TX-
1CT:1CT 15 4
TCM
5
6 11 6
RXP2 RD+ RX+
7 7
RCT
8 9 8
RXM2 RD- RX-
10
TCM_
NC1
NC2
NC3
NC4
3 R123 R131 R132 R122 3

49.9 49.9 49.9 49.9
0603 0603 0603 0603
4
12
13
HX1188 R127 R125 R124 R126 R128

ICS007 75.0 49.9 49.9 49.9 49.9
0603 0603 0603 0603 0603
C110 C113 C111

0.1UF 0.1UF 10UF
0402 0402 0805
R129 R130
49.9 49.9
0603 0603
C112
1000PF
1206
SHGND

Nashua, NH 03063

ETHERNET JACKS
Size Board No. Rev
C A0217-2008 0.2
Date 12-3-2008_14:30 Sheet 9 of 16
A B C D
A B C D
3.3V
All USB interface circuitry is considered proprietary and has
been omitted from this schematic.
When designing your JTAG interface please refer to the

Engineer to Engineer Note EE-68 which can be found at
"ENCODER ENABL"
http://www.analog.com
R140 R141 R142
511.0 511.0 511.0
0402 0402 0402
1 "ENCODER" 1
3.3V
SW14 SW19
1 1 6
ON
A SPI0_SSEL3/CUD
1
6 2 5
B CDG/ADC_A1/LED2 "JTAG"
2
5 3 4
SW1 CZM/ADC_A2/LED3
3
4 DIP3 R144 R145 PS_5V 3.3V
SW2 SWT015 10K 10K
0402 0402
2
COMMON
P1
ROTARY_ENC_EDGE 1 2 EMU
SWT025
TP1 3 4
3.3V 3.3V 5 6 TMS DA_PWR VDD_EXT_DSP
7 8 TCK
9 10 TRST RESET RESET
"UART 0" DA_SOFT_RESET DA_SOFT_RESET
GND
11 12 TDI
C116
0.1UF U21 13 14 TDO DA_STANDALONE
0402 C117
R270 1 0.1UF J2 IDC7X2_SMTA
10K C1+ 0402
0402 3
C1- 2 R143
1
V+ 10K
C115 4 6 6 0402
0.1UF C2+ V-
0402 5 2
C2-
7
2 SW10 2
1 8 11 14 3
ON
UART0_TX T1IN T1OUT

1
2 7 10 7 8
MIICRS/HWAIT T2IN T2OUT
2
3 6 12 13 4
UART0_RX R1OUT R1IN
3
TP12
4 5 9 8 9
R2OUT R2IN
4
DIP4 ADM3202ARNZ 5 3.3V

SWT018 SOIC16
CON038
C118
"UART0 SETUP" 0.1UF
0402 R203
10K
(UART 0) R149
22
0402 3.3V
0402
MMC_D0
DR0PRI/SD_D0
R146
22
0402
MMC_D1
RSCLK0/SD_D1
4
J13
R147 7
VDD
3.3V 22 DAT0
0402 8
MMC_D2 DAT1
RFS0/SD_D2 9
R148 DAT2 C154
22 1 0.01UF
0402 CD/DAT3 0402
"eMMC ENABL" TFS0/SD_D3
MMC_D3 5
CLK
GND1
GND2
3 R150 2 3
22 CMD
VCCQ3AA3
VCCQ4AA5
VCC2T10
VCCQ1W4
M6
VCC1N5
VCC3U9
VCC4K6
VCCQ2Y4
SW21 U16 0402 CON051
3
6
VCCQ5
1 4 MMC_CLK
ON
MMC_CLK TSCLK0/SD_CLK
1
2 3 R151
MMC_CMD
2
W6 22
DIP2 CLK 0402
SWT020 W5 MMC_CMD
1
SW20
16 H3
CMD
2GB eMMC DT0PRI/SD_CMD
ON
MMC_D0 D0
1
2 15 H4
MMC_D1 D1
2
3 14 H5
MMC_D2 D2
3
4 13 J2
MMC_D3 D3 "SD CARD"
4
R241 5 12 J3
D4
5
22
0402 6 11 J4
D5
6
PB1/DR1PRI/MMC_D4 7 10 J5
D6
7
8 9 J6
D7
8
R242
Y2VSSQ1
Y5VSSQ2
AA4VSSQ3
AA6VSSQ4
K2VSSQ5
22 DIP8
P5VSS1
R10VSS2
U8VSS3
K4VSS4
VDDI
0402 SWT016 3.3V

PB2/RFS1/MMC_D5
M7
MTFC2GDKDM
FBGA169
R243
22
0402
C188
RSCLK1/MMC_D6 0.1UF
0402
R244
22
0402
C179
0.01UF
C180
0.01UF
C181
0.01UF
C182
0.01UF
C183
0.01UF
C184
0.01UF
C186
0.01UF
C185
0.01UF
C187
0.01UF
Nashua, NH 03063
0402 0402 0402 0402 0402 0402 0402 0402 0402
4 ADC_A0/LED1/MMC_D7/OTP_EN

ROTARY ENCODER, JTAG, RS232, RSI
Size Board No. Rev
C A0217-2008 0.2
Date 1-15-2009_11:11 Sheet 10 of 16
A B C D
A B C D
LOGIC ANALYZER COMPRESSION LAND GRID ARRAY
A[1:19]
1 1
P5 P6 P7
A1 A1 B1 D0 A1 B1 A1 B1
D0 GND9 D[0:15] D0 GND9 MDC D0 GND9
A2 A2 B2 D1 A2 B2 A2 B2
D1 D2 AMS0 D1 D2 ETXD0 MDIO D1 D2 DR0PRI/SD_D0
A3 B3 A3 B3 A3 B3
GND0 D3 AMS1 GND0 D3 ETXD1 GND0 D3 RSCLK0/SD_D1
A3 A4 B4 D2 A4 B4 A4 B4
D4 GND10 D4 GND10 SPI0_SSEL1 D4 GND10
A4 A5 B5 D3 A5 B5 A5 B5
D5 D6 AMS3/SPI0_SEL2 D5 D6 ETXD2 SPI0_SSEL3/CUD D5 D6 RFS0/SD_D2
A6 B6 A6 B6 A6 B6
GND1 D7 ARE GND1 D7 ETXD3 GND1 D7 TFS0/SD_D3
A7 B7 A7 B7 A7 B7
CLKOUT CLK1+ GND11 CLKBUF CLK1+ GND11 SPI0_SCK CLK1+ GND11
A8 B8 A8 B8 A8 B8
CLK1- D8 AMS2 CLK1- D8 ERXD0 CLK1- D8 DT0PRI/SD_CMD
A9 B9 A9 B9 A9 B9
GND2 D9 ABE1#/SDQM1 GND2 D9 ERXD1 GND2 D9 TSCLK0/SD_CLK
A5 A10 B10 D4 A10 B10 A10 B10
D10 GND12 D10 GND12 SPI0_MISO D10 GND12
A6 A11 B11 D5 A11 B11 A11 B11
D11 D12 SCAS D11 D12 ERXD2 SPI0_MOSI D11 D12 UART0_TX
A12 B12 A12 B12 A12 B12
GND3 D13 SCKE GND3 D13 ERXD3 GND3 D13 UART0_RX
A7 A13 B13 D6 A13 B13 A13 B13
D14 GND13 D14 GND13 CDG/ADC_A1/LED2 D14 GND13
A8 A14 B14 D7 A14 B14 A14 B14
D15 D16 ABE0#/SDQM0 D15 D16 ETXEN CZM/ADC_A2/LED3 D15 D16
A15 B15 A15 B15 A15 B15
GND4 D17 SMS GND4 D17 ERXDV GND4 D17
A9 A16 B16 D8 A16 B16 A16 B16
D18 GND14 D18 GND14 SCL D18 GND14
A10 A17 B17 D9 A17 B17 A17 B17
D19 D20 SWE D19 D20 ERXER SDA D19 D20
A18 B18 A18 B18 A18 B18
GND5 D21 SRAS GND5 D21 GND5 D21
A11 A19 B19 D10 A19 B19 A19 B19
2 D22 GND15 D22 GND15 PB1/DR1PRI/MMC_D4 D22 GND15 2
A12 A20 B20 D11 A20 B20 A20 B20
D23 CLK2- D23 CLK2- PB2/RFS1/MMC_D5 D23 CLK2-
A21 B21 A21 B21 A21 B21
GND6 CLK2+ AWE GND6 CLK2+ ERXCLK GND6 CLK2+
A13 A22 B22 D12 A22 B22 A22 B22
D24 GND16 D24 GND16 RSCLK1/MMC_D6 D24 GND16
A14 A23 B23 D13 A23 B23 A23 B23
D25 D26 SA10 D25 D26 MIITXCLK ADC_A0/LED1/MMC_D7/OTP_EN D25 D26
A24 B24 A17 A24 B24 A24 B24
GND7 D27 GND7 D27 MIICRS/HWAIT GND7 D27
A15 A25 B25 D14 A25 B25 A25 B25
D28 GND17 D28 GND17 DR1SEC D28 GND17
A16 A26 B26 A19 D15 A26 B26 A26 B26
D29 D30 D29 D30 RMII_PHYINT RESET D29 D30
A27 B27 A18 A27 B27 A27 B27
GND8 D31 GND8 D31 COL GND8 D31
DMAX_ALT DMAX_ALT DMAX_ALT
DNP DNP DNP
3 3

Nashua, NH 03063

LOGIC ANALYZER CONN
Size Board No. Rev
C A0217-2008 0.2
Date 12-3-2008_14:30 Sheet 11 of 16
A B C D
A B C D
3.3V
3.3V
3.3V
R162 R161 R163

10K 10K 10K
0402 0402 0402
R164
10K U10
0402
C122 2 18 3.3V
"PB1" R165 R166 0.01UF ADC_A0/LED1/MMC_D7/OTP_EN 1A1 1Y1
100 10 0402 4 16
U6 CDG/ADC_A1/LED2 1A2 1Y2
0805 0603
1 1 2 6 14 1
CZM/ADC_A2/LED3 1A3 1Y3
SW12 8 12
74LVC14A 1A4 1Y4
MOMENTARY
SOIC14
SWT024
C123 11 9 LED3 LED2 LED1 LED13
1UF 2A1 2Y1 YELLOW YELLOW YELLOW GREEN "POWER"
0805 13 7 LED001 LED001 LED001 LED001
2A2 2Y2
15 5
2A3 2Y3
17 3
2A4 2Y4
R159 R158 R160 R157
1 330 330 330 330
"PB ENABLE" OE1 0603 0603 0603 0603
19
R168 OE2
10K
0402 IDT74FCT3244APY
SSOP20
"PB2" R167 R169 SW2
100 10 1 4
ON
U6 PB1/DR1PRI/MMC_D4
1
0805 0603
3 4 2 3
PB2/RFS1/MMC_D5
2
SW13 DIP2
SWT020
74LVC14A
MOMENTARY
SOIC14
SWT024
C124
1UF
0805
2 2
SW2: GPIO enable
POS. FROM TO DEFAULT FUNCTIONS
1 push button 1 DSP (U12, PH0) ON ON (PB1), OFF eMMC, ADC, Expansion Interface)
2 push button 2 DSP (U12, PH1) ON ON ( PB2), OFF eMMC, ADC, Expansion Interface)
3.3V
LED9
"RESET" RED
3 LED001 3
R268 R154 R156 R155

10K 10K 10K 10K
0402 0402 0402 R153 0402
330
0603
U22
1 8
MR RESET
4 7
PFI RESET RESET
5
DA_SOFT_RESET PFO
U26
1
4 ADM708SARZ
2 SOIC8
SN74LVC1G08
SW11
SOT23-5
MOMENTARY
SWT024
3.3V
3.3V
3.3V 3.3V
"RESET"
R152 R170 R171 R172 C119

10K
0402
10K
0402
10K
0402
10K
0402
0.01UF
0402 C121
0.01UF
C120
0.01UF
Nashua, NH 03063
0402 0402
4
5
U6
6 9
U6
8 11
U6
10 13
U6
74LVC14A 74LVC14A 74LVC14A 74LVC14A

SOIC14 SOIC14 SOIC14 SOIC14 Title ADSP-BF518F EZ-BOARD
PUSHBUTTONS, RESET, LEDS
Size Board No. Rev
C A0217-2008 0.2
Date 1-15-2009_11:11 Sheet 12 of 16
A B C D
A B C D
3.3V 3.3V
PS_5V PS_5V
D[0:15]
A[1:19]
J1
A1 2 1 P3 P2
ADDR1 ADDR0 1 2 1 2
A3 4 3 A2 GND1 PWR_IN1 GND1 PWR_IN1
ADDR3 ADDR2 3 4 3 4
A5 6 5 A4 GND2 PWR_IN2 GND2 PWR_IN2
ADDR5 ADDR4 5 6 5 6
A7 8 7 A6 GND3 VDDIO1 GND3 VDDIO1
ADDR7 ADDR6 7 8 7 8
A9 10 9 A8 GND4 VDDIO2 GND4 VDDIO2
ADDR9 ADDR8 9 10 9 10
A11 12 11 A10 GND5 3.3V1 GND5 3.3V1
ADDR11 ADDR10 11 12 11 12
1 A13 14 13 A12 GND6 3.3V2 GND6 3.3V2 1
ADDR13 ADDR12 13 14 13 14
A15 16 15 A14 TFS0/SD_D3 PPI0FS1 PPI0FS2 DT0PRI/SD_CMD DT0PRI/SD_CMD DTPRI DRPRI DR0PRI/SD_D0
ADDR15 ADDR14 15 16 15 16
A17 18 17 A16 AMS3/SPI0_SEL2 PPI0FS3 PPI0CLK RFS0/SD_D2 UART0_TX DTSEC DRSEC UART0_RX
ADDR17 ADDR16 17 18 17 18
A19 20 19 A18 ERXD2 PPI0D1 PPI0D0 ETXD2 TSCLK0/SD_CLK TSCLK RSCLK RSCLK0/SD_D1
ADDR19 ADDR18 19 20 19 20
22 21 ERXD3 PPI0D3 PPI0D2 ETXD3 TFS0/SD_D3 TFS RFS RFS0/SD_D2
ADDR21 ADDR20 21 22 21 22
24 23 ERXDV PPI0D5 PPI0D4 ERXCLK CZM/ADC_A2/LED3 SPISEL1 SPISEL2 MIICRS/HWAIT
ADDR23 ADDR22 23 24 23 24
26 25 SPI0_SSEL1 PPI0D7 PPI0D6 COL AMS2 SPISEL3 SPICLK RSCLK1/MMC_D6
ADDR25 ADDR24 25 26 25 26
28 27 MDIO PPI0D9 PPI0D8 MDC ADC_A0/LED1/MMC_D7/OTP_EN SPIMOSI SPISS PB1/DR1PRI/MMC_D4
ADDR27 ADDR26 27 28 27 28
30 29 ERXD0 PPI0D11 PPI0D10 ETXD0 PB2/RFS1/MMC_D5 SPIMISO TIMER DR1SEC
ADDR29 ADDR28 29 30 29 30
32 31 ERXD1 PPI0D13 PPI0D12 ETXD1 SCL SCL SDA SDA
ADDR31 ADDR30 31 32 31 32
34 33 RMII_PHYINT PPI0D15 PPI0D14 ETXEN UART0_TX UARTTX UARTRX UART0_RX
AWE AWE AOE 33 34 33 34
36 35 PPI0D17 PPI0D16 UARTRTSUARTCTS
ARDY ARE ARE 35 36 35 36
38 37 TSCLK0/SD_CLK TIMER2/GPIO TIMER1/GPIO RSCLK0/SD_D1 RESET RESET NC
AMS1 AMS1 AMS0 AMS0 37 38 37 38
40 39 RESET RESET TIMER3/GPIO UART0_TX PB1/DR1PRI/MMC_D4 GPIO1 GPIO2 PB2/RFS1/MMC_D5
AMS3/SPI0_SEL2 AMS3 AMS2 AMS2 39 40 39 40
42 41 PPI1FS1 PPI1FS2 ADC_A0/LED1/MMC_D7/OTP_EN GPIO3 GPIO4 CDG/ADC_A1/LED2
ABE1#/SDQM1 ABE1 ABE0 ABE0#/SDQM0 41 42 41 42
44 43 PPI1FS3 PPI1CLK WAKE WAKE RSVD1
ABE3 ABE2 43 44 43 44
46 45 PPI1D1/PPI0D19 PP1D0/PPI0D18 RSVD2 RSVD3
BR NMI NMI 45 46 45 46
48 47 PPI1D3/PPI0D21 PPI1D2/PPI0D20 RSVD4 RSVD5
BGH BG 47 48 47 48
50 49 PPI1D5/PPI0D23 PPI1D4/PPI0D22 RSVD6 RSVD7
CLKOUT CLKOUT RESET RESET 49 50 49 50
52 51 PPI1D7 PPI1D6 RSVD8 RSVD9
PB1/DR1PRI/MMC_D4 GPIO1 GPIO2 PB2/RFS1/MMC_D5 51 52 IDC25X2_SMTA
54 53 PPI1D9 PPI1D8
2 ADC_A0/LED1/MMC_D7/OTP_EN GPIO3 GPIO4 CDG/ADC_A1/LED2 53 54 2
D1 56 55 D0 PPI1D11 PPI1D10
DATA1 DATA0 55 56
D3 58 57 D2 PPI1D13 PPI1D12
DATA3 DATA2 57 58
D5 60 59 D4 PPI1D15 PPI1D14 3.3V
DATA5 DATA4 59 60 PS_5V
D7 62 61 D6 PPI1D17 PPI1D16
DATA7 DATA6 61 62
D9 64 63 D8 SDA SDA NC
DATA9 DATA8 63 64
D11 66 65 D10 SCL SCL RSVD1
DATA11 DATA10 65 66
D13 68 67 D12 RSVD2 RSVD3 P4
DATA13 DATA12 67 68 1 2
D15 70 69 D14 RSVD4 RSVD5 GND1 PWR_IN1
DATA15 DATA14 69 70 3 4
72 71 RSVD6 RSVD7 GND2 PWR_IN2
DATA17 DATA16 IDC35X2_SMTA 5 6
74 73 GND3 VDDIO1
DATA19 DATA18 7 8
76 75 GND4 VDDIO2
DATA21 DATA20 9 10
78 77 GND5 3.3V1
DATA23 DATA22 11 12
80 79 GND6 3.3V2
DATA25 DATA24 13 14
82 81 ADC_A0/LED1/MMC_D7/OTP_EN DTPRI DRPRI PB1/DR1PRI/MMC_D4
DATA27 DATA26 15 16
84 83 CZM/ADC_A2/LED3 DTSEC DRSEC DR1SEC
3.3V PS_5V DATA29 DATA28 17 18
86 85 CDG/ADC_A1/LED2 TSCLK RSCLK RSCLK1/MMC_D6
DATA31 DATA30 19 20
88 87 SPI0_SSEL3/CUD TFS RFS PB2/RFS1/MMC_D5
RSVD1 RSVD2 21 22
90 89 SPI0_SSEL1 SPISEL1 SPISEL2 AMS3/SPI0_SEL2
RSVD3 RSVD4 23 24
92 91 SPI0_SSEL3/CUD SPISEL3 SPICLK SPI0_SCK
RSVD5 RSVD6 25 26
94 93 SPI0_MOSI SPIMOSI SPISS AMS2
RSVD7 RSVD8 27 28
3 96 95 SPI0_MISO SPIMISO TIMER DR1SEC 3
PWR_IN1 GND1 29 30
98 97 SCL SCL SDA SDA
PWR_IN2 GND2 31 32
100 99 CZM/ADC_A2/LED3 UARTTX UARTRX DR1SEC
VDDIO1 GND3 33 34
102 101 UARTRTSUARTCTS
VDDIO2 GND4 35 36
104 103 RESET RESET NC
3.3V1 3.3V2 37 38
QMS52X2_SMT PB1/DR1PRI/MMC_D4 GPIO1 GPIO2 PB2/RFS1/MMC_D5
39 40
ADC_A0/LED1/MMC_D7/OTP_EN GPIO3 GPIO4 CDG/ADC_A1/LED2
41 42
WAKE WAKE RSVD1
43 44
RSVD2 RSVD3
45 46
RSVD4 RSVD5
47 48
RSVD6 RSVD7
49 50
RSVD8 RSVD9
IDC25X2_SMTA

Nashua, NH 03063

EXPANSION INTERFACE
Size Board No. Rev
C A0217-2008 0.2
Date 12-10-2008_14:26 Sheet 13 of 16
A B C D
A B C D
VDDOTP TP3
3.3V
VPPOTP TP2
R182 C136 L2
2.0K 0.1UF 1UH
0603 0603 IND019
D2 D5
1 PS_5V
MBR130LSFT1G MBR130LSFT1G 1
1A 1A
SJ4
SOD-123FL SOD-123FL
SHORTING
JUMPER R181
DEFAULT=NOT INSTALLED U11 140.0K
0603
2 V- V+ 1
L1 TRIM R352
"OTP FLAG ENBL" 22UH 3 ADR550B R180 VR3 21.5K
IND018 SOT23-3 1.91K 0603
0603 1 5 R179
JP14 IN OUT 21.5K
1 D4 3 0603
ADC_A0/LED1/MMC_D7/OTP_EN C127 MBR130LSFT1G EN DNP
2 VR2 10UF 1A 2 4
1210 SOD-123FL GND ADJ
IDC2X1 6 5 C129
IN SW1 2.2UF ADP1710
0805 TSOT5
7 2 C133 R178
RT FB C126 R183 1UF 10K
D3
10UF 10.0K 0603 0603
MBR130LSFT1G
3 8 1210 0603 DNP DNP
SD SS 1A
SOD-123FL
4 1
GND COMP
R173 C125 C208
10K 10UF 1UF
0402 1210 0603 ADP1610 R176 C131 R351 R184
MSOP8 24.0K 22000PF 0 3.01K
0603 0402 0603 0603 R177 C132
C135
DNP 10K 2.2UF
10UF
C209 0603 0805
1210
1UF DNP
0603
DNP
C130
2200PF
0603
2 2
L6
1UH
IND019
-12V
1 2
C201 C200
L8 10UF 10UF
22UH D9 1210 1210
IND024 MBR130LSFT1G
3 4
SOD-123FL
PS_5V C206
2.2UF
0805
1 2
L9
22UH
IND024
3 4
3 3
R350 D10
100K C204 MBR130LSFT1G L7
C205 R349 0402 2.2UF 1UH
10UF 10 0805 SOD-123FL IND019
1210 0603 +12V
C207
1000PF C203 C202
0603 10UF 10UF
R348 1210 1210
R345 VR6 44.2K
0 0603
0603 6 5
DNP IN SW1
7 2
RT FB
3 8
SD SS
4 1
R346 GND COMP
0 C199 C210
0603 1UF 1UF
0603 0603 ADP1611 R344 C197 R347
DNP MSOP8 20.0K 22000PF 4.99K
0402 0402 0603
C198
3300PF
0603 ANALOG 20 Cotton Road
Nashua, NH 03063

OTP AND DUAL POWER
Size Board No. Rev
C A0217-2008 0.2
Date 1-15-2009_11:09 Sheet 14 of 16
A B C D
A B C D
F1 FER17
3A 190
FUS004 FER002
4 3
PS_5V
1 2
J3
R267
1
C149 0
C148 10UF 0402
D8
1000PF 1210
MBRS540T3G WAKE
3 1206
5A
SMC
2
POWER
CON045
1 "5V" 3.3V R185 1

4.3 1.1 - 1.4V @ 500mA
1206
FER15
C147 600
1000PF 1206 R188
1206 4.3
1206
R190
0.05
FER16 1206
600
1206 VDDINT TP4
R186
SHGND 1.2K R246 C141 P8
0402 10K 4.7UF 1 2
U7 0402 0603
DNP VR5 IDC2X1
1 10
SHGND W A 1 5
EN GND1 "VDDINT"
2 9
AD0 B R189 2 6
1.0K IN GND2
3 8 0402 C139
AD1 VCC 0.01UF 3 7
0402 OUT GND3
4 7 SJ5
SDA SDA GND 4 8 SHORTING
ADJ GND4 JUMPER
5 6 DEFAULT=INSTALLED
SCL SCL VLOGIC
AD5258 R187 ADP1715
MSOP10 C140 C137 2.67K C138 R245 MSOP8
0.1UF 4.7UF 0402 4.7UF 10K
0402 0603 0603 0402
Remove P8 when measuring VDDINT
2 2
PS_5V
C146
10UF
C142
10UF
Remove P9 when measuring VDDEXT 1.8V @ 500mA
1210 0805
DNP SJ6
SHORTING "VDDFLASH"
JUMPER
3 3.3V @ 2A DEFAULT=INSTALLLED P11 3
1 2 TP11
3.3V TP8
IDC2X1 VDDFLASH
PGND R204
TP5 3.3V "VDDEXT" VR4 0.05
R196 R194 TP6 1206
R192 VR1 0.05 0.05 1 3
24.9K 1206 1206 P9 EN OUT
0603 5 U8 1 2 2
1 IN IN
COMP IDC2X1 VDDEXT 4
4 1 5 SS
CS L3 R191
6GND1
7GND2
8GND3
GND4
C143 C144 2 6 2.5UH 0.05 C151 C152 C150
470PF 68PF 3 6 R195 IND013 1206 2.2UF 0.1UF 2.2UF
FB PGATE
5
0603 0603 0 3 7 0805 0402 0805
GND 0603
R193 2 ADP1864AUJZ 4 8
80.6K SOT23-6 Remove P11 when measuring VDDFLASH
0603
D7
CT6 CT5 C145
MBRS540T3G
SI4411DY 220UF 2.2UF 4.7UF
SMC
SO-8 D2E B 0805
DNP R198
0.05 TP7 SJ8
R197 1206 SHORTING
255.0K JUMPER
0603 VDDMEM DEFAULT=INSTALLLED
PGND
P10
1 2
PGND
IDC2X1
W2 "VDDMEM" ANALOG 20 Cotton Road

Nashua, NH 03063
COPPER
4
4A SJ7
SHORTING
JUMPER
DEFAULT=INSTALLLED
PGND
POWER
Remove P10 when measuring VDDMEM
Size Board No. Rev
C A0217-2008 0.2
Date 12-10-2008_14:26 Sheet 15 of 15
A B C D
A B C D
RN1 RN5 RN9 RN13 RN17
D2 1 8 D2_Z A5_Z 1 8 A5 1 8 A19_Z 1 8 A19 1 8

R1A R1B R1A R1B PB1/DR1PRI/MMC_D4_Z R1A R1B PB1/DR1PRI/MMC_D4 R1A R1B SPI0_MOSI_Z R1A R1B SPI0_MOSI
1 D3 2 7 D3_Z A6_Z 2 7 A6 2 7 A18_Z 2 7 A18 2 7
1
R2A R2B R2A R2B PB2/RFS1/MMC_D5_Z R2A R2B PB2/RFS1/MMC_D5 R2A R2B SPI0_MISO_Z R2A R2B SPI0_MISO
D1 3 6 D1_Z A8_Z 3 6 A8 3 6 A17_Z 3 6 A17 3 6
R3A R3B R3A R3B RSCLK1/MMC_D6_Z R3A R3B RSCLK1/MMC_D6 R3A R3B SPI0_SCK_Z R3A R3B SPI0_SCK
D0 4 5 D0_Z A7_Z 4 5 A7 4 5 A16_Z 4 5 A16 4 5
R4A R4B R4A R4B ADC_A0/LED1/MMC_D7/OTP_EN_Z R4A R4B ADC_A0/LED1/MMC_D7/OTP_EN R4A R4B AMS2_Z R4A R4B AMS2
22 33 33 33 33
RNS005 RNS005 RNS005 RNS005 RNS005
D0 1 8 D0_ZZ A1_Z 1 8 A1 1 8 D7 1 8 D7_Z 1 8

R1A R1B R1A R1B AMS0_Z R1A R1B AMS0 R1A R1B UART0_RX_Z R1A R1B UART0_RX
D1 2 7 D1_ZZ A2_Z 2 7 A2 2 7 D6 2 7 D6_Z 2 7
R2A R2B R2A R2B AWE_Z R2A R2B AWE R2A R2B UART0_TX_Z R2A R2B UART0_TX
D2 3 6 D2_ZZ A3_Z 3 6 A3 3 6 D5 3 6 D5_Z 3 6
R3A R3B R3A R3B ARE_Z R3A R3B ARE R3A R3B TSCLK0/SD_CLK_Z R3A R3B TSCLK0/SD_CLK
D3 4 5 D3_ZZ A4_Z 4 5 A4 4 5 D4 4 5 D4_Z 4 5
R4A R4B R4A R4B AMS1_Z R4A R4B AMS1 R4A R4B DT0PRI/SD_CMD_Z R4A R4B DT0PRI/SD_CMD
22 33 33 22 33
2 2
D7_ZZ 1 8 D7 1 8 1 8 D11 1 8 D11_Z A15_Z 1 8 A15

R1A R1B TFS0/SD_D3_Z R1A R1B TFS0/SD_D3 SCKE_Z R1A R1B SCKE R1A R1B R1A R1B
D6_ZZ 2 7 D6 2 7 2 7 D10 2 7 D10_Z A14_Z 2 7 A14
R2A R2B RFS0/SD_D2_Z R2A R2B RFS0/SD_D2 SMS_Z R2A R2B SMS R2A R2B R2A R2B
D5_ZZ 3 6 D5 3 6 3 6 D9 3 6 D9_Z A13_Z 3 6 A13
R3A R3B RSCLK0/SD_D1_Z R3A R3B RSCLK0/SD_D1 SCAS_Z R3A R3B SCAS R3A R3B R3A R3B
D4_ZZ 4 5 D4 4 5 4 5 D8 4 5 D8_Z 4 5
R4A R4B DR0PRI/SD_D0_Z R4A R4B DR0PRI/SD_D0 SRAS_Z R4A R4B SRAS R4A R4B R4A R4B
22 33 33 22 33
A9_Z 1 8 A9 1 8 1 8 D15 1 8 D15_Z D11_ZZ 1 8 D11

R1A R1B SPI0_SSEL3/CUD_Z R1A R1B SPI0_SSEL3/CUD SWE_Z R1A R1B SWE R1A R1B R1A R1B
A10_Z 2 7 A10 2 7 2 7 D14 2 7 D14_Z D10_ZZ 2 7 D10
R2A R2B CDG/ADC_A1/LED2_Z R2A R2B CDG/ADC_A1/LED2 SA10_Z R2A R2B SA10 R2A R2B R2A R2B
A11_Z 3 6 A11 3 6 3 6 D13 3 6 D13_Z D9_ZZ 3 6 D9
R3A R3B CZM/ADC_A2/LED3_Z R3A R3B CZM/ADC_A2/LED3 ABE0#/SDQM0_Z R3A R3B ABE0#/SDQM0 R3A R3B R3A R3B
A12_Z 4 5 A12 4 5 4 5 D12 4 5 D12_Z D8_ZZ 4 5 D8
R4A R4B DR1SEC_Z R4A R4B DR1SEC ABE1#/SDQM1_Z R4A R4B ABE1#/SDQM1 R4A R4B R4A R4B
3 33 33 33 22 22 3
RN21
D15_ZZ 1 8 D15
R1A R1B
D14_ZZ 2 7 D14
R2A R2B
D13_ZZ 3 6 D13
R3A R3B
D12_ZZ 4 5 D12
R4A R4B
22
RNS005

Nashua, NH 03063

SERIES TERMINATORS
Size Board No. Rev
C A0217-2008 0.2
Date 12-3-2008_14:30 Sheet 16 of 16
A B C D
I INDEX
Numerics audio
2-wire interface (TWI), 2-3 interface, 1-17
codec (U31), 1-13, 1-15, 1-17, 2-10
dual connectors (J4-5), 1-18, 2-26
A SPI/TWI select switch (SW16), 2-13
AD5258 digipot, 2-2 SPORT0 enable (SW15), 1-17, 2-13
ADC7266 (U2), 2-9 test switches (SW22-23), 1-19, 2-15
ADC_A0-2 signal, 1-21
ADC channel select jumpers (JP17-28), 2-19
B
ADC range jumper (JP4), 2-17
ADM3202 line driver/receiver (U21), 1-19 background telemetry channel (BTC), 1-25
ADP1715 low dropout regulator (LDO), 2-2 battery
AMS0-3 select lines, 1-11, 2-9, 2-18 holder connector (J12), 2-26
analog audio interface, See audio supply, 1-20
analog-to-digital converter (ADC), 1-12, 1-17, bill of materials, A-1
1-18, 2-15, 2-17 board schematic (ADSP-BF518F), B-1
architecture, of this EZ-Board, 2-2 boot
ASYNC (asynchronous memory control) modes, 2-8
external memory banks 0-3, 1-10 mode select switch (SW1), 1-12, 1-14
C
CDG signal, 1-21
audio codec, See audio
configuration, of this EZ-Board, 1-4
ADSP-BF518F EZ-Board Evaluation System Manual I-1

INDEX
connectors Ethernet
diagram of locations, 2-24 interface, xiv, 1-13, 1-16
J12 (battery holder), 2-26 configuration switch (SW8), 2-11
J13 (SD), 2-26 connectors (J14-15), 1-17, 2-27
J14-15 (Ethernet), 1-17 LEDs (LED4-8, LED10-12), 2-22
J14 (Ethernet), 2-27 mode switch (SW17), 2-14
J15 (Ethernet), 2-27 PHY IC (U29), 1-13
J16-26 (SMA), 2-26 port 1 config switch (SW7), 1-16, 2-11
J1 (expansion interface II), 1-21, 2-25, 2-26 port 2 config switch (SW18), 1-16, 2-14
J2 (RS-232), 2-25 power down jumper (JP13), 2-17
J3 (power), 1-6, 2-25 reset push button (SW11), 2-12
J4-5 (dual audio), 1-18, 2-26 example programs, 1-25
J7 (SMA), 2-26 expansion interface II
P1 (JTAG), 1-6, 1-22, 2-27 J1 connector, 1-21, 1-23, 2-25, 2-26
P2 (expansion interface II), 1-21, 2-27 P2 connector, 1-19, 1-21, 1-23, 2-27
P3 (expansion interface II), 1-15, 2-28 P3 connector, 1-15, 1-23, 2-28
P4 (expansion interface II), 1-21, 2-27 P4 connector, 1-19, 1-21, 1-23, 2-27
P5-7 (DMAX land grid array), 1-22, 2-28 external memory, 1-9, 1-10
ZP1 (debug agent), 2-29
contents, of this EZ-Board package, 1-3
F
core voltage, 2-2
CUD (up) signal, 1-14, 1-15 features, of this EZ-Board, xiii
customer support, xvii flag pins, See programmable flags by name (PFx,
CZM signal, 1-21 PGs, PHx)
flash memory enable switch (SW6), 2-9
flash WP jumper (JP3), 2-17
D
Das U-Boot, universal boot loader, 1-13
G
debug agent connector (ZP1), 2-29
default configuration, of this EZ-Board, 1-4 general-purpose IO pins (GPIO), 1-21, 2-8,
down signal (CDG), 1-15 2-12, 2-14, 2-22
DR1PRI signal, 1-21 general-purpose push buttons (PB1-2), 1-21
GPIO enable switch, See SW2
E
I
eMMC
enable switches (SW20-21), 1-12 installation, of this EZ-Board, 1-4
enable switch (SW20-21), 2-15 IO voltage, 2-2
interface, 1-12
I-2 ADSP-BF518F EZ-Board Evaluation System Manual

INDEX
J M
JTAG MAC address, 1-16
interface, 1-22 media independent interface (MII), 1-16
connector (P1), 1-6, 1-22, 2-27 Media Instruction Set Computing (MISC), xi
jumpers memory map, of this EZ-Board, 1-9
diagram of locations, 2-16 MICBIAS signal, 2-18
JP11-12 (LED select), 2-17 MICIN signal, 2-18
JP13 (Ethernet power down), 2-17 microphone
JP14 (OTP flag enable), 2-18 gain switch (SW5), 2-10
JP15 (mic select), 1-17, 2-18 headphone select (SW6), 1-18, 2-10
JP16 (SPI flash CS enable), 1-15, 2-18 select jumper (JP15), 1-17, 2-18
JP17-28 (ADC channel select), 2-19 SPI/TWI switch (SW8), 1-17
JP3 (flash WP), 2-17 Micro Signal Architecture (MSA), xi
JP4 (ADC range), 1-19, 2-17 MMC_Dx signals, 1-21
JP6 (mic select), 1-17
P10 (VDDMEM power), 1-24, 2-20
N
P11 (VDDFLASH power), 1-24, 2-20
P17-28 (ADC channel select), 1-19 notation conventions, xxi
P8 (VDDINT power), 1-24, 2-19
P9 (VDDEXT power), 1-24, 2-19 O
oscilloscope, 1-24
K OTP_EN signal, 1-21
KSZ8893M PHY device, 2-14 OTP flag enable jumper (JP14), 2-18
OTP memory writes, 2-18
L
P
land grid array connectors (P5-7), 1-22, 2-28
LEDs package contents, 1-3
diagram of locations, 2-21 parallel flash memory, xiii, 1-11
LED10-12 (Ethernet), 2-22 See also NAND, flash memory
LED1-3 (PH3, PH5-6), 1-21, 2-22 parallel peripheral interface (PPI), See PPI
LED4-8 (Ethernet), 2-22 interface
LED4 (USB monitor), 1-6 PF0-7 programmable flags, 2-3
LED9 (reset), 2-22 PF8 programmable flag, 2-3
power (LED13), 2-23 PF9-15 programmable flags, 2-3
LED select jumpers (JP11-12), 2-17 PG0-10 programmable flags, 2-5
license restrictions, xii, 1-8 PG11 programmable flag, 2-5
PG12 programmable flag, 2-5
PG13-15 programmable flags, 2-5
PH0-1 programmable flags, 1-21, 2-6, 2-12

INDEX
PH2 programmable flag, 2-6 secure digital (SD) interface, 1-12, 1-13
PH3 programmable flag, 1-21, 2-6, 2-18, 2-22 serial peripheral interconnect (SPI) ports, See
PH4 programmable flag, 2-6 SPI interface
PH5-6 programmable flags, 1-21, 2-6, 2-22 session startup procedure, 1-6
PH7 programmable flag, 2-6 SMA connectors (J7, J16-26), 2-26
POST (power-on-self test) program, 1-12, 1-19, SPI0_SSEL2 signal, 2-18
1-24, 2-12 SPI flash CS enable jumper (JP16), 2-18
power SPI interface
5V wall adaptor (P14), 1-3 connections, 1-13
connector (J3), 1-6, 2-25 SPI/TWI switch (SW16), 1-17
LED (LED13), 2-23 SPISEL1 signal, 1-14
measurements, 1-24 SPISEL2 signal, 1-13
PPI interface SPISEL3 signal, 1-14
connections, 1-15 SPORT0 enable switch (SW15), 1-17, 2-13
expansion interface II connector (P3), 1-15, SPORT1 enable switch (SW4), 1-18, 2-9
2-28 SRAM memory, 1-9
programmable flag inputs PH0 -1, 1-21 SSM2602 audio codec (U1), 2-13
standalone debug agent, xii, 1-4, 1-6, 1-8, 1-11,
1-22
R
SW10 (UART0 setup) switch, 2-12
real-time clock (RTC), 1-20, 2-3 SW11 (reset) push button, 2-12
Reduced Instruction Set Computing (RISC), xi SW12-13 (IO) push buttons, 2-12
reference design info, 1-25 SW14 (rotary encoder with momentary) switch,
removable secure interface (RSI), 1-12 2-13
reset SW15 (SPORT0 enable) switch, 1-17, 2-13
LED (LED9), 2-22 SW16 (SPI/TWI config) switch, 1-17, 2-13
push button (SW11), 2-12 SW17 (Ethernet mode) switch, 2-14
restrictions, of evaluation license, 1-8 SW18 (Ethernet port 2 config) switch, 1-16,
RFS1 signal, 1-21 2-14
rotary encoder SW19 (encoder enable) switch, 1-16, 2-14
interface, 1-15 SW1 (boot mode select) switch, 1-12, 1-14, 2-8
enable switch (SW19), 1-15, 2-14 SW20-21 (eMMC enable) switches, 1-12
with momentary switch (SW14), 2-13 SW20 (eMMC enable) switch, 2-15
RS-232 connector (J2), 2-25 SW21 (eMMC enable) switch, 2-15
RTC pin, 1-20 SW22-23 (test) switches, 1-19, 2-15
SW2 (push button enable) switch, 1-21, 2-8,
S 2-13
schematic, of ADSP-BF518F EZ-Board, B-1 SW3 (flash enable) switch, 2-9
SD connector (J13), 2-26 SW4 (SPORT1 enable) switch, 1-18, 2-9
SDRAM interface, 1-10, 1-11 SW5 (mic gain) switch, 1-17, 2-10
I-4 ADSP-BF518F EZ-Board Evaluation System Manual

INDEX
SW6 (mic select) switch, 1-18, 2-10 universal asynchronous receiver transmitter, See
SW7 (Ethernet port 1 config) switch, 1-16, 2-11 UART0, UART1
SW8 (Ethernet config) switch, 2-11 USB monitor LED (LED4), 1-6
switches, diagram of locations, 2-7
system architecture, of this EZ-Board, 2-2
V
VDDEXT
T power jumper (P9), 2-19
thumbwheel control, xiv voltage domain, 1-24
TWI config switch (SW8), 1-17 VDDFLASH
power jumper (P11), 2-20
voltage domain, 1-24
U
VDDINT
UART0 interface power jumper (P8), 2-19
expansion interface II connectors (P2), 1-19, voltage domain, 1-24
2-27 VDDMEM
reset push button (SW11), 2-12 power jumper (P10), 2-20
setup switch (SW10), 2-12 voltage domain, 1-24
UART1 interface VisualDSP++ environment, 1-6
enable switch (SW14), 2-12 voltage planes, 1-23
expansion interface II connectors (P4), 1-19,
2-27
UART1_RX signal, 2-12, 2-18, 2-19 W
UART1_TX signal, 2-12, 2-18, 2-19 wall adaptor connector (J3), 1-6, 1-22
U-Boot, universal boot loader, 1-13 watchdog timer, 1-20

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ADSP-BF518F EZ-Board TM

Evaluation System Manual

Revision 1.0, January 2009

Analog Devices, Inc.

Trademark and Service Mark Notice

The EZ-Board evaluation system contains ESD (electrostatic discharge)

USING ADSP-BF518F EZ-BOARD

ADSP-BF518F EZ-Board Evaluation System Manual v

Evaluation License Restrictions ..................................................... 1-8

vi ADSP-BF518F EZ-Board Evaluation System Manual

ADSP-BF518F EZ-BOARD HARDWARE REFERENCE

ADSP-BF518F EZ-Board Evaluation System Manual vii

Flash WP Jumper (JP3) ......................................................... 2-17

viii ADSP-BF518F EZ-Board Evaluation System Manual

SD Connector (J13) .............................................................. 2-26

ADSP-BF518F EZ-BOARD BILL OF MATERIALS

ADSP-BF518F EZ-Board Evaluation System Manual ix

Power ......................................................................................... B-15

x ADSP-BF518F EZ-Board Evaluation System Manual

Thank you for purchasing the ADSP-BF518F EZ-Board™, Analog

ADSP-BF518F EZ-Board Evaluation System Manual xi

L The ADSP-BF518F EZ-Board installation is part of the Visu-

xii ADSP-BF518F EZ-Board Evaluation System Manual

The board features:

D One input MIC jack

ADSP-BF518F EZ-Board Evaluation System Manual xiii

xiv ADSP-BF518F EZ-Board Evaluation System Manual

Purpose of This Manual

ADSP-BF518F EZ-Board Evaluation System Manual xv

What’s New in This Manual

xvi ADSP-BF518F EZ-Board Evaluation System Manual

Technical or Customer Support

• E-mail tools questions to

• E-mail processor questions to

• Phone questions to 1-800-ANALOGD

ADSP-BF518F EZ-Board Evaluation System Manual xvii

Analog Devices Web Site

xviii ADSP-BF518F EZ-Board Evaluation System Manual

VisualDSP++ Online Documentation

.chm Help system files and manuals in Microsoft help format

ADSP-BF518F EZ-Board Evaluation System Manual xix

Table 1. Related Processor Publications

ADSP-BF512/ADSP-BF514/ADSP-BF516/ADSP- General functional description, pinout, and

ADSP-BF51x Blackfin Processor Hardware Refer- Description of internal processor architec-

Blackfin Processor Programming Reference Description of all allowed processor assem-

Table 2. Related VisualDSP++ Publications

ADSP-BF518F EZ-Board Evaluation System Man- Description of the hardware capabilities of

VisualDSP++ User’s Guide Description of VisualDSP++ features and

xx ADSP-BF518F EZ-Board Evaluation System Manual

Table 2. Related VisualDSP++ Publications (Cont’d)

VisualDSP++ Loader and Utilities Manual Description of the loader/splitter function

filename Non-keyword placeholders appear in text with italic style format.

ADSP-BF518F EZ-Board Evaluation System Manual xxi

Caution: Incorrect device operation may result if ...

Warning: Injury to device users may result if ...

xxii ADSP-BF518F EZ-Board Evaluation System Manual

This chapter provides specific information to assist you with development

ADSP-BF518F EZ-Board Evaluation System Manual 1-1

1-2 ADSP-BF518F EZ-Board Evaluation System Manual

ADSP-BF518F EZ-Board Evaluation System Manual 1-3

1-4 ADSP-BF518F EZ-Board Evaluation System Manual

Figure 1-1. Default EZ-Board Hardware Setup