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Shallow Junctions

&

Contacts

Prof. Krishna Saraswat

Department of Electrical Engineering Stanford University Stanford, CA 94305 saraswat@stanford.edu

Stanford University Stanford, CA 94305 saraswat@stanford.edu Stanford University 1 Saraswat / EE311 / Shallow Junctions

Stanford University

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Saraswat / EE311 / Shallow Junctions

Outline

Junction/contact scaling issues Shallow junction technology Ohmic contacts Technology to form contacts

• Ohmic contacts • Technology to form contacts Stanford University 2 Saraswat / EE311 / Shallow

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MOS Device Scaling

 
L N+ xox N+ X j N a l P o
L
N+
xox
N+
X j
N
a
l
P
o
 

Constant E Field Scaling

 

L

All device parameters are scaled by

N+ x ox N a l o N+ X j P the same factor.
N+ x ox N a l o N+ X j P
N+
x
ox
N
a
l o
N+
X j
P

the same factor.

• gate oxide thickness x ox

 

• channel length L

 

• source/drain junction depth X j

• Channel doping

 

Why do we scale MOS transistors?

 

• Supply voltage V DD

1. Increase device packing density

2. Improve frequency response α 1/L

3. Improve current drive (transconductance g m )

" V G
" V G

g m = " I D

V D = const

 

# µ n K o x o x

# µ n K o x

W

L

W

L

t

t

o x

 

V D

for V D < V D S A T , linear region

(

V G $ V T )

for V D > V D S A T , saturation region

Why do we need to scale junction depth?

Why do we need to scale junction depth?

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Short Channel Effects on Threshold voltage Ddepletion width in a long channel device W =

Short Channel Effects on Threshold voltage

Ddepletion width in a long channel device

W =

2" ( 2# F + VBG ) qN A
2" ( 2# F + VBG )
qN A

We can approximate, the bulk charge as

By trigonometry, we can write:

L + L '

2 L

= 1 "

$ ' & 1 + 2 # W " 1 ) & ) # r
$
'
&
1 + 2 # W
"
1
)
&
) # r j
%
r
(
L
j
Gate N+ source Depletion region L N+ drain P-Si L ! rj
Gate
N+ source
Depletion region
L
N+ drain
P-Si
L
!
rj

Q B

source depleted

Q by depleted drain

B

by

rj Q B source depleted Q by depleted drain B by We can then approximate the

We can then approximate the threshold voltage as:

V T = V F B ! 2 " # F ! Q B x " 1 ! &

C

o

,

+

%

*

$

1 + 2 " W r j
1 + 2 " W
r
j

! 1 ) " r j

L

'

(

-

/

.

Threshold voltage is a function of junction depth, depletion width and channel length?

L. Yau, Solid-State Electronics, vol. 17, pp. 1059, 1974

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Saraswat / EE311 / Shallow Junctions

#

$

Q B " L = q " N A " W " %

%

L + L '

2

& ' ( (

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Need for Shallow Source/Drain Junctions

  Need for Shallow Source/Drain Junctions V T = V F B ! 2 " #
  Need for Shallow Source/Drain Junctions V T = V F B ! 2 " #

V T = V F B ! 2 " # F ! Q B x " 1 ! &

C

o

,

+

%

*

$

1 + 2 " W r j
1 + 2 " W
r
j

! 1 ) " r j

L

'

(

-

/

.

•Roll-off in threshold voltage as the channel length is reduced and drain voltage is increased •To minimimize V T roll-off •Reduce as junction depth(r j ) •Increase in C ox should increase gate control

Sheet resistance increases as junction depth is reduced

Sheet resistance increases as junction depth is reduced

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Source/drain Junction Depth Year 1997 1999 2003 2006 2009 2012 Min Feature Size 0.25 !

Source/drain Junction Depth

Source/drain Junction Depth Year 1997 1999 2003 2006 2009 2012 Min Feature Size 0.25 !  

Year

1997

1999

2003

2006

2009

2012

Min Feature Size

0.25!

   

0.18!

0.13!

0.10!

0.07!

0.05!

   

15-30

10-20

Contact xj (nm)

100-200

xj at Channel (nm)

50-100

36-72

26-52

70-140

50-100

40-80

20-40

15-30

10-20

From the ITRS roadmap

•Source/drain doping requirements show continuing drive to obtain shallow junctions. •How will we form such shallow junctions? •How will we make low resistance contacts to them? •How will we minimize the sheet resistance of the junctions?

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S/D Junction Scaling Trend

 
Gate Length or SDE Depth [nm] 70 60 50 40 2001 ITRS Physical Gate Length

Gate Length or SDE Depth [nm]

70

60

50

40

70 60 50 40 2001 ITRS Physical Gate Length 60 50 Max. Ratio of R s

2001 ITRS

Physical Gate Length

60

50

Max. Ratio of R sd to Ideal R ch 40

R sd /R c -ih deal [%]

 

30

SDE Junction Depth
SDE Junction Depth

30

20

10

0

2000

2004

2008

2012

2016

Rch " R (V s h Lg s ! N s d1X j

ch!t Vox t h )

Scaled with

(L ch , t ox )

L

g

20

10

0

R

s d !

Difficult to scale (N sd const, X j )

 

Year

Ref: J. Woo (UCLA)

 

R sd /R ch

As L g scales down, R sd becomes comparable to R ch

 

R sd becomes important factor for device current

Parasitic portion of the device is now playing important role in device performance and CMOS scaling

 
 

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• • • Impact of Parasitic Series Resistance y = 0 140 NMOS 120 Scaled by
Impact of Parasitic Series Resistance y = 0 140 NMOS 120 Scaled by ITRS Roadmap
Impact of Parasitic Series Resistance
y = 0
140
NMOS
120
Scaled by ITRS Roadmap
R
100
ov
Sidewall
Gate
80
R
60
ext
Silicide
x
40
R
N
ov (y)
dp
R
20
R
ov
R csd
csd
R ext
R dp
0
30 nm 50 nm 70 nm 100 nm
Physical Gate Length
N
ext (x)
70
60
Problem in junction scaling:
NMOS
R csd
Sheet resistance of a junction is a strong
function of doping density
50
40
R
Maximum doping density is limited by solid
solubility and it does not scale !
ext
30
Silicidation can minimize the impact of
junction sheet resistance
• Contact resistance R csd is one of the dominant
components for future technology
20
R
ov
10
R dp
0
32 nm 53 nm 70 nm 100 nm
Physical Gate Length
Source: Jason Woo, UCLA
Relative Contribution [%]
Series Resistance (ohms)

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Relative Contribution [%] Series Resistance (ohms) Relative Contributions of Resistance Components: PMOSFETs 200

Relative Contribution [%]

Series Resistance (ohms)

Relative Contributions of Resistance Components: PMOSFETs

200

150

100

50

0

PMOS Scaled by ITRS Roadmap R ov R ext R dp R csd
PMOS
Scaled by ITRS Roadmap
R
ov
R
ext
R
dp
R
csd

30 nm

50 nm

70 nm

100 nm

Physical Gate Length

70

60

50

40

30

20

10

0

PMOS R csd R ov R ext R dp
PMOS
R csd
R
ov
R
ext
R dp

32 nm

53 nm

70 nm 100 nm

Physical Gate Length

Problem even more serious for PMOS

R csd will be a dominant component for highly scaled nanometer transistor ( R csd /R series >> ~ 60 % for L G < 53 nm)

Source: Jason Woo, UCLA

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Outline

Junction/contact scaling issues Shallow junction technology Ohmic contacts Technology to form contacts

• Ohmic contacts • Technology to form contacts Stanford University 10 Saraswat / EE311 / Shallow

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Dopant Diffusion Anneal/Diffusion Ion Implant Gate Stack • Solutions to diffusion equations (Fick's laws)

Dopant Diffusion

Anneal/Diffusion Ion Implant

Gate Stack
Gate Stack

• Solutions to diffusion equations (Fick's laws) gives bulk diffusivity

diffusion equations (Fick's laws) gives bulk diffusivity D i = D i o " e _

D i = D i o " e _ E O k " T

• In shallow junction technologies, numerous effects alter these values resulting in enhanced diffusion. • Transient enhanced diffusion

in enhanced diffusion. • Transient enhanced diffusion D = D i + D o " e

D = D i + D o " e _ t #

• Diffusion affected by defects, e.g.,oxidation induced point defects

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Diffusion Affected by Oxidation Induced Point Defects

TSUPREM IV simulations of oxidation enhanced diffusion of boron (OED) and oxidation retarded diffusion of antimony (ORD) during the growth of a thermal oxide on the surface of silicon.

antimony boron
antimony
boron

Oxidation increases interstitials (C I ) and decreases vacancies (C V ) from their equilibrium values. This in turn changes diffusivity.

(Ref: Plummer, et al., Silicon VLSI Technology - Fundamentals, Practice and Models)

Silicon VLSI Technology - Fundamentals, Practice and Models) Stanford University 12 Saraswat / EE311 / Shallow

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Diffusion in Polycrystalline Materials

D GB grain boundary diffusion

D L lattice diffusion

Generally D GB > > D L

lattice diffusion Generally D G B > > D L The worst-case demonstration of the defect

The worst-case demonstration of the defect enhanced diffusion of dopants is in polycrystalline silicon, which can be several times faster than diffusion in bulk Si because of defects at the grain boundaries.

in bulk Si because of defects at the grain boundaries. Stanford University 13 Saraswat / EE311

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Transient Enhanced Diffusion (TED)

τ
τ
40 keV, 10 -14 cm -2 B 750ºC anneal
40 keV, 10 -14 cm -2 B
750ºC anneal

At lower temperatures, the damage can stay around longer and enhance the dopant diffusion, while at higher temperatures the damage annihilates faster. Thus the diffusivity is a function of time during the transient.

D = Di + Do " exp % &' # t )* ( Di = Di o exp # $% " kT E 0 & '(

$

Where

is intrinsic diffusity

" kT E 0 & '( $ Where is intrinsic diffusity Ref: Plummer, et.al., Stanford University

Ref: Plummer, et.al.,

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Effect of TED on Junction Depth

Effect of TED on Junction Depth • At lower temperature longer times are needed to anneal

• At lower temperature longer times are needed to anneal the damage

• Transient enhanced dopant diffusion effects are stronger

• Junction depth is larger

• Higher temperature and shorter times are needed to minimize TED

temperature and shorter times are needed to minimize TED Stanford University 15 Saraswat / EE311 /

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Shallow Junction Formation Technologies Low Energy Implantation 40 keV As and B implants 12 keV
Shallow Junction Formation Technologies
Low Energy Implantation
40 keV As and B implants
12 keV B implants
Boron
Boron
Arsenic
BF 2
Depth
1022
Depth
as-implanted
1020
5 1 keV keV
1018
Ref. Kasnavi, PhD Thesis
1016
Stanford Univ. 2001
0
20
Depth (nm) 60
40
80
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Concentration (cm -3 )
Concentration (cm -3 )

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Ion Implantation Damage

Heavy ions (As, P) Higher energy

Light ions (B) Lower energy

ions (As, P) Higher energy Light ions (B) Lower energy • Heavy ions (As, P) cause
ions (As, P) Higher energy Light ions (B) Lower energy • Heavy ions (As, P) cause

Heavy ions (As, P) cause excessive damage turning implanted region into amorphous

Light ions (B) have buried damage

 
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Ion Implantation Damage Anneal

Light ions (B) Lower energy

Heavy ions (As, P) Higher energy

regrowth
regrowth
Buried damage

Buried damage

Amorphous

Crystalline

After implant

SPE fully annealed
SPE
fully annealed

After anneal

Fully amorphized region can be fully annealed through solid phase regrowth

Buried damage leaves defects where damage was created as regrowth takes

place both from top and bottom.

created as regrowth takes place both from top and bottom. Stanford University 18 Saraswat / EE311

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Pre-amorphization implants Implanted 10 sec 1000°C RTA Ge preamorphized Si preamorphized Not preamorphized Depth
Pre-amorphization implants
Implanted
10 sec 1000°C RTA
Ge preamorphized
Si preamorphized
Not preamorphized
Depth (nm)
Pre-amorphization implants can reduce the damage and yet get shallow junctions
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Log concentration (cm -3 )
Solid Source Diffusion Depth (nm) Depth (nm) In COSi 2 In Si after silicide removal
Solid Source Diffusion
Depth (nm)
Depth (nm)
In COSi 2
In Si after silicide removal
Boron profiles after diffusion at 950°C of 50 nm COSi 2 implanted
with 5 X 10 15 cm -2 BF 2 (a) and (b)in Si after silicide removal.
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B Concentration (cm -3 )

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Gas Immersion Laser Doping (GILD)

Gas Immersion Laser Doping (GILD) Si wafer showing the adsorption of the dopant species onto the
Gas Immersion Laser Doping (GILD) Si wafer showing the adsorption of the dopant species onto the

Si wafer showing the adsorption of the dopant species onto the clean silicon surface. The dopant is incorporated into a very shallow region upon exposure to the excimer laser pulse.

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Stanford University 21 Saraswat / EE311 / Shallow Junctions Junction Depth Vs. Sheet Resistance Tradeoff 60
Junction Depth Vs. Sheet Resistance Tradeoff 60 5 keV limit 50 Roadmap Y=2000, L g=180nm
Junction Depth Vs. Sheet Resistance Tradeoff
60
5 keV limit
50
Roadmap Y=2000, L g=180nm
40
30
1 limit keV
2005, 2002, 100nm 130nm
20
2008, 70nm
2011
, 50nm
10
2014, 35nm
1020C spike
0
0
250
750
1000
Rs 500 ( ! /
)
Ref. Kasnavi, PhD Thesis Stanford Univ. 2001
It will be difficult to meet the ITRS scaling
requirments of junction depth and sheet resistance
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Solutions to Shallow Junction Resistance Problem

  Solutions to Shallow Junction Resistance Problem   Extension implants Elevated source/ drain S i l
  Solutions to Shallow Junction Resistance Problem   Extension implants Elevated source/ drain S i l
 

Extension implants

Elevated source/ drain

Problem   Extension implants Elevated source/ drain S i l i c i d a t
Problem   Extension implants Elevated source/ drain S i l i c i d a t
S i l i c i d a t i o n Schottky Source/Drain

Silicidation

Schottky Source/Drain

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Effect of Scaling of Contacts and Junctions R (total) = Rch + Rparasitic Rparasitic =
Effect of Scaling of Contacts and Junctions
R (total) = Rch + Rparasitic
Rparasitic = Rextension + Rextrinsic
Rextension = Rd’ + Rs’
Rextrinsic = Rd + Rs + 2Rc
Ref: Ohguro, et al., ULSI Science and Technology 1997, Electrochemical Soc. Proc., Vol. 97-3
Silicidation of junctions is necessary to minimize the
impact of junction parasitic resistance
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Rcsd = L'Tc coth $%& LLcTon !"# LT = R!sh c, dp ) c '
Rcsd = L'Tc coth $%& LLcTon !"# LT = R!sh c, dp ) c ' exp$$%& qN( bif !!"#
Elevated S/D Technology
From A. Hokazono et al (Toshiba), IEDM2000
• Elevated S/D structure ⇒ Reduction of R csd by increasing N if &
reducing R sh,dp underneath silicide
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New Structures and Materials for Nanoscale MOSFETs

 
 

(From Handout #1)

 
 
    Top Gate  
 

Top Gate

 
5 3 4 2 1
5 3 4 2 1
5
3
4
2
1
G G C

GG C

         
         
D Si Source Drain

D

Si

Source

Drain

S SiO2

 
     
     
Bottom Gate

Bottom Gate

 

High µ

 

High-K

Si

channel

 
 

BULK

SOI

Double gate

 

1. Electrostatics - Double Gate

 

Retain gate control over channel

Minimize OFF-state drain-source leakage

-

-

2. Transport - High Mobility Channel

 

-

High drive current for low intrinsic delay

-

High mobility/injection velocity

- High drive current for low intrinsic delay - High mobility/injection velocity

3. Parasitics - Schottky S/D

 
 

- Reduced extrinsic resistance

4. Gate leakage - High-K dielectrics

 

-

Reduced power consumption

5. Gate depletion - Metal gate

 
 
 

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Effect of Extrinsic Resistance on Double Gate MOSFETs

 
GATE

GATE

 

II dd == KK((VV gg VV tthh II dd RR ss )) αα

t t h h – – I I d d R R s s ) )
 

Net Doping (cm-3)

1.E+21 1.E+20 1.E+19 1.E+18 1.E+17 1.E+16 1.E+15 1.E+14 1.E+13

  Net Doping (cm-3) 1.E+21 1.E+20 1.E+19 1.E+18 1.E+17 1.E+16 1.E+15 1.E+14 1.E+13 Doping

Doping

gradient

 

4nm/dec 5nm/dec

 

2nm/dec 3nm/dec

0.5nm/dec 1nm/dec

 

40

45

50

55

60

65

 

x (nm)

 

Extrinsic resistance reduces gate overdrive performance limiter in ballistic FETs

Ideally need very low specific contact resistivity and hyperabrupt lateral junctions

For a given doping abruptness:

 

Too much underlap dopants spill into channel worse SCE Too little underlap large series resistance in extension tip Extrinsic (S/D) resistance may limit performance in future ultrathin body DGFETs

   

Shenoy and Saraswat, IEEE Trans. Nanotechnology, Dec. 2003

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Stanford University

 

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Saraswat / EE311 / Shallow Junctions

Two kinds of transistors Junction S/D MOSFET Schottky S/D MOSFET Possible advantages • Better utilization
Two kinds of transistors
Junction S/D MOSFET
Schottky S/D MOSFET
Possible advantages
• Better utilization of the metal/semiconductor interface
 Possible option to overcome the higher parasitic resistance
• Modulation of the source barrier by the gate
 High V g ⇒ barrier thin ⇒ tunneling current ⇑ ⇒ I ON ⇑
 Low V g ⇒ barrier thick ⇒ tunneling current ⇓ ⇒ I OFF ⇓
• Better immunity from short channel effects
Possible Disadvantage
Tradeoff between short channel effect vs. I ON reduction due to the Schottky barrier
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• • • |I d | (A/ µ m) Schottky Barrier Source/Drain SOI MOSFET Gate Silicide

|I d | (A/ µ m)

Schottky Barrier Source/Drain SOI MOSFET

Gate Silicide Si BOX
Gate
Silicide
Si
BOX
 

PtSi PMOS

ErSi NMOS

Lg

20 nm

15 nm

Tox

4 nm

4 nm

Vg-Vt

1.2 V

1.2 V

Ion

270

uA/um

190

uA/um

Swing

100

mV/dec

150

mV/dec

Ion/Ioff

5E5

1E4

Vt

-0.7 V

-0.1 V

Metal S/D reduce extrinsic resistance

But Schottky barrier reduces I on

Need low barrier technology to ensure high I on

L g ~20 nm FETs with Complementary Silicides PtSi PMOS, ErSi NMOS

Source ErSi 2 Tilted Lg + Spacers =27nm Gate N + poly, ErSi 2 W=25nm
Source
ErSi 2
Tilted
Lg + Spacers =27nm
Gate
N + poly, ErSi 2
W=25nm

1E-3

1E-4

1E-5

1E-6

1E-7

1E-8

1E-9

1E-10

|V sd | from 0.2V to 1.4V in steps of 0.4V PMOS NMOS T ox
|V sd | from 0.2V to 1.4V
in steps of 0.4V
PMOS
NMOS
T
ox = 4nm
T
ox = 4nm
L
g = 20nm
L
g = 15nm

J. Boker et al.- UC Berkeley

-1.5

-1.0

-0.5

0.0

V g (V)

0.5

1.0

1.5

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Doped vs. Schottky S/D DG Device Comparison Simulations I ON vs. I OFF CV/I Delay
Doped vs. Schottky S/D DG Device Comparison Simulations
I ON vs. I OFF
CV/I Delay
Source: King/Bokor,U.C. Berkeley
Ref: R. Shenoy, PhD Thesis, Stanford 2004
 Low barrier height metal contact required to achieve hhiigghh II OONN aanndd llooww CCVV//II ddeellaayy
 EExxtteennssiivvee rreesseeaarrcchh nneeeeddeedd ttoo ddeevveelloopp aa low barrier technology
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Outline

Junction/contact scaling issues Shallow junction technology Ohmic contacts Need to understand the physics of contacts resistance and develop technology to minmize it Technology to form contacts

technology to minmize it • Technology to form contacts Stanford University 31 Saraswat / EE311 /

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Conduction Mechanisms for Metal/Semiconductor Contacts

Low doping I Ef V φ B (a) Thermionic emission Medium doping Schottky (b) Thermionic-field
Low doping
I
Ef
V
φ B
(a) Thermionic emission Medium doping
Schottky
(b) Thermionic-field Heavy emission doping
(c) Field emission.!
Ohmic

Contact resistance strongly depends on barrier height ( φ B ) and doping density

depends on barrier height ( φ B ) and doping density Stanford University 32 Saraswat /

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Specific Contact Resistivity (ρ c ) n+ V = V bulk + 2V contact =
Specific Contact Resistivity (ρ c )
n+
V = V bulk + 2V contact = I (R bulk + 2R contact )
= !l
!V
R b u l k = dV b u l k
dI
A
!V
For a uniform current density
= ! c
R c o n t a c t = dV c o n t a c t
dI
A
•Specific contact resistivity and not contact resistance is the fundamental
parameter characterizing a contact
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Tunneling - Ohmic Contacts

 

F m

J sm F s
J
sm
F s
F m J sm F s When X d ≤ 2.5 – 5 nm, electrons can

When X d 2.5 – 5 nm, electrons can “tunnel” through the barrier. Required doping is:

Net semiconductor to metal current is

X d = 2 K q N ! o d " i N J sm d min = " 2 A * k K T q ! X # F o d s P( $ i E " ) ( 1 6.2 " Fm % 1019 ) d E cm & 3

2

for

X d = 2.5 nm

P(E) is the tunneling probability given by

# $

h " s m * '
h
"
s m *
'

P( E ) ~ exp % - 2! B N ( &

 

Current can be shown to be

[

J s m " exp # 2 xd 2 m # q V ) / h

]

Specific contact resistivity is of the form

ρ c primarily depends upon

" c = " c o exp '' & %

2 # B h $ s m *
2
# B
h
$
s m *

N ** ) ( ohm + cm 2

 
 

• the metal-semiconductor work function, φ Β ,

• doping density, N, in the semiconductor and

 
• the effective mass of the carrier, m*.

• the effective mass of the carrier, m*.

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Specific Contact Resistivity to P-type Si P-type Si Specific contact resistivity $ ' 2 "
Specific Contact Resistivity to P-type Si
P-type Si
Specific contact resistivity
$
'
2 " B
# s m *
! c = ! co exp &
) ohm * cm 2
&
)
qh
N
%
(
Specific contact resistivity, ρ c ↓
•As doping density N↑
•Barrier height φ B ↓
(S. Swirhun, PhD Thesis, Stanford Univ. 1987)
N A (cm -3 )
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Specific contact resistivity (Ω cm 2 )

Specific Contact Resistivity to N-type Dopants

N D (cm -3 ) Specific contact resistivity (Ω cm 2 )
N D (cm -3 )
Specific contact resistivity (Ω cm 2 )

Stanford University

•Similar trends for N-type Si

•For a given doping density contact resistance is higher for n-type Si than p-type.

•This can be attributed to the barrier height φ Bn > φ Bp

(S. Swirhun, PhD Thesis, Stanford Univ. 1987)

Bn > φ Bp (S. Swirhun, PhD Thesis, Stanford Univ. 1987) 36 Saraswat / EE311 /

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Solid Solubility of Dopants in Silicon •Problem is worse for p-type dopants (B), solid solubility
Solid Solubility of Dopants in Silicon
•Problem is worse for p-type dopants (B), solid solubility is lower
•Maximum concentration of dopants is limited by solid solubility
PROBLEM: Solid solubility of dopants does not scale !
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Barrier Height of Metals and Silicides to Si

Ideal Schottky model

Height of Metals and Silicides to Si Ideal Schottky model Φ m < χ Φ m

Φ m < χ

Φ m > χ

Practical barrier with Fermi level pinning

m > χ Practical barrier with Fermi level pinning φ BN + φ BP = E

φ BN + φ BP = E g

Barrier height to n- and p-type Si

( φ BN hollow symbols and φ BP solid

symbols)

. (Ref: S. Swirhun, PhD Thesis, Stanford Univ. 1987)
. (Ref: S. Swirhun, PhD Thesis, Stanford Univ. 1987)

φ BN 2E g /3

φ BP E g /3

φ B N ⇒ 2E g /3 φ B P ⇒ E g /3 Stanford University

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S/D Series Resistance [ Ω µ m] Strategy for Series Resistance Scaling 300 240 180

S/D Series Resistance [ Ω µ m]

Strategy for Series Resistance Scaling

300

240

180

120

60

0

Graded Junction L G = 53 nm Midgap Silicide R ov Box Profile R Midgap
Graded Junction
L G = 53 nm
Midgap Silicide
R
ov
Box Profile
R
Midgap Silicide
ext
R
Box Profile
dp
Low-Barrier
Silicide
R
csd
( Φ B = 0.2 eV)

Source/Drain Engineering

Source: Jason Woo, UCLA

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• • Potential Solutions for S/D Engineering y = 0 R dp & R csd Scaling
Potential Solutions for S/D Engineering y = 0 R dp & R csd Scaling (ρ
Potential Solutions for S/D Engineering
y = 0
R dp & R csd Scaling (ρ c ↓ )
Sidewall
Gate
⇒ Maximize N if ( R sh,dp ↓ ):
- Laser annealing
Silicide
x
- Elevated S/D
N
ov (y)
R
⇒ Minimize Φ B :
ov
R csd
R ext
- Dual low-barrier silicide
(ErSi (PtSi 2 ) for N(P)MOS)
R dp
R ov & R ext Scaling
N
ext (x)
⇒ Dopant Profile Control:
ultra-shallow highly-doped box-shaped SDE profile
(e.g., laser annealing, PAI + Laser Annealing)

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Bandgap Engineering From M. C. Ozturk et al. (NCSU), IEDM2002 • Si 1-x Ge x
Bandgap Engineering
From M. C. Ozturk et al. (NCSU), IEDM2002
Si 1-x Ge x S/D & germanosilicide contact
− Assuming metal Fermi level is pinned near midgap
− Similar barrier heights on n- or p-type material
− Smaller bandgap for Si 1-x Ge x
− Reduction of R csd with single contact metal
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Energy band diagram and charging character of interface states for the metal-dielectric interface

Ideal Schottky model: when a metal and

 

a

semiconductor or a dielectric form an

interface, there is no charge transfer

interface, there is no charge transfer

across the interface

A

semiconductor or dielectric surface has

gap states due to the broken surface bonds. These are spread across the energy gap.

The wave functions of electrons in the metal tail or decay into the semiconductor in the energy range where the conduction band of the metal overlaps the semiconductor band gap. These resulting states in the forbidden

gap are known as metal-induced gap states (MIGS) or simply intrinsic states.

 

Yeo, King, and Hu, J. Appl. Phys., 15 Dec. 2002

The energy level in the band gap at which the dominant character of the interface states changes from donorlike to acceptorlike is called the charge

 

neutrality level

E CNL

neutrality level E C N L Stanford University

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Fermi Level Pinning

Fermi Level Pinning Energy band structure of the Schottky contact and the electron energy dependence of

Energy band structure of the Schottky contact and the electron energy dependence of the charging character of the metal semiconductor interface states.

The metal work function is pinned near the charge neutrality level.

The charge neutrality level is defined as the energy level at which the character of the interface states changes from donor-like to acceptor-like.

The charge neutrality level is situated at around one-third of the band gap in the case of silicon ⇒ φ bn = 2E g /3 and φ bp = E g /3

⇒ φ b n = 2E g /3 and φ b p = E g /3

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Fermi-level de-pinning

Can we alter the charge neutrality level? It may be possible to do so by passivating the interface states. This can be done by modifying the interface. An issue of current research.

An example is selenium passivation of Si/Mg interface

 An example is selenium passivation of Si/Mg interface the reconstructed Si [001] surface Se-passivated Si

the reconstructed Si [001] surface

Se-passivated Si

[001] surface

Si [001] surface Se-passivated Si [001] surface Band diagram of Mg–Si contacts (a) without interface

Band diagram of Mg–Si contacts (a) without interface states and (b) with interface states.

(a) without interface states and (b) with interface states. I – V characteristics of Mg contacts

I V characteristics of Mg contacts to Si

M. Tao et al., APL, 2003

of Mg contacts to Si M. Tao et al ., APL , 2003 Stanford University 44

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Contact Resistance: 3D Model

Contact

Majority carrier continuity equation outside the contact is

! " J = #J # x x + #J # y y + #J #z z = 0

I I
I
I
I I
 

Metal

Metal Silicon

Silicon

Metal Silicon

Current density in the semiconductor is

J

= ! " E

= "#v

Combining these two equations we obtain

I Silicide Current
I
Silicide
Current

I

!

" #!V = 0

 

Total current over the contact area is

 

I

tot = " $

J # dA

Current flow in a contact is highly non-uniform Contact resistance does not scale with area

Solution of the above equations gives information about contact resistance. However, calculations are very involved.

Stanford University 45 Saraswat / EE311 / Shallow Junctions

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Transmission Line Contact Model

A simplified 1D solution of the contacts is

I ( x ) = I1 exp x # $ % ! " c Rs
I ( x ) = I1 exp
x
# $ %
!
" c Rs
( ' &
=
I1 exp ( ! x l t )
l t = ! c Rs
l t is the characteristic length of the
transmission line - the distance at which 63%
of the current has transferred into the metal.
at which 63% of the current has transferred into the metal. Stanford University 46 Saraswat /
at which 63% of the current has transferred into the metal. Stanford University 46 Saraswat /

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Measurement of Contact Resistance and Specific Contact Resistivity (ρ c )

Resistance and Specific Contact Resistivity ( ρ c ) R f = V f / I

R f = V f / I = Rs w " c coth(d / lt )

= V f / I = R s w " c coth ( d / l

For a very large value of lt or for d << l t

R f ! wd " c = w sinh(d Rs " c / lt )
R f ! wd " c
= w sinh(d
Rs " c / lt )

Re = Ve / I

R f gives reasonable assessment of the source/drain contact resistance including the resistance of the semiconductor under the contact

Specific contact resistivity, ρ c , can be calculated by measuring I, V f or V e

Measurement of R f or R e is not straightforward and needs specialized test structures

is not straightforward and needs specialized test structures Stanford University 47 Saraswat / EE311 / Shallow

Stanford University

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Test Structure to Measure Contact Resistance:

Transmission Line Tap Resistor

Measure Contact Resistance: Transmission Line Tap Resistor V 2 4 = V f + IR S

V 2 4 = V f + IR S i + V f

R t = V 2 4 = 2 R f + R s l s w

I

R f = V f / I 1 =

R s ! c coth d / l t (
R s ! c coth d / l t
(

w

I R f = V f / I 1 = R s ! c coth d

Stanford University

R f

I 1 = R s ! c coth d / l t ( w Stanford University

) is a very small number

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Test Structure to Measure Contact Resistance:

Cross-bridge Kelvin Structure

1 2 l l 3 4 N+ Contact Metal Diffusion
1
2
l
l
3
4
N+ Contact Metal Diffusion
. Metal l l N+ Diffusion Vk . Rk = Vk I = V14 =
.
Metal
l
l
N+ Diffusion Vk
.
Rk = Vk
I
= V14
=
I23
! l2 c
.
I

Cross-bridge Kelvin structure used to measure an average contact resistance, called R K in the figure

an average contact resistance, called R K in the figure Stanford University 49 Saraswat / EE311

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Error in Specific Contact Resistivity due to 1-D Modeling

1-D model Specific contact resistivity ( ρ c )

1-D model Specific contact resistivity ( ρ c ) 2-D model C o n t a

2-D model

Contact resistance

model C o n t a c t r e s i s t a n

Specific contact resistivity (ρ c ) is a fundamental property of the interface and should be independent of contact area 1-D models overestimate the contact resistance (R c ) 2-D models give more accurate results and should be used

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give more accurate results and should be used Stanford University 50 Saraswat / EE311 / Shallow

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Outline

Junction/contact scaling issues Shallow junction technology Ohmic contacts Technology to form contacts

• Ohmic contacts • Technology to form contacts Stanford University 51 Saraswat / EE311 / Shallow

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Aluminum Contacts to Si Aluminum Oxide Oxide N+ Silicon • Silicon has high solubility in
Aluminum Contacts to Si
Aluminum Oxide
Oxide
N+ Silicon
• Silicon has high solubility in Al ~ 0.5% at 450ºC
• Silicon has high diffusivity in Al
• Si diffuses into Al. Voids form in Si which fill
with Al: “Spiking” occurs.
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Al/Si Alloy Contacts to Si

Al/Si Alloy Contacts to Si By adding 1-2% Si in Al to satisfy solubility requirement junction

By adding 1-2% Si in Al to satisfy solubility requirement junction spiking is minimmized

solubility requirement junction spiking is minimmized But Si precipitation can occur when cool down to room

But Si precipitation can occur when cool down to room temperature bad contacts to N + Si

Al-Si phase diagram

⇒ bad contacts to N + Si Al-Si phase diagram Stanford University 53 Saraswat / EE311
⇒ bad contacts to N + Si Al-Si phase diagram Stanford University 53 Saraswat / EE311

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Silicide Contacts Barrier Aluminum Oxide TiW Oxide TiN N + TiSi2 Silicon Contact PtSi •Silicides
Silicide Contacts
Barrier
Aluminum Oxide
TiW
Oxide TiN
N +
TiSi2
Silicon
Contact
PtSi
•Silicides like PtSi, TiSi 2 make excellent contacts to Si
•However, they react with Al
• A barrier like TiN or TiW prevents this reaction
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Silicide Contacts Similar methods are used for other silicides Stanford University 55 Saraswat / EE311
Silicide Contacts
Similar methods are used for other silicides
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Interfacial reactions

Saraswat / EE311 / Shallow Junctions Interfacial reactions Integrity of ohmic contacts due to a physical

Integrity of ohmic contacts due to a physical barrier between Al and silicide

contacts due to a physical barrier between Al and silicide Schottky barrier reduction due to Al

Schottky barrier reduction due to Al reaction with PtSi

T (°C)
T (°C)

Φ B (eV)

reduction due to Al reaction with PtSi T (°C) Φ B (eV) Stanford University 56 Saraswat

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Barriers Al/PtSi/Si Al/TiSi 2 /Si Al/NiSi/Si Al/CoSi 2 /Si Al/Ti/PtSi/Si Al/Ti 30 W 70 /PtSi/Si

Barriers

Al/PtSi/Si Al/TiSi 2 /Si Al/NiSi/Si Al/CoSi 2 /Si Al/Ti/PtSi/Si Al/Ti 30 W 70 /PtSi/Si Al/TiN/TiSi

Al/PtSi/Si

Al/TiSi2/Si

Al/NiSi/Si

Al/CoSi2/Si

Al/Ti/PtSi/Si

Al/Ti30W70/PtSi/Si

Al/TiN/TiSi2/Si

Compound (Al3Ni, formation Si)

Compound Al9Co2, formation Si)

Compound (Al3Ti) formation

(Al2Pt, Al12W Diffusion at 500˚C)

Compound (AlN, Al3Ti) formation

Structure

Temperature Failure (˚C)

Failure (Reaction Mechanism products)

350

400

400

400

450

500

550

Compound (Al2Pt, formation Si)

(Al5Ti7Si12, Diffusion Si at 550˚C)

Silicides react with Al at T < 400°C A barrier like TiN or TiW prevents this reaction upto T > 500°C

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Outline

Junction/contact scaling issues Shallow junction technology Ohmic contacts Technology to form contacts

• Ohmic contacts • Technology to form contacts Stanford University 58 Saraswat / EE311 / Shallow

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