ARM Instruction Set

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Name: B.Tanmayi Roll Number:AM.EN.U4ECE17013
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Load Store Instructions

Register Indirect Addressing
• Syntax:
– LDR {<condition>} {<size>} Rd, <Rn>

• STR {<condition>} {<size>} Rd, <Rn>

Variables
Rd R1 =
Rn R2 = 0x4000_0008
Memory Address 0x4000_0008
Memory Content 0x1516_7879

1. LDR R1, [R2] = 0x 4000_0008

3 3 2 2 2 22 22 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 65 43 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
1 1 1 0 0 1 0 1 1 0 0 1 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0
Memory Address Memory Content
0x4000_0000 0x1234_5678
0x4000_0004 0xAABB_CCDD
0x4000_0008 0x1516_7879
0x4000_000C 0x55AA_00FF
0x4000_0010 0xCCDD_EEFF
DST DST Value
Register
R1 0x1516_787
9

Base Register Base Address

R2 0x4000_0008
Before Execution
2. STR R1, [R2] = 0x 4000_0004
3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
1 1 1 0 0 1 0 1 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0
Memory Address Memory Content
0x4000_0000 0x1234_5678
0x4000_0004 0xAABB_CCDD
0x4000_0008 0x1516_7879
0x4000_000C 0x55AA_00FF
0x4000_0010 0xCCDD_EEFF
Memory Content
Address
0x 0x4000_000
4

SRC Register SRC Content

R1 0xAABB_CCDD
Before Execution

Variables
Rd
Rn 0x 4000_0004
Memory Address 0x 4000_0004
Memory Content 0xAABB_CCDD

3. LDRH R1, [R2] = 0x 4000_0004

3 3 2 2 2 22 22 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 65 43 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
1 1 1 0 0 0 0 1 1 0 0 1 0 0 1 0 0 0 0 1 0 0 0 0 1 0 1 1 0 0 0 0
Memory Address Memory Content
0x 4000_0004 0xAABB_CCDD
0x 0x
0x 0x
0x 0x
0x 0x
DST DST Value
Register
R1 0x0000CCDD

Base Register Base Address

R2 0x4000_0004
Before Execution
4. STRH R1, [R2] = 0x 4000_0004
3 3 2 2 2 22 22 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 65 43 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
1 1 1 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 1 1 0 0 0 0
Memory Address Memory Content
0X4000_0004 0XAABB_CCDD

Memory Content
Address
0XAABB_CC
0X4000_000 DD
4

SRC Register SRC Content

R1 0x0000_CCDD
Before Execution

Variables
Rd
Rn
Memory Address
Memory Content
5. LDRSH R1, [R2] = 0x
3 3 2 2 2 22 22 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 65 43 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
1 1 1 0 0 0 0 1 1 0 0 1 0 0 1 0 0 0 0 1 0 0 0 0 1 1 1 1 0 0 0 0
Memory Address Memory Content

0x4000_0010 0xCCDD_EEFF
DST DST Value
Register
R1 0xEEFF
 Base Register Base Address
R2 0x4000_0010
Before Execution

6. STRSH R1, [R2] = 0x

3 3 2 2 2 22 22 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 65 43 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
1 1 1 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 1 1 1 0 0 0 0
Memory Address Memory Content

0x4000_0010

Memory Content
Addr
0x1111_EEF
0x4000_001 F
0

SRC Register SRC Content

R1 0xCCDD_EEFF
Before Execution

Variables
Rd
Rn
Memory Address
Memory Content

7. LDRB R1, [R2] = 0x

3 3 2 2 2 22 22 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 65 43 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
1 1 1 0 0 0 0 1 1 0 0 1 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 1 0 0 0 0
Memory Address Memory Content
0x4000_0010 0xFFEE_2233
0x 0x
0x 0x
0x 0x
0x 0x
 DST DST Value
Register
R1 0x0000_003
3

Base Register Base Address

R2 0x4000_0010
Before Execution

8. STRB R1, [R2] = 0x

3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
1 1 1 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 1 0 0 0 0
Memory Address Memory Content
0x4000_4004 0x4455_6677

Memory Content
Address
0x4000_400 0x0000_007
4 7

SRC Register SRC Content

R1 0x4455_6677
Before Execution

Variables
Rd
Rn
Memory Address
Memory Content
9. LDRSB R1, [R2] = 0x
3 3 2 2 2 22 22 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 65 43 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
1 1 1 0 0 0 0 1 1 0 0 1 0 0 1 0 0 0 0 1 0 0 0 0 1 1 0 1 0 0 0 0
Memory Address Memory Content
0x4000_4004 0xFFFF_6677

DST DST Value

Register
R1 0x1111_117
7

Base Register Base Address

R2 0x4000_4004
Before Execution

10. STRSB R1, [R2] = 0x

3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
1 1 1 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 1 0 1 0 0 0 0
Memory Address Memory Content
0x4000_4004 0xFFFF_CCCC

Memory Content
Address
0x4000_400 0x1111_11C
4 C

SRC Register SRC Content

R1 0x4000_4004
Before Execution
Register Relative Addressing
• Syntax:
– LDR {<condition>} {<size>} Rd, <Rn>, #offset, !

• STR {<condition>} {<size>} Rd, <Rn>, #offset, !

• Variables
Rd
Rn
Memory Address
Memory Content

11. LDR R1, [R2, #4] = 0x -- Pre-increment without write back

3 3 2 2 2 22 22 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 65 43 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

Memory Address Memory Content

DST DST Value

Register
R1 0x

Base Register Base Address

R2
Before Execution
 Base Address Offset Effective Address = Base Address + offset
0x 0x

12. STR R1, [R2, #-4] = 0x -- Pre-decrement without write back

3 3 2 2 2 22 22 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 65 43 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

Memory Address Memory Content

Memory Content
Addr
0x 0x

SRC Register SRC Content

R1
Before Execution

Base Address Offset Effective Address = Base Address + offset

0x 0x

• Variables
Rd
Rn
Memory Address
Memory Content
13. LDR R1, [R2, #4]! = 0x -- Pre-increment with write back
3 3 2 2 2 22 22 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 65 43 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

Memory Address Memory Content

DST DST Value

Register
R1 0x

Base Register Base Address

R2
Before Execution

Base Address Offset Effective Address = Base Address + offset

0x 0x

14. STR R1, [R2, #-4]! = 0x -- Pre-decrement with write back

3 3 2 2 2 22 22 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 65 43 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

Memory Address Memory Content

Memory Content
Addr
0x 0x

SRC Register SRC Content

R1
Before Execution

Base Address Offset Effective Address = Base Address + offset

0x 0x

• Variables
Rd
Rn
Memory Address
Memory Content

15. LDR R1, [R2], #4 = 0x -- Post-increment with default write back

3 3 2 2 2 22 22 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 65 43 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
Memory Address Memory Content

DST DST Value

Register
R1 0x

Base Register Base Address

R2
Before Execution
 Base Address Offset Effective Address = Base Address + offset
0x 0x

16. STR R1, [R2], #-4 = 0x -- Post-decrement with default write back
3 3 2 2 2 22 22 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 65 43 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

Memory Address Memory Content

Memory Content
Addr
0x 0x

SRC Register SRC Content

R1
Before Execution

Base Address Offset Effective Address = Base Address + offset

0x 0x

In the same manner, other instructions like, LDRB, STRB, LDRH, STRH,
LDRSB, STRSB, LDRSH & STRSH could be constructed.
Based Indexed Addressing
• Syntax:
– LDR {<condition>} {<size>} Rd, <Rn>, <Rm>, !

• STR {<condition>} {<size>} Rd, <Rn>, <Rm>, !

• Variables
Rd
Rn
Rm
Memory Address
Memory Content

17. LDR R1, [R2, R3] = 0x -- Pre-increment without write back

3 3 2 2 2 22 22 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 65 43 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

Memory Address Memory Content

DST DST Value

Register
R1 0x

Base Register Base Address

R2
Before Execution

Base Address Index Effective Address = Base Address + index

0x 0x

18. STR R1, [R2, R3] = 0x -- Pre-decrement without write back

3 3 2 2 2 22 22 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 65 43 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
 Memory Address Memory Content

Memory Content
Addr
0x 0x

SRC Register SRC Content

R1
Before Execution

Base Address Index Effective Address = Base Address + index

0x 0x

• Variables
Rd
Rn
Rm
Memory Address
Memory Content

19. LDR R1, [R2, R3]! = 0x -- Pre-increment with write back

3 3 2 2 2 22 22 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 65 43 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

Memory Address Memory Content

 DST DST Value
Register
R1 0x

Base Register Base Address

R2
Before Execution

Base Address Index Effective Address = Base Address + index

0x 0x

20. STR R1, [R2, R3]! = 0x -- Pre-decrement with write back

3 3 2 2 2 22 22 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 65 43 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

Memory Address Memory Content

Memory Content
Addr
0x 0x

SRC Register SRC Content

R1
Before Execution

Base Address Index Effective Address = Base Address + index

0x 0x
 • Variables
Rd
Rn
Rm
Memory Address
Memory Content

21. LDR R1, [R2], R3 = 0x -- Post-increment with write back

3 3 2 2 2 22 22 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 65 43 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

Memory Address Memory Content

DST DST Value

Register
R1 0x

Base Register Base Address

R2
Before Execution

Base Address Index Effective Address = Base Address + index

0x 0x
22. STR R1, [R2], R3 = 0x -- Post-decrement with write back
3 3 2 2 2 22 22 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 65 43 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

Memory Address Memory Content

Memory Content
Addr
0x 0x

SRC Register SRC Content

R1
Before Execution

Base Address Index Effective Address = Base Address + index

0x 0x

In the same manner, other instructions like, LDRB, STRB, LDRH, STRH,
LDRSB, STRSB, LDRSH & STRSH could be constructed.

Based with scaling addressing

• Syntax:
– LDR {<condition>} {<size>} Rd, <Rn>, <Rm>, <SHIFT Method> !

• STR {<condition>} {<size>} Rd, <Rn>, <Rm>, <SHIFT Method>!

• Variables
Rd
Rn
 Rm
Memory Address
Memory Content

23. LDR R1, [R2, R3, LSL, #2] = 0x -- Pre-increment without write back
3 3 2 2 2 22 22 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 65 43 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

Memory Address Memory Content

DST DST Value

Register
R1 0x

Base Register Base Address

R2
Before Execution

Base Address Index Effective Address = Base Address + index

0x 0x
After Shifting
0x

24. STR R1, [R2, R3, LSL, #2] = 0x -- Pre-decrement without write back
3 3 2 2 2 22 22 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 65 43 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

Memory Address Memory Content

Memory Content
Addr
0x 0x
 SRC Register SRC Content
R1
Before Execution

Base Address Index Effective Address = Base Address + index

0x 0x
After shifting

• Variables
Rd
Rn
Rm
Memory Address
Memory Content

25. LDR R1, [R2, R3, LSR, #3]! = 0x -- Pre-increment with write back
3 3 2 2 2 22 22 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 65 43 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
Memory Address Memory Content

DST DST Value

Register
R1 0x

Base Register Base Address

R2
Before Execution

Base Address Index Effective Address = Base Address + index

0x 0x
 After Shifting
0x

26. STR R1, [R2, R3, LSR, #3]! = 0x - Pre-decrement with write back
3 3 2 2 2 22 22 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 65 43 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

Memory Address Memory Content

Memory Content
Addr
0x 0x

SRC Register SRC Content

R1
Before Execution

Base Address Index Effective Address = Base Address + index

0x 0x
After shifting

• Variables
Rd
 Rn
Rm
Memory Address
Memory Content

27. LDR R1, [R2], R3, ASR #2 = 0x -- Post-increment with write back
3 3 2 2 2 22 22 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 65 43 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

Memory Address Memory Content

DST DST Value

Register
R1 0x

Base Register Base Address

R2
Before Execution

Base Address Index Effective Address = Base Address + index

0x 0x
After Shifting
0x

28. STR R1, [R2], R3, ASR, #4 = 0x -- Post-decrement with write back
3 3 2 2 2 22 22 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 65 43 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

Memory Address Memory Content

Memory Content
Addr
0x 0x
 SRC Register SRC Content
R1
Before Execution

Base Address Index Effective Address = Base Address + index

0x 0x
After shifting

• Variables
Rd
Rn
Rm
Memory Address
Memory Content

29. LDRSH R1, [R2], R3, ASR #2 = 0x -- Post-increment with write back
3 3 2 2 2 22 22 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 65 43 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
Memory Address Memory Content

DST DST Value

Register
R1 0x

Base Register Base Address

 R2
Before Execution

Base Address Index Effective Address = Base Address + index

0x 0x
After Shifting
0x

30. STRSH R1, [R2], R3, ASR, #4 = 0x -- Post-decrement with write back
3 3 2 2 2 22 22 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 65 43 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

Memory Address Memory Content

Memory Content
Addr
0x 0x

SRC Register SRC Content

R1
Before Execution

Base Address Index Effective Address = Base Address + index

0x 0x
After shifting
Data Processing Instructions
• Logical AND
Syntax:
– AND {<condition>} {<S>} Rd, <Rn>, <Operand 2>

<Operand2> 1. <#Immediate Value>

2. <Rm>, <SHIFT Method> <Shift Length>
3. <Rm>, <SHIFT Method> <Rs>

• Immediate Shift
31. AND R1, R2, #100, 4 = 0x

Variables Variables
Rd Rs/ Shift Length
Rn Immediate Value
Rm Shift Method

3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

ROR N times

3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Variables Value
Rn
 Operand2
Rd

• Register Shift
32. AND R1, R2, R3, LSL, #2 = 0x
Variables Variables
Rd Rs/ Shift Length
Rn Immediate Value
Rm Shift Method

3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

Shift Rm

3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

Variables Value
Rn
Operand2
Rd

• Register Scaled Shift

33. AND R1, R2, R3, LSL, R4 = 0x
Variables Variables
Rd Rs/ Shift Length
Rn Immediate Value
Rm Shift Method

3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
 Shift Rm

3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

Variables Value
Rn
Operand2
Rd

• Logical EOR

• Immediate Shift
34. EOR R1, R2, #120, 4 = 0x
Variables Variables
Rd Rs/ Shift Length
Rn Immediate Value
Rm Shift Method

3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

ROR N times

3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
 Variables Value
Rn
Operand2
Rd

• Register Shift
35. EOR R1, R2, R3, LSR, #4 = 0x
Variables Variables
Rd Rs/ Shift Length
Rn Immediate Value
Rm Shift Method

3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

Shift Rm

3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

Variables Value
Rn
Operand2
Rd

• Register Scaled Shift

36. EOR R1, R2, R3, ASR, R4 = 0x
 Variables Variables
Rd Rs/ Shift Length
Rn Immediate Value
Rm Shift Method

3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

Shift Rm

3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

Variables Value
Rn
Operand2
Rd

• Arithmetic Subtraction

• Immediate Shift
37. SUB R1, R2, #120, 4 = 0x
Variables Variables
Rd Rs/ Shift Length
Rn Immediate Value
Rm Shift Method

3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

ROR N times

3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
 Variables Value
Rn
Operand2
Rd

• Register Shift
38. SUB R1, R2, R3, ROR, #6 = 0x
Variables Variables
Rd Rs/ Shift Length
Rn Immediate Value
Rm Shift Method

3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

Shift Rm

3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

Variables Value
Rn
Operand2
 Rd

• Register Scaled Shift

39. SUB R1, R2, R3, LSR, R4 = 0x
Variables Variables
Rd Rs/ Shift Length
Rn Immediate Value
Rm Shift Method

3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

Shift Rm

3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

Variables Value
Rn
Operand2
Rd

• Arithmetic Reverse Subtraction

• Immediate Shift
40. RSB R1, R2, #201, 4 = 0x
Variables Variables
Rd Rs/ Shift Length
Rn Immediate Value
Rm Shift Method

3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
ROR N times

3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Variables Value
Rn
Operand2
Rd

• Register Shift
41. RSB R1, R2, R3, ASR, #4 = 0x
Variables Variables
Rd Rs/ Shift Length
Rn Immediate Value
Rm Shift Method

3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

Shift Rm

3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
Variables Value
Rn
Operand2
Rd

• Register Scaled Shift

42. RSB R1, R2, R3, LSL, R4 = 0x
Variables Variables
Rd Rs/ Shift Length
Rn Immediate Value
Rm Shift Method

3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

Shift Rm

3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

Variables Value
Rn
Operand2
Rd
 • Arithmetic Addition

• Immediate Shift
43. ADD R1, R2, #120, 4 = 0x
Variables Variables
Rd Rs/ Shift Length
Rn Immediate Value
Rm Shift Method

3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

ROR N times

3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Variables Value
Rn
Operand2
Rd

• Register Shift
ADD R1, R2, R3, ROR, #6 = 0x
Variables Variables
Rd Rs/ Shift Length
Rn Immediate Value
Rm Shift Method

3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

Shift Rm

3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

Variables Value
Rn
Operand2
Rd

• Register Scaled Shift

44. ADD R1, R2, R3, LSR, R4 = 0x
Variables Variables
Rd Rs/ Shift Length
Rn Immediate Value
Rm Shift Method

3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

Shift Rm

3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
 Variables Value
Rn
Operand2
Rd

• Arithmetic Addition with carry

• Immediate Shift
45. ADC R1, R2, #120, 4 = 0x
Variables Variables
Rd Rs/ Shift Length
Rn Immediate Value
Rm Shift Method

3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

ROR N times

3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Variables Value
Rn
Operand2
 Rd

• Register Shift
46. ADC R1, R2, R3, ROR, #6 = 0x
Variables Variables
Rd Rs/ Shift Length
Rn Immediate Value
Rm Shift Method

3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

Shift Rm

3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

Variables Value
Rn
Operand2
Rd

• Register Scaled Shift

47. ADC R1, R2, R3, LSR, R4 = 0x
Variables Variables
Rd Rs/ Shift Length
Rn Immediate Value
Rm Shift Method

3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
Shift Rm

3 3 2 2 2 22 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 65 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

Variables Value
Rn
Operand2
Rd

• Arithmetic Subtraction with carry

• Immediate Shift
48. SBC R1, R2, #120, 4 = 0x
Variables Variables
Rd Rs/ Shift Length
Rn Immediate Value
Rm Shift Method

3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

ROR N times

3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
 Variables Value
Rn
Operand2
Rd

• Register Shift
49. SBC R1, R2, R3, ROR, #6 = 0x
Variables Variables
Rd Rs/ Shift Length
Rn Immediate Value
Rm Shift Method

3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

Shift Rm

3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

Variables Value
Rn
Operand2
Rd

• Register Scaled Shift

50. SBC R1, R2, R3, LSR, R4 = 0x
Variables Variables
Rd Rs/ Shift Length
Rn Immediate Value
 Rm Shift Method

3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

Shift Rm

3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

Variables Value
Rn
Operand2
Rd

• Arithmetic Reverse Subtract with carry

• Immediate Shift
51. RSC R1, R2, #120, 4 = 0x
Variables Variables
Rd Rs/ Shift Length
Rn Immediate Value
Rm Shift Method

3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
ROR N times

3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Variables Value
Rn
Operand2
Rd

• Register Shift
52. RSC R1, R2, R3, ROR, #6 = 0x
Variables Variables
Rd Rs/ Shift Length
Rn Immediate Value
Rm Shift Method

3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

Shift Rm

3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
Variables Value
Rn
Operand2
Rd

• Register Scaled Shift

53. RSC R1, R2, R3, LSR, R4 = 0x
Variables Variables
Rd Rs/ Shift Length
Rn Immediate Value
Rm Shift Method

3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

Shift Rm

3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

Variables Value
Rn
Operand2
Rd
9, Test Bit (TST)
• Syntax: TST (instructions which do not produce a result) <Opcode> {Cond} Rn, <Op2>

• Immediate Shift
54. TST R1, R2, #120, 4 = 0x
Variables Variables
Rd Rs/ Shift Length
Rn Immediate Value
Rm Shift Method

3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

ROR N times

3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Variables Value
Rn
Operand2
Rd

• Register Shift
55. TST R1, R2, ROR, #6 = 0x
Variables Variables
Rd Rs/ Shift Length
Rn Immediate Value
Rm Shift Method

3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

Shift Rm

3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

Variables Value
Rn
Operand2
Rd

• Register Scaled Shift

56. TST R1, R2, LSR, R4 = 0x
Variables Variables
Rd Rs/ Shift Length
Rn Immediate Value
Rm Shift Method

3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

Shift Rm

3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
 Variables Value
Rn
Operand2
Rd

• Test Equivalence (TEQ)

• Syntax:
TEQ (instructions which do not produce a result) <Opcode> {Cond} Rn, <Op2>

• Immediate Shift
57. TEQ R1, R2, #120, 4 = 0x
Variables Variables
Rd Rs/ Shift Length
Rn Immediate Value
Rm Shift Method

3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

ROR N times

3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Variables Value
 Rn
Operand2
Rd

• Register Shift
58. TEQ R1, R2, ROR, #6 = 0x
Variables Variables
Rd Rs/ Shift Length
Rn Immediate Value
Rm Shift Method

3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

Shift Rm

3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

Variables Value
Rn
Operand2
Rd

• Register Scaled Shift

59. TEQ R1, R2, LSR, R4 = 0x

Variables Variables
Rd Rs/ Shift Length
Rn Immediate Value
Rm Shift Method
 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

Shift Rm

3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

Variables Value
Rn
Operand2
Rd

• Compare (CMP)
• Syntax: CMP (instructions which do not produce a result) <Opcode> {Cond} Rn, <Op2>

• Immediate Shift
60. CMP R1, R2, #120, 4 = 0x
Variables Variables
Rd Rs/ Shift Length
Rn Immediate Value
Rm Shift Method

3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

ROR N times

3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
 Variables Value
Rn
Operand2
Rd

• Register Shift
61. CMP R1, R2, ROR, #6 = 0x
Variables Variables
Rd Rs/ Shift Length
Rn Immediate Value
Rm Shift Method

3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

Shift Rm

3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

Variables Value
Rn
Operand2
Rd
 • Register Scaled Shift
62. CMP R1, R2, LSR, R4 = 0x

Variables Variables
Rd Rs/ Shift Length
Rn Immediate Value
Rm Shift Method

3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

Shift Rm

3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

Variables Value
Rn
Operand2
Rd

• Compare Negated (CMN)

• Syntax:
CMN (instructions which do not produce a result) <Opcode> {Cond} Rn, <Op2>

• Immediate Shift
63. CMN R1, R2, #120, 4 = 0x
Variables Variables
Rd Rs/ Shift Length
Rn Immediate Value
Rm Shift Method
 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

ROR N times

3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Variables Value
Rn
Operand2
Rd

• Register Shift
64. CMN R1, R2, ROR, #6 = 0x
Variables Variables
Rd Rs/ Shift Length
Rn Immediate Value
Rm Shift Method

3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

Shift Rm

3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
 Variables Value
Rn
Operand2
Rd

• Register Scaled Shift

65. CMN R1, R2, LSR, R4 = 0x
Variables Variables
Rd Rs/ Shift Length
Rn Immediate Value
Rm Shift Method

3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

Shift Rm

3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

Variables Value
Rn
Operand2
Rd

• Logical OR
Syntax:
– ORR {<condition>} {<S>} Rd, <Rn>, <Operand 2>
 • Immediate Shift
66. ORR R1, R2, #100, 4 = 0x

Variables Variables
Rd Rs/ Shift Length
Rn Immediate Value
Rm Shift Method

3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

ROR N times

3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Variables Value
Rn
Operand2
Rd

• Register Shift
67. ORR R1, R2, R3, LSL, #2 = 0x
Variables Variables
Rd Rs/ Shift Length
Rn Immediate Value
Rm Shift Method
3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

Shift Rm

3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

Variables Value
Rn
Operand2
Rd

• Register Scaled Shift

68. ORR R1, R2, LSR, R4 = 0x
Variables Variables
Rd Rs/ Shift Length
Rn Immediate Value
Rm Shift Method

3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

Shift Rm

3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

Variables Value
 Rn
Operand2
Rd

• Move (MOV)
• Syntax: MOV (single operand instructions.)<opcode>{cond}{S} Rd,<Op2>

• Immediate Shift
69. MOV R1, R2, #120, 4 = 0x
Variables Variables
Rd Rs/ Shift Length
Rn Immediate Value
Rm Shift Method

3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

ROR N times

3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Variables Value
Rn
Operand2
Rd

• Register Shift
70. MOV R1, R2, ROR, #6 = 0x
Variables Variables
Rd Rs/ Shift Length
Rn Immediate Value
Rm Shift Method

3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

Shift Rm

3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

Variables Value
Rn
Operand2
Rd

• Register Scaled Shift

71. MOV R1, R2, LSR, R4 = 0x
Variables Variables
Rd Rs/ Shift Length
Rn Immediate Value
Rm Shift Method

3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

Shift Rm

3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
 Variables Value
Rn
Operand2
Rd

• Move Negated (MVN)

• Syntax: MVN (single operand instructions.)<opcode>{cond}{S} Rd,<Op2>
• Immediate Shift
72. MVN R1, R2, #120, 4 = 0x
Variables Variables
Rd Rs/ Shift Length
Rn Immediate Value
Rm Shift Method

3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

ROR N times

3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
 Variables Value
Rn
Operand2
Rd

• Register Shift
73. MVN R1, R2, ROR, #6 = 0x
Variables Variables
Rd Rs/ Shift Length
Rn Immediate Value
Rm Shift Method

3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

Shift Rm

3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

Variables Value
Rn
Operand2
Rd

• Register Scaled Shift

74. MVN R1, R2, LSR, R4 = 0x
Variables Variables
Rd Rs/ Shift Length
Rn Immediate Value
Rm Shift Method
 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

Shift Rm

3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

Variables Value
Rn
Operand2
Rd

• Bit Clear (BIC)

• Syntax: BIC<opcode>{cond}{S} Rd,Rn,<Op2>

• Immediate Shift
75. BIC R1, R2, #120, 4 = 0x
Variables Variables
Rd Rs/ Shift Length
Rn Immediate Value
Rm Shift Method

3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

ROR N times

3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
 Variables Value
Rn
Operand2
Rd

• Register Shift
76. BIC R1, R2, R3, LSL, #6 = 0x
Variables Variables
Rd Rs/ Shift Length
Rn Immediate Value
Rm Shift Method

3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

Shift Rm

3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

Variables Value
Rn
Operand2
Rd
 • Register Scaled Shift
77. BIC R1, R2, R3, LSL, R4 = 0x
Variables Variables
Rd Rs/ Shift Length
Rn Immediate Value
Rm Shift Method

3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

Shift Rm

3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

Variables Value
Rn
Operand2
Rd

Date: Signature of the Faculty