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Microcontroller
Programmer’s View
– Memory Organization
– Register Set
– Instruction Set
Program Memory
After reset, the MCS-51 starts fetching instructions
from 0000H.
This can be either on-chip or external depending on
the value of the EA input pin.
• We connect the EA pin to Vcc to indicate that the
program code is stored in the microcontroller’s
on-chip ROM.
• To indicate that the program code is stored in
external ROM, EA pin must be connected to
GND.
To use external program memory, All we have to do
is to connect the EA pin to ground and connect the
(microcontroller) chip to external ROM containing
the program code
Since the PC (program counter) of the 8051 is 16-bit, it is
capable of accessing up to 64K bytes of program code.
In the 8051, port 0 and port 2 provide the 16-bit address
to access external memory.
Of these two ports, PO provides the lower 8 bit addresses
AO – A7, and P2 provides the upper 8 bit addresses A8 –
A15.
More importantly, PO is also used to provide the 8-bit
data bus DO – D7. In other words, pins PO.O – P0.7 are
used for both the address and data paths. This is called
address/data multiplexing in chip design
How do we know when P0 is used for the data path
and when it is used for the address path?
This is the job of the ALE (address latch enable) pin.
When ALE = 0 the 8051 uses P0 for the data path,
and when ALE = 1, it uses it for the address path.
To extract the addresses from the P0 pins we connect
P0 to a latch and use the ALE pin to latch the
address
Program Memory(External Access Cycle)
Port 0 acts as a multiplexed address/data bus sending
the low byte of the program counter (PCL) as an
address(through latch)
Port 2 sends the program counter high byte of the
program counter (PCH) as an address directly to the
external memory.
The signal ALE allows an external latch to store the
PCL byte while the multiplexed bus is made ready to
receive the code byte from the external memory.
Port 0 then switches function and becomes the data
bus receiving the byte from memory
Memory Organisation of MCS-51
Data Memory
The 8051 has 256 bytes of RAM on-chip.
– The lower 128 bytes are intended for internal data storage.
– The upper 128 bytes are the Special Function Registers (SFRs).
Data Memory
The lowest 32 bytes of the on-chip RAM form
4 banks of 8 registers each.
– Only one of these banks can be active at
any time.
– Bank is chosen by setting 2 bits in PSW
– Default bank (at power up) is Bank 0
Data Memory
The next 16 bytes – locations
20H to 2FH – form a block that
can be addressed as either bytes
or individual bits.
Data Memory
SFRs
The upper 128 bytes of the on-chip RAM are used to
house Special Function Registers.
In reality, only about 21 of these bytes are actually used.
(The others are reserved for future versions of the 8051.)
– These are registers associated with important
functions in the operation of the MCS-51.
– Some of these registers are bit-addressable as well
as byte-addressable.
The address of bit 0 of the register will be the same as
the address of the register.
Memory Organisation of MCS-51
SFRs
SFRs in 8051
Accumulator
Almost all the data transfer& arithmetic instructions
involve accumulator
Can be referred to in several ways:
– Implicitly in opcodes.
– Referred to as ACC (or A) for instructions that
allow specifying a register.
– By its SFR address 0E0H.
Bit addressable.
– ACC.2 means bit 2 of the ACC register
SFRs in 8051
The B Register
The B register is not frequently used, when used it acts as
a temporary register, much like a 9th R register.
Used Specifically by two instructions
– mul AB
– div AB
Here, B register holds the second operand initially and
will hold part of the result after the execution of
instruction
– It houses upper 8 bits of the multiplication result
– It houses Remainder in case of division.
Can also be accessed through its SFR address of 0F0H.
Bit addressable
SFRs in 8051
Bit
Function
position
CY PSW.7 Carry Flag
AC PSW.6 Auxiliary Carry Flag, for BCD Operations
F0 PSW.5 Flag 0. Available to the user for general purposes.
RS1 PSW.4 Register bank select bits. Set by software to
RS0 PSW.3 determine which register bank is being used.
OV PSW.2 Overflow Flag
- PSW.1 Reserved
P PSW.0 Parity Flag
SFRs in 8051
Control Registers
IP – Interrupt Priority
IE – Interrupt Enable
TMOD – Timer Mode
TCON – Timer Control
T2CON – Timer 2 Control (8052)
SCON – Serial Port Control
PCON – Power Control
Program Counter(PC)
PC is not a SFR!!
PC is a 16-bit register (consist of PCL and PCH- 8bits
each)
PC is the only register which does not have an
internal address
PC holds the address of next instruction to be
executed
PC automatically increments (+1) after every
instruction byte is fetched