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Digital electronics: A field of science which deals with discrete quantities which are
either 0 or 1.
Analogue electronics: Deals with continuously varying quantities with respect to time.
0 Ӆ 2Ӆ 3Ӆ 4Ӆ
0 1 0 1 0 1
0 time
5 5 5
Hundredths Tens Ones
5 x 102 5 x 101 5 x 100
Maximum
10th 10th 2nd 1st 1st
9 9 1 0 0
1 1 1
1 x 22 1 x 21 1 x 20
20 2-1
Counting
1st No ……. 2nd No 2nd 1st……2nd 2nd 2nd 1st 1st
0 1 1 0 1 1 1 1 1
Maximum
2nd 2nd 2nd 2nd 1st 1st 1st 2nd 2nd 2nd 2nd
1 1 1 1 0 0 0 1 1 1 1
e.g. 66.45
6 6. 4 5
80 8-1
Counting
1st No ……. 8th No 2nd 1st……2nd 8th 3rd 1st…. 3rd 8th
0 7 1 0 1 7 2 0 2 7
Maximum
8th 8th 2nd 1st 1st
7 7 1 0 0
7 7 7
e.g. 689.A73
6 8 9. A 7 3
160 16-1
Counting
1st No ……. 16th No 2nd 1st……2nd 16th
0 15 1 0 1 F
Maximum
16th 16th 2nd 1st 1st
F F 1 0 0
a) Weights Method
Procedure
i. Take the binary weights up to slightly more than the number given.
ii. Divide the decimal weight by the number given then indicate how many times
either 0 or 1 and take the remainder to the next weight.
iii. Continue till the remainder is 0
Example 1
Convert 139 to binary
139 139 11 11 11 11 3 3 1
256 128 64 32 16 8 4 2 1
0 1 0 0 0 1 0 1 1
13910 = 100010112
Example 2
Convert 156 to binary
156 156 28 28 28 12 4 0 0
256 128 64 32 16 8 4 2 1
0 1 0 0 1 1 1 0 0
15610 = 100111002
b) Divide by 2 Method
Procedure
i. Take the number, divide by 2 and indicate the remainders
ii. The remainders are read from down-up
Example 1
Convert 139 to binary
2 139 Remainders
2 69 1
2 34 1
2 14 0
2 8 1
2 4 0
2 2 0
2 1 0
2 0 1
13910 = 100010112
Example 1
Convert 0.625 to binary
2 0.625 Carry
2 0.25 1
2 0.5 0
2 0.0 1
0.62510 = 0.1012
Example 2
Convert 0.728 to binary
2 0.728 Carry
2 0.456 1
2 0.912 0
2 0.824 1
2 0.648 1
2 0.296 1
2 0.592 0
0.72810 ~ 0.101112
Binary to Decimal
Integer Values
Procedure
i. Indicate the weights to the corresponding binary digits
ii. Cross out the weights that have zero above them
iii. Sum up the weights that have 1’s above them
Example 10010112
1 0 0 1 0 1 1
64 32 16 8 4 2 1
64 + 8 + 2 + 1 = 75
10010112 = 7510
NB:
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
A 10 1 0 1 0
B 11 1 0 1 1
C 12 1 1 0 0
D 13 1 1 0 1
E 14 1 1 1 0
F 15 1 1 1 1
Example
Convert 0.3610 to Octal
8 0.36 Carry
8 0.88 2
8 0.04 7
8 0.32 0
2 0.56 2
2 0.48 4
0.3610 ~ 0.270248
Octal to Decimal
Weights Method
7 7 4
82 81 80
7 x 82 + 7 x 81 + 4 x 80 = 448 + 56 + 4
7748 = 50810
0. 0 3 2
3 x 8-2 + 2 x 8-3
0.0328 = 0.05110
Binary to Octal
Procedure
i. Group the binary digits into groups of 3
ii. Then convert to decimal
iii. Conversion is done integer from point to left whereas for fraction from point
to right
0 0 1 1 1 0 1 1 0. 1 0 1 1 0 0
1 6 6. 5 4
1110110.1011 = 166.548
Octal to Binary
Procedure
Convert the number to groups of 3 bits
2 1 0 7. 3 1
2107.318 = 010001000111.0110012
3 8. 9 F
48 + 8. + 0.5625 + 0.05859
38.9F = 56.06210910
Decimal to Hexadecimal
Example 89.2510
16 89 Remainder
16 5 9
0 5
89.2510 = 5916
Fractional to Hexadecimal
Example 0.25
16 0.25 Carry
0 4
0.25 = 0.416
Hexadecimal to Binary
Procedure
i. Convert each hexadecimal digit to a group of 4 bits
ii. Then combine them to give a string of bits (binary)
Hexadecimal Binary
4 0100
8 1000
2 0010
6 0110
B 1011
48.26B16 = 01001000.0010011010112
0 0 1 1 0 1 1 0. 0 1 0 1 0 1 0 0
3 6. 5 4
110110.0101012 = 36.5416
Hexadecimal to Octal
Procedure
i. First convert the hexadecimal number to binary
ii. Group the bits in groups of 3 to convert them into Octal
0 1 1 0 0 1 0 1 1 1 0 1. 1 0 1 0 1 1 0 0 0 0 1 1
3 1 3 5. 5 3 0 3
65D.AC316 = 3135.53038
Octal to Hexadecimal
Procedure
i. Convert the Octal number to binary
ii. Thereafter convert it to hexadecimal
1 1 1 1 1 0 0 1 1. 1 0 1 1 0 0
1 F 3. B
763.548= 1F3.B16
1) Addition
2) Subtraction
3) Multiplication
4) Division
1. Addition
Binary Addition
It involves adding two binary numbers
A B Addition
0 0 0
0 1 1
1 0 1
1 1 0 Carry 1 = 1 0
A= 1011101.1101+
B= 1110011.0111
1010001.0100
2. Binary Subtraction
Methods of Subtraction
i) Direct Subtraction
ii) Subtraction using 1’s complements
iii) Subtraction using 2’s complements
iv)
A B Addition
0 0 0
0 1 1 Borrow 1
1 0 1
1 1 0
Direct Subtraction
A= 11001.101-
B= 10111.111
00001.110
A= 10000 -
B= 1111
00001
1’s Complement
Example: 1 0 1 1 02 01001
2’s Complement
Procedure
i. First obtain 1’s complement
ii. Add a 1 to the Least Significant Bit
Procedure
i. Take the binary and check for the first 1 from the LSB
ii. Arrange the binary bits the way they appear including the first bit
iii. Complement the rest
Example 1: 10110010
0 1 0 0 1 1 1 0 2’s Complement
Example 2: 10010000
0 1 1 0 0 0 0 0 2’s Complement
Example 1:
A= 101101-
B= 100011
001010
A= 101101+
B’ = 011100
1 0 0 1 0 0 1 + Result is a POSITIVE so add it
1
001010
Example 2:
B= 100011-
A= 101101
001010
A’ = 010010+
B= 100011
0 1 1 0 1 1 1 + Result is a NEGATIVE so re-complement
001000
Example 1:
A= 101101
B= 100011
B’ + 1 = 111101+
A = 101101
1 0 0 1 0 1 0 Discard the carry 1
A’ + 1 = 010011+
B = 100011
0 1 1 0 1 1 0 Result is a NEGATIVE so re-complement
001001
Multiplication
A B Result
0 0 0
0 1 0
1 0 0
1 1 1
A 1 1 0 1. 1 0 1
B 1 0 1 1. 1 1
1011 01
1011 01
1011 01
000000
1011 01
1 0 1 0 0 0 0 0. 0 0 0 1 1
Division
Whole numbers/integers
Example 1:
Dividend 20 10100
Divisor 5 101
100
101√10100
101
000
Done by subtracting the divisor from the dividend and shifting it to the left until the
remainder is 0
Example 2:
Dividend 111.101
Divisor 0 .1 1
Procedure
i. First remove the point from both the dividend and divisor by multiplying them
to make them whole numbers (integers).
1010.00101
110√111101
110
110
110
01000
110
1000
11 1.101 ≈ 1010.00101
0.11
Example 3:
Dividend 1 1 1 . 1 1 x 100 = 11111
Divisor 0 .1 x 100 10
1111.1
10√11111
10
11
10
11
10
11
10
10
10
11 1.11 ≈ 1111.1
0.1
Example
1410 11102
NB:
Decimal BCD
0 0000
1 0001
2 0010
3 0011
4 0100
5 0101
6 0110
7 0111
8 1000
9 1001
Example: 45810
4 = 0100
5 = 0101
8 = 1000
45810 = 010001011000BCD
Example 1: 1 0 0 1 1 0 0 1 0 12
2 6 510
10011001012 = 26510
Example 2: 1 0 0 1 0 1 1 1 0 0 1 02
9 7 210
1001011100102 = 97210
3. Excess-3
Obtained by adding 3 to each decimal digit and converting to binary in groups
of 4-bits
Combine them to form a string of bits
2 7
3 3
5 10 convert to binary = 0101 1010
2710 = 01011010Excess-3
010111001010Excess-3 = 29710
4. Gray Code
This represents the numbers in a way that each consecutive number will differ
by 1 in binary form
Example: 1 bit
A
0
1
Example: 2 bits
A B
0 0
0 1
1 1
1 0
Example: 4 bits
A B C D
0 0 0 0
0 0 0 1
0 0 1 1
0 0 1 0
0 1 1 0
0 1 1 1
0 1 0 1
0 1 0 0
1 1 0 0
1 1 0 1
1 1 1 1
1 1 1 0
1 0 1 0
1 0 1 1
1 0 0 1
1 0 0 0
Definition of Abbreviations
NUL Null/Idle SI Shift in
SOH Start of header DLE Data link escape
STX Start of text DC1-DC4 Device control
ETX End of text NAK Negative
acknowledgement
OET End of transmission SYN Synchronous idle
0 1
Off On
No Yes
Negative Positive
False True
Low High
Absence Presence
1 0
Truth table
Has inputs and outputs
The output usually depends on different combinations of input
They are used to analyze different gates
Input Output
A F
0 1
1 0
F = A’
Inputs Output
AB F
0 0 0
0 1 1
1 0 1
1 1 1
F=A+B
Inputs Output
AB C F
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 1
F=A+B+C
BOOLEAN EXPRESSION
This is an equation which represents an output for different inputs
It contains output variables and input variables using the alphabet
It is used to analyze logic gates
It can be obtained from the truth tables
Examples
F = A’
F=A+B
F = AB + CD
TYPES OF GATES
i. Inverter – NOT
ii. OR
iii. AND Basic Gates
iv. XOR
v. XNOR
vi. NOR Universal Gates
vii. NAND
Symbol:
Features:
It has a bubble as an output
Has 1-input and 1-output
It inverts an input
D
I/P ov
4.4V O/P
5V
0.6V R
I/P O/P
5V 0.6V
R
RC 5v high
C 2v low
O/P
I/P 5V high
B
Ov low RO E
0V
SWITCHES
A B
off
Truth table
Input Output
A F
0 1
1 0
ii) OR Gate
A gate which gives an output of 0 only when all inputs are 0
Features:
It has 2 or more inputs
Has 1-output
D1
0v 5v
I/ P A A
5 v - h ig h
0v F
0v 5v
I /P B B
5v
5 v lo w D2
INPUTS OUTPUT
A B VO
Low Low Low
Low High High
High Low High
High High High
SA
VS SB
Bulb
INPUTS OUTPUT
SA SB Bulb
Off Off OFF
Off On ON
On Off ON
On On ON
Boolean expression:
F=A+B
Symbol:
A
F
B
Features:
It has 2 or more inputs
Has 1-output
Gives an output of 1 when both inputs are 1
Behaves like a multiplexer
D1 sv
VA
low
o/p
R
VB
low
D2
INPUTS OUTPUT
A B VO
Low Low Low
Low High Low
High Low Low
High High High
SA SB
bulb
VS
INPUTS OUTPUT
SA SB Bulb
Open Open OFF
Open Closed OFF
Closed Open OFF
Closed Closed ON
Truth table
Inputs Output
AB F
0 0 0
0 1 0
1 0 0
1 1 1
Boolean expression:
F=AB
Symbol:
A
F
B
Features:
It has 2 or more inputs
Gives out only 1-output
Gives an output of 1 when either inputs are 1
D1
I/P
Out put
5v R
D2
INPUTS OUTPUT
A B VO
Low Low Low
Low High High
High Low High
High High High
SA
SB
Bulb
VS
INPUTS OUTPUT
SA SB Bulb
Off Off OFF
Off On ON
On Off ON
On On OFF
Truth table
Inputs Output
AB F
0 0 0
0 1 1
1 0 1
1 1 0
F= A B
F = A’B + AB’
v) XNOR Gate
A gate which gives an output of 1 only when both inputs are the same
Symbol:
A
F
B
Features:
It has 2 or more inputs
Gives out only 1-output
Gives an output of 1 when either inputs are 0 or 1
VS
SA
Bulb
Selenoid
SB
INPUTS OUTPUT
SA SB Bulb
Off Off ON
Off On OFF
On Off OFF
On On ON
Boolean expression:
F= AʘB
F = AB + A’B’
Symbol:
A
F
B
Features:
It has 2 or more inputs
Gives out only 1-output
Gives an output of 1 when all inputs are 0
VS
SA
Bulb
Selenoid
SB
INPUTS OUTPUT
SA SB Bulb
Off Off ON
Demorgan’s Theorem
Procedure:
i. Remove the overbar
ii. Change the OR gate to an AND gate or vice versa
iii. Complement individual variables/literals
Hence F=A+B
Will be same as F = A.B
Truth table
Inputs Output
AB F
0 0 1
0 1 0
1 0 0
1 1 1
Boolean expression:
F=A+B
Symbol:
Features:
It has 2 or more inputs
It has a bubble
Gives out only 1-output
Gives an low output only when all inputs are high
VS
Bulb
SA
Selenoid
SB
INPUTS OUTPUT
SA SB Bulb
Off Off ON
Off On ON
On Off ON
On On OFF
Demorgan’s Theorem
F=A+B
A
F
B
Boolean expression:
F=AB
NB:
NOR & NAND GATES
These are universal gates
Hence they can be used to implement all the other gates
Exercise
1.
a) Implement all the other gates using the NOR Gate
b) Implement all the other gates using the NAND Gate
c) Implement the following using NOR gates and NAND gates
F = AB + BC + CD
F = ABC + ABC
F = ACD + BC + AC
F = ABC + AB + BD
OR LAWS
A+0=A
A+1=1
A+A=A
A+A=1
AND LAWS
A.0 = 0
A.1 = A
A.A = A
A. A = 0
COMPLEMENTING LAWS
0=1
1=0
A=0 A=1
A=1 A=0
COMMUTATIVE LAWS
A+B=B+A
AB = BA
ASSOCIATIVE LAWS
(A+B) + C = A + (B+C)
A(BC) = (AB)C
DISTRIBUTIVE LAWS
(A+B) (A+C) = A + BC
A + AB = A+B
A +AB = A +B
ABSORPTIVE LAWS
A(A+B) = A
A + AB = A
A(A +B) = AB
1. (A+B) (A+C) = A + BC
= AA + AB + AC + BC
= A + AB + AC + BC
= A (1 + B) + AC + BC
= A + AC + BC
= A (1+C) + BC
= A + BC
2. A + AB = A + B
= A.1 + AB
= A (1 + B) + AB
= A + AB + AB
= A+ B (A + A)
=A+B
3. A + AB
= A.1 + AB
= A (1+B) + AC + BC
= A + AB + AB
= A + B (A + A)
=A+B
Using Boolean algebra, simplify the following expressions and implement them using
the minimum number of gates
i) F = AB + AC + ABC
ii) F = ABC + ABC + ABC + ABC +ABC
iii) F= (x+ y) x (y+z) + xy + xz
i) F = AB + A + AB = 0
ii) F = AB + AC + ABC (AB+C) = 1
Example
F(A,B,C) = ABC + ABC is a domain of 3 variables A, B & C
SOP is a combination of several products OR’ed together
Example
F(A,B,C) =AB + AC + C
Example
F(A,B,C) = (A+B+C)(A+B+C)
POS is a combination of several sums AND’ed together
Example:
F(A,B) = AB + AB
E.g. AB(C+C)
Example:
F(A,B,C) = A + BC + BC
iv. Continue till all the literals appear in each term or sum
v. Eliminate the repeated sums
F(A,B,C) = A(B+C)
= (A+BB) (AA+B+C)
E.g. 2 literals 22 =4
3 literals 23 = 8
4 literals 24 = 16
iii. Change the literals to their binary equivalent by using the following
A barred literal =0
A non-barred literal =1
Example:
F(A,B,C) = ∑m (0,3,4,5,7)
E.g. 2 literals 22 =4
3 literals 23 = 8
4 literals 24 = 16
iii. Change the literals to their binary equivalent by using the following
A barred literal =1
A non-barred literal =0
Example:
Truth table
A B C F
0 0 0 0 0
1 0 0 1
2 0 1 0 0
3 0 1 1
4 1 0 0
5 1 0 1 0
6 1 1 0
7 1 1 1
F(A,B,C) = Πm (0,2,5)
Example
Convert the following to SSOP and SPOS using the table below
Truth table
A B C D F
0 0 0 0 0 0
1 0 0 0 1 1
2 0 0 1 0 1
3 0 0 1 1 0
4 0 1 0 0 0
5 0 1 0 1 0
6 0 1 1 0 0
7 0 1 1 1 1
8 1 0 0 0 1
9 1 0 0 1 1
10 1 0 1 0 1
11 1 0 1 1 0
12 1 1 0 0 1
13 1 1 0 1 0
14 1 1 1 0 1
15 1 1 1 1 1
SSOP
F = (A,B,C,D)
= ∑m(1,2,7,8,9,10,12,14,15)
SPOS
F = (A,B,C,D)
= Πm(0,3,4,5,6,11,13)
(A+B+C+D) (A+B+C+D)
1011 1101
Exercise
1. Using the following equations:
i) Obtain SSOP
ii) Convert to SPOS using a truth table
F(A,B,C,D) = AB + CD +BC
F(A,B,C,D) = BCD + A + CD
F(A,B,C,D) = AB(C+D)
K-MAP SIMPLIFICATION
Karnaugh Map
It’s a representation which uses squares to represent SSOP or SPOS
The number of squares depends on the number of input variables
Example
2-input variables 22 squares
3-input variables 23 squares
4-input variables 24 squares
The binary equivalent of the input variables is represented using the gray code
format to get the adjacent squares
The 1’s for SSOP are called Min-terms or Prime Implicants
General Representation
1. 2-Variable K-Map
A A A
B 0 1
0 2
B 0 AB AB
00 10
1 3
AB AB
B 1 01 11
2. 3-Varible K-Map
AB
AB AB AB AB
C 00 01 11 10
0 2 4 6
C 0 ABC ABC ABC ABC
000 010 100 110
1 3 5 7
ABC ABC ABC ABC
C 1 001 011 101 111
3. 4-Variable K-Map
AB
AB AB AB AB
CD 00 01 11 10
0 4 12 8
CD 00 ABCD ABCD ABCD ABCD
0000 0100 1100 1000
1 5 13 9
ABCD ABCD ABCD ABCD
CD 01 0001 0101 1101 1001
3 7 15 11
ABCD ABCD ABCD ABCD
CD 11 0011 0111 1111 1011
2 6 14 10
ABCD ABCD ABCD ABCD
CD 10 0010 0110 1110 1010
AB AB AB AB AB
C 00 01 11 10
0 2 4
C 0 1 1 1
7 5
C 1 1 1
SPOS Representation
Procedure
i. Identify the max-term
ii. Change input variables to their binary equivalent
iii. In the table indicate a 0 to correspond with the square with the binary equivalent
of the max-term
1. 2-Variable K-Map
A
A A
B 0 1
0 2
B 0 A+B A+B
00 10
1 3
A+B A+B
B 1 01 11
2. 3-Varible K-Map
AB AB AB AB AB
C 00 01 11 10
0 2 4 6
C 0 A+B+C A+B+C A+B+C A+B+C
000 010 100 110
1 3 5 7
A+B+C A+B+C A+B+C A+B+C
C 1 001 011 101 111
AB AB AB AB AB
CD 00 01 11 10
0 4 12 8
CD 00 A+B+C+D A+B+C+D A+B+C+D A+B+C+D
0000 0100 1100 1000
1 5 13 9
A+B+C+D A+B+C+D A+B+C+D A+B+C+D
CD 01 0001 0101 1101 1001
3 7 15 11
A+B+C+D A+B+C+D A+B+C+D A+B+C+D
CD 11 0011 0111 1111 1011
2 6 14 10
A+B+C+D A+B+C+D A+B+C+D A+B+C+D
CD 10 0010 0110 1110 1010
Example:
Represent the following expression using K-map
F(A,B,C,D) = Πm (1,2,3,5,7,8,12,14)
AB AB AB AB AB
CD 00 01 11 10
12 8
CD 00 0 0
1 5
CD 01 0 0
3 7
CD 11 0 0
2 14
CD 10 0 0
i) F(A,B,C) = ∑m(1,3,4,6,7)
AB
AB AB AB AB
C 00 01 11 10
6 4
C 0 1 1
1 3 7
1 1 1
C 1
F(A,B,C) = AC + AB + AC
AB AB AB AB
CD 00 01 11 10
CD 00 1 1 1
CD 01 1 1 1 1
CD 11 1 1 1
CD 10 1 1
F(A,B,C,D) = AC + BD + BC + AC
i) F(A,B,C) = Πm(2,3,5,6,7)
AB AB AB AB AB
C 00 01 11 10
C 0 0 0
C 1 0 0 0
F(A,B,C) = B(A + C)
AB AB AB AB AB
CD 00 01 11 10
CD 00 0 0 0
CD 01 0
CD 11 0 0
CD 10 0 0
AB AB AB AB AB
C 00 01 11 10
C 0 1 1 1
C 1 1 1 1 X
F(A,B,C) = (C + A)
AB AB AB AB AB
CD 00 01 11 10
CD 00 X 1 1 1
CD 01 1 1 1 1
CD 11 1 1 1
CD 10 1 1 X
F(A,B,C,D) = A+C+B
Exercise:
From the following expressions:
i) Obtain the minimized expressions
ii) Draw the logic diagrams for the obtained equation
Types include:
i. Adders
ii. Subtractors
iii. Multiplexers
iv. Demultiplexers
v. Encoders
vi. Decoders
1. Adders
They add inputs to obtain a sum and a carry out
Types of adders
i. Half Adder
Has 2 inputs and 2 outputs
Block Diagram
A
S
Half - adder
B
Cout
S
A
B 0 1
0 0
1 1
CO
A
B 0 1
1 1
CO
Truth table
A B S CO
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
Block Diagram
A S
B Full - adder
Cin Cout
S
A
B 00 01 11 10
0 1 1
1 1 1
CO
A
B 00 01 11 10
1
0
1 1 1 1
Logic Diagram
A B CO
S0
2. Subtractors
They subtract inputs to obtain a difference and a borrow out
Types of subtractors
i. Half Subtractor
Has 2 inputs and 2 outputs
Block Diagram
A D
Half -
subtractor
B
bo
Truth table
A B D BO
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0
0 1
1 1
𝐷 = 𝐴̅𝐵 + 𝐴𝐵̅
A B
b0(AB)
A
B 0 1
1 1
̅𝑩
𝒃𝟎 = 𝑨
Logic Diagram
A
D
B
bo
Block Diagram
A D
Full -
B subtractor
bi b0
D(A,B,bi)
AB
C 00 01 11 10
0 1 1
1 1 1
bi(A, B, bi)
AB
C 00 01 11 10
0 1
1
1 1 1
̅ 𝒃𝒊 + 𝑨
𝑨𝒊 = 𝑨 ̅ 𝑩 + 𝑩𝒃𝒊
Logic Diagram
A
B
D
bi
bi
Full-subtractor
Block Diagram
I0
I1
MUX F
n to 1
In-1
S0 S1
SM-1
Number of inputs = n
Number of outputs =1
Number of select lines = m
The relationship between the select lines and inputs is given by:
Inputs – n = 2m
I0
MUX F
2 to 1
I1
S0 I1 I0
Truth table
Inputs Output
S0 I1 I0 F
0 X 0 0
0 X 1 1
1 0 X 0
1 1 X 1
When S0 = 0; Io is selected
When S0 = 1; I1 is selected
I1 and I0 can either be 0 or 1
I0
I1
4 to 1
F
I2 MUX
I4
S0 S1
Truth table
Inputs Output
S1 S0 I3 I2 I1 I0 F
0 0 X X X 0 0
0 0 X X X 1 1
0 1 X X 0 X 0
0 1 X X 1 X 1
1 0 X 0 X X 0
1 0 X 1 X X 1
1 1 0 X X X 0
1 1 1 X X X 1
F = S1 S0 I0 + S1 S0 I1 + S1 S0 I2 + S2 S0 I3
S S0 I3 I2 I1 I0
1
Exercise
i) Design a 8 to 1 MUX
ii) Design a 8 to 1 MUX using 2 to 1 MUX
iii) Design a 8 to 1 MUX using 4 to 1 MUX
F0
Output
Input
EN DEMUX F1
FM-1
S0 S 1 S 2 Sm-1
Select lines
Number of inputs = 1
Number of outputs =n
Number of select lines = m
The relationship between the select lines and inputs is given by:
2m = n
Design a 1 to 2 Demux
Block Diagram
1 to 2 F0
I Demux
F1
SO
Truth table
Inputs Output
S0 I F1 F0
0 0 0 0
0 1 0 1
1 0 0 0
1 1 1 0
F0 = S0 I
F1 = S0 I
F0
F1
Design a 1 to 4 Demux
Block Diagram
1 to 2 F0
I Demux F1
F2
F3
SO i0 I1
Truth table
Inputs Output
S1 I0 I F3 F2 F1 F0
0 0 I 0 0 0 1
0 1 I 0 0 1 0
1 0 I 0 1 0 0
1 1 I 1 0 0 0
F0 = S1 S0 I
F1 = S1 S0 I
F2 = S1 S0 I
F3 = S1 S0 I
Exercise
i. Design a 1 to 8 Demux
ii. Design a 1 to 8 Demux using 1 to 2 Demux
iii. Design a 1 to 8 Demux using 1 to 4 Demux
Encoders
Direct several inputs to a few outputs using the following relation
n = 2m
Where n = inputs
and m = ouputs
I0 F0
I!
ENCODER F1
In-1
FM-1
Design a 2 to 1 encoder
Block Diagram
I0
2 to 1 F0
I1 encorder
Truth table
Inputs Output
I1 I0 F
0 1 0
1 0 1
F=I
EN I0
F0
F1
Design a 4 to 2 encoder
Block Diagram
I0 F0
I1 4 to 2
I2 encorder
I3 F0
F0 = I1 + I3
F1 = I2 + I3
Solution
D0
A
D1
D2
D3
B
D4
D5
D6 C
D7
(2 marks)
It has 8 inputs, one for each of the eight digits of the octal system, and
three outputs which will generate corresponding equivalent binary
numbers. It is constructed by using three OR gates.
A=D4+D5+D6+D7
B=D2+D3+D6+D7
C=D1+D2+D5+D7
Decoders
Direct a few inputs to several outputs using the following relation
2m = n
Where m = inputs
and n = outputs
Block Diagram
EN F0
I0
DECODER F1
In-1
FM-1
F0
EN
DECODER
I0 F1
Truth table
Inputs Outputs
I F1 F0
0 0 1
1 1 0
F0 = I
F1 = I
Design a 2 to 4 encoder
Block Diagram
I0 F0
2 to 4 F1
Decoder F2
I1 F3
Truth table
Inputs Output
I1 I0 F3 F2 F1 F0
0 0 0 0 0 1
0 1 0 0 1 0
1 0 0 1 0 0
1 1 1 0 0 0
F0 = I1 I0
F1 = I1 I0
F2 = I1 I0
F3= I1 I0
EN A B C D0 D1 D2 D3 D4 D5 D6 D7
1 X X X 0 0 0 0 0 0 0 0
0 0 0 0 1 0 0 0 0 0 0 0
0 0 0 1 0 1 0 0 0 0 0 0
0 0 1 0 0 0 1 0 0 0 0 0
0 0 1 1 0 0 0 1 0 0 0 0
0 1 0 0 0 0 0 0 1 0 0 0
0 1 0 1 0 0 0 0 0 1 0 0
0 1 1 0 0 0 0 0 0 0 1 0
0 1 1 1 0 0 0 0 0 0 0 1
A
D1
D2
B
D3
D4
C
D5
D6
D7
A decoder is used to decode the binary information in a digital system into some other
type of number system, preferably decimal or hexadecimal number system. For the
one above 3 bit binary information is decoded into eight outputs. The three NOT gates
on input side give the complement of the inputs and eight AND gates are used, so that
the outputs are active ‘high’. It can also be referred to as a binary to octal decoder or a
1 to 8 decoder. It is applied in binary to octal converter. The input variables will
represent the three digit binary number and output will represent the eight digits in the
octal number system, as only one of the eight outputs is activated at a time.
Inputs Outputs
Combinational
circuit
Memory
elements
A logic circuit whose output depends on the present inputs and past outputs
Made of combinational logic circuits and memory elements
Have feedback
Can store a 1 or a 0
Mostly they have two outputs complementing each other
Outputs Q and Q
If Q = 1; then Q = 0
If Q = 0; then Q = 1
1. Synchronous
All the sequential circuits are controlled by a common clock
The propagation delay of the whole system is equivalent to the propagation
delay of the constituent parts of the system
They are stable
Q Q
clk
2. Asynchronous
Not controlled by a common clock
Have a large propagation delay (time shift between input and output)
They are unstable
They are prone to many errors
clk
Flip Flop
These are circuits which can change state according to the inputs
Block Diagram
SET
J Q
inputs outputs
K CLR Q
R CLR Q
R Q
S Q
R Q
S Q
Operation
S R Qn+1
0 0 Invalid
0 1 0 Reset
1 0 1 Set
1 1 No change
Level one
Level zero
Rising edge Falling edge
A. Edge triggering
Where a circuit is triggered by a rising (leading) or a falling (trailing) edge
B. Level triggering
Triggering is done by either a 1 or 0
CLK
CLK
SET
S Q
clock
R CLR Q
Logic diagram
R
Q
clk
S Q
Truth table
Clk S R Qn+1
0 0 0 No change
0 0 1 No change
0 1 0 No change
0 1 1 No change
1 0 0 No change
1 0 1 0 Reset
1 1 0 1 Set
1 1 1 Invalid
K CLR Q
Logic Diagram
K
Q
clk
J
Q
Truth table
Q J K Qn+1
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 0
SET
D Q
clock
CLR Q
Logic diagram
D
Q
clk
T Q
clk
Ǭ
Logic diagram
T
Q
clk
Truth table
Q T Qn+1
0 0 0
0 1 1
1 0 1
1 1 0
JK Flip Flop
Used in designing of counters
Transition table
Inputs
Q Qn+1 J K
0 0 0 X
Transition Diagram
1/X
O/X
0 1 X/O
X/1
5. D Flip Flop
Transition table
Input
Q Qn+1 D
0 0 0
0 1 1
1 0 0
1 1 1
Transition Diagram
O
0 1 1
O
T Flip Flop
Transition table
Input
Q Qn+1 T
0 0 0
0 1 1
1 0 1
1 1 0
Transition Diagram
O
0 1 0
1
REGISTERS
Device used to store data
Mostly constructed using flip flops particularly D Flip Flops
Can be used to shift data serially or in parallel
Use a common clock
Types of Registers
i. Serial Input Serial Output (SISO)
They are used to obtain a single bit input and single bit output
Diagram
QA QB
QC
Input SET SET SET
D Q D Q D Q
Diagram
QD QC QB QA
Operation
Information/data is transferred with every clock pulse from right to left.
If for instance there is an input of 1100 after each clock pulse the bits will be
transferred from one flip flop to another.
3 1
Types of Counters
i. Synchronous
Features
Have a common clock
Have less propagation time (PT) i.e. time it takes for data to move in circuit
from input to output
Stable
Has very few errors
ii. Asynchronous
Features
Don’t have a common clock
Have more propagation time (PT)
Not stable i.e. in terms of reliability
More prone to errors compared to the synchronous
Synchronous
Design
Procedure
i. Determine the number of steps the counter goes through.
ii. Determine the number of flip flops to be used using a number of states
Formula
2n = N; Number of states
Where n = Number of flip flops
n = Log N
Log 2
iii. Round off to the higher number all the time even if you obtain < point 5.
iv. Use transition diagram to obtain inputs to the flip flops to be used
v. Document in a truth table
vi. Draw the logic diagram
Example:
Design a BCD counter
Synchronous and asynchronous using T flip flops
Synchronous
BCD 0 9 goes through
0
1
9 2
8
3
7 4
6 5
Truth table
Present State Next State Flip flop inputs
A B C D A B C D TA TB TC TD
0 0 0 0 0 0 0 1 0 0 0 1
0 0 0 1 0 0 1 0 0 0 1 1
0 0 1 0 0 0 1 1 0 0 0 1
0 0 1 1 0 1 0 0 0 1 1 1
0 1 0 0 0 1 0 1 0 0 0 1
0 1 0 1 0 1 1 0 0 0 1 1
0 1 1 0 0 1 1 1 0 0 0 1
0 1 1 1 1 0 0 0 1 1 1 1
1 0 0 0 1 0 0 1 0 0 0 1
1 0 0 1 0 0 0 0 1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
AB
CD 00 01 11 10
00 X
01 1 1 X
11 1 1 X X
10 X
X
𝑇𝐶 = 𝐴̅𝐷
TD
AB
CD 00 01 11 10
1 1 X 1
00
01 1 1 X 1
11 1 1 X X
10 1 1 X
X
𝑇𝐷 = 1
TB
AB
CD 00 01 11 10
00 X
01 X
11 1 1 X X
10 X
X
𝑇𝐵 = 𝐶𝐷
00 X
01 X 1
11 1 X X
10 X
X
𝑇𝐴 = 𝐵𝐶𝐷 + 𝐴𝐷
SET
D Q
A
CLR Q
SET
D Q
B
CLR Q
SET
D Q
C
CLR Q
SET
D Q
‘I’ D
CLR Q
Truth table
Present State Next State Flip flop inputs
A B C D A B C D CA CB CC CD
0 0 0 0 0 0 0 1 0 0 0 1
0 0 0 1 0 0 1 0 0 0 1 1
0 0 1 0 0 0 1 1 0 0 0 1
0 0 1 1 0 1 0 0 0 1 1 1
0 1 0 0 0 1 1 1 0 0 0 1
0 1 0 1 0 1 1 0 0 0 1 1
0 1 1 0 0 1 0 0 0 0 0 1
0 1 1 1 1 0 0 0 1 1 1 1
1 0 0 0 1 0 0 1 0 0 0 1
1 0 0 1 0 0 0 0 1 0 0 1
AB
CD 00 01 11 10
00 X
01 X 1
11 1 X X
10 X
X
𝐶𝐴 = 𝐵𝐶𝐷 + 𝐴𝐷
AB
CD 00 01 11 10
00 X
01 X
11 1 1 X X
10
X
𝐶𝐵 = 𝐶𝐷
AB
CD 00 01 11 10
00 X
01 1 1 X
11 1 1 X X
10 X
X
𝐶𝐶 = 𝐴̅𝐷
𝐶𝐷 = 1
CLR Q
SET
D Q
B
CLR Q
SET
D Q
C
CLR Q
SET
D Q
D
CLR Q