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IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. IA-19, NO. 6, NOVEMBER/DECEMBER 1983

1057

Generalized Structure of a Multilevel PWM Inverter

PRADEEP M. BHAGWAT, MEMBER, IEEE, AND V. R. STEFANOVIC, SENIOR MEMBER, IEEE

Abstract-A generalized structure of a multilevel voltage source

thyristor inverter is proposed. The multilevel concept is used to de- crease the harmonic distortion in the output waveform without de-

creasing the inverter power output. A simple uniform PWM control of

the output voltage is seen to be sufficient to practically remove all

remaining harmonics. Harmonic analysis of n-step waveform is given,

and the experimental results obtained on a three-step inverter are presented.

INTRODUCTION THE CURRENT shift to variable-frequency ac drives with associated emphasis on improved performance and in- creased power ratings is again focusing attention to the prob- lem of inverter harmonic distortion. The distortion is particu- larly of concern in drives above 50 hp where power transistors cannot be applied so easily and the pulsewidth modulation (PWM) control becomes less attractive. In fact, an adjustable- voltage adjustable-frequency inverter operating with essentially square-wave output voltage can be viewed as a generator of higher harmonics [1]. Presently, three basic methods for

harmonic reduction exist.

1) Multilevel Waveforms: In the past, multilevel operation

was achieved by summing the outputs of several inverters

operating in parallel through phase shifting transformers [2].

Obviously, this technique is no longer attractive for most

applications due to the large reactive elements used. Recently, a transistor inverter with a multilevel voltage waveform was

proposed [3], [4]. Although the inverter provides an efficient reduction of harmonic distortion, due to the existing transistor

technology its use is limited to low-power applications. 2) Sinusoidal PWM [5].- By chopping the output waveform and by appropriately controlling the width of the resulting voltage pulses, one can successfully eliminate all dominant harmonics. The problem here is that the scheme results in the voltage derating of the inverter.

3) Pulsewidth Control: By producing several pulses during

each half-period of the output waveform and by controlling their position and width, selected harmonics can be eliminated

from the inverter output [6]. However, the voltage control is limited, while the inverter is still derated with this technique.

The proposed inverter shown in Fig. 1 is conceptually sim-

ple and can be easily implemented by using power transistors. If a higher power output is desired, the use of thyristors will be required. It will be shown that, in the multilevel inverter,

Paper IPCSD 82-9, approved by

the Static Power Committee of the

IEEE Industry Applications

Society for presentation at the 1980 In-

dustry Applications Society Annual

by

Meeting, Cincinnati, OH,

Septem-

publication April 2, 1982.

ber 29-October 3. Manuscript released for

This work was supported in part

Canada and the Department of Education, Province of Quebec.

the National Research Council of

P. M. Bhagwat is with Black and Decker Co., 701 East Joppa Rd.,

is with General Electric Company, POB 8106,

Towson, MD 21204. V. R. Stefanovic

Charlottesville, VA 22906.

Fig. 1.

T

Schematic of half-bridge multilevel inverter.

the use of conventional commutation circuits will result in a complex firing control. The new versatile commutation cir-

cuit [7] has the capability of instantaneously commutating

any conducting thyristor and therefore is ideally suited for the

multilevel inverter. This flexibility permits a PWM control of the inverter output voltage. The harmonic analysis of an inverter with n voltage levels is given, and a number of necessary semiconductor switches

is specified. The circuit implementation of such an inverter is described, and the concept is illustrated by considering a three-

level inverter which has been actually designed and con-

structed in-the laboratory. Voltage control of this type of in-

verter is then discussed, and the harmonic analysis of a three-

level PWM inverter is presented. It is seen that, with ten uniform pulses per half-period of the output waveform, all harmonics below the twenty-third are reduced to less than or equal to ten percent of the fundamental harmonic. Experi- mental results, corresponding to the theoretical calculations

are given in Fig. 13. The proposed inverter structure is be-

lieved to offer the following advantages when applied to vari- able-frequency ac drives.

1) The voltage contiol below the motor base frequency can

be obtained by a very simple uniform PWM control while reducing practically all harmonics from the motor input

voltage. 2) For maximum voltage output (constant power operation above the motor base frequency), the inverter full power can be used, while at the same time reducing all dominant har- monics from the motor input voltage.

II. HARMONICS IN THE OPTIMIZED STEPPED WAVEFORMS A. Optimization Techniques There is a considerable complexity in trade-offs when choosing the number of voltage steps [8] . Considering Fig. 2,

0093-9994/83/1100-1057$01.00 © 1983 IEEE

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1058

IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. IA-19, NO. 6, NOVEMBER/DECEMBER 1983

Fig. 2. Generalized stepped waveform.

three possible optimization techniques exist to reduce the low- order harmonics: 1) assuming equally spaced steps, step heights are optimized; 2) assuming the steps of equal heights, their spacing is optimized; 3) optimizing both height and spacings.

The Fourier expression for the -waveform in Fig. 2 is

4

e=-

z

(V1 cosn01 + V2 cosn02 +--

7f n=odd

+vcosn0p)

4

=_

7r

1

p

2

n=odd k=l

sin (nct)

n

n

(Vk cos nOk)

sin (nwt)

n

(1)

(2)

where p denotes the number of steps in a quarter-cycle, 0k k

a quarter-wave symmetry in the waveform is assumed.

For equally spaced steps with no dwell at zero voltage, i.e., 0 1 = 0, (2) becomes

ir/2 and

4

e =-

z [V1 + V2 cos +V3 cos 2nO +

XT n=odd

where 0 = ir/2p and Vk = V1 (cos Ok/cos 01). For waveforms of this type, the harmonics will occur as follows:

hn = 4pn ± 1

where n = 1, 2, 3 -e. Therefore, for the optimized 12-step waveforms with p = 3, the first low-order harmonic will be

the eleventh.

B. Harmonic Reduction in the Three-Level Inverter

In practice, however, a trade-off has to be made between the required number of steps and the design complexity.

Harmonics can be reduced as required through PWM voltage

control, but harmonic reduction becomes impossible when the inverter is delivering its full output, at which time the

harmonic content of the output waveform is that of a typical square wave, with the absence of triplen harmonics. Fig. 3(a) shows the multilevel inverter schematic with a

minimum number of voltage references, which are a) positive reference, b) negative reference, and c) zero reference. Fig. 3(b) shows a typical waveform of a half-bridge inver-

ter. From (1), it can be seen that a specific duration of a zero interval can eliminate any one specific harmonic. Rewriting

(1)for Fig. 3(b),

+ Vp cos (p-l)nO] X

sin nO

n

=-

4 .p

z

z (Vk cos ((k-l )nO))

7T n=odd k=1

sinnO

n

(3)

where 0 = ir/2p and Vk = 2V1 cos (k - 1) 0.

For equally spaced steps with dwell at zero voltage such

that 01 = a/2, 02 = 3a/2, 03 = 5a/2, Ok = (2k - I)a/2,

(2)becomes

4

e=-

p

Y4 Vk cos((2k- l)nO) sin-

nO

7f n=odd k=1

n

(4)

e=-TV1 cosn01 sinncot

irn

(5)

where V1 =

0.5 Ed =0.5 V

* if 01 =

18°, the fifth harmonic will be zero,

* if 01 = 12.850, the seventh harmonic will be zero, etc.

Fig. 3(c) shows the typical line-to-line voltage waveform ob-

tained in the proposed multilevel inverter. This waveform can be optimized by any one of the techniques discussed before. The harmonics of this waveform can be expressed as

An= V cos (nO0) + V2 cos (nO2).

(6)

As this waveform is the difference between any two phase

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BHAGWAT AND STEFANOVIC: GENERALIZED STRUCTURE OF MULTILEVEL PWM INVERTER

0 eil

_rrr - ---

(a)

I

(b)

I

(c)

Fig. 3. (a), (b) Schematic of three-level inverter and output waveform.

inverter.

(c) Typical phase and line voltages in three-level

voltages, V1 should be equal to V2 and 0 1 should be equal to

((iT/3)-02)

A

=0.5Ed [cosn (- 02) + cos](n2)1

(7)

02 can be selected so as to eliminate any particular harmonic or to reduce the total harmonic distortion. Eliminating only one particular harmonic will not significantly improve the waveshape; therefore, reducing the total harmonic distortion (THD) may be desirable.

C. Minimizing the Total Harmonic Distortion Total harmonic distortion can be expressed as

THD percent = 100

IVt

- -

1

where

Vt rms value of the stepped wave,

Vf rms value of the fundamental, for the waveform shown in Fig. 3(c):

Vf =

2V

[0.5Vcos01 + 0.5Vcos 02]

=- V(cos01 +COS02)

and

V 2 02

V 2_

2V2 -

2 fr/2

(o.v7)2 dO+-J

_

v2 do

=-~-2 - 0.7502 - 0.250,

1059

(8)

(9)

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1060

IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. IA-19, NO. 6, NOVEMBER/DECEMBER 1983

As

.vt2

vf

- -

- 0.7502 - 0.2501]

(COS 0

+ COS0-)2

and simplifying,

(10)

dO

(

3

2

Cos (-02) + COS 02

sin 02 -)sin

-02

=0.

7r

0 1=3-02

3

and

iT <02

6

ir/3.

Substituting 01 and 02 in (8) and (9),

Vf = 7

os (-02) + COS 02]

Vt2 =-[- --0.7502-0.25 (- -02)]

Numerical solution gives 02 = 0.79068 rad = 45.3030. Thus 02 = 450 and 01 = (ff/3) - 02 = 150. Table I shows

the harmonic amplitudes for the two waveforms. From Table I it can be seen that significant reduction occurs in the total

harmonic distortion from 31.08 percent in the conventional waveform to 16.86 percent in the proposed waveform. At the same time, the dominant fifth and seventh harmonics are also

reduced from 20 percent to 5.35 percent and 14 percent to

3.82 percent, respectively. Fig. 3(c) shows that the proposed waveform and a conventional line-to-line voltage waveform (11) have the same average value. This means that this harmonic reduction is achieved by maintaining the same average power output as that of a conventional PWM inverter.

III. GENERALIZED METHOD OF COMMUTATION IN A MULTILEVEL INVERTER

2V2

=

~ -

ir -12

- 0.502

Vt2 2V2 57T

2V2

Vf

7

2 - -0502 /72

COS 3-2

v 2

IT

12

7T 32°0

\

+ COS

02j

iT1

[COS(7r/3-02) Co02 *

(12)

(13)

To minimize the total harmonic distortion the term Vt2/Vf2 should be minimum. Let

t2

Xr

_

_

2-°0502

[cos (-02) + COS 02]

minimizing y,

.-=o= [cos (-02) +cos02][-0.5]

[I12.*

2] [cos (C-02) ±CO2]

sin 02-sin ( -0 2)

A. Classification of the Commutation Types

Fig. 4 shows the generalized single phase of a half-bridge multilevel inverter where A denotes the output terminal.

Current IA through node A is defined as positive when it

flows from

node A to the load. Current IA is defined as nega-

tive when it flows from the load to node A. From these

definitions, it may be observed that if IA is positive, any one

of the semiconductors having its cathode connected to termi- nal A can conduct for a given time. If IA is negative, then any

one of the semiconductors with its anode connected to termi- nalA can conduct for a given time. Under normal operation due to di/dt restrictions during

commutation, two semiconductors will conduct simultane-

ously until a current transfer from one semiconductor to the other is completed.

Using these definitions, one can identify four types of

commutations: commutation of a thyristor when current is positive and is transferred from any semiconductor to a semiconductor at a) a higher potential or b) a lower potential;

commutation of a thyristor when current is negative and is

transferred from any semiconductor to a semiconductor at c) a higher potential or d) a lower potential. From Fig. 4 it is interesting to note that thyristor com- mutation is automatically achieved for cases a) and d) when

the desired current transfer is done. This is due to the fact that

when a current transfer is made, the previously conducting thyristor automatically gets reverse biased, and therefore special forced commutation is not required. For cases b) and c), special forced commutation is required to turn off the conducting thyristor. It is also interesting to note that if a positive current is freewheeling in the freewheeling diode at the extreme nega-

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BHAGWAT AND STEFANOVIC: GENERALIZED STRUCTURE OF MULTILEVEL PWM INVERTER

1061

TABLE I

 

An.,

An%

-Harmonic

Conventional

Optimized

Number

Waveform

Waveform

al

127.3

122.9

a3

0.000

0.000

a5

20

5.35

a7

14.2

3.82

a

0.000

0.000

a11

9.09

9.09

a13

7.69

7.69

al5

0.000

0.000

a17

5.88

1.57

a19

5.26

1.41

a21

0.000

0.000

a23

4.34

4.34

a25

4.0

4.0

827

0.000

0.000

829

3.44

0.92

THD

31.08:

[

16.86%

Fig. 4. Semiconductor arrangement in generalized multilevel inverter.

tive voltage level, it can be transferred to any required voltage

level without any commutation process. Similarly, a negative current can be transferred to any voltage level if it is free- wheeling in the diode at the extreme positive voltage level. The following approach illustrates how the commutation process may be simplified for cases b) and c). The first step during commutation is to trigger a thyristor at the extreme positive or negative reference for cases b) and c), respectively. This will transfer the positive or negative current automatically to the extreme positive or negative voltage reference. The second step is to turn off the triggered thyristor and to transfer the current to the freewheeling diode

at the complementary reference. The third step is to transfer

the current to a desired thyristor. If the PWM switching is used to control the inverter output

voltage, one would need two conventional commutation

circuits for each inverter phase. The reason is as follows: with

a conventional circuit, the commutation capacitor has to be

charged with correct polarity before any given thyristor can be turned off. Thus with aPWM control, when the same thyristor

is repeatedly switched on and off during each half-cycle, while the load current is not changing the direction, one has to call for redundant (negative current) commutation, although no thyristor is conducting and the load current is freewheeling through a diode. This commutation is necessary to recharge the commutation capacitor with a correct polarity for the next thyristor commutation. Such an approach-is not practical with a PWM-controlled multilevel inverter with a zero-reference switch Sz (Fig. 3), since one would have to know in advance the pattern of the load current switching, including the op- eration at zero voltage across the load. As a result, if a pre- charged commutation capacitor is used, two commutation circuits (one for the upper and one for the lower thyristor groups) would be necessary. The ideal commutation circuit for this application would be the one where the charge on the commutation capacitor is zero before and after the commutation process. In that case, the circuit becomes "impartial" to the commutation in the upper or lower thyristor group, being able to follow any switching sequence. Detailed description of such a circuit is given in [7] and is briefly discussed here.

Fig. 5. shows a half-bridge multilevel inverter with the com-

mutation circuit. In Fig. 5, thyristor T-1 and diode D-1 are

connected to the positive voltage reference, thyristors TZ1

and TZ2 are connected to the zero reference level, and thyris- tor T-2 and diode D-2 are connected to the negative reference

level. Note that in an N-level multilevel inverter, T-1, D-1 and

T-2, D-2 will be at the extreme positive and negative references,

respectively. TA-1 and TA-2 are the auxiliary thyristors, and

DA-1 and DA-2 are the auxiliary diodes. Thyristors TD-1 and TD-2 are discharge thyristors. Assuming that the load current

is substantially constant during commutation and that thyris-

tor T-1 is conducting, commutation of T-1 is achieved by triggering thyristor TA-2 at t = to. (Fig. 6.). An oscillatory

current will flow from the dc source, through LD, thyristor

T-1, inductance L, commutation capacitor C, and thyristor

TA-2 to charge the capacitor to the voltage = 2ED, (t = t1).

At t = t1, the capacitor current reverses, and the energy stored on the capacitor is fed back to the source through diode D-1, inductance L, LD, source, and the diode DA-2. As the capacitor current increases, the current in thyristor T-1 will be reduced to zero at t = t2, thus transferring the total load cur- rent to the capacitor C. Excess commutation current ic - IL

will flow through diode D-1 which will reverse bias thyristor

T-1 and turn it off. After reaching the commutation peak,

capacitor current will sinusoidally decrease to the load cur- rent IL (t - t3). After t = t3, the capacitor will be discharged

at a constant current IL with the rate of

discharge given by

d V/dt = IL/C. At t = t4=h2r/(LD + L)C the thyristor pair TD-1 and TD-2 is triggered to ensure a complete discharge of

the commutation capacitor. Load current will be in fact trans-

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1062

1IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. IA-19, NO. 6, NOVEMBER/DECEMBER 1983

Fig. 5. One phase of three-level inverter with commutation circuit.

Vp=2ED

--II

/

t2

(a)

t3

t4

i~~~~

CAPACITOR CURRENT

CAPACITOR VOLTAGE

(b)

Fig. 6. Commutation current and voltage waveforms.

ferred to diode D-2 when the capacitor becomes unable to maintain it constant. Under ideal conditions, the capacitor will

be discharged to zero before TD-1 and TD-2 are triggered. At t = 27T\/(LD ±r L)C + RDC any required thyristor can be

triggered to transfer a current from diode D-2 to the required

thyristor. The total time to transfer current from one thyristor

to another can be given as follows:

t= 27r\(LD+L)C +RDC+

ILLD

E

d

(14)

An exception for this equation is the time required to transfer current to the thyristors at extreme positive and negative ref-

erences; for these cases, the transfer time is 2ir /(LD + L)C s.

If no commutation is called, the time for any appropriate cur-

TABLE II

TRIGGERING SEQUENqCE

CURRENT TRANSFER

POSITIVE

NE GATI VE

CURRENT

CURRENT

Positive to Zero T-1,TA-2,*,TZ1,TZ2 TZ1,TZ2

Reference

-Positive to

Neg- T-1,TA-2,*,T-2

T-2

ative Reference

Zero to Positive

T-1

T-2,TA-1,*,

Reference

T-1

Zero to

Nega-

T-1,TA-2,*,T-2

T-2

tive Reference

Negative to zero

TZl ,TZ2

T-2,TA-1,*,

Reference

TZI,TZ2

Negative to Posi-

T-1

T-2,TA-l,*,

tive

Reference

T-1

= Force commutation process is required. All remaining transfers may not call -for the commutation.

* Trigger after commutation delay, which also includes triggering of TD-1 and TD-2 to ensure complete discharge of commutation

capacitor.

rent transfer will be

t =

IL *OLD

ED

In conclusion, it appears that zero commutation voltage on a commutation capacitor gives the flexibility of programming any commutation sequence. As a result, any voltage reference

level can be applied to load at any instant, regardless of the

current direction. Also, it can be seen that any particular reference pair (or all pairs except extreme positive and nega-

tive) can be eliminated from the programmed sequence, by

blocking the pulses to thyristors, when the current is trans- ferred to either extreme positive or negative reference.

When all such pairs are blocked the inverter will behave like a conventional voltage source inverter. Table II shows the

triggering strategy for the proposed inverter.

IV. PWM OF A THREE-LEVEL WAVEFORM

A. Symmetrical Pulsewidth Modulation ofa Three-Level

Waveform

A three-level waveform of a single-phase half-bridge inverter

is shown in Fig. 3(c). To obtain a voltage control, symmetrical or uniform PWM technique can be applied to such a waveform if certain constraints are followed. It is well-known that with a sufficient number of switches per cycle, the harmonic con- tent of a modulated waveform approaches that of the base

envelope [6].

Fig. 7 shows how the uniform PWM scheme can be applied to the three-level inverter. The basic constraint followed is to

have an odd quarter-wave symmetry in a line-to-line voltage waveform. To have this symmetry and uniform pulsewidths, the 150° conduction period is divided into five equal seg-

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BHAGWAT AND STEFANOVIC: GENERALIZED STRUCTURE OF MULTILEVEL PWM INVERTER

1063

AAAAAtAAAAAAAAAAAA/

o~~onnnnn

TE~~~~~~~~~~~o n nuul

u~~~~~~Ld

u

.r.f.r.f.rd

U0

c

J

It

2

*(I * 1)

U.Uuuu,uu

5m pub" Fig. 7. PWM of three-level inverter.

ments. Ideally, each segment can have any number of equal width pulses. If m is any integer 1, 2, 3, , m, then to have the quarter- wave symmetry in an L - L waveform, the chopping fre- quency of the fixed amplitude triangle carrier should be 12

mf, where f is the frequency of the output waveform. With this condition satisfied, it follows that a) the number of pulses in the half-cycle of a phase voltage waveform will be 6m; b)

the number of pulses in the half-cycle of a line voltage will be 5m; c) the spacing between the center of each pulse will be 7r/6m rad; d) there will be 2m number of pulses with ampli- tudes equal to 0.5 ED; e) the number of pulses with the ampli- tude equal to ED will be 3m; f) the first pulse will be spaced at

(7/12) + (ir/12m) rad from the reference axis; h) If 6 is the

variable pulsewidth of a pulse, the theoretical maximum pulse- width will be A = iT/6m rad.

B. Harmonic Analysis of the Three-Level PWM Waveform

The Fourier expression for a waveform with an odd quarter- wave symmetry is

00

e(cot) = z A, sin nuc.t

n=l

where n is an odd number and

An =

4

7r

7ri/2

f(c,t) sin (ncwt)d(wt).

(15)

(16)

Analysis of a generalized line-to-line voltage with 5m

number of pulses per half-cycle will be divided into two

parts: a) when m is odd and b) when m is even.

From Fig. 1,

4

A --

12(

)+2

7r Jl2( 1+ m)6

O.5Ed sin(nct)(dct)

+ -

7T

4 Xlm)+6m6

f

I)6

(1+_m)+_;T -

2

O.5Ed sin (ncot) (dcot) +

4 12(+m)+(P-1) v+6

+-

J7(+ m -+p)6m 2

7T

2

ir r

6

OSEd05 sin (nwt) dwt

4 12m+2 +6-Ed sin (nct) (dwt) +--

+ 7r2

-4 1 2m

4

6

2

7r+1Tr +(P-1)6 +r 6

+ _

4+ 12mT+(p_ 1)67

6

Ed sin (nwt) (dwt)

I4

+- Ed sin (ncwt) (dcot).

7T

.7r_

2

5)

2

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1064

IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. IA-19, NO. 6, NOVEMBER/DECEMBER 1983

-=[(cos

4Ed

2P-1)[m

12F

Icosn

I~/2-

-cos n

F/I 6]]

12

r

---

- cos n

nt

-

+ 3_+_

12

L

p=L

m

_

2_

m

2p-1 )I1

6]]

12

2

m=

+

4Ed

nir

cosn

/Tr

f5

1--

\2

2/

4EdFm //r /2p-1

sin ()

/n5\

Isin )

(17)

+t2 -

± n+ (si

(sin (-2+ 3

\ 12\\

m

n

t

\2

(

/2p- 1 (2

+

m

2p

i

(

+)

Similarly, when n is even,

A =

±

nrr

n7r

~

Lp

1. m

/

(in

n-

F, (sin -

sin

\2

l) sin6 ))]

Isin

m2

(2))

(18)

(19)

I1

.ni

=)- .5

RELATIVE PULSE WIUTH

(a)

m =I

For the specific case, when m = 1, (18) becomes

A =

4Ed

nrr

n7r

n8

n7t

n6

sin -sin -+ 2 sin -sin-

6

2

3

2

nit

n6

+ sin-sin-.-

2

2

If K is the relative pulsewidth 6/A where A

An =

4Ed

niT

sin

nKrr

12

niT

niT

=

- r/6m,

nT1

[sin-+2sin-+sin-

6

3

2

(20

(21

and form = 2, substituting 6 = KA =TKr/6m,(9) becomes

 

4Ed

nKr

3nTr

5niT

An =

sin-

sin -

sin

 

nn'

24

24

24

 

lin1

+ 2sin 24

2

7n7r

2sin-±2

24

9niT

24

(2TJ

RELATIVE PULSE WIDTH

(b)

Fig. 8. Harmonic amplitude versus relative pulsewidth, m - 1.

C. Discussion

The set of Figs. 8(a)-10(b) illustrates the fundamental

plotted against the

relative pulsewidth for three different values of m. It can be

seen that for m = 1, the eleventh and thirteenth harmonics

can reach up to 37 and 31 percent of the fundamental, while

the twenty-third and twenty-fifth harmonics attain up to 17s8

and