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GATE - EC - 1990
(1) The op-Amp of fig. has a very poor open loop voltage gain of 45 but is otherwise ideal. The gain of the
Amplifier equals -
rV r || R 2
(A) a voltage source with voltage (B) a voltage source with voltage V
R1 || R 2 R1
r || R 2 V R2 V
(C) a current source with current (D) a current source with current
R1 + R 2 r R1 + R 2 r
It is desired to make full wave rectifier using above two half-wave rectifiers. The resultants circuit will be
(A) (B)
(C) (D)
(a)
(b)
(c)
The cut-off frequencies of F1 and F2 are f1 and f2 respectively. If f1<f2, the resultant circuit exhibits the
characteristic of a
(A) Band-pass filter (B) Band-stop filter
(C) All pass filter (D) High-Q filter
Ans. (B) VIDEO SOLUTION LINK
GATE - IN - 1996
(14) In the circuit shown in figure, if ei sin t , the voltage V0 is :
1 1
(A) 2 sin t (B) 2 sin t (C) sin t (D) sin t
4 4 2 4 2 4
The time t, in milliseconds, at which the output voltage vOUT crosses −10 V is
R2 e1 e1
(A) e0 e1 (B) e0 e1 (C) I (D) I
R1 R2 R1
Ans. (D) VIDEO SOLUTION LINK
GATE - IN - 2017
(18) The two-input voltage multiplier, shown in the figure has a scaling factor of 1 and produces voltage
output. If V1 15V and V2 3V , the value of the V0 in volt is _______.
1
(C) g m1 r01 || || r02 || r03
gm2
1
(D) g m1 r01 || || r03 || r02
g m3
(22) In the circuit shown below, capacitors C1 and C 2 are very large and shorts at the input frequency. v i is
(A) maximum
(B) minimum
(C) unity
(D) zero
(30) The sinusoidal ac source in the figure has an rms value of 20 V . Considering all possible value of R L ,
2
the minimum value of R S in to avoid burnout of the Zener diode is ______ .
(A) 105 rad / sec, 2 104 (B) 2 104 rad / sec, 2 104
(C) 2 104 rad / sec, 105 (D) 105 rad / sec, 105
GATE - EC - 1996
(33) The circuit shown in the figure is that of –
(A) +5V and -5V (B) +7V and -3V (C) +3V and -7V (D) +3V and -3V
Ans. (B) VIDEO SOLUTION LINK
GATE - IN - 2008
(36) In the op-amp circuit shown below the input voltage Vin is gradually increases from 0 V to +10V.
Assuming that the output voltage V0 saturates at – 10 V and +10V0 will change from
(A) 5 V in the positive slope only. (B) 5 V in the negative slope only.
(C) 5 V in the positive and negative slopes. (D) 3 V in the positive and negative slopes.
Ans. (A) VIDEO SOLUTION LINK
VIDEO SERIES ON
TOUGHEST ANALOG GATE PREVIOUS YEAR PROBLEMS [EC | EE | IN] PART 2
GATE - EC - 2017
(1) In the figure shown, the npn transistor acts as a switch
For the input Vin t as shown in the figure, the transistor switches between the cut-off and saturation
regions of operation, when T is large. Assume collector-to-emitter voltage at saturation VCEsat 0.2V and
base-to-emitter voltage. The minimum value of the common-base current gain ( ) of the transistor for
the switching should be :
GATE - EC - 2017
(2) In the figure, D1 is a real silicon pn junction diode with a drop of 0.7 V under forward bias condition and
D2 is a Zener diode with breakdown voltage of –6.8 V. The input Vin (t ) is a periodic square wave of
period T, whose one period is shown in the figure.
Assuming 10 T , where is the time constant of the circuit, the maximum and minimum values of
the output waveform are respectively.
GATE - IN - 2004
V
(4) The gain 0 of the amplifier circuit shown in figure is
Vi
(A) 8 (B) 4
3RL
(C) –4 (D)
R
Ans. (A) Video Solution Link
GATE - EE - 2017
VCC
(5) For the circuit shown in the figure below, it is given that VCE . The transistor has 29 and
2
VBE 0.7 V when the B-E junction is forward biased.
RB
For this circuit, the value of is :
R
(A) 43 (B) 92
(C) 121 (D) 129
Ans. (D) Video Solution Link
GATE - EE - 2005
(6) Consider the inverting amplifier, using an ideal operational amplifier shown in the figure. The designer
wishes to realize the input resistance seen by the small-signal source to be as large as possible, while
keeping the voltage gain between –10 and –25. The upper limit on R F is 1M . The value of R 1 should
be
R2 R2
(A) V (B) V
R R1
R2 R2
(C) V (D) V
R1 R(1 )
GATE - IN - 2011
(8) Assuming base-emitter voltage of 0.7 V and 99 of transistor Q1 , the output voltage V0 in the ideal
opamp circuit shown below is :
(A) –1 V (B) –1/3.3V
(C) 0 V (D) 2 V
Ans. (C) Video Solution Link
GATE - EE - 2015
(9) Consider the circuit shown in the figure. In this circuit R = 1k , and C = 1F . The input voltage is
sinusoidal with a frequency of 50 Hz, represented as a phasor with magnitude Vi and phase angle 0
radian as shown in the figure. The output voltage is represented as a phasor with magnitude V 0 and phase
angle radian. What is the value of the output phase angle (in radian) relative to the phase angle of
the input voltage?
(A) 0 (B)
(C) / 2 (D) / 2
Ans. (D) Video Solution Link
GATE - IN - 2015
(10) For the circuit shown in the figure, the rising edge triggered D-flip flop with asynchronous reset has a
clock frequency of 1 Hz. The NMOS transistor has an ON resistance of 1000 and an OFF resistance
of infinity. The nature of the output waveform is :
(A)
(B)
(C)
(D)
Ans. (A) Video Solution Link
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