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1 Universal Gates 2
5 Latches, S-R FF, J-K FF, D-FF , T-FF & M-S J-K Flip Flops. 24
Shift Left & Sift Right registers, SISO, SIPO, PISO & PIPO
6 29
Shift registers.
12 Mini Project
LIST OF EXPERIMENTS:
DIGITAL LOGIC & CIRCUIT LAB MANUAL 2
NATIONAL INSTITUTE OF TECHNOLOGY, PATNA
EXPERIMENT - 1
Universal Gates
OBJECTIVES: (i) Identification and verification of NAND gate (IC chip #7400) and NOR gate
(IC chip #7402).
(ii) Construction and Verification of all other gate (AND, OR, NOT, XOR &
XNOR) USING
a) Only NOR gate
b) Only NAND gate
MATERIAL REQUIRED:
OBJECTIVE-1
NAND Gate: The NAND gate is a contraction of AND-NOT. The output is high when both
inputs are low and any one of the input is low .The output is low level when both inputs are
high.
NOR Gate: The NOR gate is a contraction of OR-NOT. The output is high when both inputs
DIGITAL LOGIC & CIRCUIT LAB MANUAL 3
NATIONAL INSTITUTE OF TECHNOLOGY, PATNA
are low. The output is low when one or both inputs are high.
OBJECTIVE-2
Universal Gates: Universal Gates are those gates from which all other gates can be made.
NAND & NOR gates are called as Universal gates.
A Y =A'
A
B
Y=A B
Y=A+B
B
A'
B
Y = A'B+AB'
A
B'
XNOR Gate Using NAND Gate:
A'
B'
A A'B' + AB
B
A
Y =A'
B Y=A B
B Y=A+B
XOR Gate Using NOR:
A'
B'
Y= A'B +AB'
A
B
A A'B' + AB
B'
PROCEDURE:
DIGITAL LOGIC & CIRCUIT LAB MANUAL 5
NATIONAL INSTITUTE OF TECHNOLOGY, PATNA
INPUT OUTPUT
-----
A B Y= A+B
0 0 1
0 1 0
1 0 0
1 1 0
Truth Table 0f NOT Using NAND/NOR Gate Truth Table Of AND Using NAND/NOR Gate
INPUT OUTPUT
A B Y= AB
0 0 0
0 1 0
1 0 0
1 1 1
INPUT OUTPUT
A B Y= A+B
0 0 0
0 1 1
1 0 1
1 1 1
RESULT: Truth table of NAND and NOR gates are checked and other gates using NAND
/NOR gates are constructed and verified.
EXPERIMENT - 2
OBJECTIVES:
(i) Identification & verification of NOT (7404), AND (7408) OR (7432) & XOR (7486)
gates.
(ii) Designing, construction and verification of Binary to Gray convertor and Grey to
Binary convertor.
(iii) Design, construction and verification of 3-bit Parity Generator and 4-bit odd parity
checker circuit.
MATERIAL REQUIRED:
Sl. No. Equipment/ Component Name Specification Qty.
1 NOT Gate IC # 7404 1
2 AND Gate IC # 7408 1
3 OR Gate IC # 7432 1
4 XOR Gate IC # 7486 1
5 LED - 3
6 Resistor 330 Ω 3
7 Breadboard - 1
8 DC Power Supply 5 Volt 1
9 Connecting Wires - -
THEORY:
OBJECTIVE -1:
NOT Gate: The NOT gate is called an inverter. The output is high when the input is low.
The output is low when the input is high.
AND Gate: The AND gate performs a logical multiplication commonly known as AND
function. The output is high when both the inputs are high. The output is low level when any
one of the inputs is low.
DIGITAL LOGIC & CIRCUIT LAB MANUAL 8
NATIONAL INSTITUTE OF TECHNOLOGY, PATNA
OBJECTIVE-2:
Truth Table:
Logic Functions: G2 = B2
G1 = B2 XOR B1
G0 = B1 XOR B0
Logic Diagram:
B2 G2
G1
B1
G0
B0
Truth Table:
Logic Functions: B2 = G2
B1 = B2 XOR G1
B0 = B1 XOR G0
DIGITAL LOGIC & CIRCUIT LAB MANUAL 10
NATIONAL INSTITUTE OF TECHNOLOGY, PATNA
Logic Diagram:
G2
B2
G1 B1
B0
G0
OBJECTIVE- 3:
Basic Principle to generate the parity bit is “the module sum of even number of 1’s is
0 and the module sum of odd number of 1’s is 1. Parity Generator generates a bit to pair
with the code group so as to make the number of 1’s either odd or even as desired at the
transmitter side.
Truth Table:
Input Output
X Y Z Peven Podd
0 0 0 0 1
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 0
Podd = X (Y Z)
X
Y
P
Z even
X
Y
P
Z odd
DIGITAL LOGIC & CIRCUIT LAB MANUAL 11
NATIONAL INSTITUTE OF TECHNOLOGY, PATNA
At Receiver, checks each code group to see that the total number of 1’s (including
Parity bit) is consistent with the agreed upon type of Parity (with Transmitter).
Logic Diagram:
X
Y
P
(Parity Bit) P
checker
1 (Even)
0 (Odd)
PROCEDURE:
INPUT OUTPUT
A B Y= AB
0 0 0
0 1 0
1 0 0
1 1 1
Truth Table of OR Gate: Truth Table of 3 Bit Binary to Gray Code Converter
0 1 0 0 1 1
0 1 1 0 1 0
1 0 0 1 1 0
1 0 1 1 1 1
1 1 0 1 0 1
1 1 1 1 0 0
Truth Table of 3 Bit Gray to Binary Code
Converter Truth Table of 3 Bit Even/Odd Parity Generator
Input Output
X Y Z Peven Podd
0 0 0 0 1
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 0
Input Output
X Y Z P Pchecker
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
RESULT: Binary to Gary code, Gary to binary code converter and parity generator and
checker circuits are constructed and their truth tables are verified.
EXPERIMENT – 3
(i) Design, construction and verification of Half Adder and Half Subtractor circuit.
DIGITAL LOGIC & CIRCUIT LAB MANUAL 13
NATIONAL INSTITUTE OF TECHNOLOGY, PATNA
(ii) Design, construction and verification of Full Adder and Full Subtractor circuit.
(iii) Design, construction and verification of 1-bit and 4-bit Magnitude comparator.
MATERIAL REQUIRED:
Logic Diagram:
A
S
B
Half Subtractor: It subtracts two binary digits (X & Y) results Difference output (D) & a
Borrow Output (B).
Truth Table:
Input Output
X Y D B
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0
DIGITAL LOGIC & CIRCUIT LAB MANUAL 14
NATIONAL INSTITUTE OF TECHNOLOGY, PATNA
Logic Diagram:
X
D
Y
OBJECTIVE-2:
Full Adder: It adds three binary digits (A, B & Cin). Cin is the carry resulted from the
previous addition. It gives a sum Output (S) and a Carry output (C out).
Truth Table:
Input Output
A B Cin S Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
-- -- -- -- -- --
Logic Functions: S = A B Cin + A B Cin + A B Cin + A B Cin
-- -- -- -- --
= Cin (A B + A B) + Cin (A B + A B)
= Cin A B
-- -- --
Cout = A B Cin + A B Cin + A B Cin + A B Cin
-- --
= Cin (A B + A B) + A B
= Cin (A B) + A B
A
B
S
Cin
Cout
Full Subtractor: It subtracts three binary digits (X, Y & Bin). Bin is the borrow input. It gives
a Difference Output (D) and a Borrow output (Bout).
Truth Table:
Input Output
X Y Bin D Bout
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
-- -- -- -- -- --
Logic Functions: D = X Y Bin + X Y Bin + X Y Bin + X Y Bin
-- -- -- -- --
= Bin (X Y + X Y ) + Bin (X Y + X Y)
= Bin X Y
-- -- -- -- --
Bout = X Y Bin + X Y Bin + X Y Bin + X Y Bin
------------ ---
= Bin (X Y ) + X Y
X
Y
D
Bin
Bout
OBJECTIVE-3:
Magnitude Comparator:
It is a combinational logic circuit that compares two input binary quantities and
generates output to indicate which one has greater magnitude.
Input Output
A B A>B A=B A<B
0 0 0 1 0
0 1 0 0 1
1 0 1 0 0
1 1 0 1 0
Logic Functions: A > B = A’B
A < B = AB’
Logic Diagram:
A<B
A
A=B
B
A>B
7485 is a 4 Bit Magnitude Comparator IC. A0, A1, A2, A3 and B0, B1, B2, B3 are the
two binary inputs to be compared.
DIGITAL LOGIC & CIRCUIT LAB MANUAL 17
NATIONAL INSTITUTE OF TECHNOLOGY, PATNA
15 A3 (A>B)OUT 5
1 B3 (A=B)OUT 6
13 A2 (A<B)OUT 7
14 B2
12 A1
11
10
B1
A0
7485N
9 B0
4 (A>B)IN
3 (A=B)IN
2 (A<B)IN
PROCEDURE:
PRECAUTION:
EXPERIMENT – 4
Decoder, Encoder, Multiplexer & De-Multiplexer
OBJECTIVES: (i) Construction and verification of BCD to 7-segment decoder using IC #7447.
(ii) Construction and verification of 8 to 3 line Encoder circuits.
DIGITAL LOGIC & CIRCUIT LAB MANUAL 18
NATIONAL INSTITUTE OF TECHNOLOGY, PATNA
Blank output and Blank input are used to blank the digit zero on the display.
VCC 5V
U2
7 Com
13
A OA U3
A 1 12
B OB SEVEN_SEG_COM_K
2
B C OC
11
6 10
C D OD
9 AB CDE FG
D 3 OE
15
5 LT OF
14
4 RBI OG
BI/RBO
7447N
OBJECTIVE-3
MULTIPLEXER: It selects one input among many at a time and sends it to the output line.
For an n – input MUX, m select inputs are required, where n = 2m.
4:1 MUX: 4 inputs (I0, I1, I2, I3) and 2 select inputs (S0, S1)
Block Diagram of 4:1 MUX:
DIGITAL LOGIC & CIRCUIT LAB MANUAL 20
NATIONAL INSTITUTE OF TECHNOLOGY, PATNA
I0
I1
I2 Y
I3
4 I0 Y 5
3 I1
2 I2 ~W 6
1 I3
15 I4
14 I5
13 I6
12 I7
11 S0
10 S2
9 S1
7 E
74151N 8 10
E0 W
7 E1
16:1 MUX: 74150 is 16:1 multiplexer IC 6
5
E2
E3
4 E4
3 E5
2 E6
1 E7
23 E8
22 E9
21 E10
20 E11
19 E12
18 E13
17 E14
16 E15
15 A
14 B
13 C
11 D
9 G
OBJECTIVE - 4
74150N
DEMULTIPLEXER: Accepts a single input and distributes it
on one among several outputs
according to selector input value.
1:4 DEMUX: 2 select inputs and 4 output lines.
DIGITAL LOGIC & CIRCUIT LAB MANUAL 21
NATIONAL INSTITUTE OF TECHNOLOGY, PATNA
Block Diagram:
I
Y0
Y1
Y2
Y3
OBSERVATION TABLES:
OBJECTIVE – 1: BCD to 7 Segment Decoder
Display
D C B A a b c d e f g
0 0 0 0 1 1 1 1 1 1 0
0 0 0 1 0 1 1 0 0 0 0
.
.
.
.
1 0 0 1
Select
Output
Inputs
S1 S0 Y
0 0 I0
0 1 I1
1 0 I2
1 1 I3
DIGITAL LOGIC & CIRCUIT LAB MANUAL 23
NATIONAL INSTITUTE OF TECHNOLOGY, PATNA
Data Select
Outputs
Input Inputs
I S1 S0 Y0 Y1 Y2 Y3
1 0 0 1 0 0 0
1 0 1 0 1 0 0
1 1 0 0 0 1 0
1 1 1 0 0 0 1
RESULT: By 7447 and seven segment display, the display of decimal digits from 0 to 9
is done and the truth tables of multiplexer and de-multiplexer are verified.
EXPERIMENT – 5
Latches, S-R FF, J-K FF, D-FF , T-FF & M-S J-K Flip Flops.
DIGITAL LOGIC & CIRCUIT LAB MANUAL 24
NATIONAL INSTITUTE OF TECHNOLOGY, PATNA
OBJECTIVES:
(i) Construction and Verification of a Latch circuit using NAND/NOR gates.
(ii) Construction and Verification of S-R Flip Flop using above Latch circuits.
(iii) Verification of J-K Flip Flop using IC # 7476 (Dual J-KFF)
(iv) Construction and Verification of D-Flip Flop and T-Flip Flop using J-K FF(IC #7476).
(v) Construction and Verification of Master Slave J-K Flip Flop.
MATERIAL REQUIRED:
OBJECTIVE-1:
LATCH: 1 Bit information can be locked or latched. It consists of two inverters. There
is no provision to get any desired digital information we wish to store in the latch.
Q'
OBJECTIVE – 2
S -R FLIP-FLOP:
DIGITAL LOGIC & CIRCUIT LAB MANUAL 25
NATIONAL INSTITUTE OF TECHNOLOGY, PATNA
S
Q
CLK
Q'
R
OBJECTIVE – 3
J-K FLIP-FLOP: 7476 is a dual negative edge triggered J-K Flip-flop IC.
2
~PRE
4 J Q 15
1 CLK
16 1K ~Q 14
~CLR
OBJECTIVE – 4
2
~PRE
D 4 15
J Q
1 CLK
16 1K ~Q 14
~CLR
3
2
~PRE
4 15
T J Q
1 CLK
16 1K ~Q 14
~CLR
3
OBJECTIVE – 5:
PROCEDURE:
OBSERVATION TABLES:
OBJECTIVE- 1: LATCH
Q Q’
0 1
1 0
CLK D Q Q’
Π 0 0 1
Π 1 1 0
Truth Table of T FF
Π 1 Qn’ Qn Toggle
DIGITAL LOGIC & CIRCUIT LAB MANUAL 28
NATIONAL INSTITUTE OF TECHNOLOGY, PATNA
Π 1 0 1 0 Reset
Π 1 1 Qn’ Qn Toggle
RESULT: Latch using NAND and NOR gates, and different flip-flops are constructed and
verified their truth tables.
EXPERIMENT – 6
Shift Left & Sift Right registers, SISO, SIPO, PISO & PIPO Shift registers.
(iii) Construction and verification of a 2-bit Shift Left Register using IC # 7474.
(iv) Verification of SISO, SIPO, PISO & PIPO Shift Registers.
MATERIAL REQUIRED:
OBJECTIVE-1: D Flip-flop:
4
~PRE1
2 D1 Q1 5
3 CLK1 ~Q1 6
~CLR1
1
~CLR1 ~CLR2
1 1
Data
Output
4 4
Data
~PRE1 Q1 Input ~PRE2
Q2
2 D1 Q1 5 2 D2 Q2 5
~CLR1 ~CLR2
1 1
OBJECTIVE- 4:
4 4
Q2
~PRE1 ~PRE2
Serial Data Input Serial Data Output
2 D1 Q1 5 2 D2 Q2 5
~CLR1 ~CLR2
1 1
4 Q1 4
Q2
~PRE1 ~PRE2
Serial Data Input
2 D1 Q1 5 2 D2 Q2 5
~CLR1 ~CLR2
1 1
____
Shift/Load
D2
D1
4 4
Q2
~PRE1 ~PRE2
Serial Data Out
2 D1 Q1 5 2 D2 Q2 5
D1 D2
4 4
~PRE1 ~PRE2
2 D1 Q1 5 2 D2 Q2 5
~CLR1 ~CLR2
1 1
Q1 Q2
Parallel Output Data
PROCEDURE:
DIGITAL LOGIC & CIRCUIT LAB MANUAL 32
NATIONAL INSTITUTE OF TECHNOLOGY, PATNA
OBSERVATION TABLES:
DIGITAL LOGIC & CIRCUIT LAB MANUAL 33
NATIONAL INSTITUTE OF TECHNOLOGY, PATNA
CLK Data Q1 Q2
0
1 0
0
Π 1 1
Π 1
CLK Q1 Q2 Data
0 1
0
Π 1 1
0
Π 1 1
1 0 0
Π 1 1 0
Π 1 1 1
Serial
Parallel Data
Data
Input
Output
Shift/Load CLK D1 D2 Q1 Q2
0 1 1 0 0
0 Π 1 1 1 1
1 Π 0 0 0 1
EXPERIMENT – 7
(ii) Construction and verification of Mod-3 up and Mod-3 down synchronous counter.
(iii) Construction and verification of 2-bit Ring counter using J-K FF.
(iv) Construction and verification of 2-bit twisted Ring (Johnson) counter using J-K FF.
MATERIAL REQUIRED:
Ripple counter is the simplest type of counter in which flip-flops are not clocked
simultaneously. The output of previous FF becomes the clock input for next FF. The inputs J
and K of the FF are connected to logic 1.
Q0 Q1
1 1 1 1
~PRE ~PRE
J0 Q0 J1 Q1
CLK CLK
K0 ~Q0 K1 ~Q1
CLK
~CLR ~CLR
1
1
Counting Table:
CLK Q1 Q0 Counting
State
0 0 0
Π 0 1 1
Π 1 0 2
Π 1 1 3
DIGITAL LOGIC & CIRCUIT LAB MANUAL 36
NATIONAL INSTITUTE OF TECHNOLOGY, PATNA
Synchronous counters are the counters which are clocked such that each FF in the
counter is triggered at the same time.
Design
Step-2:
0 0 0 1 0 X 1 X
0 1 1 0 1 X X 1
1 0 0 0 X 1 0 X
Step-3: Using K-map, Find the desired value for J0, K0, J1 & K1
For J1 For K1
Q0
Q1 0 1
0 0 1
1 X X
DIGITAL LOGIC & CIRCUIT LAB MANUAL 37
NATIONAL INSTITUTE OF TECHNOLOGY, PATNA
J1 = Q0 K1 = 1
For J0 For K0
Q0
Q1 0 1
0 1 X
1 0 X J0 = Q1’ K0 = 1
Q0 Q1
1 1
~PRE ~PRE
J0 Q0 J1 Q1
CLK CLK
K0 ~Q0 K1 ~Q1
CLK 1 ~CLR
1 ~CLR
1
1
Similar way we can design the circuit for Mod 3 down synchronous counter
Q0 Q1
1 1
~PRE ~PRE
J0 Q0 J1 Q1
CLK CLK
K0 ~Q0 K1 ~Q1
CLK 1 1
~CLR ~CLR
1
1
Ring Counter is a SISO shift register with the output of last flip-flop is connected back
to input of the first flip-flop.
Q0 Q1
1 1
~PRE ~PRE
J0 Q0 J1 Q1
CLK CLK
K0 ~Q0 K1 ~Q1
CLK
~CLR ~CLR
1
1
Counting Table:
In this, output of each flip-flop stage is connected to the input of next stage but Q’
output of last stage is connected to input of first stage.
Q0 Q1
1 1
~PRE ~PRE
J0 Q0 J1 Q1
CLK CLK
K0 ~Q0 K1 ~Q1
CLK
~CLR ~CLR
1
1
Counting Table:
CLK Q1 Q0
0 0
Π 0 1
Π 1 1
Π 1 0
PROCEDURE: Π 0 0
DIGITAL LOGIC & CIRCUIT LAB MANUAL 39
NATIONAL INSTITUTE OF TECHNOLOGY, PATNA
3. Apply clock pulses and note the outputs after each clock pulse of counters.
PRECAUTIONS:
RESULT: Asynchronous and Synchronous counters are constructed and their counting tables
are verified.
EXPERIMENT -8
MATERIAL REQUIRED:
Sl.
Equipment/ Component Name Specification Qty.
No.
1 555 Timer 555 1
2 Potentiometer 100KΩ 2
3 Capacitor 0.01µF 2
4 Breadboard - 1
5 Cathode Ray Oscilloscope 30 MHz 1
6 DC Power Supply 5 Volt 1
7 Connecting Wires Single Strand -
THEORY:
OBJECTIVE -1
Pin Diagram of 555 Timer:
GND + Vcc
Discharge
Trigger
IC 555
Threshold
output
Control voltage
Reset
ASTABLE MULTIVIBRATOR
An astable multivibrator is a multivibrator with no stable state. It has two states and
both of them are quasi-stable. The moment it is connected to the supply, it keeps on
switching back and forth between its quasi-stable states.
Astable Multivibrator Using 555 Timer:
Circuit Diagram:
DIGITAL LOGIC & CIRCUIT LAB MANUAL 41
NATIONAL INSTITUTE OF TECHNOLOGY, PATNA
Vcc = 5V/12V
RA
33kohm
8
4 VCC
RB RST
7 3
Vout
30-60Kohm
6 DIS OUT
2 THR 555
TRI
5 TIMER
CON
GND
1
0.01uF
0.01uF
The capacitor C1 charges through the resistance RA and RB and discharges through the
resistance RB only. The capacitor charges and discharges between 1/3 Vcc to 2/3 Vcc.
Charging time of the capacitor is given by = TON = 0.693 (RA+RB) C1
Discharging time of the capacitor = TOFF = 0.693 RB C1
Time Period = T = TON +TOFF = 0.693 (RA + 2 RB) C1
Frequency of Oscillation = f = 1 / T.
% of Duty Cycle = (TON/ T) x 100.
PROCEDURE:
1 30
2 60
OBJECTIVE – 2
MONOSTABLE MULTIVIBRATOR:
It has one stable state. When triggered, it changes from its stable state to quasi-
stable state and returns back to its stable state.
Circuit Diagram:
DIGITAL LOGIC & CIRCUIT LAB MANUAL 43
NATIONAL INSTITUTE OF TECHNOLOGY, PATNA
+Vcc
8
50%
4 VCC
RST
7 3
6 DIS OUT Vout
2 THR
C TRI
5
8200pF CON
GND
Trigger 1
C2
2200pF
When Timer 555 is connected in monostable mode, trigger input is given through pin 2.
PROCEDURE:
OBSERVATION TABLE:
1 30
2 40
3 50
RESULT: Verified the working of 555 Timer as Astable and Monostable mutivibrator and
DIGITAL LOGIC & CIRCUIT LAB MANUAL 44
NATIONAL INSTITUTE OF TECHNOLOGY, PATNA
EXPERIMENT – 9
MATERIAL REQUIRED:
Sl.
Equipment/ Component Name Specification Qty.
No.
1 DAC Trainer Kit - 1
2 ADC Trainer Kit - 1
3 Digital Multimeter - 1
4 DC Power Supply 0-30V 1
THEORY: OBJECTIVE -1:
Circuit Diagram:
DIGITAL LOGIC & CIRCUIT LAB MANUAL 45
NATIONAL INSTITUTE OF TECHNOLOGY, PATNA
Vref = 5V
R/2
GND
B3
Vcc
R
B2
2R
Vout
B1
4R Vee
B0 8R
4 Binary inputs (B0, B1, B2 and B3) results, 24 = 16 analog output values.
Working:
o/p voltage op-amp (Vout) due to all four inputs (B0, B1, B2 and B3) is
= V1 +V2+ V3 + V4
= - Vref { (B0/16) + (B1/8) + (B2/4) + (B3/2)}
Circuit Diagram:
DIGITAL LOGIC & CIRCUIT LAB MANUAL 46
NATIONAL INSTITUTE OF TECHNOLOGY, PATNA
2R
Vcc
R R R 2R
2R 2R 2R 2R
2R
Vout
B1 Vee
B3 B2 B0
GND
Vref = 5V
PROCEDURE:
1. Connect the wires in the Trainer kit as per the circuit diagram.
2. Connect reference voltage point Vref to +5 Volt.
3. Apply different combination of 4 bit binary inputs (B0, B1, B2 and B3) and
measure the analog voltage at the output of op-amp (Vout) by multimeter.
4. Tabulate the readings in the observation table.
Vref = 5 Volt
OBJECTIVE – 2
DIGITAL LOGIC & CIRCUIT LAB MANUAL 47
NATIONAL INSTITUTE OF TECHNOLOGY, PATNA
The Counter type ADC is the basic type of ADC which is also called as digital ramp
type ADC or stair case approximation ADC. This circuit consists of N bit counter, DAC and Op-
amp comparator as shown in below figure.
The N bit counter generates an n bit digital output which is applied as an input to the
DAC. The analog output corresponding to the digital input from DAC is compared with the
input analog voltage using an op-amp comparator. The op-amp compares the two voltages
and if the generated DAC voltage is less, it generates a high pulse to the N bit counter as a
clock pulse to increment the counter. The same process will be repeated until the DAC
output equals to the input analog voltage.
If the DAC output voltage is equal to the input analog voltage, then it generates low
clock pulse and it also generates a clear signal to the counter and load signal to the storage
resistor to store the corresponding digital bits. These digital values are closely matched with
the input analog values with small quantization error.
The maximum conversion of Counter type ADC is = (2N-1) T
Where, T is the time period of clock pulse.
If N=2 bit then the Tmax = 3T.
PROCEDURE:
1. Connect the wires in the Trainer kit as per the circuit diagram.
2. Apply analog voltage at the input and observe digital output from the output
LEDs of the trainer kit.
3. Tabulate the readings in the observation table.
RESULT: Verified the conversion of digital input to analog voltage through weighted resistor
and R-2R ladder type DAC. Also verified the conversion of analog voltge into digital
quantity by counter type and successive approximation method.