Week 7: Weekly Report

Saurabh Chaubey
27th Nov
 Status Update: Till 26th Nov
# Tasks Status Internal Comments
Deadline
1 May Tape-out Re- Ongoing: 1st Dec Testing the (¾) and (2/3) modes
Started on 16th 300mA and above loads
Testing
Nov.
2 Inductive Converter Completed Not time Converting notes into
Modelling bound PPTs and PDFs for future
ref.
3 Journal Paper: First Ongoing: To 3rd Dec A 10 page first draft of the
Draft be completed CICC invited capacitive
(Capacitive Converter) modelling paper
4 PCB/Bonding Diagram Completed 1st Dec Would complete by 1 Dec
for OCT. Tapeout
5 Analysis of having 3.3 Ongoing Not time (Optional)
V input voltage (SRC bound Changes required in
feedback) programmable converter
for 3.3 V input

University of Minnesota © Ramesh Harjani 2

Tasks Done:
 Completed PCB for OCT 2015
 Working on first draft of CICC invited paper’s Journal
version
 Testing of May Tapeout chip
 Recording high load conditions
 Efficiency for high power range (>300mW)
 69%! Measured Vs 78% simulated
 IR Loss not accounted in simulated
 Completed the Analysis of Inductive Converter Modelling
 Average Model
 Inductive Vs Capacitive modelling
 Step by Step design of inductive
 Frequency Modeling
 Working on analysis of 3.3 V programmable DC-DC
converter
University of Minnesota © Ramesh Harjani 3
 Glimpse of Inductive Modelling
 Average signal model

 Gives insight to the critical parameters

 Assumptions
 Ctank is present (And large)
 Switches should snap instantly (Can be non ideal though!)
 Always to remain in Continuous Conduction Mode (CCM)
 All parasitic can be lumped
 Similarity and differences between capacitive and
inductive converter modelling (Important !)
 Step by Step Design for inductive

University of Minnesota © Ramesh Harjani 4

Types of Inductive Converters
 Exactly like capacitive, we can classify them as:
 Buck
 Boost
 Negative

 Model them as DC-Average transformer Model

 Model the losses

 Step by step design

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 Modelling Inductive Converter

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Average Modelling Vin
Ф1 Ф2
Active Low
IL IL Vo
Ф1 Vo
VA
VA
Ф2
PMOS
Active

Ф1

Vo , avg  DVin ; D  Duty  cycle Ф2

dI L V t VA Vo=DVin
L  Vo  I L   0 ;  2
dt L
dI L (Vin  Vo )t
L  Vin  Vo  I L  ; 1 IL
dt L

University of Minnesota © Ramesh Harjani 7

NEW: Average Model Continued

Iin Ф1 Ф1
IL
Vo Ф2

IL I out , Avg
Ic Iout,avg

Iin I in, Avg

Really Important

Ig
Ф2
IL
Vo
Ic
Ig
Ic
Vo Vout , Avg
Iout,avg
Vp-p

t
University of Minnesota © Ramesh Harjani 8
Assumptions (Extra than usual):
 Cfilter provides low impedance path
 How low? Let us see..(Say, for 100mA, 0.5V output voltage, 500MHz)
30
25
• Model predicts with 98% accuracy for a filter
% Error

20
cap of 2nF. More the cap more the accuracy.
15
10
• All the wave forms plotted in slide 6, 7 follow
5
almost exactly the Spice simulation
0
0 0.2 0.4 0.6 0.8 1
x 10-8
Filter Capacitor
 NMOS is deep(est) triode (Really Important!)
 Switches snap instantly (Otherwise a snapping type of loss)*
 Average Model (Not very useful for CMOS technology! )
I in, Avg   V out, Avg D
I out, Avg  V in, Avg  D=Duty Cycle
* To be discussed later
University of Minnesota © Ramesh Harjani 9
 Average Inductive Model
Rloss  ESR  1/ D  RMOS ,ON
2

Vin
Iin Iin Rloss
Vo + Io +

Io Vin Vo
DIo DVin
- -

Rloss=ESR of Inductor+Referred Loss

I   V D Vin  Vo  (D)  DVin  I o Rloss  (Io )  1

n
in, Avg out, Avg
I  lim
I
out, Avg  V in, Avg  L , pp
Lf s Rloss 0 Vin I in

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 Inductive Model Vs Capacitive Model
Iin Rloss Iin
Rcond
+ Io + + Io +

Vin Vo Vin Vo
DIo DVin KIo KVin
- - - K:1 -

• Io is independent of Rloss !! • Io = (KVin-Vo)/Rcond

• Theoretically Rloss can be • Rcond cannot be zero for
zero for finite Io finite Io
• eff->1 (For zero Rloss) • eff->0 (For zero Rcond)

I in, Avg   V D

out, Avg I in, Avg   Vout, Avg 1
I out, Avg  V 
in, Avg I
out, Avg  V in, Avg  k
n  lim
 DVin  I o Rloss  (Io )  1 n
Vo
Rloss 0 Vin I in Vin
University of Minnesota © Ramesh Harjani 11
Approximate Frequency Domain Model
I call it “2 pole 1 zero model”
 
Vo(s)  Vin   (1  srC) 
L   
d ( s )  LC   (s 2  s( 1  r )  1 ) 
+
 RC L LC 
C
Veq R Vo(s)
r
Vo(s)  (1  srC) 
-   R 
Io( s )  (1  sRC ) 
Equivalent Model of
Buck For Freq Analysis
1 UGB

LC 100
University of Minnesota © Ramesh Harjani 12
Open Loop Design Considerations
Vin
1. Typical given/know
 Vout, Vin, Iout I L , pp 
Vin  Vo  (D)
Iin  CCM only! Lf s
Vo  So L*fs known
Io
2. Voltage ripple VC, pp 
Vin  Vo  (D)
LCf s 2
 C*F fixed
3. L to be minimized [Best
Rloss=25mΩ/nH]
4. L-C product should be more!
(Stabilty)
5. L/C known 

University of Minnesota © Ramesh Harjani 13

 Simple Open Loop Design Example
Specs Value Vin
Note: It can be exact
Vin 1.2V Iin
(1.2)/2 unlike
Vout 0.6V capacitive converter Vo

Iout 100mA Io

Ripple-pp 30mV
UGB 100GHz

1. Step 1:
Fixing the duty cycle (First Cut)

V0
D  0.5
Vin

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Continued
 Step 2:
 We know that: I L , pp 
Vin  Vo  (D)
Lf s

I out , Avg
 Also from slide 7 we know I L, pp   50mA
2
 So we know L*fs product
 L.fs = 6

Lf s 
Vin  Vo  (D) 0.6(0.5)
 6
I L , pp 0.05

University of Minnesota © Ramesh Harjani 15

Continued
 Step 3: (C-Fs Product)
 Slide 7 tells us voltage ripple as VC, pp 
Vin  Vo  (D)
LCf s 2

 Ripple is 30mV peak to peak so,

C. f 
Vin  Vo  (D)

0.6(0.5)
 0.1667
Lf VC, pp s (6)(0.03)

 Step 4: (L/C becomes known)

 From step 2 and 3, L/C is 36 !

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Continued
 Step 5: For stability (Slide 11):
1 UGB
 𝐿𝐶 = 10−18
LC 100 Vin
Iin
 From step 3 L  6nH Vo
L
 36 Io
C C  1nF

 So, L  6nH
Fopt  1GHz
C  1nF

University of Minnesota © Ramesh Harjani 17

Summary of Inductive Modelling
 Average model predicts upto 98% accuracy easily (Only
in CCM –Continuous Conduction Mode)
 Fundamental difference in loss modelling than capacitive
converter
 Open loop design easy (5 steps)
 Frequency Domain:
 Just two poles and 1 zero explains the overall complicated transfer
function multipole inductive converter
 Switch sizing is recursive and not very critical!
 Slides in making
 PID analog control loop analysis has been completed. Slides will
be attached in next weekly report.
 Complete simulation of model Vs Spectre
University of Minnesota © Ramesh Harjani 18