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Volume 4 Issue 2
Abstract
Field Programmable Gate Arrays is an empowering technology for
application-oriented systems, providing a means for rapid prototyping and
evaluation, as well as algorithm acceleration. Many FPGA vendors have
recently started experimenting with embedded processors in their devices, like
Xilinx with ARM Cortex A cores, together with programmable logic cells.
These are known as Programmable System on Chip (PSoC). These ARM cores
(embedded in the Processing System or PS) communicate with the
programmable logic cells (PL) using ARM standard AXI buses. The hardware
setup used in this project is Zedboard along with ADFMCOMMS2-EBZ is a
high speed analog module which has preinstalled IIO OSCILLOSCOPE and
GNU RADIO software. The IIO OSCILLSCOPE Linux Application supports
different plots for real time processing and analyzing the signals obtained
from the antennas of the analog module. This application captures the desired
incoming RF signal in the IIO OSCILLOSCOPE wherein the entire
computation is run on to the PS, while the FPGA fabric remained idle during
this process. During profiling it was found that the most computational
expensive block is Fast Fourier transform (FFT) block that took a longer time
to display the output. So to lessen the computation time we transfer the FFT
block on to the PL side via AXI buses to communicate to the PS side of the
board. Due to the parallel nature of FPGA the capability to calculate large
mathematical calculation can be made smoother and in lesser time period.
Xilinx Vivado suite offers the designer a The essential part of the Zedboard is that
variety of environment to work on the the PS and PL are both linked by a series
zedboard that includes flexible design, of interfaces which follow the AMBA
support for designing and testing of IP AXI4 interconnect standard as seen in Fig-
blocks which can be used and reused for 1. This interface enables a designer to
various design approach. The Zedboard’s implement custom logic blocks according
powerful mix of on-board peripherals and to their requirements in the PL which can
expansion capabilities make it an ideal then be connected to the PS and also
platform for both starter and experienced extend the range of peripherals that are on
designer. This board contains everything the AXI bus are easily available and are
that is necessary for any developer to visible on to the processor’s memory map
create a Linux, Android, Windows® or through the use of software.
other OS/RTOS based design.
C. AD9361- ANALOG DEVICES
The Zynq SOC chip consist of 2 major The AD-FMComms2-EBZ is an FPGA
sections Mezzanine Cards (FMC) board for
PS: Processing System AD9361,a highly integrated RF Agile
Dual ARM Cortex-A9 processors, Transceiver™. The purpose of the AD-
866 MHz to 1GHz frequency. FMComms2-EBZ is to provide an RF
Multiple peripherals platform which shows the greater extent
Hard silicon core performance of the AD9361.
Dedicated DDR memory controller
The expected performance displayed by
PL: Programmable Logic this platform according to the datasheet
Logic cells – 28k-44k specification is up to 2.4GHz frequency.
AD converter – two 12 bits This device combines an RF front end with
Provides the user the ability to a flexible mixed- signal baseband section
develop their own custom logic or and integrated frequency synthesizers,
IP which can work in conjunction simplifying design-in by providing a
with the software running on configurable digital interface to a
processor core. processor or FPGA as seen in Fig-2
Zedboard is interfaced with AD9361.
The Fast Fourier Transform code that is Making use of synchronization pulse to
used in this project is composed of a series keep track of the butterfly output and a
of stages. These stages right from the start counter which is used to keep things
are split into an even and odd stage. The aligned, produces the first pulse, next N/4
first stage is numbered N according to the clock cycles will produce valid butterfly
size it represents, the second stage is outputs. The left output is sent
labelled as N/2, N/4 and so on down to immediately to the next FFT stage, where
N=8 as seen in the Fig-5. Internal to each the right output is saved in the memory.
FFT stages is a butterfly and complexes
multiply stage. These FFT stages are a Once this cycle is complete the butterfly
form of decimation in frequency FFT, the outputs will be invalid for the next N/4
coefficients are alternated between 2 clock cycles. During this clock cycles, the
stages. The even stages get all the even FFT stage output’s data that had been
coefficients, and the odd stages get all the stored in the memory as can be analyzed in
odd coefficients. Each stage spends the Fig-5. The complex multiply formed in the
first N/4 clocks storing its inputs into the internal of butterfly, is formed from three
allocated memory, and then the next N/4 very simple shifts and adds multiplies,
clocks pairing a stored input with a single whose output’s is then transformed into a
external input, so this value obtained single complex output. The complex
becomes input to the butterfly. Later on coefficient, Zn, for these multiplies are
the butterfly coefficients is read from given by
small ROM table.
Due to timing and speed constraints of the are then either transmitted or received
system have made it mandatory to make based on the user requirements and
use of H/W acceleration, since algorithms displayed on to the in-built Linux
implemented in the PL will need lesser Application of IIO OSCILLOSCOPE. The
execution time compared to its software above Fig-6 demonstrates the hardware
counterpart. connection and its internal connection
between Zynq platform and AD-
The AD-FMComms2 EBZ analog module FMComms2 board. Since the application
is interfaced with zedboard to create a IIO OSCILLOSCOPE runs entirely on PS
Software Defined Radio (SDR) platform side and therefore the highly extensive
which enables the hardware to capture or calculations needed for the Linux
send signals of desired application on to Application makes it a slower process.
the antennas of the AD9361. These signals
an operating system by reading the kernel on a given board and has been choosen by
and any other required data into memory default mechanism to be passed on as low-
and executing the kernel with the proper level hardware information from the
argument. Bootloader to the Kernel. The DTB file is
build from the Device Tree Source (DTS)
d) Generation of "boot.bin" file: For file. The DTS file is the DTB file write in
adding the Boot image partitions, the most a human-editable format.
important order that is to be followed is:
First, bootloader i.e. First Stage Boot f) Linux Kernel File, uImage: It is a
Loader ("zynq fsbl.elf"); second the zImage file that has a U-Boot wrapper that
Programmable Logic includes the OS types and loader
Bitstream("system.bit") and finally the information.
software application _le i.e. U-Boot("u-
boot.elf"). All this _le names are stored in g) Root File System Image, "uramdisk.
a boot.bif file. "Bootgen" is a standalone image.gz": It is basically a compressed _le
tool to create a bootable image appropriate which contains all the operating system
for Zedboard. Making use of following files. Below Fig- illustrates in brief all
command: accommodation of _les in the SD Card
which is then later on attached to the SD
bootgen -image boot.bif -o i boot.bin. Card slot in the Zedboard.
The above program assembles the boot The below Fig-8 give a brighter step by
image by merging the elf an the bit files to step initializatoion of creating Custom
develop a single boot image with the Embedded OS on Zedboard. This all files
binary output file boot.bin file which is are then later on embedded into the SD
then introduced in the SD Card. Card which is attached to the SD Card slot
of the Zedboard as can be seen in Fig-9.
e) Device Tree Binary, "devicetree.dtb":
The Linux Kernel uses board specific data
structure called "Device Tree Blob" or
"Device Tree Binary (DTB)" to describe
the hardware. It basically is a database
which represents the hardware components
Below Fig-10, shows the systhesis result automatically reads the driver code and
obtained from the interaction of Axi Bus implements the necessary allocation of
pheripheral master and slave units with the data on the memory and makes it available
Fast Fourier Transform IP. After the on the display console.
overall process has been completed a code
is run on to the PS side of the Zedboard so CONCLUSION
as to map the evaluation results obtained The dissertation aim was to implement a
from the PL on to the PS and directly custom application-specific design on the
display on the user console so as to view Programmable Logic of the Zedboard
the correctness of the code an also to fabric was accomplished with optimized
evaluate the speed of the Fast Fourier and proper output. This experiment not
Transform on to the ARM processor. only gave the insight that due to to its
Basically mmap is used for mapping the Computing platform and excellent
outputs of the PL onto the PS. mmap() is performance to perform parallel in nature
basically a Unix System call that allocates and also to execute at a faster rate than the
or maps files or devices on to the memory. Processing System of The ARM. The Task
The c code is run on to the Zedboard and it of communication with the PL an d PS
was very much accomplished with the help Electronics (Comptelix) Manipal
of a AXI- standard bus which had its own University Jaipur, Malaviya
sets of peripherals that enabled any user to National Institute of Technology
create a custom code in association with Jaipur & IRISWORLD, July 01-
peripherals and talk to the PS with no 02,2017
further disturbances. The use of Software
gave better perspective of a System-on- II. Real-Time System Implementation
Chip process. Later on the software details for Image Processing with Hard-
had to be made available in the proper ware/Software Co-design on the
bootable image that was developed using Xilinx Zynq Platform M. Ali
the Software Development Kit. Lastly Altuncu, Taner Guven, Yasar
using a executable c code that was Becerikli, and Suhap Sahin
compactible with the ARM Processing International Journal of
system was executed and result was then Information and Electronics
obtained. Engineering, Vol. 5, No. 6,
November 2015.
ACKNOWLEDGMENT
I would like to thank the immense III. REAL TIME
guidance provided by my guide Prof. IMPLEMENTATION OF
Nitesh Guinde in accomplishing this SPATIAL FILTERING ON FPGA,
dissertation. I would also like to thank my Chaitannya Supe, Advances in
College for providing me access to various Vision Computing: An
materials and hardware facility whenever I International Journal (AVC),
would require. Vol.1, No.4, December 2014
VII. https://wiki.analog.com/resources/e
val/user-guides/ad-fmcomms2
ebz/software/linux/zynq 2014r2
VIII. https://wiki.analog.com/resources/f
pga/docs/build