Sl. No. Experiment No 1a 3: Analog and Digital Electronics Laboratory (17CSL37)

Analog and Digital Electronics Laboratory (17CSL37)
CONTENTS
Sl. Experiment Page
No. No
1a Design and construct a Schmitt trigger using Op-Amp for given UTP and LTP values 3
and demonstrate its working.
2a Design and construct a rectangular waveform generator (Op-Amp relaxation 8

oscillator) for given frequency and demonstrate its working.
3 Design and implement an Astable Multivibrator circuit using 555 timer for a given 11
frequency and duty cycle.
4 Design and implement Half adder, Full Adder, Half Subtractor, Full Subtractor using 16
basic gates.
5a Given a 4-variable logic expression, simplify it using Entered Variable Map and 22
realize the simplified logic expression using 8:1 multiplexer IC.
6 Design and implement code converter I) Binary to Gray (II) Gray to Binary Code 27
using basic gates.
7 Design and verify the Truth Table of 3-bit Parity Generator and 4-bit Parity Checker 31
using basic Logic Gates with an even parity bit.
8a Realize a J-K Master / Slave Flip-Flop using NAND gates and verify its truth table. 34
9a Design and implement a mod-n (n<8) synchronous up counter using J-K Flip-Flop ICs 37
10 Design and implement an asynchronous counter using decade counter IC to count up 42

from 0 to n (n<=9) and demonstrate on 7-segment display (using IC-7447).
11 Generate a Ramp output waveform using DAC0800 (Inputs are given to DAC through 46
IC74393 dual 4-bit binary counter).
Mohan H G, Assistant Professor, Dept. of CSE, JNNCE, Shimoga. Page 1

SIMULATION
1b Design and implement a Schmitt trigger using Op-Amp using a simulation package 49
for two sets of UTP and LTP values and demonstrate its working.
2b Design and implement a rectangular waveform generator (Op-Amp relaxation 51

oscillator) using a simulation package and demonstrate the change in frequency when
all resistor values are doubled.
5b Design and develop the Verilog /VHDL code for an 8:1 multiplexer. Simulate and 53
verify its working.
8b Design and develop the Verilog / VHDL code for D Flip-Flop with positive-edge 54
triggering. Simulate and verify its working.
9b Design and develop the Verilog / VHDL code for mod-8 up counter. Simulate and 55
verify its working.
List of IC Numbers
IC Number
NAND Gate (2-input) 7400
NAND Gate ( 3-input) 7410
NOR Gate (2-input) 7402
NOT Gate 7404
AND Gate (2-input) 7408
AND Gate (3-input) 7411
OR Gate (2-input) 7432
XOR Gate (2-input) 7486
Multiplexer 74251
7-Segment 7447
Decade Counter 7490
JK Flip Flop 7476
Op-Amp µA741
4-bit Binary Counter 74393

1a Design and construct a Schmitt Trigger using Op-Amp for given UTP and LTP values
Aim : To design and implement a Schmitt trigger using Op-Amp for given UTP and LTP
values.
Components :
Sl. No. Particulars Specification Quantity

1 Op-Amp µA741 1
2 Resistors As per Design
3 DC Power Supply 1
4 Signal generator 1
5 CRO, Probes 3
6 Connecting Wires 1
7 Bread Board 1
Background:
 Schmitt Trigger is an Op-Amp circuit which converts an irregular input waveform into a
rectangular waveform. It is an active circuit which converts an analog input signal to a
digital output signal.
 The circuit is named a “trigger” because the output retains its value until the input changes
sufficiently to trigger a change. The input voltage triggers the output voltage every time it
exceeds the certain voltage levels (UTP and LTP).
 In a Inverting Schmitt trigger, the input voltage at which the output switches from +Vsat
to –Vsat is called Upper Trigger Point (UTP). The input voltage at which output
switches from –Vsat to +Vsat is called Lower Triggering Point (LTP).
 The difference between the two trip points is called Hysteresis. The Hysteresis loop can be
shifted to either side of zero by connecting a voltage source.
 It is an inverting comparator circuit with a positive feedback. The amplitude of the output
square wave is independent of the peak-to-peak value of the input waveform.

Formulas:
𝐑𝟏 × 𝐕𝐫𝐞𝐟 𝐑𝟐 × 𝐕𝐬𝐚𝐭
UTP = +
𝐑𝟏 + 𝐑𝟐 𝐑𝟏 + 𝐑𝟐
𝐑𝟏 × 𝐕𝐫𝐞𝐟 𝐑𝟐 × 𝐕𝐬𝐚𝐭
LTP = −
𝐑𝟏 + 𝐑𝟐 𝐑𝟏 + 𝐑𝟐
Design:
For the given values of UTP and LTP, find out the values of Vref, R1 and R2. Vsat is fixed at
12V.
𝟐 × 𝐑𝟏 × 𝐕𝐫𝐞𝐟
UTP + LTP = - - - - - - (1)
𝐑𝟏 + 𝐑𝟐
𝟐 × 𝐑𝟐 × 𝐕𝐬𝐚𝐭
UTP - LTP = - - - - - - (2)
𝐑𝟏 + 𝐑𝟐
1. Given UTP = 1V and LTP = -1V, Choose Vsat = 12V [ Without Reference Voltage ]
Substituting the UTP and LTP values in Eq 1 and 2 will give
2 × R1 × Vref
UTP + LTP = 0 = - - - - - - (1)
R1 + R2
2 × R2 × 12
UTP – LTP = 2 = - - - - - - (2)
R1 + R2
12 × R2 = R1 + R2
R1 = 11 × R2
Practical values of Resistors selected are : R1 = 10 K Ω and R2 = 1 K Ω.
When UTP = -LTP, then Vref = 0 V (No need to connect Vref Voltage Source)
2. Given UTP = 4V and LTP = 2V, Choose Vsat = 12V [ With Reference Voltage ]
Substituting the UTP and LTP values in Eq 1 and 2 will give
2 × R1 × Vref
UTP + LTP = 6 = - - - - - - (1)
R1 + R2
6 × ( R1 + R2 ) = 2 × R1 × Vref
2 × R2 × 12
UTP – LTP = 2 = - - - - - - (2)
R1 + R2

2 R1 + 2 R2 = 24 R2
2R1 = 22 R2
R1 = 11 R2 - - - - - - (3)
Substitute Eq. 3 in Eq 1
6 × ( 11 R2 + R2 ) = 2 × 11 R2 × Vref
72 R2 = 22 R2 × Vref
Vref = 3.27 V
Practical values of Resistors selected are : R1 = 10 K Ω and R2 = 1 K Ω.
3. Given UTP = 6V and LTP = -2V, Choose Vsat = 12V
Practical values of Resistors selected are : R1 = _______ K Ω and R2 = _______ K Ω.
4. Given UTP = 4V and LTP = -4V, Choose Vsat = 12V
Circuit Diagram (Without Reference Voltage):

Circuit Diagram (With Reference Voltage):
Waveforms displayed on CRO
Hysterisis Voltage Plot [CRO in X-Y Mode]
Procedure:
1. Check all the components using a Multimeter.
2. Verify the Probes for good working condition using the CRO’s test square waveform.
3. Make the appropriate settings in the CRO.
4. Set the Frequency of Function Generator in between 100 - 300 Hz and Peak to Peak
Voltage to 20V.
5. Compute the values of Resistors R1, R2 and Vref for the given values of UTP and LTP.
6. Choose the nearest available Resistor values for making the circuit.
7. Connect the Function Generator to the Pin 2 of IC µA-741 using Positive end of the Probe.
8. Make the connections as shown in the circuit diagram and switch on the power supply.

9. Observe the input waveform at Function Generator on Channel-1 of CRO by connecting

through the positive end of the Probe.
10. Observe the Output waveform at pin 6 of IC µA-741on Channel-2 of CRO by connecting
11. Connect the negative end of Probes to the Ground.
12. After Observing the Input and Output waveforms on the CRO. Put the CRO to the X-Y
Mode and Observe the Hysterisis Voltage Plot. Adjust the Frequency of the Function
Generator to get the UTP and LTP values near to the design.
13. Note the Values of UTP and LTP from Hysterisis Voltage Plot by considering the Channel
1 Volts/Div setting on CRO.
Result: The Schmitt Trigger is designed and implemented with the following values.
UTP LTP
Sl. UTP LTP
(Practical) (Practical)
No (Theoretical) (Theoretical)
(CRO Value × Volts/Div Value) (CRO Value × Volts/Div Value)

2a Design and Construct a Rectangular Waveform Generator (Op-Amp Relaxation

Oscillator) for given Frequency and demonstrate its working.
Aim : To design and implement an Op-Amp Relaxation Oscillator for the given Frequency.
Components :

1 Op-Amp µA741 1
3 Capacitors 0.1µF 1
4 CRO, Probes 2
6 Bread Board 1
Background:
 Relaxation oscillators are non-sinusoidal oscillators which generate triangular, square and
pulse waveforms using a circuit building block known as Multivibrators.
 The op-amp operates in the saturation region. Here, a fraction (R2/(R1+R2)) of output is
fed back to the non-inverting input terminal. Hence the reference voltage is (R2/(R1+R2))
Vo and may take values as +(R2/(R1+R2)) Vsat or - (R2/(R1+R2)) Vsat.
 The output is also fed back to the inverting input terminal after integrating by means of a
low-pass RC combination. Whenever the voltage at inverting input terminal just exceeds
reference voltage, switching takes place resulting in a Square Wave output.
Formula:
Let, Frequency = f, Time Period = T, Inverting Feedback Resistor = R, Coupling Capacitor = C

Circuit Diagram:
Waveforms on CRO
Calculations:
If R1 = R2, then T = 2 × R × C × ln(3)

T = 2 × R × C × 1.098 [Substituting Natural Log of 3]
T = 2.196 × R × C - - - - - - (1)
1. Given Frequency f = 1 KHz
T = 1/f = 1/1K = 1 ms
Choose C = 0.1µF, R1 = R2 = 1K Ω
1m = 2.196 × R × 0.1µ [Substituting C and T in Eq. 1]
R = 4.55 K Ω
Practical values of Resistors selected are : R1 = 1 K Ω, R2 = 1 K Ω and R = 4.7 K Ω.
2. Given Frequency f = 800 Hz
T = 1/f = 1/800 = 1.25 ms

Choose C = 0.1µF, R1 = R2 = 1K Ω
1.25 m = 2.196 × R × 0.1µ [Substituting C and T in Eq. 1]
R = 5.69 K Ω
Practical values of Resistors selected are : R1 = 1 K Ω, R2 = 1 K Ω and R = 5.6 K Ω.

3. Given Frequency f = 2 K Hz
Practical values of Resistors selected are : R1 = 1 K Ω, R2 = 1 K Ω and R = K Ω.
4. Given Frequency f = 5 K Hz
Practical values of Resistors selected are : R1 = 1 K Ω, R2 = 1 K Ω and R = K Ω.
Procedure:
1. Check all the components using a Multimeter. Verify the Probes for good working
condition using the CRO’s test square waveform.
3. Compute the value of Resistor ‘R’ for the given Frequency.
5. Observe the input waveform at pin 2 of IC µA-741 on Channel-1 of CRO by connecting

6. Observe the Output waveform at pin 6 of IC µA-741 on Channel-2 of CRO by connecting

7. Connect the negative end of Probes to the Ground.
8. Note the Value of Time Period of Rectangular Waveform by considering the Channel 2
Time/Div setting on CRO and calculate the Frequency.
Result: The Relaxation Oscillator is designed and implemented with the following values.
Sl. Time Period Frequency Time Period (Practical) Frequency

No (Theoretical) (Theoretical) T = (CRO Value × Time/Div Value) (Practical)

3 Design and implement an Astable Multivibrator circuit using 555 Timer for a given
Frequency and Duty Cycle.
Aim : To design and implement an Astable Multivibrator circuit using 555 Timer for a given
Frequency and Duty Cycle.
Components :

1 Timer IC 555 1
3 Capacitors 0.01µF, 0.1µF 2
4 Diode IN4007 1
5 CRO, Probes 2
7 Bread Board 1
Background:
 A Multivibrator is an electronic circuit used to implement a variety of simple multi-state

systems such as oscillators, timers and flip-flops. It is characterized by two amplifying
devices (transistors, electron tubes or other devices) cross-coupled by resistors or
capacitors.
 Some common types of Multivibrator circuits are:
 Astable Multivibrator : The circuit is not stable in either state, it continually

switches from one state to the another state. This circuit functions as a Relaxation
Oscillator.
 Monostable Multivibrator : In this circuit one of the states is stable and another
state is unstable. A trigger pulse causes the circuit to enter the unstable state. After
entering the unstable state, the circuit will return to the stable state after a set time.
 Bistable Multivibrator : The circuit is stable in both the states. It can be flipped
from one state to the other by an external trigger pulse. This circuit is also known
as a flip-flop. It can be used to store one bit of information.

 Astable Multivibrator Mode of 555 Timer IC is also called as Free Running or Self-
Triggering Mode. It doesn’t have any stable state, it has two quasi stable state (High and
Low). No external triggering is required in Astable Mode, it automatically interchanges
between the two states after an interval of time, hence generates a rectangular waveform.
 Using 555 Timer IC, one can generate precise time duration of High and Low output, from
micro seconds to hours which is determined by the external resistors (R1 and R2) and a
capacitor (C).
Design:
1
Let, Frequency = f Time Period = T =
f
Duty Cycle = D Capacitance = C
Capacitor Charging Time = TC = D × T

Capacitor Discharging Time = TD = (1 - D) × T and T = TC + TD
For a given Frequency (f) and Duty Cycle (D), Find T, TC and TD
Case 1 : If Duty Cycle D > 50% [ D > 0.5 ]
TC = 0.693 × ( R1 + R2 ) × C [Capacitor charges through R1 and R2]
TD = 0.693 × R2 × C [Capacitor discharges through R2 only]
Case 2 : If Duty Cycle D <= 50% [ D <= 0.5 ]
TC = 0.693 × R1 × C [Capacitor charges through R1 only, and

R2 is bypassed using a diode]
TD = 0.693 × R2 × C [Capacitor discharges through R2 only]
Choose Capacitance C = 0.1μF in both the cases and find the R1 and R2 Resistor values by
substituting C in the respective equations.

Circuit Diagram for D > 50% [ D > 0.5 ]:
Circuit Diagram for D <= 50% [ D <= 0.5 ]:
Output Waveforms

Calculations:
1. Given Frequency f = 1 KHz and Duty Cycle D = 70 %
T = 1/f = 1 ms
D = 0.7 = TC / T Hence TC = 0.7 ms and TD = T - TC = 1 - 0.7 = 0.3 ms
Choose C = 0.1μ F and by substituting the values we have
TC = 0.693 ( R1 + R2 ) C [Formula for Duty Cycle > 50%]

0.7 = 0.693 ( R1 + R2 ) 0.1 μ F ---------------- (1)
TD = 0.693 R2 C
0.3 = 0.693 R2 0.1 μ F ---------------- (2)
R2 = 4.33 K Ω [by solving Eq 2]

R1 = 5.77 K Ω [by substituting R2 in Eq 1]
T = 1/f = 1 ms
D = 0.5 = TC / T Hence TC = 0.5 ms and TD = T - TC = 1 - 0.5 = 0.5 ms
Choose C = 0.1μ F and by substituting the values we have
TC = 0.693 R1 C [Formula for Duty Cycle <= 50%]

0.5 = 0.693 R1 0.1 μ F ---------------- (1)
TD = 0.693 R2 C
0.5 = 0.693 R2 0.1 μ F ---------------- (2)


Procedure:
1. Check all the components using Multimeter.
2. Verify the Probes for good working condition using the CRO’s test square waveform.
4. For the given Frequency and Duty Cycle, Compute the values of Resistors R1 and R2.
6. Use the Diode only when the given Duty Cycle <= 50%
7. Make the connections as shown in the circuit diagram and switch on the power supply.
8. Observe the Capacitor Voltage waveform at pin 6 of 555 Timer on Channel-1 of CRO by
connecting through the positive end of the Probe.
9. Observe the Output waveform at pin 3 of 555 Timer on Channel-2 of CRO by connecting
through the Positive end of the Probe.
10. Connect the Negative end of Probes to the Ground.
11. Note the TC and TD values of output waveform by considering the Time/Div settings in the
CRO and calculate the Frequency of output waveform.
Result: The Astable Multivibrator is designed and implemented with following values.
TC TD Frequency Duty
Sl. Frequency Duty Cycle (CRO Value (CRO Value Period Cycle
(Practical) (Practical)
No (Theoretical) (Theoretical) × Time/Div × Time/Div T = TC + TD
Value) Value) f = 1/T D = TC / T

4a Design and implement Half Adder, Full Adder, Half Subtractor, Full Subtractor using
Basic Gates.
Aim : To design and verify the working of Half adder, Full Adder, Half and Full Subtractor.
Components :

1 AND Gate (2-input) 7408 1
2 AND Gate (3-input) 7411 2
3 OR Gate 7432 2
4 NOT Gate 7404 1
5 Patch Cords - 20
Background:
 An adder is a digital circuit that performs addition of numbers. Adders are used in the
arithmetic logic units, to calculate addresses, table indices, increment and decrement
operators, and similar operations.
 The Half Adder adds 2 one bit binary digits and produces two outputs as sum and carry.
The carry signal represents an overflow into the next digit of a multi-digit addition.
 A one-bit Full Adder adds three one-bit numbers, represented as A, B, and Cin. A and B
are the operands and Cin is a bit carried in from the previous less-significant stage.
 Subtractor is used to subtract two binary number (digit) and provides Difference and
Borrow as outputs.
 The Half Subtractor is a combinational circuit which is used to perform subtraction of two
bits. It has two inputs X, Y and two outputs the Difference (D = X - Y) and Borrow Out
(Bout).
 The Borrow Out signal is set when the Subtractor needs to borrow from the next digit in a
multi-digit subtraction. Bout = 1, when X < Y. Since X and Y are bits, Bout = 1 if and
only if X = 0 and Y = 1.
 The Full Subtractor is a used for subtraction of three input bits: X, Y, and Bin (Borrow in).
It generates two output bits, the Difference (D) and Borrow Out (Bout). Bin is set when
the previous digit borrowed from X. A Full Subtractor is represented as X – Y – Bin.

1. Half Adder Design :
Inputs Outputs
Carry Sum
A B
(Cout) (S)
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
S = A ̅̅𝐁̅̅ + ̅𝐀
̅̅̅ 𝐁 , Cout = A B
The Sum equation can also be realized using XOR gate
S = A , Cout = A B
2. Full Adder Design :
Inputs Outputs
Carry in Carry out Sum
A B
(Cin) (Cout) (S)
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

Kmap
Simplified Equation for Sum can be written as
S = A C
Cout = A B + A Cin + B Cin
3. Half Subtractor Design :
Inputs Outputs
Borrow Difference
X Y
(Bout) (D)
0 0 0 0
0 1 1 1
1 0 0 1
1 1 0 0

D = X ̅̅̅
𝐘 + ̅̅̅
𝐗 𝐘 , Bout = ̅̅̅
𝐗 𝐘
Simplified Equation for Difference can be written as, D = X Y
4. Full Subtractor Design :
Inputs Outputs
Borrow in Borrow out Diff
X Y
(Bin) (Bout) (D)
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 1 0
1 0 0 0 1
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
Kmap

Simplified Equation for Difference is
D = X YBin
Bout = ̅̅̅̅̅
𝐗 𝐁𝐢𝐧 + Y Bin + ̅̅̅̅̅
𝐗 𝐘
Procedure :
1. Verify all the components and patch cords for their good working condition.
2. Connect A, B, Cin (X, Y, Bin) to the input ports and S, Cout (D, Bout) to the output ports
of the trainer kit, such that A (X) is MSB bit.
3. Use IC 7404 (NOT), 7408 (2-input AND), 7486 (2-input XOR), 7432 (2-input OR) and
make the connections as shown in the circuit diagrams.
4. Connect GND and Vcc to all the ICs.
5. Provide the inputs to circuit via trainer kit switches (A, B, Cin, X, Y, Bin) and verify the
truth table.
6. It can be observed the sum and difference equations of Adders and Subtractors are same,
thus the same connections can be retained while conducting the experiment.
Result : The circuit designed is verified for the truth tables of Half Adder, Full Adder, Half and
Full Subtractor.

5a Given a 4-variable logic expression, simplify it using Entered Variable Map and
realize the simplified logic expression using 8:1 multiplexer IC.
Aim : To simplify a given 4-variable logic expression using EVM and realize it using a 8:1
Multiplexer IC.
Components :

1 Multiplexer IC 74251 1
2 NOT Gate 7404 1
3 Trainer Kit - 1
4 Patch Cords - 20
Background:
 Multiplexer means many into one. It is a circuit with many inputs but only one output. By
applying control signals, it can steer any input to the output.
 The number of inputs to a multiplexer is multiple of 2 (2, 4, 8, 16, …) but the number of
output is always one. Hence, it is also called as data selector. Control inputs are termed as
select inputs.
 The circuit has n input signals, m control signals and 1 output signal. m control signals
can select at the most 2m input signals, thus n <= 2m.
 Multiplexer is sometimes called as universal logic circuit because a 2n to 1 multiplexer

can be used as a design solution for any n variable truth table.
 In Entered Variable Map, one of the input variable is placed inside the output of truth
table, this variable is called as Map Entered Variable (MEV).
 The method records how this variable is related to the output. Hence, truth table size is
reduced by a degree of one.
 For instance, a 4 variable problem has 24 = 16 entries in truth table, using EVM method it
can be reduced to 24 - 1 = 23 = 8.

Function Table of Multiplexer IC 74251:
Inputs Outputs
Observation
A B C ̅̅̅̅
𝐄𝐍 Q ̅
𝐐
X X X 1 1 1 If EN pin is 0 then irrespective of the input values,

the output will be 1.
0 0 0 0 D0 ̅̅̅̅
D0 If EN pin is 0 and input is 0 0 0 then output will be D0
0 0 1 0 D1 ̅̅̅̅
0 1 0 0 D2 ̅̅̅̅
0 1 1 0 D3 ̅̅̅̅
1 0 0 0 D4 ̅̅̅̅
1 0 1 0 D5 ̅̅̅̅ If EN pin is 0 and input is 1 0 1 then output will be D5

D5
1 1 0 0 D6 ̅̅̅̅
1 1 1 0 D7 ̅̅̅̅
EVM Method :
 Let’s consider A, B and C variables to be fed as select inputs and fourth variable D to be
present as data input using Entered Variable Map method.
 All combinations of 3 select inputs and the data input is written in the truth table.
Corresponding Q value (the output) is written using the given logic expression.

 Observe how the MEV variable D is related to the output and make the corresponding
entries in the MEV map.
 Don’t care (X) values can be treated as either 1 or 0.
 For all 8 combinations of control inputs, the corresponding 8 data inputs for the MUX are
calculated.
 Using these 8 data inputs, the 8:1 MUX circuit can be designed and implemented.
 ̅̅̅̅ is the active low strobe pin, which activates the MUX IC.
𝐄𝐍
Entry in MEV Map for all possible values of MEV (D) and Output (Q)
MEV Output Entry in MEV Output Entry in

D Q MEV Map D Q MEV Map
0 0 0 1
0 1
1 0 1 X
0 1 0 X
̅
D 0
1 0 1 0
0 1 0 X
1 1
1 1 1 1
0 0 0 X
D X
1 1 1 X
0 0 1 X
0 X
1 X 0 X
Input: A 4 variable logic Expression, F (A,B,C,D) = ∑ m (2,4,5,7,10,11,14) + d(8,9,12,13,15)
Decimal Inputs MEV Output

Value Entry in MEV Map
A B C D Q
0 0 0 0 0 0
̅.0 +D.0 =0
D0 = D
1 0 0 0 1 0
2 0 0 1 0 1
̅.1 +D.0 =D
D1 = D ̅
3 0 0 1 1 0
4 0 1 0 0 1
̅.1 +D.1 =1
D2 = D
5 0 1 0 1 1

6 0 1 1 0 0
̅.0 +D.1 =D
D3 = D
7 0 1 1 1 1
8 1 0 0 0 X
̅.X +D.X =X
D4 = D
9 1 0 0 1 X
10 1 0 1 0 1
̅.1 +D.1 =1
D5 = D
11 1 0 1 1 1
12 1 1 0 0 X
̅.X +D.X =X
D6 = D
13 1 1 0 1 X
14 1 1 1 0 1
̅.1 +D.X =1
D7 = D
15 1 1 1 1 X
Circuit :
Procedure :
1. Verify all the components and patch cords for their good working condition.
2. Connect A, B, C, D to the input ports and Q to the output port of the trainer kit, such that
A is MSB bit and D is LSB bit.
3. Don’t care (X) entries in the data input can be connected to either Ground or Vcc.

̅ , connect pin 14 to Vcc, pin 7 to Ground and input D to pin 1.

4. Use IC 7404 (NOT) to get D
̅ can be obtained at pin 2 of IC 7404.
D
̅ is required.
5. Connect IC 74251 pins to pin 2 of IC 7404 where ever D
6. Pin 7 is active low strobe (enable) and is connected to ground. Pin 6 is not connected.
7. Make the connection as shown in the circuit diagram.
8. Give the power supply to the trainer kit.
9. Provide the input data to circuit via trainer kit switches (A, B, C and D) and verify the
truth table.
Result : The circuit designed using multiplexer is verified for the given logical expression.

6 Design and implement code converter I) Binary to Gray II) Gray to Binary Code using
Basic Gates.
Aim : To design and realize a Binary to Gray and Gray to Binary Code converter using Basic
Gates.
Components :

1 2-input XOR IC 7486 1
2 Trainer Kit - 1
3 Patch Cords - 30
Background:
 The logical circuit which converts binary code to equivalent gray code is known as binary
to gray code converter. The gray code is a non weighted code.
 The successive gray code differs in one bit position only that means it is a unit distance
code. It is also referred as cyclic code.
 Binary to Gray Code :
1. The MSB bit of Binary Code and Gray Code are same.
2. For a N-bit Binary Code, The Mth Bit of a Gray Code will be
GM = BM XOR BM+1
 Gray to Binary Code :
1. The MSB bit of Gray Code and Binary Code are same.
2. For a N-bit Gray Code, The Mth Bit of a Binary Code will be
BM = GM XOR GM+1 XOR … XOR GN

Binary Code to Gray Code Function Table :
Binary Code Gray Code

Decimal Input Output
B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0 0 0 0 0 0
1 0 0 0 1 0 0 0 1
2 0 0 1 0 0 0 1 1
3 0 0 1 1 0 0 1 0
4 0 1 0 0 0 1 1 0
5 0 1 0 1 0 1 1 1
6 0 1 1 0 0 1 0 1
7 0 1 1 1 0 1 0 0
8 1 0 0 0 1 1 0 0
9 1 0 0 1 1 1 0 1
10 1 0 1 0 1 1 1 1
11 1 0 1 1 1 1 1 0
12 1 1 0 0 1 0 1 0
13 1 1 0 1 1 0 1 1
14 1 1 1 0 1 0 0 1
15 1 1 1 1 1 0 0 0
Boolean Expressions for Binary Code to Gray Code:
G3 = B3 G2 = B2 

G1 = B1 G0 = B0 
Gray Code to Binary Code Function Table :
Gray Code Binary Code

Input Output
G3 G2 G1 G0 B3 B2 B1 B0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 1 0 0 1 0
0 0 1 0 0 0 1 1
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 1
0 1 0 1 0 1 1 0
0 1 0 0 0 1 1 1
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 1
1 1 1 1 1 0 1 0
1 1 1 0 1 0 1 1
1 0 1 0 1 1 0 0
1 0 1 1 1 1 0 1

1 0 0 1 1 1 1 0
1 0 0 0 1 1 1 1
Boolean Expressions for Gray Code to Binary Code:
B3 = G3 B2 = G2 G
B1 = G1 GGG1  B2 B0 = G0 G1GG3 = G0  B1
Procedure:
1. Verify all the components and patch cords for the good working condition.
2. For Binary Code to Gray Code, Connect B3, B2, B1, B0 to the input ports of trainer kit
such that B3 will be MSB bit and B0 is LSB Bit. Connect G3, G2, G1, G0 to the output
ports of the trainer kit such that G3 is the MSB bit and G0 is LSB Bit.
3. For Gray Code to Binary Code converter, connect G3, G2, G1, G0 to the input ports of
trainer kit such that G3 will be MSB bit and G0 is LSB Bit. Connect B3, B2, B1, B0 to the
output ports of the trainer kit such that B3 is the MSB bit and B0 is the LSB Bit.
4. Make the connections as shown in the circuit. Connect the VCC and Ground to all the IC’s.
5. For all combinations of input codes verify the corresponding converted output codes.
Result : The circuit designed is verified for the 4-bit Binary code to Gray code converter and
Gray code to Binary code converter.

7 Design and verify the Truth Table of 3-bit Parity Generator and 4-bit Parity Checker
using basic Logic Gates with an even parity bit.
Aim : To design and implement Parity Generator and Parity Checker for even parity using
Basic Gates.
Components :

1 2-input XOR IC 7486 1
2 Trainer Kit - 1
3 Patch Cords - 30
Background:
 Parity of a binary number is defined based on number of 1’s present in it. If the number of
1’s present is odd then the binary number is said to have odd parity. If the number of 1’s
present is even then the binary number is of even parity.
 Even Parity Generator, generates an additional bit which when padded with the input bits
produces an even parity binary number.
 Parity Checker generates the output as 1 if the input binary number is of odd parity and 0
if input is of even parity.
Even Parity Generator Truth Table :
Input Output
Decimal A B C P A B C
0 0 0 0 0 0 0 0
1 0 0 1 1 0 0 1
2 0 1 0 1 0 1 0
3 0 1 1 0 0 1 1
4 1 0 0 1 1 0 0
5 1 0 1 0 1 0 1
6 1 1 0 0 1 1 0
7 1 1 1 1 1 1 1

Boolean Expression for Even Parity Generator:
P = ̅̅̅̅̅
A B C + ̅̅̅
A B ̅̅̅
C + A ̅̅̅̅̅̅
BC + ABC
P = ̅̅̅ B C + B ̅̅̅
A ( ̅̅̅ C ) + A ( ̅̅̅̅̅̅
BC + BC)
P=A B  C
4-Bit Parity Checker :
Inputs Output
Decimal
A B C D P
0 0 0 0 0 0
1 0 0 0 1 1
2 0 0 1 0 1
3 0 0 1 1 0
4 0 1 0 0 1
5 0 1 0 1 0
6 0 1 1 0 0
7 0 1 1 1 1
8 1 0 0 0 1
9 1 0 0 1 0
10 1 0 1 0 0
11 1 0 1 1 1
12 1 1 0 0 0
13 1 1 0 1 1
14 1 1 1 0 1
15 1 1 1 1 0

Boolean Expression for 4-Bit Parity Checker :
P = A BCD
Procedure:
2. For Even Parity Generator, connect A, B, C to the input ports and A, B, C, P to the output
ports of the trainer kit.
3. For 4-bit Parity Checker, connect A, B, C, D to the input ports and P to the output port of
the trainer kit.
4. Make the connections as shown in the circuit.
5. Connect the VCC and Ground to all the IC’s.
6. For all combinations of inputs verify the corresponding truth tables. If the output P is 1
then the input binary number is of odd parity and if P is 0 then input is of even parity.
Result : The circuit implemented is verified for the Parity Generator and Checker.

8a Realize a J-K Master / Slave Flip-Flop using NAND gates and verify its truth table.
Aim : To J-K Master Flip-Flop using NAND gates only.
Components :

1 3 Input NAND IC 7410 1
3 Trainer Kit - 1
4 Patch Cords - 30
Background:
 A flip-flop or latch is a circuit that has two stable states and can be used to store state
information. A flip-flop is a bistable multivibrator. The circuit can be made to change
the state by applying signals to one or more control inputs and will have one or two
outputs.
 A flip-flop stores a single bit of data, one of its two states represents a “one” and the
other represents a “zero”. Such data storage can be used for storage of state, and such a
circuit is described as sequential logic.
 When used in a finite-state machine, the output and next state depend not only on its
current input, but also on its current state. It can also be used for counting of pulses, and
for synchronizing variably-timed input signals to some reference timing signal.
 The JK flip-flop augments the behavior of the SR flip-flop (J=Set, K=Reset) by

interpreting the J = K = 1 condition as a “flip” or toggle command. Specifically, the
combination J = 1, K = 0 is a command to set the flip-flop; the combination J = 0,
K = 1 is a command to reset the flip-flop; and the combination J = K = 1 is a command
to toggle the flip-flop, i.e., change its output to the logical complement of its current
value.
 The characteristic equation of the JK flip-flop is:
̅ +𝐊
Qnext = J 𝐐 ̅Q

Pin Details of ICs:
Circuit Diagram:
JK Flip-Flop Truth Table:
J K CLK Q ̅
𝐐
0 0 Pos – Edge No Change
0 1 Pos – Edge 0 1
1 0 Pos – Edge 1 0
1 1 Pos – Edge Toggle

Procedure:
̅ to output ports of the trainer kit.

2. Connect J and K to input ports, Q and Q
3. The circuit needs two 3-input NAND gate and seven 2-input NAND gates.
4. Take two 2-input NAND gate IC’s (each IC contains four 2-input NAND gates) and one 3
input NAND gate (contains three 3-input NAND gate).
5. Place the 3-input NAND gate in first IC base, 1st 2-input NAND gate IC in 2nd IC base and
2nd 2-input NAND gate in 3rd IC base of the trainer kit.
6. Connect the VCC and Ground to all the three IC’s.
7. Connect the clock input to Monopulse (High) or 1Hz TTL pin of the trainer kit.
8. Make connection as shown in the circuit diagram.
9. Provide input data to the circuit via input switches and verify the truth table.
Result : The truth table of JK Flip Flop is verified.

9a Design and implement a mod-n (n<8) synchronous up counter using J-K Flip-Flop ICs
Aim : To design a synchronous up counter for Mod N using J-K Flip-Flop ICs
Components :

1 JK Flip Flop IC 7476 2
2 2 Input AND IC 7408 1
5 Trainer Kit - 1
6 Patch Cords - 25
Background:
 In digital logic and computing, a counter is a device which stores (displays) the number of
times a particular event or process has occurred, often in relationship to a clock signal.
 A synchronous counter is one whose output bits change state simultaneously, such a
counter circuit can be built from JK flip-flop by connecting all the clock inputs together,
so that each and every flip-flop receives the same clock pulse at the same time.
 All individual output bits changing state at exactly the same time in response to the
common clock signal with no ripple effect i.e. with no propagation delay.
 By examining the four-bit binary count sequence, it is noticed that just before a bit toggles,
all preceding bits are “high”. Thus a synchronous up-counter can be implemented by
toggling a bit, when all of the least significant bits are at logic high state.
 For example, bit 1 toggles, when bit 0 is high. Bit 2 toggles, when both bit 1 and bit 0 are
high. Bit 3 toggles when bit 2, bit 1 and bit 0 are high.
 IC 7476 contains 2 JK flip-flops, when Preset (PRE) pin is low, the flip flop value is set to
1. When the Clear (CLR) pin is low, the flip flop value is set to 0.

Design For Mod 8 UP Counter:
Present State Next state Flip Flop Inputs

QC QB QA QC+1 QB+1 QA+1 JC KC JB KB JA KA
0 0 0 0 0 1 0 X 0 X 1 X
0 0 1 0 1 0 0 X 1 X X 1
0 1 0 0 1 1 0 X X 0 1 X
0 1 1 1 0 0 1 X X 1 X 1
1 0 0 1 0 1 X 0 0 X 1 X
1 0 1 1 1 0 X 0 1 X X 1
1 1 0 1 1 1 X 0 X 0 1 X
1 1 1 0 0 0 X 1 X 1 X 1
Design:

Circuit Diagram of Mod – 8 Counter:
Pin Diagram of IC 7476:
Procedure :
2. Connect QA, QB and QC to output ports of the trainer kit, such that QA is LSB and QC is
MSB.
3. Give VCC to Pin 5 and Ground to Pin 13 of IC 7476.
4. Connect the Vcc and GND to AND and NAND IC’s.

5. Connect the clock input to Monopulse (High) or 1Hz TTL pin of the trainer kit.
6. Make the connections as shown in the circuit diagram.
7. Give the power supply to the trainer kit and verify the truth table.
Mod-5 Circuit Diagram:
 5 is represented in binary as 101, which means QC = 1, QB = 0 and QA = 1.
 The counter must be reset when it reaches 101, thus CLR pin must be low when QA and
QC are high. Hence, remove the Vcc connection from CLR pins. Connect QA and QC
to NAND gate inputs, NAND gate output to CLR pins of all JK Flip Flops.
Designing Other Modulo’s:
 Mod 2 counter can be obtained by connecting QB to both the inputs of NAND gate and
output of NAND gate connected to CLR pins of all JK Flip Flops.
 Mod 3 counter can be obtained by connecting QA and QB to the inputs of NAND gate and
 Mod 4 counter can be obtained by connecting QC to both the inputs of NAND gate and
 Mod 6 counter can be obtained by connecting QB and QC to the inputs of NAND gate and
 Mod 7 counter can be obtained by connecting QA, QB and QC to the inputs of NAND
gate and output of NAND gate connected to CLR pins of all JK Flip Flops. (Use 3 input
NAND Gate IC 7410).
 Remove the Vcc connection from CLR pins for all cases, except Mod 8.
Result : The truth table for the given Mod N is verified.

10 Design and implement an asynchronous counter using Decade Counter IC to count up

from 0 to n (n<=9) and demonstrate on 7-segment display (using IC-7447).
Aim : To design an asynchronous counter for a given N.
Components :

1 Decade Counter IC 7490 1
2 7-Segment Display 7447 1
3 2 input - AND Gate 7408 1
4 Trainer Kit - 1
5 Patch Cords - 25
Background:
 A counter is a register that goes through a predetermined sequence of states upon the
application of input pulses. In asynchronous counter a clock signal is provided for one
flip-flop and its output is provided as clock source for next flip-flop. The output of
asynchronous counter is not synchronized with clock signal.
 A decade counter follows a sequence of 10 states and returns to zero after the count of
Nine. Such a counter must have atleast 4 flip flops to represent each decimal digit,
represented by a binary code with 4 bits.
IC 7490:
 The 74LS90 is a simple counter, it can count from 0 to 9 cyclically in its natural mode. It
counts the input pulses and provides the output as a 4-bit binary number through pins QA,
QB, QC and QD.
 The chip can count up to other maximum numbers and return to zero by changing the
modes of 7490. The modes are set by changing the connection of reset pins R1 - R4.
 For example, if either R1 & R2 are high or R3 & R4 are ground, then it will reset QA, QB,
QC and QD to 0000. If reset pins R3 & R4 are high, then the count on QA, QB, QC and
QD goes to 1001.

Pin Diagram and Function Table of IC 7490:
Input Output
R1 R2 R3 R4 QD QC QB QA
H H L X 0 0 0 0
H H X L 0 0 0 0
L X H H 1 0 0 1
X L H H 1 0 0 1
L X L X COUNT
X L X L COUNT
L X X L COUNT
X L L X COUNT
It can be noted that the outputs will be set to 0000, whenever R1and R2 are high. And the outputs
will be set to 1001, whenever R3and R4 are high. In all other cases, the outputs will follow the
counter.
Pin Diagram and Function Table of IC 7447:
Procedure :
1. Connect power supply, VCC to pin 5 and GND to pin 10 of IC 7490.
2. Connect pin 14 to mono pulse or TTL (1Hz) Clock

3. Pins QA (pin 12), QB (pin 9), QC (pin 8) and QD (pin 11) are connected to Pins of IC
7447.
4. Note that QD is MSB pin followed by QC, QB, QA.
5. Reset pins R1, R2, R3 and R4 are connected to GND, i.e pin 2, pin 3, pin 6 and pin 7 to
GND.
6. Connect power supply, VCC to pin 8 and GND to pin 16 of IC 7447.
7. Connect a, b, c, d, e, f and g pins of IC 7447 to the 7- Segment Display on the Trainer Kit.
8. Apply clock pulse using mono-pulse or TTL, the counter starts counting from “0” to “9”
repeatedly on 7-Segment Display. This verifies the working of a Decade Counter.
Designing Mod 5 Counter :
 Mod 5 counter must count from 0 to 4, which means when the output becomes 0101, it
must be reset to 0. The counter can be reset to 0 by making R1 and R2 values as 1 (High).
 Observe the number 0101, where QD = 0, QC = 1, QB = 0 and QA = 1.
 Consider only those output bit values which are high. In this case QC and QA are high.
Thus, the counter must be reset to 0 when ever QC and QA are high.
 Connect the QC to R1 and QA to R2 pins of IC 7490, When ever QC and QA are high,
the counter will be reset to 0.

Circuit for Mod 5 Counter

Designing Mod 4 Counter :
 Mod 4 counter must count from 0 to 3, which means when the output becomes 0100, it
must be reset to 0. Where QD = 0, QC = 1, QB = 0 and QA = 0.
 The counter must be reset to 0 when ever QC is high. Hence, directly connect QC to R1
and R2 pins of IC 7447.
Design all Modulo’s by connecting R1 and R2 as :
Mod R1 R2
2 QB QB
3 QA QB
4 QC QC
5 QC QA
6 QC QB
7 QA . QC QB
8 QD QD
9 QD QA
Result : The circuit designed is verified for the given value of Mod N.

11 Generate a Ramp output waveform using DAC0800 (Inputs are given to DAC through
IC74393 Dual 4-Bit Binary Counter).
Aim : To generate a Ramp waveform using a DAC circuit.
Components :

1 DAC IC0800 1
2 4-Bit Binary Counter IC74393 1
3 Trainer Kit 1
4 Patch Cords - 25
5 Multimeter/Voltmeter - 1
Background:
 Digital-To-Analog (D/A) and Analog-To-Digital (A/D) conversion form two very

important aspects of digital data processing. These converters are used in communication
Systems such as Modems.
 D/A conversion involve translation of digital information into equivalent analog

information. As an example, the output of a digital system might be changed to analog
form for the purpose of driving a pen recorder.
 Digital to analog converter (DAC) is used to get an Analog voltage corresponding to the
input digital signal. The process of Digital to Analog conversion is done by using
DAC0800 IC.
 The DAC fundamentally converts finite-precision numbers (usually fixed-point binary

numbers) into a physical quantity, usually an electrical voltage. DAC output is linear
function of the input number.
 The output voltage is held at the current value until the next input number is latched
resulting in a piecewise constant output. The DAC IC is driven by a Dual 4-Bit Binary
Counter IC74393.

Pin Diagrams:
Circuit :
Procedure :
1. Make the connections as shown in the circuit.
2. Connect pin 13 of IC74393 to mono pulse Clock.
3. Connect Pin 8, 9, 10 and 11 of IC 74393 to Pin 9, 10, 11 and 12 of DAC IC.
4. Also connect Pin 8, 9, 10 and 11 of IC 74393 to output ports of the Trainer kit.
5. Note that QD is MSB pin followed by QC, QB, QA.
6. Connect Multimeter to pin 4 of DAC IC.
7. Apply clock pulse using mono-pulse, the counter starts counting from “0” to “15”
repeatedly. On each count note the Current and Voltage value on the Multimeter.
8. Plot a Graph of Decimal value of Counter Vs Current Values.
Graph :
Result:
Decimal Value Voltage Current

(V) (µA)

Simulation of Circuits using MultiSim Software
1. Open the Multisim Software.
2. Click on File → New, a circuit window will appear. Maximize the circuit window.
3. Construct the circuit by selecting the components from the Components Bar, output devices
from Instruments Bar.
4. After finishing the circuit construction, click on the ‘save’ button and give a file name.
5. Double click on any component to change its property values.
6. Run the simulation by clicking on ‘Run’ Button.
7. To check the output readings, double click on the output devices.
8. To change any components/values click on deactivate button, change the values/components

and Run the simulation.
9. If any Window/Bars are not visible then Go to ‘View’ and enable them.

1b Design and implement a Schmitt trigger using Op-Amp using a simulation package
for two sets of UTP and LTP values and demonstrate its working.
Vref
(UTP = 1V and LTP = -1V) (UTP = 4V and LTP = 2V)
 Select “VOLTAGE_CONTROLLED_SINE_WAVE” as function generator, and set the

frequency array to 100Hz, output peak low value to -10V and output peak high value to 10V.
 Select Virtual Resistors for constructing the circuit.
 Vary the R1, R2 and Vref values according to the given UTP and LTP and run the simulation.
 Put the Oscilloscope to A/B or B/A Mode to view the Hysterisis Voltage Plot.

Results :
Sl. No UTP LTP UTP LTP UTP LTP

(Theoretical) (Theoretical) (Practical) (Practical) (Simulation) (Simulation)

2b Design and implement a Rectangular Waveform Generator (Op-Amp relaxation

oscillator) using a simulation package and demonstrate the change in frequency when
all resistor values are doubled.
 Select virtual Resistors for constructing the circuit.
 Vary the R1, R2 and R values according to the given Frequency and Run the Simulation.
 Double all the Resistor values and Run the Simulation.
Results :
Sl. No f T f T f T
(Theoretical) (Theoretical) (Practical) (Practical) (Simulation) (Simulation)
Sl. No R1 R2 R f 2 × R1 2 × R2 2×R f

Simulation using Xilinix Software
1. Open the Xilinix software.
2. Click on File → New Project. Type a Project name say ‘ADELAB’, select ‘HDL’ as Top
Level Module Type and click ‘Next’ button.
3. Select ‘Spartan2’ as Device Family click ‘Next’ button.
4. Click ‘New Source’ then, Type File Name, Select ‘Verilog Module’ and click ‘Next’ button.
5. Enter Module Name, Input and Output Port Variables. Enter the MSB, LSB values for
variables of type Array and click ‘Next’ button. Then click ‘Finish’ button.
6. Click ‘Next’ and ‘Finish’ until Design Summary Tab appears.
7. Click on Source file (.v file) and type the Verilog code.
8. Double Click on ‘Check Syntax’ in the ‘Process for Source’ Tab to Compile the Verilog
code.
9. On the successful compilation a green tick mark is displayed, If there are any errors then a
red cross mark will appear and Errors will be displayed on the Console Tab.
10. Debug the Verilog program and ‘Check Syntax’ until green tick mark is displayed.
11. After the Successful Compilation, Double click on the ‘Launch ModelSim Simulator’ in the
‘Process for Source’ Tab. Now the ‘Objects’ and ‘Wave’ windows will be loaded.
12. Force the values according to the requirements and click on the ‘run’ icon.
13. Observe the Input and Output waveforms on the ‘Wave’ window and verify them.
Note:
 To change the value of the variables during the simulation stage, right click on the variable
in the Wave window, select ‘Force’, type the value and click on ‘OK’ button.
 If any of the Window is not visible, then go to ‘View’ menu and select them.
 Right click on Wave Window and Select ‘Zoom In’ option according to the requirement.

5b Design and develop the Verilog /VHDL code for an 8:1 multiplexer. Simulate and verify
its working.
module MUX(S,D,Y);
input [2:0]S;
input [7:0]D;
output Y;
reg Y;
always @ (S or D)
case (S)
0: Y = D[0];
1: Y = D[1];
2: Y = D[2];
3: Y = D[3];
4: Y = D[4];
5: Y = D[5];
6: Y = D[6];
7: Y = D[7];
endcase
endmodule
 D is Data Inputs Array with D[0] as LSB and D[7] as MSB.

 S is Select lines (Control inputs) of the Multiplexer.
 Y is the output signal.
 Simulation:
1. Force a 8 bit value to variable D (say 10110100)
2. Force a 3 bit value to S and Run the simulation,
Observe the value of output signal Y.
3. Run the simulation for each possible value of S
and Verify the working of Multiplexer.

8b Design and develop the Verilog / VHDL code for D Flip-Flop with positive-edge
triggering. Simulate and verify its working.
module DFF(D, CLK, Q);

input D;
input CLK;
output Q;
reg Q;
always @(posedge CLK)
Q = D;
endmodule
 D is the flip flop input, Q is the output.

 During simulation, right click on the ‘CLK’ variable in the
‘Wave’ window, select ‘clock’ then click on ‘OK button’.
 The output follows input, but with a delay of one clock cycle.
 Run the Simulation for different values of D and verify its
Truth Table.
D Flip Flop Truth Table
Input Output
CLK
D Q
Neg-edge X No Change
Pos-edge 0 0
Pos-edge 1 1

9b Design and develop the Verilog / VHDL code for mod-8 up counter. Simulate and verify
its working.
module MOD8(CLK, RST, Q);

input RST, CLK;
output [2:0] Q;
reg [2:0] Q;
always @(posedge CLK)
begin
if(RST)
Q = 3'b000;
else
Q = Q+1;
end
endmodule
 CLK is clock, RST is the reset input and Q is the output signal.
 When RST value is 1, Q will remain as ‘000’.
 When the RST value is 0, Q value will get incremented on each
positive edge of the clock pulse.
 During simulation:
1. Right click on the ‘RST’ variable in Wave window,
select ‘force’ then type the value ‘1’ and click on ‘OK’.
2. Right click on the ‘CLK’ variable in the Wave window
select ‘clock’ and click on ‘OK’.
3. Run the Simulation.
4. Right click on the ‘RST’ variable in Wave window,
select ‘force’ then type the value ‘0’ and click on ‘OK’.
5. Run the Simulation and Verify the output signal.

VIVA QUESTIONS
1. List the differences between Analog and 26. What is a comparator?

Digital Signal. 27. What are the applications of comparator?
2. What is Rise, Fall and Switching time? 28. Derive the Boolean expressions of one bit
3. Define Period and Frequency. comparator and two bit comparators.
4. What are Asymmetric and Symmetric 29. What are the applications of decoder?
Signals. 30. What is the difference between decoder &
5. Why NAND & NOR gates are called encoder?
universal gates? 31. Explain PAL and PLA.
6. What are the different methods to obtain 32. Differentiate between a latch and a Flip-
minimal expression? Flop.
7. What is a Min term and Max term? 33. What are the different types of flip-flops?
8. State the difference between SOP and POS. Give the truth table?
9. What is meant by canonical representation? 34. Differentiate between the Sequential and
Combinational circuits.
10. What is K-map? Why is it used?
35. Explain the working of a MS-JK flip-flop.
11. What is a multiplexer?
36. What is the difference between +ve edge
12. What is a de-multiplexer?
triggered and –ve edge triggered circuit?
13. What are the applications of multiplexer and
37. What are the different types of shift
de-multiplexer?
registers?
14. Derive the Boolean expression for
38. Differentiate between SIPO, PISO, PIPO
multiplexer and de-multiplexer.
and SISO.
15. How do you realize a given function using
39. What are the applications of registers and
multiplexer?
counters?
16. What is the difference between multiplexer
40. Differentiate between a Ring counter and
& demultiplexer?
Johnson counter.
17. In 2n to 1 multiplexer how many selection
41. What is a counter?
lines are there?
42. Differentiate between synchronous and
18. Implement an 8:1 mux using 4:1 mux’s?
asynchronous counters.
19. What is the advantage of using EVM
43. What types of flip-flops can be used to
Technique?
implement the memory elements of a
20. What is the importance of Enable Pin? counter?
21. How to decide the number of Select lines for 44. Explain the use of PRESET and CLEAR
any MUX? pins in flip-flop.
22. What are Half/Full adders and Subtractors? 45. Difference between BCD and Binary
23. What do you mean by Parity Generator? counter.
24. How to Generate Odd/Even Parity? 46. List the steps in designing a counter?
25. What are Grey Codes? 47. What is ADC? What is DAC?

48. Mention the types of DAC. 64. What changes will happen in Hysterisis
Curve if reference voltage is increased?
49. What are Monotonicity and Steady State
Accuracy Test? 65. Explain the working of Relaxation
Oscillator.
50. What is Resolution & Accuracy of a DAC?
51. What is the advantage of using R-2R over 66. What is Duty Cycle.
weighted resistor method? 67. Explain Duty Cycle High and Low.
52. Which is the fastest ADC? Why? 68. Define Ton / Thigh / Tcharging / Toff / Tlow /
Tdischarge ?
53. Mention the types of ADC.
69. List different Multivibrators.
54. Explain the structure of Verilog Code.
55. Which are the different types of Models in 70. Define Astable, Bistable and Monostable
Multivibrators.
HDL.
56. Explain assign, always, reg and wire 71. What are the features of CRO?
keywords. 72. How to calculate a Voltage value of
Signal in a CRO?
57. What is test bench and why it is needed ?
58. Write the Verilog code for de-multiplexer, 73. How to calculate a Time Period of Signal
in a CRO?
ring counter, Mod 5 counter and JK flip flop.
74. What is the use of Time/Div and
59. List some simulation tools for HDL.
Volts/Div settings in a CRO?
60. Explain the functionality of Op-Amp.
75. How to identify a Resistor value based on
61. How does Schmitt Trigger works? its Color Codes?
62. What is the significance of UTP and LTP 76. How Bread Board is Organized?
values.
77. What are Function Generators?
63. What is Hysterisis Curve ?

Sl. No. Experiment No 1a 3: Analog and Digital Electronics Laboratory (17CSL37)

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Analog and Digital Electronics Laboratory (17CSL37)

2a Design and construct a rectangular waveform generator (Op-Amp relaxation 8

10 Design and implement an asynchronous counter using decade counter IC to count up 42

Mohan H G, Assistant Professor, Dept. of CSE, JNNCE, Shimoga. Page 1

2b Design and implement a rectangular waveform generator (Op-Amp relaxation 51

Mohan H G, Assistant Professor, Dept. of CSE, JNNCE, Shimoga. Page 2

Sl. No. Particulars Specification Quantity

Mohan H G, Assistant Professor, Dept. of CSE, JNNCE, Shimoga. Page 3

Substituting the UTP and LTP values in Eq 1 and 2 will give

Practical values of Resistors selected are : R1 = 10 K Ω and R2 = 1 K Ω.

Substituting the UTP and LTP values in Eq 1 and 2 will give

Mohan H G, Assistant Professor, Dept. of CSE, JNNCE, Shimoga. Page 4

Practical values of Resistors selected are : R1 = 10 K Ω and R2 = 1 K Ω.

3. Given UTP = 6V and LTP = -2V, Choose Vsat = 12V

Practical values of Resistors selected are : R1 = _______ K Ω and R2 = _______ K Ω.

4. Given UTP = 4V and LTP = -4V, Choose Vsat = 12V

Practical values of Resistors selected are : R1 = _______ K Ω and R2 = _______ K Ω.

Circuit Diagram (Without Reference Voltage):

Mohan H G, Assistant Professor, Dept. of CSE, JNNCE, Shimoga. Page 5

Circuit Diagram (With Reference Voltage):

Waveforms displayed on CRO

Hysterisis Voltage Plot [CRO in X-Y Mode]

1. Check all the components using a Multimeter.

3. Make the appropriate settings in the CRO.

Mohan H G, Assistant Professor, Dept. of CSE, JNNCE, Shimoga. Page 6

9. Observe the input waveform at Function Generator on Channel-1 of CRO by connecting

11. Connect the negative end of Probes to the Ground.

Mohan H G, Assistant Professor, Dept. of CSE, JNNCE, Shimoga. Page 7

2a Design and Construct a Rectangular Waveform Generator (Op-Amp Relaxation

Sl. No. Particulars Specification Quantity

Let, Frequency = f, Time Period = T, Inverting Feedback Resistor = R, Coupling Capacitor = C

Mohan H G, Assistant Professor, Dept. of CSE, JNNCE, Shimoga. Page 8

If R1 = R2, then T = 2 × R × C × ln(3)

1. Given Frequency f = 1 KHz

Practical values of Resistors selected are : R1 = 1 K Ω, R2 = 1 K Ω and R = 4.7 K Ω.

2. Given Frequency f = 800 Hz

T = 1/f = 1/800 = 1.25 ms

Practical values of Resistors selected are : R1 = 1 K Ω, R2 = 1 K Ω and R = 5.6 K Ω.

Mohan H G, Assistant Professor, Dept. of CSE, JNNCE, Shimoga. Page 9

Practical values of Resistors selected are : R1 = 1 K Ω, R2 = 1 K Ω and R = K Ω.

Practical values of Resistors selected are : R1 = 1 K Ω, R2 = 1 K Ω and R = K Ω.

2. Make the appropriate settings in the CRO.

3. Compute the value of Resistor ‘R’ for the given Frequency.

5. Observe the input waveform at pin 2 of IC µA-741 on Channel-1 of CRO by connecting

6. Observe the Output waveform at pin 6 of IC µA-741 on Channel-2 of CRO by connecting

7. Connect the negative end of Probes to the Ground.

Sl. Time Period Frequency Time Period (Practical) Frequency

Mohan H G, Assistant Professor, Dept. of CSE, JNNCE, Shimoga. Page 10

Sl. No. Particulars Specification Quantity

 A Multivibrator is an electronic circuit used to implement a variety of simple multi-state

 Some common types of Multivibrator circuits are:

 Astable Multivibrator : The circuit is not stable in either state, it continually

Mohan H G, Assistant Professor, Dept. of CSE, JNNCE, Shimoga. Page 11

Duty Cycle = D Capacitance = C

Capacitor Charging Time = TC = D × T

Case 1 : If Duty Cycle D > 50% [ D > 0.5 ]

TC = 0.693 × ( R1 + R2 ) × C [Capacitor charges through R1 and R2]

TD = 0.693 × R2 × C [Capacitor discharges through R2 only]

Case 2 : If Duty Cycle D <= 50% [ D <= 0.5 ]

TC = 0.693 × R1 × C [Capacitor charges through R1 only, and

Mohan H G, Assistant Professor, Dept. of CSE, JNNCE, Shimoga. Page 12

Circuit Diagram for D > 50% [ D > 0.5 ]:

Practical values of Resistors selected are : R1 = _ K Ω and R2 = _ K Ω.

Practical values of Resistors selected are : R1 = _ K Ω and R2 = _ K Ω.

Practical values of Resistors selected are : R1 = _ K Ω and R2 = _ K Ω.

Practical values of Resistors selected are : R1 = _ K Ω and R2 = _ K Ω.

Practical values of Resistors selected are : R1 = _ K Ω and R2 = _ K Ω.