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A CMOS Hysteresis Undervoltage Lockout with Current Source

Inverter Structure

Chao Zhang, Zhijia Yang, Zhipeng Zhang

Shenyang Institute of Automation Chinese Academy of Sciences, Shenyang 110016, China


Email: zhangchao@sia.cn

Abstract voltage and may disable the system circuits when the
supply voltage drops below the threshold voltage [2].
This paper describes a simple architecture and low Many conventional undervoltage lockout circuits
power consumption undervoltage lockout (UVLO) employ a bandgap circuit for generating a reference
circuit with hysteretic threshold. The UVLO circuit voltage and a separate comparator circuit for comparing
monitors the supply voltage and determines whether or the reference voltage to a voltage divided representation
not the supply voltage satisfies a predetermined of the supply voltage, as shown in Figure 1.
condition. The under voltage lockout circuit is designed
based on CSMC 0.5um CMOS technology, utilizing a
VDD
relatively few amount of circuitry. It is realized with a
current source inverter. The threshold voltage is
determined by the WIL ratio of current source inverter
and resistor in reference generator. The hysteresis is
realized by using a feedback circuit to overcome the bad
disturbance and noise rejection of the single threshold.
Hysteretic threshold range is 40mV. The quiescent
current is about luA at 3V supply voltage, while the
power of circuit consumes only 3uW.

1. Introduction
Figure 1. Traditional UVLO circuit topology
Many circuits are sensitive to fluctuations in supply
voltage. More particularly, when the supply voltage Some undervoltage lockout circuits with bandgap
decrease below a minimum specified operating voltage, structure don't need separate comparator and reference
an under voltage condition may occur. Some circuits circuit [3], [4]. Figure 2 shows one of the undervoltage
may either be damaged or they may exhibit lockout circuit with bandgap structure. For the bandgap
unpredictable operation when operation may be structure using NPN transistors, the circuit can't be used
especially critical in circuits that include processing in standard CMOS processes.
engines such as microprocessors, microcontrollers, and
digital signal processors, for example.
The power supply is required to be stable under all
operating conditions, with all possible component
variations that may occur during the lifetime of the
system [1]. Unfortunately, there may be various reasons
for undervoltage events. In a typical battery-operated M7 Me
system such as a portable communication or computing
device, for example, the charge (and thus the voltage
potential) stored in the battery will inevitably decay. To
prevent damage or unpredictable circuit operation, it
may be desirable to disable circuit operation during
undervoltage events.
Many systems may employ an undervoltage lockout Figure 2. UVLO circuit with bandgap structure [4]
circuit to prevent operation of system circuits during
undervoltage condition. In such systems, the protection Unfortunately, these conventional implementations of
circuit may enable the system circuits to operate while undervoltage lockout circuits may utilize a relatively
the supply voltage is above a predetermined threshold large amount of circuitry and thus layout area. This also

978-1-61284-193-9/11/$26.00 ©2011 IEEE


may consume a relatively large amount of power during diode-connected MI form a V,threshold reference,
operation. generating a reference voltage VR• N-channel transistors
MI and M2 have same W/L ratio, forming a current
2. Circuit design mirror. Transistors M2 and M3 make up an inverter with
current source load. Transistors M4, M5, M6, M7, M8
IC designers often use the UVLO circuit to make sure and M9 form a Schmitt trigger. MlO, Mll and MI2
that the system starts up normally and works steadily. form a delay circuit to prevent the UVLO circuit enable
Moreover, the UVLO circuit has the function of from an acceptable ripple in supply voltage. MlO is
supervising the power supply voltage momentarily to designed to have large LlW ratio to get large RDS(ON)'
avoid its fluctuation jeopardizes the total circuits and the When undervoltage lockout occurs, the gate of MI2 is
system. getting high slowly for the large RDs(oN) of MlO. The
delay circuit acts as a low-pass filter. BUFI and BUF2
2.1 Principle of the undervoltage lockout circuit
shape the waveform of the output enable signal UVLO .
The undervoltage lockout function presented in this M13 acts as a switch to alter the resistance load of
paper is accomplished by using an inverter with current reference generator so as to realize hysteretic threshold.
source load [5]. As shown in Figure 3, transistor M2 is a
current source load, VR is a reference voltage.

VDD

G D

Figure 3. Curent source inverter


Figure 5. Schematic ofUVLO circuit
Asuming VR=I.5V, the relation between VOUT and
VDD of the circuit in Figure 3 is shown in Figure 4. Reference circuit is a simple V,threshold reference,
When supply voltage VDD is above threshold voltage as shown in left part of Figure 5. From the discussion in
VTH, the output of current source inverter VOUT is equal [5], VR is given as follow:
to VDD approximately. When VDD is below VTH,
VOUT is equal to GND approximately. The principle of
this circuit is similar to the undervoltage lockout (1)
function.

,
Where
(7) 2
,
,
I I I I I I KN2 = lin Cox (2)
4
I I I I I I

/
r-----'------,------T------ ------r

: : : : �� : :
: : : (!' "VOUT : In order to reduce the power consumption of this
> I I I I I
I I I I I I
I I I I I I circuit, the load resistor of the reference generator is
�-----J------J---i--l------L------L
I I I I I I

I VR: : : : : often very large.


,
,
The threshold of UVLO circuit is given as follow.
: I I
I I I: Assuming the current mirror (MI and M2) is ideal, the
I
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o Il
��----�----�-1--�------�------� current through M3 is equal to M2, ID2=ID3, ignoring
channel length modulation,
o 2 VTH 3 4 5
VDD(V)
Figure 4. Curent source inverter

2.2 Circuit design Where


A simple and low power undervoltage lockout circuit
is designed based on CSMC O.5um CMOS process. The
circuit is shown in Figure 5. Resistors RI, R2 and From Equation (3), the threshold voltage, VTH, is
VTH = +
(1 J:;;) VR + VTP3 - � VTN 2 (5) I
I
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I
I I

Two methods can determine the threshold voltage VTH• 800m -�------------�-----------
I I
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One is changing the W /L ratio of current source inverter, > : VRH (R 2 ) :


which is mainly determining VTH• Another is modifying : I I

g; 750m -+--------- - .- ----------- + ------------ �-


the reference voltage VR• Different resistance of RI and
: :VRL (R 1 +R2 ) : :
R2 can make different VR• This can be useful for I
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hysteresis function, which will be discussed later. I


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When power supply is in normal condition, VDD is 700m -�


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--------- �
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------------- + ------------ �
I I
-

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above threshold voltage VTH, the current through M3 is I I I

, I , , i ' , , , i ' , , I i
larger than the current through M2, the output of the 2 3 4
inverter consisted of transistors M2 and M3 (VI) is VDD ( V)
getting high, Mil is cut off. The current charges the Figure 6. The relation between VDD and VR
capacitor (MI2) through MIO (as a resistor). The voltage
V3 changes high, M13 is turned off. The branch of 3. Simulation and layout
generating reference voltage has resistor load made up of
RI and R2. The circuit output UVLO is high. The undervoltage lockout circuit is simulated by using
The gate-source voltage of M3 is getting small, while Hspice simulator based on CSMC 0. 5um CMOS process.
supply voltage is decreasing. When current through M3 First, the supply voltage VDD dc sweep ananlysis is
is less than that of M2, the output of inverter with current simulated. The hysteretic threshold is shown in Figure 7.
source load (V I) changes from high to low. The Schmitt VTHHand VTHL are different due to different initial voltage
trigger output (V2) tum on the transistor Mll, when VI VDD. Respectively, VTHH=2.57V, VTHL =2.53 V, about
is below the threshold voltage of Schmitt trigger. The 40mV hysteresis range is obtained.
capacitor (MI2) is discharged to GND through Mil,
node V3 is getting low. The circuit output UVLO
3 -
changes low to control relative circuit.
Hysteretic threshold is realized by changing the load 2.S -
resistance of the reference generator. When VDD is
above VTH, the gate of control transistor M13 is high, 2
M13 is cutoff. Equation (1) is modified to: >
1.S
u... VT VT H '
>
L

1 2(VOO-VTN2) 1 :::J
VR L = VTN 2 - KN2(R1 +R2) + KN2(R1 +R2)
+
KF.2(R1 +R2)2
SOOm
(6)
0 "'
--'-
When supply voltage VDD is below VTH, the gate of I I
2 2.S 3
control transistor M13 is low, M13 is turned on.
VOO(V)
Neglecting the RDS(ON) of M13, Equation (I) changes to:
Figure 7. Hysteretic threshold

The temperature simulation result is given in Figure 8.


For the UVLO circuit using Vrthreshold reference, VTH
is more sensitive to temperature than the circuit offered
According to the discussion above, the relation
in [3], but the result can be acceptable in ordinary
between VR and VDD is shown in Figure 6.
application.
From Equation (6) (7) and simulation result in Figure
Low power design is a challenge work for IC
6, it is easy to fmd VRH> VRL at the same supply voltage.
designers. The UVLO circuit consume less than 2uA
According to the relation between VTH and VR shown in
current along with VDD from OV to 5V, as shown in
Equation (5), VTHH > VTHL is obtained. The hysteretic
Figure 9. The power consumption is lOuW at most.
threshold is realized as shown in Equation (8). It can be
The layout of presented undervoltage lockout circuit is
concluded that hysteresis range is determined by RI.
shown in Figure 10 based on CSMC 0.5um standard
CMOS process. It is recommended to make R2 as large
as possible to reduce the power consumption.
--
VT
- - -
VT ' H

2.5 I

8 ),'C
> 1. 5 )"C

0...
> -', '"-C
::J I

5 00rn

0 I.:.r---'----'-...J. -----......L... ----


1" 'i I' ,'i I" i ii" iii" " I'" 'I' '" I' i' 'I

2.5 2.5 2 2.54 2.56 2.58 2.6 2.5 2


VDD(V)
Figure 8. Temperature characteristic of VTH

o -� ------��-- i ------ �------- i -


I

-r------i-------:: ------i------i----�-
: : � I

-2u I

I I I I I I
�-4u -�------i-------� ------i------�-------�-
� I I I I I I
Figure 10. Layout ofUVLO circuit
�-5u _ L ______ l _______ � ______ l ______ J _______ _ l
I I I I I I

:s
I I I I I I

-8u -�------f-------� ------f------�-------T-


I I I I I I

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�'10u -�------!-------� ------!------J-------l-


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References
-12u -�------i-------� ------i------�-------�-
I I I I I I
I I I I I I
[1] Raymond B . Ridley, B o H. Cho and Fred C. Y. Lee,
I' I i i i i i ' , , , I ' , , , I ' , , , i i i , , I 'I
" Analysis and interpretation of loop gains of
o 1 2 3 4 5
VDD(V) multiloop-controlled switching regulators", Power
Figure 9. Power consumption ofUVLO circuit Electronics , p.489-498 (1988).
[2] Yoshikazu Sasaki, Hashimoto and Yamamoto,
4. Conclusion "Under voltage lock out circuit and method", US
patent, No. 7,768,247 (2010).
Many systems may employ an undervoltage lockout [3] Zhao Fanglan, Feng Quanyuan and Gong Kunlin,
circuit to prevent operation of system circuits during " An undervoltage lockout of hysteretic threshold of
undervoltage condition. A simple and low power UVLO zero temperature coefficients", APMC 2005
circuit has been described. The circuit is designed in proceedings (2005).
standard CMOS process, utilizing a relatively few [4] Li Fuhua, Wang Wei and Hang Qiuping, " Design of a
amount of circuitry. The threshold voltage is determined under voltage lock out circuit with bandgap
by the W /L ratio of current source inverter. Hysteretic structure", Proc of 12th ISIC, p.224-227 (2009).
threshold range is about 40mV. The quiescent current is [5] Phillip E. Allen and Douglas R. Holberg, " CMO S
about 2uA at 5V supply voltage, while the power analog circuit design", Second edition, O xford
consumption is lOuW. University, p.I72-176 (2002).