Short Paper

Int. J. of Recent Trends in Engineering and Technology, Vol. 4, No. 4, Nov 2010

VLSI Implementation of Memory Efficient Single

Bit Processor for Industrial Control Applications
1
Jayasanthi Ranjith. M.E, 2Dr.N.J.R.Muniraj,
1
PhD scholar, Anna University, 2 Dept of ECE,
Karpagam College of Engg, Coimbatore, TN, India
E-mail: mjayasanthi@yahoo.co.in, njrmuniraj@yahoo.com

Abstract-This paper describes bit serial architecture with
reduced memory area which has the advantage of a very
compact design solution that avoids many of the place and
route problems commonly associated with FPGAs. The bit
clock required to obtain the required data rate pushes the
upper limits of today’s FPGAs. Delta–Sigma (∆∑) modulator
is frequently used in the Conversion of signals from analog or
digital form into bit streams at very high sampling rate. Here
a novel single bit memory efficient control system processor
that can be used for industrial and other control applications
is described. It is a small and fast application-specific
processor in SOC and mixed signal applications. Another
increasing concern in processor design is improved Code
density, since it reduces the need for the scarce resource
memory and also implicitly improves power consumption and
performance. Any physical system can be efficiently
controlled by this processor which compresses the data during
off-line phase, decompresses and processes it during on-line
phase. A dictionary based data compression technique which
provides a substantial improvement in the compression
efficiency and the power reduction is used here.
Keywords- 1-bit processing, ∆∑ modulation, control system
processor, system-on-chip (SOC), Mixed signal, Code
compression,Dictionary based compression, code density,
VLSI.
I. INTRODUCTION
Implementation of control laws in digital systems is an
important part of the design process. Analogue signals are
encoded into a simple 1-bit stream using Delta Sigma
modulator, at very high sampling frequencies [15]. It
possible to implement the control laws directly on those 1-
bit signals, that can be also used to drive physical systems
directly. Since the memory chip dominates a large part of
the chip area, a reduction of the cost can be achieved by
reducing the memory size. This is done by using code
compression which can also reduce the power consumption
[2]. This paper describes a novel, ∆∑-based control system
processor with efficient code density to control physical
systems for very demanding control applications. Fig 1.
Shows the resulting block diagram which describes the
process of compressing and decompressing code in ∆∑-
CSP during design and runtime phases. The analogue
signal is first encoded into its corresponding l-bit format by
passing through a simple analogue ∆∑ modulator. The
output of the controller is in multi-bit format [16]. Hence a
digital ∆∑ modulator is placed after it to convert the
control signal into a bit-stream. This 1-bit signal can be
used to control the physical system directly. In the design
phase, the original program instructions are compressed
and then stored along with decoding tables. During the
runtime phase, the original instructions are recovered from
the compressed ones by using the decoding table(s) along
with some decoding hardware or software [2].
CONTROL
SYSTEM
PROCESSOR WITH
I/P ∆∑ ∆∑
COMPRESSION &
DECOMPRESSION
UNIT
Physical PDM
system
Fig 1:∆∑-CSP during Design and Runtime Phases.
Related works of this paper is discussed in next section.
The concept of ∆∑ modulator, 1 bit processor and its
architecture are introduced in Section III. Section IV
describes the code compression and decompression
schemes. The performance of the entire work is described
and compared with CSP Section V. Section VI concludes
and suggests future applications where the high speed ∆∑-
CSP can be utilized.
II. RELATED WORK & CONTRIBUTION
A. Related work
∆∑ based control system processor; a small and fast
application-specific processor was implemented for very
demanding control Applications [2]. The memory required
for storage of data in the processor can be still improved by
using compression and decompression techniques [1]. A
37.5%compression ratio is achieved for the ARM processor
without taking into account the large external ROM size
overhead[3]. Common to all work in code compression is
that Look-up Tables are deployed for decoding. In any
case, these tables will take space in memory and
significantly impact the total compression ratio. Hence, an
efficient compression ratio can be accomplished by
minimizing both the code itself and the tables.
B. Novel contribution
• Canonical Huffman coding combined with table
compression scheme is introduced in ∆∑-CSP.
• Power consumed in the processor is optimized.
• Hardware implementation for both schemes
with and without the compression schemes are

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Short Paper
Int. J. of Recent Trends in Engineering and Technology, Vol. 4, No. 4, Nov 2010

performed. 2) Instruction Set Architecture:

• Experimental results are presented and the Table 1 shows the instruction set of this processor.
comparison is shown at the end of this paper.
TABLE I
INSTRUCTION SET
III. ∆∑ CONTROL SYSTEM PROCESSOR
BINARY OPCODE OPERATION
000 HLT Halt Execution
A. Delta sigma (Δ -Σ) modulator To rotate in forward
001 FRW
Delta-sigma modulator converts an analog input signal direction
into a high speed, 1-bit data stream with on-chip digital Feedback voltage from
010 FBV
encoder
isolation [6].For first order delta-sigma (Δ -Σ) modulator To rotate in forward
(oversampling converter,the multi-bit format of the input’ 011 REV
direction
Xi’ is calculated from [9]. 100 IP1
User’s input voltage
101 IP2
Xi=1/N∑Yi i=1,2……N (1) Set/Reset if difference is
110 SET/RSET
Yi =1 if Xn>=0 (2) more plus/minus
=0 Xn <0
Where N the number of samples, 111 SETF Set Sampling Frequency
Xn is the last integrator’s output,
Yi is the output of the 1-bit quantizer.
IV. CODE COMPRESSION AND DECOMPRESSION
B. Control System Processor
A. Dictionary-based code compression
Processor design involves defining the instruction set
and designing the data path that performs all the operations 1) Generating the Compressed Code:
included in the instruction set [8]. To generate the encoded instructions and the LUT, first
the original (i.e., uncompressed) instruction words are
unified and then every unique instruction word is replaced
with a binary index to the LUT in ascending order[3] [5].

2) Compressing the Decoding Table:

. compression scheme [1]. In LUT, each compressed column
Fig.3 Processor design
1) Instruction Decoder :
The instruction decoder fetches the instructions from the
program RAM and separates the opcode field, oper and1
and operand2 fields. Here instruction decoder is 13-bits
wide, one operand being 4-bits wide, and another operand
being 9-bits wide.These opcodes, operand 1 and operand2
are mapped to Arithmetic and Logic Unit (ALU) which is
the portion of the data path unit.
The principle of compressing the table is to minimize the
number of bit transitions per column and then saving the
indices only where a bit toggle occurs [4].In our case, the
distance between two entries is the Hamming Distance
which is the sum of bit toggles between these entries[12].
B. De-compression
LUT decoder is used in The dictionary based
is stored in each Block RAMs, and un-compressed columns
are stored in external ROM [3].When the compressed
instruction is received by the decoder, it finds out its
position in each Block RAM. If it is in an even position, the
decoder generates ’0’ in that position, otherwise ’1’ is
generated [5]. The compressed address in the memory is
computed as following:
Compressed address =Uncompressed address from CPU
Encoded instruction length in memory
V. SIMULATION & HARDWARE IMPLEMENTATION
High speed clock for sampling the analog signal is
generated using Digital Clock manager (DCM). The
objective is to control the speed and direction of the motor.
The control program is stored in program RAM The output
of the processor is given to the motor drive. This motor
signal is accepted by the encoder and is compared with the
reference value 256 volts and the result is fed back to the
processor for further control applications. The Δ-Σ

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Int. J. of Recent Trends in Engineering and Technology, Vol. 4, No. 4, Nov 2010

modulator, processor, encoder, decoder, compressor and
de-compressor are modeled in VHDL. The whole Δ-Σ CSP
system will be implemented in FPGA technology. Fig. 4
shows simulated output of ∆∑CSP for DC motor control. It
shows that motor is ON and running in forward direction.
This scheme is powerful when regular schemes do not
work well, i.e., when the number of unique instruction
words is large compared to all instruction words of an
application. For the given input 28% of storage area has
been saved using this approach. This is a noticeable
improvement over previous approaches. Since the memory
used is small, a significant amount of power can also be
reduced in this project.

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