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MODES TYPE:
1. FUNCTIONAL MODE.
2. TEST MODE.
IT CONTAINS SDC CONSTRAINTS.
IN DESIGN DIFFERENT FUNCTIONALITY MODES CONTAINS DIFFERENT SDC'S.
IN DESIGN DIFFERENT FUNCTIONALITY MODES ARE PRESENT.
|
_____________WORST CASE CORNER.
_
FOR SETUP :
Arrival Path-------- |
|--------------------->Max Dealys
Data path------------|
Reqired Path------------------------------->Min Delays
FOR HOLD :
Arrival Path-------- |
|--------------------->Min Dealys
Data path------------|
PHYSICAL VERIFICATION:
IN PHYSICAL VERIFICATION IT CHECKS:
1. LVS(LAYOUT VERSUS SCHEMATIC)
2. DRC(DESIGN RULE CONSTRAINTS CHECK)
3. ERC(ELECTRICAL RULE CHECK)
LAYOUT VERSUS SCHEMATIC(LVS):
INPUTS ARE (.LVS.V) AND (.GDSII) FILES AND RULE DECK FILES.
COMPARISION TWO ELECTRICAL CIRCUITS EQUIVALENT WITH RESPECT TO THEIR
"CONNECTIVITY" AND "TOTAL TRANSISTOR COUNT".
CHECKS ARE:
● WELL AND SUBSTRATE AREAS FOR PROPER CONTACTS AND SPCINGS THERE BY
ENSURING CORRECT POWER CONTACTS AND GROUND CONNECTIONS.
● TO LOCATE FLOATING DEVICES AND FLOATING WELLS.
● TO LOCATE DEVICE WICH ARE SHORTED.
● TO LOCATE DEVICES WITH MISSING CONNECTIONS.
● GATE CONNECTRD DIRECTLY TO SUPPLIES.
● FLOATING INPUTS.
FORMAL VERIFICATIONS:
SETUP CHECK:THE DATA LAUNCHED AT THE SENSITIVE EDGE OF THE LAUNCH FLOP
SHOULD BE CAPTURED AT THE NEXT SENSITIVE EDGE OF THE CAPTURED FLOP.
HOLD TIME: THE MINIMUM AMOUNT OF TIME THE DATA SHOULD BE STABLE AFTER
ARRIVAL OF SENSITIVE CLOCK.
HOLD CHECK: THE DATA LAUNCHED AT THE SENSITIVE EDGE OF THE LAUNCH FLOP
SHOULD NOT BE CAPTURE AT THE SAME SENSITIVE EDGE OF CAPTURED FLOP.
SETUP FIXES:
1. BUFFER INSERTION
2. UPSIZING THE DRIVER CELL
3. REDUCE NET LENGTH
4. CELL UP SIZING.
5. DRIVE STRENGTH OF LAUNCH FLOP INCREASE.
6. LOGICAL OPTIMIZATION ON DATA PATH.
7. USEFUL SKEW.
8. PIPELINING.
9. USE SYNC CELLS.
10. NET WIDTH INCREASE.
11. USE LVT CELLS.
12. SPLITTING THE COMBINATIONAL LOGIC.
13. INCREASE CLOCK PERIOD.
14. USING DOUBLE SYNCHRONIZER USING FLIP FLOPS.
15. REDUNDANT VIA.
16. REDUCE THE MORE FANOUT NETS WITHIN THE LOGIC
17. DOUBLE VIA
18. LAYER JUMPING
HOLD FIXES:
WHEN HIGH CURRENT DENSITY TRANSFERRING THROUGH A LONG WIRE FOR A LONG
TIME DUE TO THIS ELECTRONS MOVED WITH HIGH ACCELARATIONS ,DUE TO THIS
THOSE ARE TRANSFERRING THEIR MOMENTUM TO THE METAL ATOMS.DUE TO THESE
CAN MIGRATE AND MOVE AWAY FROM THE METAL .
FIXES
FIXING CROSSTALK
CROSS TALK:
REDUCING TECHNIQUES:
FIXING DRC'S
DRC'S FIXING
DRC'S ARE DIFFERENT TYPES :
1. LOGICAL DRC'S.
2. PHYSICAL DRC'S.
LOGICAL DRC'S:
1. MAX TRANSITION
2. MAX CAPACITANCE
3. MAX FANOUT
MAX TRANSITION:
FIXING TECHNIQUES:
MAX CAPACITANCE:
FIXING TECHNIQUES:
MAX FANOUT:
FIXING TECHNIQUES:
PHYSICAL DRC'S:
FIXING TECHNIQUES:
● STDCELLS:
○ Nothing But Base cells(Gates,flops).
● TAP CELLS:
○ Avoids Latch up Problem(Placing these cells with a particular distance).
○ Cells are physical-only cells that have power and ground pins and dont have
signal pins.
○ Tap cells are well-tied cells that bias the silicon infrastructure of n-wells or
p-wells.
○ They are traditionally used so that Vdd or Gnd are connected to substrate or
n-well respectively.
○ This is to Help TIE Vdd and Gnd which results in lesser drift and prevention
from latchup.
○ Required by some technology libraries to limit resistance between Power or
Ground connections to well of the substrate.
● TIE CELLS :
○ It is used for preventing Damage of cells; Tie High cell(Gate One input is
connected to Vdd, another input is connected to signal net);Tie low cells Gate
one input is connected to Vss, another input is connected to signal .
○ Tie - high and Tie - low cells are used to connect the gate of the transistor to
either Power and Ground.
○ In lower technology nodes, if the gate is connected to Power or Ground. The
transistor might be turned "ON/OFF" due to Power or Ground Bounce.
○ These cells are part of the std cell library.
○ The cells which require Vdd(Typically constant signals tied to 1) conncet to tie
high cells.
○ The cells which require Vss/Vdd (Typically constant signals tied to 0) connect
to tie low cells.
● END CAP CELLS:
○ To Know the end of the row,and At the edges endcap cells are placed to avoid
the cells damages at the end of the row to avoid wrong laser wavelength for
correct manufacturing.
○ You can add Endcap cells at both Ends of a cell row.
○ Endcap cells surrounding the core area features which serve as second poly to
cells
○ placed at the edge of row.
○ The library cells do not have cell connectivity as they are only connected to
Power and Ground rail,
○ Thus ensure that gaps do not occure between "WELL" and "IMPLANT LAYER"
and to prevent the DRC violations by satisfying "WELL TIE - OFF"
requirements for core rows we use End cap cells.
○ Usually adding the "Well Extension" for DRC correct designs.
○ End caps are a "POLY EXTENSION" to avoid drain source SHORT
● DECAP CELLS:
○ Charge Sharing;To avoid the Dynamic IR drop ,charge stores in the cells and
release the charge to Nets.
○ Decoupling capacitor cells , or Decap cells, are cells that have a capacitor
placed.
○ Between the Power rail and Ground rail to Over come Dynamic voltage drop.
○ Dynamic IR Drop happens at the active edge of the clock at which a High
currents is drawn from the Power Grid for a small Duration.
○ If the Power is far from a flop the chances are there that flop can go into
Metastable State.
○ To overcome decaps are added , when current requirements is High this
Decaps discharges and provide boost to the power grid.
● FILLER CELLS:
○ Filler cells are used to connect the gaps between the cells after placement.
○ Filler cells are ussed to establish thecontinuity of the N-Wells and the
IMPLANT LAYERS on the standard cells rows, some of the cells also don't
have the Bulk Connection (Substrate connection) Because of their small size
(thin cells).
○ In those cases, the abutment of cells through inserting filler cells can connect
those substrates of small cells to the Power/Ground nets.
○ i.e. those tin cells can use the Bulk connection of the other cells(this is one of
the reason why you get stand alone LVS check failed on some cells)
● ICG CELLS:
○ Clock gating cells ,to avoid Dynamic power Dissipation.
○ Register banks disabled during some clock cycles.
○ During idle modes, the clocks can be gated-offs to save Dynamic power
dissipation on flipflops.
○ Proper circuit is essential to achive a gated clock state to prevent false glithes
on the clock paths
● POWER GATING CELLS:
■ In Power gating to avoid static power Dissipation.
○ Power Gating Cells:
■ Power switches
■ Level Shifters
■ Retention registers
■ Isolation cells
■ Power controler
● PAD CELLS:
○ To Interface with outside Devices;Input to of Power,Clock,Pins are connected
to pad cells and outside also.
● CORNER CELLS:
○ Corner Pads are used for Well Continity.
○ To lift the chip.
● MACRO CELLS:
○ Memories.
○ The memory cells are called Macros.
○ To store information using sequntial elements takes up lot of area.
○ A single flipflop could take up 15 to 20 transistors to store one bit store the
data efficiently and also do not occupy much space on the chip comparatively
by using macros.
● SPARE CELLS:
○ Used at the ECO.
○ Spare cells are standard cells in a design that are not used by the netlist.
○ Placing the spare cells in your design provides a margin for correcting logical
error that might be detected later in the design flow, or for adjusting the speed
of your design.
○ Spare cells are used by the fix ECO command during ECO process.
● PAD FILLER CELLS:
○ Used for Well Continity, Placed in between Pads.
● JTAG CELLS:
○ These are used to check the IO connectivity.
FILES:
CALCULATIONS:
POWER CALCULATIONS:
----->NUMBER OF THE CORE POWER PAD REQUIRED FOR EACH SIDE OF CHIP=(TOTAL
CORE POWER)/{NUMBER OF SIDE)*(CORE VOLTAGE)*MAXIMUM ALLOWABLE CURRENT
FOR A I/O PAD)} .
Wtotalstrap = Itotal/(2*Rj)
L<(Vmax)/(Rj*Rs)
Rs=SHEET RESISTANCE
H=HEIGHT
W=WIDTH
IR DROP:
=IstrapAvg*Rs*(W/2)*(1/Wstrap)
Nstrappinspace = Dpadspacing/Lspace.
POWER
=LEAKAGE POWER+[{(Vdd*Isc)+(C*V*V*F)+(1/2*C*V*V*F)]
C=LOAD CAP
FINAL VERIFICATION:
1. PARASITICS EXTRACTION:IT EXTRACT R,C VALUES FOR GETTING ORIGINAL
DELAYS. TOOL:STAR RC XT LICENCE
2. TIMING VERIFICATION:IT IS FIND BY USING PRIME TIME TOOL.
3. LVS ,ERC CHECKS:THESE IS FIND OUT BY USING CALIBRE,HERCULIES TOOLS.
4. DRC CHECKS:THESE IS FIND OUT BY USING CALIBRE,HERCULIES TOOLS.
AFTER VERIFICATION:
AFTER GDS
CHIP FINISHING:
WE NEED TO DO:
● REDUNDANT VIA IS THE TECHNIQUE FOR REDUCING VOIDS IN THE METAL LAYER.
● FILLER CELL INSERTION IS THE ONE OF THE TECHNIQUE FOR UTILIZING THE
TOTAL AREA WITH OUT GAPS .
● IT IS GOOD TECHNIQUE BECAUSE IN THE FUTURE WE CAN REPLACE FILLER
CELLS WITH SPARE CELLS WITH A LOGIC.
● AT THE TIME OF ETCHING THEY USE SOME TYPE OF CHEMICALS DUE TO THAT
CHEMICALS METAL LOSSES MORE FOR THAT ONE WE ARE INSERTING THE METAL
FILLS.
METAL SLOTTING
● METAL SLOTTING IS TECHNIQUE FOR AVOIDING THE PROBLEMS LIKE METAL LIFT
OFF , METAL EROSION.
ECO:
| |
----------------------------- ---------------------------
| | | |
--------->IN FREEZE SILICON ECO WE HAVE NO CHANCE OF ADDING CELL, HERE SPARE
CELLS ARE USED FOR THESE.
----------->IN NON FREEZE SILICON ECO WE CAN ADD THE CELLS AFTER ROUTING.
DETAIL ROUTING:
----->DETAIL ROUTING DOES NOT WORK ON THE ENTIRE CHIP AT THE SAME TIME LIKE
TRACK ASSIGNMENT.
SBOX : DIVIDE THE BLOCK INTO MINI BOXES THESE ARE USED FOR THE DETAIL ROUTE.
TRACK ASSIGNMENTS :
---->ASSIGNS EACH NET TO THE SPACIFIC TRACKS.
----->TRACES=METAL CONNECTIVITY..
GLOBAL ROUTING:
--->FIRST THE DESIGN IS DIVIDED INTO SMALL BOXES EVERY BOX IS CALLED GLOBAL
ROUTING CELLS (GCELLS OR BUCKETS)
------->IF ANY GCELL HAVE CONGESTION THEN DETOURING(AVOID THE GCELL ROUTING
THROUGH ANOTHER GCELL).
ROUTING
ROUTING:
(i)GLOBAL ROUTING
(ii)TRACK ASSIGNMENT
(iii)DETAIL ROUTING
EXTRA ONE
(iv)SEARCH AND REPAIR
CTS OPTOMIZATION
OPTIMIZATIONS TECHNIQUES:
OPTIMIZATION PROCESS:
NDR'S:
(ii)DOUBLE SPACING.
(iii)SHEILDING
BY DEFAULT, NON DEFAULT ROUTING RULE APPLIES ON ALL LEVELS CLOCK TREE. BUT
USING NDR RULES AT THE CLOCK SINK PIN POINTS IS BETTER TO AVOID.
SETUP TIME :THE MINIMUM AMOUNT OF TIME THE DATA SHOULD BE STABLE BEFORE
ARRIVAL OF SENSITIVE CLOCK.
HOLD TIME :THE MINIMUM AMOUNT OF TIME THE DATA SHOULD BE STABLE AFTER
ARRIVAL OF SENSITIVE CLOCK.
SETUP CHECK:THE DATA LAUNCHED AT SENSITIVE EDGE OF THE LAUNCH FLOP SHOULD
BE CAPTURED AT NEXT SENSITIVE EDGE OF THE CAPTURED FLOP.
(ii)OUTPUT PORT.
BY THE COMBINATION OF THE THESE START AND END POINTS WE HAVE THE PATHS LIKE
ARE
BY DEPENDING ON THE START POINTS AND END POINTS WE HAVE FOUR TIMING GROUPS
PRESENT.
1. INPUT GROUP
2. REGISTER GROUP
3. FEED THROUGH GROUP.
4. OUTPUT GROUP.
----->CTS IS THE CONNECT THE CLOCKS TO THE ALL CLOCK PIN OF SEQUENTIAL
CIRCUITS.
(ii)max capacitance,
(iii)max fanout,
------->A BUFFER TREES IS BUILT TO BALANCE THE LOADS AND MINIMIZE THE SKEW.
-------->A CLOCK TREE WITH BUFFER LEVELS BETWEEN THE CLOCK SOURCE AND CLOCK
SINKS(END POINTS).
-------->CLOCK PINS ARE DIFFERENT TYPES ,THOSE ARE (i) STOP PINS,
(ii)FLOAT PINS,
(iii)EXCLUDE PINS.
--------->NON-STOP PINS: NONSTOP PINS ARE PINS THROUGH WHICH CLOCK TREE
TRACING THE CONTINOUS AGAINEST THE DEFAULT BEHAVIOUR .
PLACEMENT OPTIMIIZATION
PLACEMENT OPTIMIZATION:
BY USING THE AREA RECOVERY OPTION WE CAN REDUCE THE CELLS , POWER, TIMING.
BY USING THE DFT OPTION WE CAN REDUCE THE ROUTING RESOURECES BY REORDER
THE SCAN CHAINS.
POWER SETUP:
WE HAVE TWO TYPE OF THE POWER DISSIPATIONS:
STATIC POWER DISSIPATION IS, IF THE CELLS ARE PRESENT AT THE "OFF" STATE THEN
DUE TO THE LEAKAGE OF CELLS STATIC POWER DISSIPATION OCCURRS.
IN THE MOST OF THE ARCHITECTURES WE WILL USE THE POWER GATING FOR
REDUSING THE STATIC POWER DISSIPATION.
REDUCING THE HIGH TOGGLE RATE NET NET LENGTHS. THESE TOGGLE RATE IS
GETTING FROM SWITCHING FILE(.SAIF ) THIS IS GETTING FROM SIMULATION PEOPLE.
AND FOR AVOIDING THIS WHICH CELLS HAVING HIGH TOGGLE RATE NET LENTHS
CONNECTED NEARER TO CONNECTED CELLS.
ANOTHER TECHNIQUE IS ADDING THE BUFFER IN BETWEEN THE HIGH NET LENGTH
NETS. FOR REDUCING THE HIGH COUPLING CAPACITANCE.(REDUCE THE LOAD
CAPACITANCE)
ANOTHER TECHNIQUE IS CLONING , IT IS CREATING THE SAME CELL AND CONNECT THE
SOME OF THE OUTPUT NET TO THESE.(SHARING THE LOAD)
MOSTLY IN DESIGN WE WILL USE THE CLOCK GATING TO REDUSING THE DYNAMIC
POWER DISSIPATION
PLACEMENT (DFT SETUP)
DFT SETUP:
SCAN CHAINS: SCAN CHAINS ARE NOTHING BUT A GROUP OF REGISTERS CONNECTED
SERIALLY.
THE ISSUE IS PREEXISTING SCAN CHAINS ARE CONNECTED FAR AWAY , BECAUSE THEY
ARE CONNECTED BASED ON THE FUNCTIONALITY BASED,
INSERT THE SCAN CHAINS FILE. IF PROBLEM WITH PREEXISTING SCAN CHAINS THEN
REORDER THE NAMES OF THE SCAN REGISTER NAMES.
IF THE GIVEN NETLIST IS .ddc FORMAT THEN THERE IS NO NEED OF LOADING .scandef
IF THE GIVEN NETLIST IS .v FORMAT THEN WE HAVE TO LOAD THE .scandef FILE
PLACEMENT
1. PLACEMENT CHECKS,
2. AHFNS
3. DFT SETUP.
4. POWER SETUP.
5. PLACEMENT OPTIMIZATION.
PLACEMENT :
-->FIX MACRO PLACEMENT AGAIN, BECAUSE AFTER INSERTING THE DESIGN IF MACROS
ARE MOVED THE CHECK.
-->NON DEFAULT RULES ARE SPECIAL RULES. LIKE DOUBLE SPACING, DOUBLE
WIDTHING. THESE ARE APPLIED FOR CLOCK WIRES. BECAUSE THOSE HIGH ACTIVITY
NETS.
1. FLOOR PLAN ,
2. NETLIST,
3. NARROW PLACEMENT REGIONS,
4. R,C FOR ROTING LAYERS,
5. DESIGN CONSTRAINTS.
FLOORPLAN(TIMING)
AFTER ACCEPTING THE CONGESTION, TIMING THEN WRITE OUT THE .def file
SAVE THE DESIGN .AND THESE .def FILE IS GIVEN AS INPUT TO THE PLACEMENT.
FLOORPLAN (CONGESTION)
MORE FIXES :
POWER PLANNING
IN POWER PLANNING
----->NUMBER OF THE CORE POWER PAD REQUIRED FOR EACH SIDE OF CHIP=(TOTAL
CORE POWER)/{(NUMBER OF SIDE)*(CORE VOLTAGE)*MAXIMUM ALLOWABLE CURRENT
FOR A I/O PAD)} .
Wtotalstrap = Itotal/(2*Rj)
L<(Vmax)/(Rj*Rs)
Rs=SHEET RESISTANCE
W=WIDTH
IR DROP:
=IstrapAvg*Rs*(W/2)*(1/Wstrap)
Nstrappinspace = Dpadspacing/Lspace.
POWER
=LEAKAGE POWER+[{(Vdd*Isc)+(C*V*V*F)+(1/2*C*V*V*F)]
C=LOAD CAP
IN FLOOR PLAN
1. CREATE PHYSICAL ONLY PAD CELLS. PHYSICAL ONLY CELLS MEANS ONLY
THOSE HAVING PHYSICAL INFORMATION ONLY. NO LOGICAL INFORMATION
PRESENT. AND THEY DON'T HAVE TIMING INFORATION ALSO.
2. PHYSICAL ONLY PAD CELLS ARE (i)VDD,VSS PADC CELLS,(ii)CORNER PAD CELLS.
3. PAD CELLS ACTS LIKE AS PORTS AT THE CHIP LEVEL.
4. CHIP OUTSIDE PINS ARE CONNECTED TO THE INNER CHIP PADS.
5. PADS TYPES:(i)POWER PADS, (ii)DATA PADS .
6. FOR THE POWER SUPPLY TO THE ALL PADS CREATING A PAD POWER RING .
7. VDD,VSS PADS ARE CONNECTED TO THE CORE VDD,VSS POWER RINGS.
8. FOR FILLING THE GAPS BETWEEN THE PADS FILLED BY PAD FILLER CELLS.
9. THESE PAD FILLER CELLS ARE FOR WELL CONTINUITY.
1. PAD CELLS.
2. END CAP CELLS.
3. TAP CELLS.
4. DECAP CELLS.
FLOOR PLAN:
AT CHIP LEVEL:
WELL CONTINITY , WELL CONTINITY MEANS IF THE WELL IS NOT CONTINOUS THEN WE
HAVE TO CREATE SPECIAL MASKS.
HARD MACRO:THE CIRCUIT IS FIXED. AND WE DON'T NO WHICH TYPE OF GATES USING
INSIDE.WE KNOW THE ONLY TIMING INFORMATION.WE DON'T KNOW THE FUNCTIONALITY
INFORMATION.
SOFT MACRO:THE CIRCUIT IS NOT FIXED.WE KNOW WHICH TYPE OF GATES USING
INSIDE.WE KNOW THE TIMING INFORMATION. WE KNOW THE FUNCTIONALITY
INFORMATION.
(ii)HARD BLOCKAGES.
SOFT BLOCKAGES MEANS NO ONE STD CELLS PLACED FIRST, BUT AT THE TIME OF
OPTIMIZATION ONLY BUFFERS ARE PLACED, AND THESE ARE USED AT (i)BETWEEN TWO
MACROS,
HARD BLOCKAGES MEANS NO ONE STD CELLS PLACED.AND THESE ARE USED AT THE
AROUND THE MACRO.BECAUSE PIN ACCESSING.
I/O PLACEMENTS.
CORE AREA :CORE AREA IS DEFINED FOR THE PLACEMENT OF STD CELLS,AND
MACROS.
(ii)UTILIZATION.
UTILIZATION=(STD CELL AREA+MACRO AREA+BLOCKAGE AREA)/TOTAL AREA.
----->I/O PLACEMENT.
PADS ARE USED FOR INTERFACING PURPOSE,AND THESE ARE USED FOR
PROVIDING POWER SUPPLY, DATA SIGNAL,CLOCK SIGNAL.
(ii)SIGNAL PADS.
(iii)CORNER PADS.
(iv)I/O PADS.
OPTIMIZATION CONTROLS
SDC
Constraints are
--------------->Clock latency
--------------->Clock Uncertainity
--------------->Clock Transition
.V ---------->Logical Connectivity
TECHNOLOGY FILE
Layer Info :
1. Mask Name
2. Visible
3. Selectable
4. Line Style(Solid)
5. Patteren
6. Pitch
7. Cut Layer
8.
PHYSICAL LIBRARIES
-------------->Size(Dimensions,Area)
------------->Pin
------------->Port
------------->Layer
------------->Direction
--------------->Use(Signal,Power,Ground)
--------------->layer
LEFs are 3 Types : .Macro lef (Macro Info)
1)Cell View:
2)FRAM view:
LOGIC LIBRARIES
---------->Internal Power
---------->Rise Transition
----------->Fall transition
---------->>Setup rise
----------->Setup fall
----------->Hold rise
------------>Hold fall
------------->Recovery rise
-------------->Removal fall
--------------->Cell rise
-------------->Cell fall
-------------->Pin Capacitance
1. Cell name
2. Area(represent with Nand Equ Area)
3. Power (Funtion of input transition, Total output net Cap )
4. Funtionality
5. Delay
6. Max Cap
7. Max Trans
8. Foot Print
2)Physical Design(PD)
1. DATA PREPARATION.
2. FLOOR PLAN.
3. POWER PLAN-->POWER ROUTING [PRE ROUTE]
4. PLACEMENT.
5. CLOCK TREE SYNTHESIS.-->CLOCK ROUTING.
6. ROUTING.-->DATA ROUTING.-->[POST ROUTE]
7. CHIP FINISHING.
8. VERIFICATION.
9. GDSII FILE.